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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
7 * Copyright (C) 2007 Maciej W. Rozycki
8 */
9#ifndef _ASM_WAR_H
10#define _ASM_WAR_H
11
12#include <war.h>
13
14/*
15 * Work around certain R4000 CPU errata (as implemented by GCC):
16 *
17 * - A double-word or a variable shift may give an incorrect result
18 * if executed immediately after starting an integer division:
19 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
20 * erratum #28
21 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
22 * #19
23 *
24 * - A double-word or a variable shift may give an incorrect result
25 * if executed while an integer multiplication is in progress:
26 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
27 * errata #16 & #28
28 *
29 * - An integer division may give an incorrect result if started in
30 * a delay slot of a taken branch or a jump:
31 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
32 * erratum #52
33 */
34#ifdef CONFIG_CPU_R4000_WORKAROUNDS
35#define R4000_WAR 1
36#else
37#define R4000_WAR 0
38#endif
39
40/*
41 * Work around certain R4400 CPU errata (as implemented by GCC):
42 *
43 * - A double-word or a variable shift may give an incorrect result
44 * if executed immediately after starting an integer division:
45 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
46 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
47 */
48#ifdef CONFIG_CPU_R4400_WORKAROUNDS
49#define R4400_WAR 1
50#else
51#define R4400_WAR 0
52#endif
53
54/*
55 * Work around the "daddi" and "daddiu" CPU errata:
56 *
57 * - The `daddi' instruction fails to trap on overflow.
58 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
59 * erratum #23
60 *
61 * - The `daddiu' instruction can produce an incorrect result.
62 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
63 * erratum #41
64 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
65 * #15
66 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
67 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
68 */
69#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
70#define DADDI_WAR 1
71#else
72#define DADDI_WAR 0
73#endif
74
75/*
76 * Another R4600 erratum. Due to the lack of errata information the exact
77 * technical details aren't known. I've experimentally found that disabling
78 * interrupts during indexed I-cache flushes seems to be sufficient to deal
79 * with the issue.
80 */
81#ifndef R4600_V1_INDEX_ICACHEOP_WAR
82#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
83#endif
84
85/*
86 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
87 *
88 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
89 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
90 * executed if there is no other dcache activity. If the dcache is
91 * accessed for another instruction immeidately preceding when these
92 * cache instructions are executing, it is possible that the dcache
93 * tag match outputs used by these cache instructions will be
94 * incorrect. These cache instructions should be preceded by at least
95 * four instructions that are not any kind of load or store
96 * instruction.
97 *
98 * This is not allowed: lw
99 * nop
100 * nop
101 * nop
102 * cache Hit_Writeback_Invalidate_D
103 *
104 * This is allowed: lw
105 * nop
106 * nop
107 * nop
108 * nop
109 * cache Hit_Writeback_Invalidate_D
110 */
111#ifndef R4600_V1_HIT_CACHEOP_WAR
112#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
113#endif
114
115
116/*
117 * Writeback and invalidate the primary cache dcache before DMA.
118 *
119 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
120 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
121 * operate correctly if the internal data cache refill buffer is empty. These
122 * CACHE instructions should be separated from any potential data cache miss
123 * by a load instruction to an uncached address to empty the response buffer."
124 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
125 * in .pdf format.)
126 */
127#ifndef R4600_V2_HIT_CACHEOP_WAR
128#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
129#endif
130
131/*
132 * Workaround for the Sibyte M3 errata the text of which can be found at
133 *
134 * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
135 *
136 * This will enable the use of a special TLB refill handler which does a
137 * consistency check on the information in c0_badvaddr and c0_entryhi and
138 * will just return and take the exception again if the information was
139 * found to be inconsistent.
140 */
141#ifndef BCM1250_M3_WAR
142#error Check setting of BCM1250_M3_WAR for your platform
143#endif
144
145/*
146 * This is a DUART workaround related to glitches around register accesses
147 */
148#ifndef SIBYTE_1956_WAR
149#error Check setting of SIBYTE_1956_WAR for your platform
150#endif
151
152/*
153 * Fill buffers not flushed on CACHE instructions
154 *
155 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
156 * for that line can get stale data from the fill buffer instead of
157 * accessing memory if the previous icache miss was also to that line.
158 *
159 * Workaround: generate an icache refill from a different line
160 *
161 * Affects:
162 * MIPS 4K RTL revision <3.0, PRID revision <4
163 */
164#ifndef MIPS4K_ICACHE_REFILL_WAR
165#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
166#endif
167
168/*
169 * Missing implicit forced flush of evictions caused by CACHE
170 * instruction
171 *
172 * Evictions caused by a CACHE instructions are not forced on to the
173 * bus. The BIU gives higher priority to fetches than to the data from
174 * the eviction buffer and no collision detection is performed between
175 * fetches and pending data from the eviction buffer.
176 *
177 * Workaround: Execute a SYNC instruction after the cache instruction
178 *
179 * Affects:
180 * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
181 * MIPS 20Kc RTL revision <4.0, PRID revision <?
182 */
183#ifndef MIPS_CACHE_SYNC_WAR
184#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
185#endif
186
187/*
188 * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
189 * the line which this instruction itself exists, the following
190 * operation is not guaranteed."
191 *
192 * Workaround: do two phase flushing for Index_Invalidate_I
193 */
194#ifndef TX49XX_ICACHE_INDEX_INV_WAR
195#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
196#endif
197
198/*
199 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
200 * opposes it being called that) where invalid instructions in the same
201 * I-cache line worth of instructions being fetched may case spurious
202 * exceptions.
203 */
204#ifndef ICACHE_REFILLS_WORKAROUND_WAR
205#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
206#endif
207
208/*
209 * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
210 * may cause ll / sc and lld / scd sequences to execute non-atomically.
211 */
212#ifndef R10000_LLSC_WAR
213#error Check setting of R10000_LLSC_WAR for your platform
214#endif
215
216/*
217 * 34K core erratum: "Problems Executing the TLBR Instruction"
218 */
219#ifndef MIPS34K_MISSED_ITLB_WAR
220#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
221#endif
222
223#endif /* _ASM_WAR_H */