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1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36/* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
38 */
39
40/**
41 * DOC: uevents generated by i915 on it's device node
42 *
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
49 *
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
56 *
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * the GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
60 */
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65/*
66 * i915_user_extension: Base class for defining a chain of extensions
67 *
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
73 *
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
79 */
80struct i915_user_extension {
81 __u64 next_extension;
82 __u32 name;
83 __u32 flags; /* All undefined bits must be zero. */
84 __u32 rsvd[4]; /* Reserved for future use; must be zero. */
85};
86
87/*
88 * MOCS indexes used for GPU surfaces, defining the cacheability of the
89 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
90 */
91enum i915_mocs_table_index {
92 /*
93 * Not cached anywhere, coherency between CPU and GPU accesses is
94 * guaranteed.
95 */
96 I915_MOCS_UNCACHED,
97 /*
98 * Cacheability and coherency controlled by the kernel automatically
99 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
100 * usage of the surface (used for display scanout or not).
101 */
102 I915_MOCS_PTE,
103 /*
104 * Cached in all GPU caches available on the platform.
105 * Coherency between CPU and GPU accesses to the surface is not
106 * guaranteed without extra synchronization.
107 */
108 I915_MOCS_CACHED,
109};
110
111/*
112 * Different engines serve different roles, and there may be more than one
113 * engine serving each role. enum drm_i915_gem_engine_class provides a
114 * classification of the role of the engine, which may be used when requesting
115 * operations to be performed on a certain subset of engines, or for providing
116 * information about that group.
117 */
118enum drm_i915_gem_engine_class {
119 I915_ENGINE_CLASS_RENDER = 0,
120 I915_ENGINE_CLASS_COPY = 1,
121 I915_ENGINE_CLASS_VIDEO = 2,
122 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
123
124 /* should be kept compact */
125
126 I915_ENGINE_CLASS_INVALID = -1
127};
128
129/*
130 * There may be more than one engine fulfilling any role within the system.
131 * Each engine of a class is given a unique instance number and therefore
132 * any engine can be specified by its class:instance tuplet. APIs that allow
133 * access to any engine in the system will use struct i915_engine_class_instance
134 * for this identification.
135 */
136struct i915_engine_class_instance {
137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
138 __u16 engine_instance;
139#define I915_ENGINE_CLASS_INVALID_NONE -1
140#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
141};
142
143/**
144 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
145 *
146 */
147
148enum drm_i915_pmu_engine_sample {
149 I915_SAMPLE_BUSY = 0,
150 I915_SAMPLE_WAIT = 1,
151 I915_SAMPLE_SEMA = 2
152};
153
154#define I915_PMU_SAMPLE_BITS (4)
155#define I915_PMU_SAMPLE_MASK (0xf)
156#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
157#define I915_PMU_CLASS_SHIFT \
158 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
159
160#define __I915_PMU_ENGINE(class, instance, sample) \
161 ((class) << I915_PMU_CLASS_SHIFT | \
162 (instance) << I915_PMU_SAMPLE_BITS | \
163 (sample))
164
165#define I915_PMU_ENGINE_BUSY(class, instance) \
166 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
167
168#define I915_PMU_ENGINE_WAIT(class, instance) \
169 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
170
171#define I915_PMU_ENGINE_SEMA(class, instance) \
172 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
173
174#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
175
176#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
177#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
178#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
179#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
180
181#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
182
183/* Each region is a minimum of 16k, and there are at most 255 of them.
184 */
185#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
186 * of chars for next/prev indices */
187#define I915_LOG_MIN_TEX_REGION_SIZE 14
188
189typedef struct _drm_i915_init {
190 enum {
191 I915_INIT_DMA = 0x01,
192 I915_CLEANUP_DMA = 0x02,
193 I915_RESUME_DMA = 0x03
194 } func;
195 unsigned int mmio_offset;
196 int sarea_priv_offset;
197 unsigned int ring_start;
198 unsigned int ring_end;
199 unsigned int ring_size;
200 unsigned int front_offset;
201 unsigned int back_offset;
202 unsigned int depth_offset;
203 unsigned int w;
204 unsigned int h;
205 unsigned int pitch;
206 unsigned int pitch_bits;
207 unsigned int back_pitch;
208 unsigned int depth_pitch;
209 unsigned int cpp;
210 unsigned int chipset;
211} drm_i915_init_t;
212
213typedef struct _drm_i915_sarea {
214 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
215 int last_upload; /* last time texture was uploaded */
216 int last_enqueue; /* last time a buffer was enqueued */
217 int last_dispatch; /* age of the most recently dispatched buffer */
218 int ctxOwner; /* last context to upload state */
219 int texAge;
220 int pf_enabled; /* is pageflipping allowed? */
221 int pf_active;
222 int pf_current_page; /* which buffer is being displayed? */
223 int perf_boxes; /* performance boxes to be displayed */
224 int width, height; /* screen size in pixels */
225
226 drm_handle_t front_handle;
227 int front_offset;
228 int front_size;
229
230 drm_handle_t back_handle;
231 int back_offset;
232 int back_size;
233
234 drm_handle_t depth_handle;
235 int depth_offset;
236 int depth_size;
237
238 drm_handle_t tex_handle;
239 int tex_offset;
240 int tex_size;
241 int log_tex_granularity;
242 int pitch;
243 int rotation; /* 0, 90, 180 or 270 */
244 int rotated_offset;
245 int rotated_size;
246 int rotated_pitch;
247 int virtualX, virtualY;
248
249 unsigned int front_tiled;
250 unsigned int back_tiled;
251 unsigned int depth_tiled;
252 unsigned int rotated_tiled;
253 unsigned int rotated2_tiled;
254
255 int pipeA_x;
256 int pipeA_y;
257 int pipeA_w;
258 int pipeA_h;
259 int pipeB_x;
260 int pipeB_y;
261 int pipeB_w;
262 int pipeB_h;
263
264 /* fill out some space for old userspace triple buffer */
265 drm_handle_t unused_handle;
266 __u32 unused1, unused2, unused3;
267
268 /* buffer object handles for static buffers. May change
269 * over the lifetime of the client.
270 */
271 __u32 front_bo_handle;
272 __u32 back_bo_handle;
273 __u32 unused_bo_handle;
274 __u32 depth_bo_handle;
275
276} drm_i915_sarea_t;
277
278/* due to userspace building against these headers we need some compat here */
279#define planeA_x pipeA_x
280#define planeA_y pipeA_y
281#define planeA_w pipeA_w
282#define planeA_h pipeA_h
283#define planeB_x pipeB_x
284#define planeB_y pipeB_y
285#define planeB_w pipeB_w
286#define planeB_h pipeB_h
287
288/* Flags for perf_boxes
289 */
290#define I915_BOX_RING_EMPTY 0x1
291#define I915_BOX_FLIP 0x2
292#define I915_BOX_WAIT 0x4
293#define I915_BOX_TEXTURE_LOAD 0x8
294#define I915_BOX_LOST_CONTEXT 0x10
295
296/*
297 * i915 specific ioctls.
298 *
299 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
300 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
301 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
302 */
303#define DRM_I915_INIT 0x00
304#define DRM_I915_FLUSH 0x01
305#define DRM_I915_FLIP 0x02
306#define DRM_I915_BATCHBUFFER 0x03
307#define DRM_I915_IRQ_EMIT 0x04
308#define DRM_I915_IRQ_WAIT 0x05
309#define DRM_I915_GETPARAM 0x06
310#define DRM_I915_SETPARAM 0x07
311#define DRM_I915_ALLOC 0x08
312#define DRM_I915_FREE 0x09
313#define DRM_I915_INIT_HEAP 0x0a
314#define DRM_I915_CMDBUFFER 0x0b
315#define DRM_I915_DESTROY_HEAP 0x0c
316#define DRM_I915_SET_VBLANK_PIPE 0x0d
317#define DRM_I915_GET_VBLANK_PIPE 0x0e
318#define DRM_I915_VBLANK_SWAP 0x0f
319#define DRM_I915_HWS_ADDR 0x11
320#define DRM_I915_GEM_INIT 0x13
321#define DRM_I915_GEM_EXECBUFFER 0x14
322#define DRM_I915_GEM_PIN 0x15
323#define DRM_I915_GEM_UNPIN 0x16
324#define DRM_I915_GEM_BUSY 0x17
325#define DRM_I915_GEM_THROTTLE 0x18
326#define DRM_I915_GEM_ENTERVT 0x19
327#define DRM_I915_GEM_LEAVEVT 0x1a
328#define DRM_I915_GEM_CREATE 0x1b
329#define DRM_I915_GEM_PREAD 0x1c
330#define DRM_I915_GEM_PWRITE 0x1d
331#define DRM_I915_GEM_MMAP 0x1e
332#define DRM_I915_GEM_SET_DOMAIN 0x1f
333#define DRM_I915_GEM_SW_FINISH 0x20
334#define DRM_I915_GEM_SET_TILING 0x21
335#define DRM_I915_GEM_GET_TILING 0x22
336#define DRM_I915_GEM_GET_APERTURE 0x23
337#define DRM_I915_GEM_MMAP_GTT 0x24
338#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
339#define DRM_I915_GEM_MADVISE 0x26
340#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
341#define DRM_I915_OVERLAY_ATTRS 0x28
342#define DRM_I915_GEM_EXECBUFFER2 0x29
343#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
344#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
345#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
346#define DRM_I915_GEM_WAIT 0x2c
347#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
348#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
349#define DRM_I915_GEM_SET_CACHING 0x2f
350#define DRM_I915_GEM_GET_CACHING 0x30
351#define DRM_I915_REG_READ 0x31
352#define DRM_I915_GET_RESET_STATS 0x32
353#define DRM_I915_GEM_USERPTR 0x33
354#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
355#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
356#define DRM_I915_PERF_OPEN 0x36
357#define DRM_I915_PERF_ADD_CONFIG 0x37
358#define DRM_I915_PERF_REMOVE_CONFIG 0x38
359#define DRM_I915_QUERY 0x39
360#define DRM_I915_GEM_VM_CREATE 0x3a
361#define DRM_I915_GEM_VM_DESTROY 0x3b
362/* Must be kept compact -- no holes */
363
364#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
365#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
366#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
367#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
368#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
369#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
370#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
371#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
372#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
373#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
374#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
375#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
376#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
377#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
378#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
379#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
380#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
381#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
382#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
383#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
384#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
385#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
386#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
387#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
388#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
389#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
390#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
391#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
392#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
393#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
394#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
395#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
396#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
397#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
398#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
399#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
400#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
401#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
402#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
403#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
404#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
405#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
406#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
407#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
408#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
409#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
410#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
411#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
412#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
413#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
414#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
415#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
416#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
417#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
418#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
419#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
420#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
421#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
422#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
423#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
424
425/* Allow drivers to submit batchbuffers directly to hardware, relying
426 * on the security mechanisms provided by hardware.
427 */
428typedef struct drm_i915_batchbuffer {
429 int start; /* agp offset */
430 int used; /* nr bytes in use */
431 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
432 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
433 int num_cliprects; /* mulitpass with multiple cliprects? */
434 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
435} drm_i915_batchbuffer_t;
436
437/* As above, but pass a pointer to userspace buffer which can be
438 * validated by the kernel prior to sending to hardware.
439 */
440typedef struct _drm_i915_cmdbuffer {
441 char __user *buf; /* pointer to userspace command buffer */
442 int sz; /* nr bytes in buf */
443 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
444 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
445 int num_cliprects; /* mulitpass with multiple cliprects? */
446 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
447} drm_i915_cmdbuffer_t;
448
449/* Userspace can request & wait on irq's:
450 */
451typedef struct drm_i915_irq_emit {
452 int __user *irq_seq;
453} drm_i915_irq_emit_t;
454
455typedef struct drm_i915_irq_wait {
456 int irq_seq;
457} drm_i915_irq_wait_t;
458
459/*
460 * Different modes of per-process Graphics Translation Table,
461 * see I915_PARAM_HAS_ALIASING_PPGTT
462 */
463#define I915_GEM_PPGTT_NONE 0
464#define I915_GEM_PPGTT_ALIASING 1
465#define I915_GEM_PPGTT_FULL 2
466
467/* Ioctl to query kernel params:
468 */
469#define I915_PARAM_IRQ_ACTIVE 1
470#define I915_PARAM_ALLOW_BATCHBUFFER 2
471#define I915_PARAM_LAST_DISPATCH 3
472#define I915_PARAM_CHIPSET_ID 4
473#define I915_PARAM_HAS_GEM 5
474#define I915_PARAM_NUM_FENCES_AVAIL 6
475#define I915_PARAM_HAS_OVERLAY 7
476#define I915_PARAM_HAS_PAGEFLIPPING 8
477#define I915_PARAM_HAS_EXECBUF2 9
478#define I915_PARAM_HAS_BSD 10
479#define I915_PARAM_HAS_BLT 11
480#define I915_PARAM_HAS_RELAXED_FENCING 12
481#define I915_PARAM_HAS_COHERENT_RINGS 13
482#define I915_PARAM_HAS_EXEC_CONSTANTS 14
483#define I915_PARAM_HAS_RELAXED_DELTA 15
484#define I915_PARAM_HAS_GEN7_SOL_RESET 16
485#define I915_PARAM_HAS_LLC 17
486#define I915_PARAM_HAS_ALIASING_PPGTT 18
487#define I915_PARAM_HAS_WAIT_TIMEOUT 19
488#define I915_PARAM_HAS_SEMAPHORES 20
489#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
490#define I915_PARAM_HAS_VEBOX 22
491#define I915_PARAM_HAS_SECURE_BATCHES 23
492#define I915_PARAM_HAS_PINNED_BATCHES 24
493#define I915_PARAM_HAS_EXEC_NO_RELOC 25
494#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
495#define I915_PARAM_HAS_WT 27
496#define I915_PARAM_CMD_PARSER_VERSION 28
497#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
498#define I915_PARAM_MMAP_VERSION 30
499#define I915_PARAM_HAS_BSD2 31
500#define I915_PARAM_REVISION 32
501#define I915_PARAM_SUBSLICE_TOTAL 33
502#define I915_PARAM_EU_TOTAL 34
503#define I915_PARAM_HAS_GPU_RESET 35
504#define I915_PARAM_HAS_RESOURCE_STREAMER 36
505#define I915_PARAM_HAS_EXEC_SOFTPIN 37
506#define I915_PARAM_HAS_POOLED_EU 38
507#define I915_PARAM_MIN_EU_IN_POOL 39
508#define I915_PARAM_MMAP_GTT_VERSION 40
509
510/*
511 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
512 * priorities and the driver will attempt to execute batches in priority order.
513 * The param returns a capability bitmask, nonzero implies that the scheduler
514 * is enabled, with different features present according to the mask.
515 *
516 * The initial priority for each batch is supplied by the context and is
517 * controlled via I915_CONTEXT_PARAM_PRIORITY.
518 */
519#define I915_PARAM_HAS_SCHEDULER 41
520#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
521#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
522#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
523#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
524#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
525
526#define I915_PARAM_HUC_STATUS 42
527
528/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
529 * synchronisation with implicit fencing on individual objects.
530 * See EXEC_OBJECT_ASYNC.
531 */
532#define I915_PARAM_HAS_EXEC_ASYNC 43
533
534/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
535 * both being able to pass in a sync_file fd to wait upon before executing,
536 * and being able to return a new sync_file fd that is signaled when the
537 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
538 */
539#define I915_PARAM_HAS_EXEC_FENCE 44
540
541/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
542 * user specified bufffers for post-mortem debugging of GPU hangs. See
543 * EXEC_OBJECT_CAPTURE.
544 */
545#define I915_PARAM_HAS_EXEC_CAPTURE 45
546
547#define I915_PARAM_SLICE_MASK 46
548
549/* Assuming it's uniform for each slice, this queries the mask of subslices
550 * per-slice for this system.
551 */
552#define I915_PARAM_SUBSLICE_MASK 47
553
554/*
555 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
556 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
557 */
558#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
559
560/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
561 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
562 */
563#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
564
565/*
566 * Query whether every context (both per-file default and user created) is
567 * isolated (insofar as HW supports). If this parameter is not true, then
568 * freshly created contexts may inherit values from an existing context,
569 * rather than default HW values. If true, it also ensures (insofar as HW
570 * supports) that all state set by this context will not leak to any other
571 * context.
572 *
573 * As not every engine across every gen support contexts, the returned
574 * value reports the support of context isolation for individual engines by
575 * returning a bitmask of each engine class set to true if that class supports
576 * isolation.
577 */
578#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
579
580/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
581 * registers. This used to be fixed per platform but from CNL onwards, this
582 * might vary depending on the parts.
583 */
584#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
585
586/*
587 * Once upon a time we supposed that writes through the GGTT would be
588 * immediately in physical memory (once flushed out of the CPU path). However,
589 * on a few different processors and chipsets, this is not necessarily the case
590 * as the writes appear to be buffered internally. Thus a read of the backing
591 * storage (physical memory) via a different path (with different physical tags
592 * to the indirect write via the GGTT) will see stale values from before
593 * the GGTT write. Inside the kernel, we can for the most part keep track of
594 * the different read/write domains in use (e.g. set-domain), but the assumption
595 * of coherency is baked into the ABI, hence reporting its true state in this
596 * parameter.
597 *
598 * Reports true when writes via mmap_gtt are immediately visible following an
599 * lfence to flush the WCB.
600 *
601 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
602 * internal buffer and are _not_ immediately visible to third parties accessing
603 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
604 * communications channel when reporting false is strongly disadvised.
605 */
606#define I915_PARAM_MMAP_GTT_COHERENT 52
607
608/*
609 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
610 * execution through use of explicit fence support.
611 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
612 */
613#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
614/* Must be kept compact -- no holes and well documented */
615
616typedef struct drm_i915_getparam {
617 __s32 param;
618 /*
619 * WARNING: Using pointers instead of fixed-size u64 means we need to write
620 * compat32 code. Don't repeat this mistake.
621 */
622 int __user *value;
623} drm_i915_getparam_t;
624
625/* Ioctl to set kernel params:
626 */
627#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
628#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
629#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
630#define I915_SETPARAM_NUM_USED_FENCES 4
631/* Must be kept compact -- no holes */
632
633typedef struct drm_i915_setparam {
634 int param;
635 int value;
636} drm_i915_setparam_t;
637
638/* A memory manager for regions of shared memory:
639 */
640#define I915_MEM_REGION_AGP 1
641
642typedef struct drm_i915_mem_alloc {
643 int region;
644 int alignment;
645 int size;
646 int __user *region_offset; /* offset from start of fb or agp */
647} drm_i915_mem_alloc_t;
648
649typedef struct drm_i915_mem_free {
650 int region;
651 int region_offset;
652} drm_i915_mem_free_t;
653
654typedef struct drm_i915_mem_init_heap {
655 int region;
656 int size;
657 int start;
658} drm_i915_mem_init_heap_t;
659
660/* Allow memory manager to be torn down and re-initialized (eg on
661 * rotate):
662 */
663typedef struct drm_i915_mem_destroy_heap {
664 int region;
665} drm_i915_mem_destroy_heap_t;
666
667/* Allow X server to configure which pipes to monitor for vblank signals
668 */
669#define DRM_I915_VBLANK_PIPE_A 1
670#define DRM_I915_VBLANK_PIPE_B 2
671
672typedef struct drm_i915_vblank_pipe {
673 int pipe;
674} drm_i915_vblank_pipe_t;
675
676/* Schedule buffer swap at given vertical blank:
677 */
678typedef struct drm_i915_vblank_swap {
679 drm_drawable_t drawable;
680 enum drm_vblank_seq_type seqtype;
681 unsigned int sequence;
682} drm_i915_vblank_swap_t;
683
684typedef struct drm_i915_hws_addr {
685 __u64 addr;
686} drm_i915_hws_addr_t;
687
688struct drm_i915_gem_init {
689 /**
690 * Beginning offset in the GTT to be managed by the DRM memory
691 * manager.
692 */
693 __u64 gtt_start;
694 /**
695 * Ending offset in the GTT to be managed by the DRM memory
696 * manager.
697 */
698 __u64 gtt_end;
699};
700
701struct drm_i915_gem_create {
702 /**
703 * Requested size for the object.
704 *
705 * The (page-aligned) allocated size for the object will be returned.
706 */
707 __u64 size;
708 /**
709 * Returned handle for the object.
710 *
711 * Object handles are nonzero.
712 */
713 __u32 handle;
714 __u32 pad;
715};
716
717struct drm_i915_gem_pread {
718 /** Handle for the object being read. */
719 __u32 handle;
720 __u32 pad;
721 /** Offset into the object to read from */
722 __u64 offset;
723 /** Length of data to read */
724 __u64 size;
725 /**
726 * Pointer to write the data into.
727 *
728 * This is a fixed-size type for 32/64 compatibility.
729 */
730 __u64 data_ptr;
731};
732
733struct drm_i915_gem_pwrite {
734 /** Handle for the object being written to. */
735 __u32 handle;
736 __u32 pad;
737 /** Offset into the object to write to */
738 __u64 offset;
739 /** Length of data to write */
740 __u64 size;
741 /**
742 * Pointer to read the data from.
743 *
744 * This is a fixed-size type for 32/64 compatibility.
745 */
746 __u64 data_ptr;
747};
748
749struct drm_i915_gem_mmap {
750 /** Handle for the object being mapped. */
751 __u32 handle;
752 __u32 pad;
753 /** Offset in the object to map. */
754 __u64 offset;
755 /**
756 * Length of data to map.
757 *
758 * The value will be page-aligned.
759 */
760 __u64 size;
761 /**
762 * Returned pointer the data was mapped at.
763 *
764 * This is a fixed-size type for 32/64 compatibility.
765 */
766 __u64 addr_ptr;
767
768 /**
769 * Flags for extended behaviour.
770 *
771 * Added in version 2.
772 */
773 __u64 flags;
774#define I915_MMAP_WC 0x1
775};
776
777struct drm_i915_gem_mmap_gtt {
778 /** Handle for the object being mapped. */
779 __u32 handle;
780 __u32 pad;
781 /**
782 * Fake offset to use for subsequent mmap call
783 *
784 * This is a fixed-size type for 32/64 compatibility.
785 */
786 __u64 offset;
787};
788
789struct drm_i915_gem_set_domain {
790 /** Handle for the object */
791 __u32 handle;
792
793 /** New read domains */
794 __u32 read_domains;
795
796 /** New write domain */
797 __u32 write_domain;
798};
799
800struct drm_i915_gem_sw_finish {
801 /** Handle for the object */
802 __u32 handle;
803};
804
805struct drm_i915_gem_relocation_entry {
806 /**
807 * Handle of the buffer being pointed to by this relocation entry.
808 *
809 * It's appealing to make this be an index into the mm_validate_entry
810 * list to refer to the buffer, but this allows the driver to create
811 * a relocation list for state buffers and not re-write it per
812 * exec using the buffer.
813 */
814 __u32 target_handle;
815
816 /**
817 * Value to be added to the offset of the target buffer to make up
818 * the relocation entry.
819 */
820 __u32 delta;
821
822 /** Offset in the buffer the relocation entry will be written into */
823 __u64 offset;
824
825 /**
826 * Offset value of the target buffer that the relocation entry was last
827 * written as.
828 *
829 * If the buffer has the same offset as last time, we can skip syncing
830 * and writing the relocation. This value is written back out by
831 * the execbuffer ioctl when the relocation is written.
832 */
833 __u64 presumed_offset;
834
835 /**
836 * Target memory domains read by this operation.
837 */
838 __u32 read_domains;
839
840 /**
841 * Target memory domains written by this operation.
842 *
843 * Note that only one domain may be written by the whole
844 * execbuffer operation, so that where there are conflicts,
845 * the application will get -EINVAL back.
846 */
847 __u32 write_domain;
848};
849
850/** @{
851 * Intel memory domains
852 *
853 * Most of these just align with the various caches in
854 * the system and are used to flush and invalidate as
855 * objects end up cached in different domains.
856 */
857/** CPU cache */
858#define I915_GEM_DOMAIN_CPU 0x00000001
859/** Render cache, used by 2D and 3D drawing */
860#define I915_GEM_DOMAIN_RENDER 0x00000002
861/** Sampler cache, used by texture engine */
862#define I915_GEM_DOMAIN_SAMPLER 0x00000004
863/** Command queue, used to load batch buffers */
864#define I915_GEM_DOMAIN_COMMAND 0x00000008
865/** Instruction cache, used by shader programs */
866#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
867/** Vertex address cache */
868#define I915_GEM_DOMAIN_VERTEX 0x00000020
869/** GTT domain - aperture and scanout */
870#define I915_GEM_DOMAIN_GTT 0x00000040
871/** WC domain - uncached access */
872#define I915_GEM_DOMAIN_WC 0x00000080
873/** @} */
874
875struct drm_i915_gem_exec_object {
876 /**
877 * User's handle for a buffer to be bound into the GTT for this
878 * operation.
879 */
880 __u32 handle;
881
882 /** Number of relocations to be performed on this buffer */
883 __u32 relocation_count;
884 /**
885 * Pointer to array of struct drm_i915_gem_relocation_entry containing
886 * the relocations to be performed in this buffer.
887 */
888 __u64 relocs_ptr;
889
890 /** Required alignment in graphics aperture */
891 __u64 alignment;
892
893 /**
894 * Returned value of the updated offset of the object, for future
895 * presumed_offset writes.
896 */
897 __u64 offset;
898};
899
900struct drm_i915_gem_execbuffer {
901 /**
902 * List of buffers to be validated with their relocations to be
903 * performend on them.
904 *
905 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
906 *
907 * These buffers must be listed in an order such that all relocations
908 * a buffer is performing refer to buffers that have already appeared
909 * in the validate list.
910 */
911 __u64 buffers_ptr;
912 __u32 buffer_count;
913
914 /** Offset in the batchbuffer to start execution from. */
915 __u32 batch_start_offset;
916 /** Bytes used in batchbuffer from batch_start_offset */
917 __u32 batch_len;
918 __u32 DR1;
919 __u32 DR4;
920 __u32 num_cliprects;
921 /** This is a struct drm_clip_rect *cliprects */
922 __u64 cliprects_ptr;
923};
924
925struct drm_i915_gem_exec_object2 {
926 /**
927 * User's handle for a buffer to be bound into the GTT for this
928 * operation.
929 */
930 __u32 handle;
931
932 /** Number of relocations to be performed on this buffer */
933 __u32 relocation_count;
934 /**
935 * Pointer to array of struct drm_i915_gem_relocation_entry containing
936 * the relocations to be performed in this buffer.
937 */
938 __u64 relocs_ptr;
939
940 /** Required alignment in graphics aperture */
941 __u64 alignment;
942
943 /**
944 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
945 * the user with the GTT offset at which this object will be pinned.
946 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
947 * presumed_offset of the object.
948 * During execbuffer2 the kernel populates it with the value of the
949 * current GTT offset of the object, for future presumed_offset writes.
950 */
951 __u64 offset;
952
953#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
954#define EXEC_OBJECT_NEEDS_GTT (1<<1)
955#define EXEC_OBJECT_WRITE (1<<2)
956#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
957#define EXEC_OBJECT_PINNED (1<<4)
958#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
959/* The kernel implicitly tracks GPU activity on all GEM objects, and
960 * synchronises operations with outstanding rendering. This includes
961 * rendering on other devices if exported via dma-buf. However, sometimes
962 * this tracking is too coarse and the user knows better. For example,
963 * if the object is split into non-overlapping ranges shared between different
964 * clients or engines (i.e. suballocating objects), the implicit tracking
965 * by kernel assumes that each operation affects the whole object rather
966 * than an individual range, causing needless synchronisation between clients.
967 * The kernel will also forgo any CPU cache flushes prior to rendering from
968 * the object as the client is expected to be also handling such domain
969 * tracking.
970 *
971 * The kernel maintains the implicit tracking in order to manage resources
972 * used by the GPU - this flag only disables the synchronisation prior to
973 * rendering with this object in this execbuf.
974 *
975 * Opting out of implicit synhronisation requires the user to do its own
976 * explicit tracking to avoid rendering corruption. See, for example,
977 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
978 */
979#define EXEC_OBJECT_ASYNC (1<<6)
980/* Request that the contents of this execobject be copied into the error
981 * state upon a GPU hang involving this batch for post-mortem debugging.
982 * These buffers are recorded in no particular order as "user" in
983 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
984 * if the kernel supports this flag.
985 */
986#define EXEC_OBJECT_CAPTURE (1<<7)
987/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
988#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
989 __u64 flags;
990
991 union {
992 __u64 rsvd1;
993 __u64 pad_to_size;
994 };
995 __u64 rsvd2;
996};
997
998struct drm_i915_gem_exec_fence {
999 /**
1000 * User's handle for a drm_syncobj to wait on or signal.
1001 */
1002 __u32 handle;
1003
1004#define I915_EXEC_FENCE_WAIT (1<<0)
1005#define I915_EXEC_FENCE_SIGNAL (1<<1)
1006#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1007 __u32 flags;
1008};
1009
1010struct drm_i915_gem_execbuffer2 {
1011 /**
1012 * List of gem_exec_object2 structs
1013 */
1014 __u64 buffers_ptr;
1015 __u32 buffer_count;
1016
1017 /** Offset in the batchbuffer to start execution from. */
1018 __u32 batch_start_offset;
1019 /** Bytes used in batchbuffer from batch_start_offset */
1020 __u32 batch_len;
1021 __u32 DR1;
1022 __u32 DR4;
1023 __u32 num_cliprects;
1024 /**
1025 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1026 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
1027 * struct drm_i915_gem_exec_fence *fences.
1028 */
1029 __u64 cliprects_ptr;
1030#define I915_EXEC_RING_MASK (0x3f)
1031#define I915_EXEC_DEFAULT (0<<0)
1032#define I915_EXEC_RENDER (1<<0)
1033#define I915_EXEC_BSD (2<<0)
1034#define I915_EXEC_BLT (3<<0)
1035#define I915_EXEC_VEBOX (4<<0)
1036
1037/* Used for switching the constants addressing mode on gen4+ RENDER ring.
1038 * Gen6+ only supports relative addressing to dynamic state (default) and
1039 * absolute addressing.
1040 *
1041 * These flags are ignored for the BSD and BLT rings.
1042 */
1043#define I915_EXEC_CONSTANTS_MASK (3<<6)
1044#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1045#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1046#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1047 __u64 flags;
1048 __u64 rsvd1; /* now used for context info */
1049 __u64 rsvd2;
1050};
1051
1052/** Resets the SO write offset registers for transform feedback on gen7. */
1053#define I915_EXEC_GEN7_SOL_RESET (1<<8)
1054
1055/** Request a privileged ("secure") batch buffer. Note only available for
1056 * DRM_ROOT_ONLY | DRM_MASTER processes.
1057 */
1058#define I915_EXEC_SECURE (1<<9)
1059
1060/** Inform the kernel that the batch is and will always be pinned. This
1061 * negates the requirement for a workaround to be performed to avoid
1062 * an incoherent CS (such as can be found on 830/845). If this flag is
1063 * not passed, the kernel will endeavour to make sure the batch is
1064 * coherent with the CS before execution. If this flag is passed,
1065 * userspace assumes the responsibility for ensuring the same.
1066 */
1067#define I915_EXEC_IS_PINNED (1<<10)
1068
1069/** Provide a hint to the kernel that the command stream and auxiliary
1070 * state buffers already holds the correct presumed addresses and so the
1071 * relocation process may be skipped if no buffers need to be moved in
1072 * preparation for the execbuffer.
1073 */
1074#define I915_EXEC_NO_RELOC (1<<11)
1075
1076/** Use the reloc.handle as an index into the exec object array rather
1077 * than as the per-file handle.
1078 */
1079#define I915_EXEC_HANDLE_LUT (1<<12)
1080
1081/** Used for switching BSD rings on the platforms with two BSD rings */
1082#define I915_EXEC_BSD_SHIFT (13)
1083#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1084/* default ping-pong mode */
1085#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1086#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1087#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1088
1089/** Tell the kernel that the batchbuffer is processed by
1090 * the resource streamer.
1091 */
1092#define I915_EXEC_RESOURCE_STREAMER (1<<15)
1093
1094/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1095 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1096 * the batch.
1097 *
1098 * Returns -EINVAL if the sync_file fd cannot be found.
1099 */
1100#define I915_EXEC_FENCE_IN (1<<16)
1101
1102/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1103 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1104 * to the caller, and it should be close() after use. (The fd is a regular
1105 * file descriptor and will be cleaned up on process termination. It holds
1106 * a reference to the request, but nothing else.)
1107 *
1108 * The sync_file fd can be combined with other sync_file and passed either
1109 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1110 * will only occur after this request completes), or to other devices.
1111 *
1112 * Using I915_EXEC_FENCE_OUT requires use of
1113 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1114 * back to userspace. Failure to do so will cause the out-fence to always
1115 * be reported as zero, and the real fence fd to be leaked.
1116 */
1117#define I915_EXEC_FENCE_OUT (1<<17)
1118
1119/*
1120 * Traditionally the execbuf ioctl has only considered the final element in
1121 * the execobject[] to be the executable batch. Often though, the client
1122 * will known the batch object prior to construction and being able to place
1123 * it into the execobject[] array first can simplify the relocation tracking.
1124 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1125 * execobject[] as the * batch instead (the default is to use the last
1126 * element).
1127 */
1128#define I915_EXEC_BATCH_FIRST (1<<18)
1129
1130/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1131 * define an array of i915_gem_exec_fence structures which specify a set of
1132 * dma fences to wait upon or signal.
1133 */
1134#define I915_EXEC_FENCE_ARRAY (1<<19)
1135
1136/*
1137 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1138 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1139 * the batch.
1140 *
1141 * Returns -EINVAL if the sync_file fd cannot be found.
1142 */
1143#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1144
1145#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
1146
1147#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1148#define i915_execbuffer2_set_context_id(eb2, context) \
1149 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1150#define i915_execbuffer2_get_context_id(eb2) \
1151 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1152
1153struct drm_i915_gem_pin {
1154 /** Handle of the buffer to be pinned. */
1155 __u32 handle;
1156 __u32 pad;
1157
1158 /** alignment required within the aperture */
1159 __u64 alignment;
1160
1161 /** Returned GTT offset of the buffer. */
1162 __u64 offset;
1163};
1164
1165struct drm_i915_gem_unpin {
1166 /** Handle of the buffer to be unpinned. */
1167 __u32 handle;
1168 __u32 pad;
1169};
1170
1171struct drm_i915_gem_busy {
1172 /** Handle of the buffer to check for busy */
1173 __u32 handle;
1174
1175 /** Return busy status
1176 *
1177 * A return of 0 implies that the object is idle (after
1178 * having flushed any pending activity), and a non-zero return that
1179 * the object is still in-flight on the GPU. (The GPU has not yet
1180 * signaled completion for all pending requests that reference the
1181 * object.) An object is guaranteed to become idle eventually (so
1182 * long as no new GPU commands are executed upon it). Due to the
1183 * asynchronous nature of the hardware, an object reported
1184 * as busy may become idle before the ioctl is completed.
1185 *
1186 * Furthermore, if the object is busy, which engine is busy is only
1187 * provided as a guide and only indirectly by reporting its class
1188 * (there may be more than one engine in each class). There are race
1189 * conditions which prevent the report of which engines are busy from
1190 * being always accurate. However, the converse is not true. If the
1191 * object is idle, the result of the ioctl, that all engines are idle,
1192 * is accurate.
1193 *
1194 * The returned dword is split into two fields to indicate both
1195 * the engine classess on which the object is being read, and the
1196 * engine class on which it is currently being written (if any).
1197 *
1198 * The low word (bits 0:15) indicate if the object is being written
1199 * to by any engine (there can only be one, as the GEM implicit
1200 * synchronisation rules force writes to be serialised). Only the
1201 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1202 * 1 not 0 etc) for the last write is reported.
1203 *
1204 * The high word (bits 16:31) are a bitmask of which engines classes
1205 * are currently reading from the object. Multiple engines may be
1206 * reading from the object simultaneously.
1207 *
1208 * The value of each engine class is the same as specified in the
1209 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1210 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1211 * reported as active itself. Some hardware may have parallel
1212 * execution engines, e.g. multiple media engines, which are
1213 * mapped to the same class identifier and so are not separately
1214 * reported for busyness.
1215 *
1216 * Caveat emptor:
1217 * Only the boolean result of this query is reliable; that is whether
1218 * the object is idle or busy. The report of which engines are busy
1219 * should be only used as a heuristic.
1220 */
1221 __u32 busy;
1222};
1223
1224/**
1225 * I915_CACHING_NONE
1226 *
1227 * GPU access is not coherent with cpu caches. Default for machines without an
1228 * LLC.
1229 */
1230#define I915_CACHING_NONE 0
1231/**
1232 * I915_CACHING_CACHED
1233 *
1234 * GPU access is coherent with cpu caches and furthermore the data is cached in
1235 * last-level caches shared between cpu cores and the gpu GT. Default on
1236 * machines with HAS_LLC.
1237 */
1238#define I915_CACHING_CACHED 1
1239/**
1240 * I915_CACHING_DISPLAY
1241 *
1242 * Special GPU caching mode which is coherent with the scanout engines.
1243 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1244 * cache mode (like write-through or gfdt flushing) is available. The kernel
1245 * automatically sets this mode when using a buffer as a scanout target.
1246 * Userspace can manually set this mode to avoid a costly stall and clflush in
1247 * the hotpath of drawing the first frame.
1248 */
1249#define I915_CACHING_DISPLAY 2
1250
1251struct drm_i915_gem_caching {
1252 /**
1253 * Handle of the buffer to set/get the caching level of. */
1254 __u32 handle;
1255
1256 /**
1257 * Cacheing level to apply or return value
1258 *
1259 * bits0-15 are for generic caching control (i.e. the above defined
1260 * values). bits16-31 are reserved for platform-specific variations
1261 * (e.g. l3$ caching on gen7). */
1262 __u32 caching;
1263};
1264
1265#define I915_TILING_NONE 0
1266#define I915_TILING_X 1
1267#define I915_TILING_Y 2
1268#define I915_TILING_LAST I915_TILING_Y
1269
1270#define I915_BIT_6_SWIZZLE_NONE 0
1271#define I915_BIT_6_SWIZZLE_9 1
1272#define I915_BIT_6_SWIZZLE_9_10 2
1273#define I915_BIT_6_SWIZZLE_9_11 3
1274#define I915_BIT_6_SWIZZLE_9_10_11 4
1275/* Not seen by userland */
1276#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1277/* Seen by userland. */
1278#define I915_BIT_6_SWIZZLE_9_17 6
1279#define I915_BIT_6_SWIZZLE_9_10_17 7
1280
1281struct drm_i915_gem_set_tiling {
1282 /** Handle of the buffer to have its tiling state updated */
1283 __u32 handle;
1284
1285 /**
1286 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1287 * I915_TILING_Y).
1288 *
1289 * This value is to be set on request, and will be updated by the
1290 * kernel on successful return with the actual chosen tiling layout.
1291 *
1292 * The tiling mode may be demoted to I915_TILING_NONE when the system
1293 * has bit 6 swizzling that can't be managed correctly by GEM.
1294 *
1295 * Buffer contents become undefined when changing tiling_mode.
1296 */
1297 __u32 tiling_mode;
1298
1299 /**
1300 * Stride in bytes for the object when in I915_TILING_X or
1301 * I915_TILING_Y.
1302 */
1303 __u32 stride;
1304
1305 /**
1306 * Returned address bit 6 swizzling required for CPU access through
1307 * mmap mapping.
1308 */
1309 __u32 swizzle_mode;
1310};
1311
1312struct drm_i915_gem_get_tiling {
1313 /** Handle of the buffer to get tiling state for. */
1314 __u32 handle;
1315
1316 /**
1317 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1318 * I915_TILING_Y).
1319 */
1320 __u32 tiling_mode;
1321
1322 /**
1323 * Returned address bit 6 swizzling required for CPU access through
1324 * mmap mapping.
1325 */
1326 __u32 swizzle_mode;
1327
1328 /**
1329 * Returned address bit 6 swizzling required for CPU access through
1330 * mmap mapping whilst bound.
1331 */
1332 __u32 phys_swizzle_mode;
1333};
1334
1335struct drm_i915_gem_get_aperture {
1336 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1337 __u64 aper_size;
1338
1339 /**
1340 * Available space in the aperture used by i915_gem_execbuffer, in
1341 * bytes
1342 */
1343 __u64 aper_available_size;
1344};
1345
1346struct drm_i915_get_pipe_from_crtc_id {
1347 /** ID of CRTC being requested **/
1348 __u32 crtc_id;
1349
1350 /** pipe of requested CRTC **/
1351 __u32 pipe;
1352};
1353
1354#define I915_MADV_WILLNEED 0
1355#define I915_MADV_DONTNEED 1
1356#define __I915_MADV_PURGED 2 /* internal state */
1357
1358struct drm_i915_gem_madvise {
1359 /** Handle of the buffer to change the backing store advice */
1360 __u32 handle;
1361
1362 /* Advice: either the buffer will be needed again in the near future,
1363 * or wont be and could be discarded under memory pressure.
1364 */
1365 __u32 madv;
1366
1367 /** Whether the backing store still exists. */
1368 __u32 retained;
1369};
1370
1371/* flags */
1372#define I915_OVERLAY_TYPE_MASK 0xff
1373#define I915_OVERLAY_YUV_PLANAR 0x01
1374#define I915_OVERLAY_YUV_PACKED 0x02
1375#define I915_OVERLAY_RGB 0x03
1376
1377#define I915_OVERLAY_DEPTH_MASK 0xff00
1378#define I915_OVERLAY_RGB24 0x1000
1379#define I915_OVERLAY_RGB16 0x2000
1380#define I915_OVERLAY_RGB15 0x3000
1381#define I915_OVERLAY_YUV422 0x0100
1382#define I915_OVERLAY_YUV411 0x0200
1383#define I915_OVERLAY_YUV420 0x0300
1384#define I915_OVERLAY_YUV410 0x0400
1385
1386#define I915_OVERLAY_SWAP_MASK 0xff0000
1387#define I915_OVERLAY_NO_SWAP 0x000000
1388#define I915_OVERLAY_UV_SWAP 0x010000
1389#define I915_OVERLAY_Y_SWAP 0x020000
1390#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1391
1392#define I915_OVERLAY_FLAGS_MASK 0xff000000
1393#define I915_OVERLAY_ENABLE 0x01000000
1394
1395struct drm_intel_overlay_put_image {
1396 /* various flags and src format description */
1397 __u32 flags;
1398 /* source picture description */
1399 __u32 bo_handle;
1400 /* stride values and offsets are in bytes, buffer relative */
1401 __u16 stride_Y; /* stride for packed formats */
1402 __u16 stride_UV;
1403 __u32 offset_Y; /* offset for packet formats */
1404 __u32 offset_U;
1405 __u32 offset_V;
1406 /* in pixels */
1407 __u16 src_width;
1408 __u16 src_height;
1409 /* to compensate the scaling factors for partially covered surfaces */
1410 __u16 src_scan_width;
1411 __u16 src_scan_height;
1412 /* output crtc description */
1413 __u32 crtc_id;
1414 __u16 dst_x;
1415 __u16 dst_y;
1416 __u16 dst_width;
1417 __u16 dst_height;
1418};
1419
1420/* flags */
1421#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1422#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1423#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1424struct drm_intel_overlay_attrs {
1425 __u32 flags;
1426 __u32 color_key;
1427 __s32 brightness;
1428 __u32 contrast;
1429 __u32 saturation;
1430 __u32 gamma0;
1431 __u32 gamma1;
1432 __u32 gamma2;
1433 __u32 gamma3;
1434 __u32 gamma4;
1435 __u32 gamma5;
1436};
1437
1438/*
1439 * Intel sprite handling
1440 *
1441 * Color keying works with a min/mask/max tuple. Both source and destination
1442 * color keying is allowed.
1443 *
1444 * Source keying:
1445 * Sprite pixels within the min & max values, masked against the color channels
1446 * specified in the mask field, will be transparent. All other pixels will
1447 * be displayed on top of the primary plane. For RGB surfaces, only the min
1448 * and mask fields will be used; ranged compares are not allowed.
1449 *
1450 * Destination keying:
1451 * Primary plane pixels that match the min value, masked against the color
1452 * channels specified in the mask field, will be replaced by corresponding
1453 * pixels from the sprite plane.
1454 *
1455 * Note that source & destination keying are exclusive; only one can be
1456 * active on a given plane.
1457 */
1458
1459#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1460 * flags==0 to disable colorkeying.
1461 */
1462#define I915_SET_COLORKEY_DESTINATION (1<<1)
1463#define I915_SET_COLORKEY_SOURCE (1<<2)
1464struct drm_intel_sprite_colorkey {
1465 __u32 plane_id;
1466 __u32 min_value;
1467 __u32 channel_mask;
1468 __u32 max_value;
1469 __u32 flags;
1470};
1471
1472struct drm_i915_gem_wait {
1473 /** Handle of BO we shall wait on */
1474 __u32 bo_handle;
1475 __u32 flags;
1476 /** Number of nanoseconds to wait, Returns time remaining. */
1477 __s64 timeout_ns;
1478};
1479
1480struct drm_i915_gem_context_create {
1481 __u32 ctx_id; /* output: id of new context*/
1482 __u32 pad;
1483};
1484
1485struct drm_i915_gem_context_create_ext {
1486 __u32 ctx_id; /* output: id of new context*/
1487 __u32 flags;
1488#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1489#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1490#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1491 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1492 __u64 extensions;
1493};
1494
1495struct drm_i915_gem_context_param {
1496 __u32 ctx_id;
1497 __u32 size;
1498 __u64 param;
1499#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1500#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1501#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1502#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1503#define I915_CONTEXT_PARAM_BANNABLE 0x5
1504#define I915_CONTEXT_PARAM_PRIORITY 0x6
1505#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1506#define I915_CONTEXT_DEFAULT_PRIORITY 0
1507#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1508 /*
1509 * When using the following param, value should be a pointer to
1510 * drm_i915_gem_context_param_sseu.
1511 */
1512#define I915_CONTEXT_PARAM_SSEU 0x7
1513
1514/*
1515 * Not all clients may want to attempt automatic recover of a context after
1516 * a hang (for example, some clients may only submit very small incremental
1517 * batches relying on known logical state of previous batches which will never
1518 * recover correctly and each attempt will hang), and so would prefer that
1519 * the context is forever banned instead.
1520 *
1521 * If set to false (0), after a reset, subsequent (and in flight) rendering
1522 * from this context is discarded, and the client will need to create a new
1523 * context to use instead.
1524 *
1525 * If set to true (1), the kernel will automatically attempt to recover the
1526 * context by skipping the hanging batch and executing the next batch starting
1527 * from the default context state (discarding the incomplete logical context
1528 * state lost due to the reset).
1529 *
1530 * On creation, all new contexts are marked as recoverable.
1531 */
1532#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1533
1534 /*
1535 * The id of the associated virtual memory address space (ppGTT) of
1536 * this context. Can be retrieved and passed to another context
1537 * (on the same fd) for both to use the same ppGTT and so share
1538 * address layouts, and avoid reloading the page tables on context
1539 * switches between themselves.
1540 *
1541 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1542 */
1543#define I915_CONTEXT_PARAM_VM 0x9
1544
1545/*
1546 * I915_CONTEXT_PARAM_ENGINES:
1547 *
1548 * Bind this context to operate on this subset of available engines. Henceforth,
1549 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1550 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1551 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1552 * Use
1553 * engine_class: I915_ENGINE_CLASS_INVALID,
1554 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1555 * to specify a gap in the array that can be filled in later, e.g. by a
1556 * virtual engine used for load balancing.
1557 *
1558 * Setting the number of engines bound to the context to 0, by passing a zero
1559 * sized argument, will revert back to default settings.
1560 *
1561 * See struct i915_context_param_engines.
1562 *
1563 * Extensions:
1564 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1565 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1566 */
1567#define I915_CONTEXT_PARAM_ENGINES 0xa
1568/* Must be kept compact -- no holes and well documented */
1569
1570 __u64 value;
1571};
1572
1573/**
1574 * Context SSEU programming
1575 *
1576 * It may be necessary for either functional or performance reason to configure
1577 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1578 * Sub-slice/EU).
1579 *
1580 * This is done by configuring SSEU configuration using the below
1581 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1582 * userspace intends to use.
1583 *
1584 * Not all GPUs or engines support this functionality in which case an error
1585 * code -ENODEV will be returned.
1586 *
1587 * Also, flexibility of possible SSEU configuration permutations varies between
1588 * GPU generations and software imposed limitations. Requesting such a
1589 * combination will return an error code of -EINVAL.
1590 *
1591 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1592 * favour of a single global setting.
1593 */
1594struct drm_i915_gem_context_param_sseu {
1595 /*
1596 * Engine class & instance to be configured or queried.
1597 */
1598 struct i915_engine_class_instance engine;
1599
1600 /*
1601 * Unknown flags must be cleared to zero.
1602 */
1603 __u32 flags;
1604#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1605
1606 /*
1607 * Mask of slices to enable for the context. Valid values are a subset
1608 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1609 */
1610 __u64 slice_mask;
1611
1612 /*
1613 * Mask of subslices to enable for the context. Valid values are a
1614 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1615 */
1616 __u64 subslice_mask;
1617
1618 /*
1619 * Minimum/Maximum number of EUs to enable per subslice for the
1620 * context. min_eus_per_subslice must be inferior or equal to
1621 * max_eus_per_subslice.
1622 */
1623 __u16 min_eus_per_subslice;
1624 __u16 max_eus_per_subslice;
1625
1626 /*
1627 * Unused for now. Must be cleared to zero.
1628 */
1629 __u32 rsvd;
1630};
1631
1632/*
1633 * i915_context_engines_load_balance:
1634 *
1635 * Enable load balancing across this set of engines.
1636 *
1637 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1638 * used will proxy the execbuffer request onto one of the set of engines
1639 * in such a way as to distribute the load evenly across the set.
1640 *
1641 * The set of engines must be compatible (e.g. the same HW class) as they
1642 * will share the same logical GPU context and ring.
1643 *
1644 * To intermix rendering with the virtual engine and direct rendering onto
1645 * the backing engines (bypassing the load balancing proxy), the context must
1646 * be defined to use a single timeline for all engines.
1647 */
1648struct i915_context_engines_load_balance {
1649 struct i915_user_extension base;
1650
1651 __u16 engine_index;
1652 __u16 num_siblings;
1653 __u32 flags; /* all undefined flags must be zero */
1654
1655 __u64 mbz64; /* reserved for future use; must be zero */
1656
1657 struct i915_engine_class_instance engines[0];
1658} __attribute__((packed));
1659
1660#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1661 struct i915_user_extension base; \
1662 __u16 engine_index; \
1663 __u16 num_siblings; \
1664 __u32 flags; \
1665 __u64 mbz64; \
1666 struct i915_engine_class_instance engines[N__]; \
1667} __attribute__((packed)) name__
1668
1669/*
1670 * i915_context_engines_bond:
1671 *
1672 * Constructed bonded pairs for execution within a virtual engine.
1673 *
1674 * All engines are equal, but some are more equal than others. Given
1675 * the distribution of resources in the HW, it may be preferable to run
1676 * a request on a given subset of engines in parallel to a request on a
1677 * specific engine. We enable this selection of engines within a virtual
1678 * engine by specifying bonding pairs, for any given master engine we will
1679 * only execute on one of the corresponding siblings within the virtual engine.
1680 *
1681 * To execute a request in parallel on the master engine and a sibling requires
1682 * coordination with a I915_EXEC_FENCE_SUBMIT.
1683 */
1684struct i915_context_engines_bond {
1685 struct i915_user_extension base;
1686
1687 struct i915_engine_class_instance master;
1688
1689 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1690 __u16 num_bonds;
1691
1692 __u64 flags; /* all undefined flags must be zero */
1693 __u64 mbz64[4]; /* reserved for future use; must be zero */
1694
1695 struct i915_engine_class_instance engines[0];
1696} __attribute__((packed));
1697
1698#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1699 struct i915_user_extension base; \
1700 struct i915_engine_class_instance master; \
1701 __u16 virtual_index; \
1702 __u16 num_bonds; \
1703 __u64 flags; \
1704 __u64 mbz64[4]; \
1705 struct i915_engine_class_instance engines[N__]; \
1706} __attribute__((packed)) name__
1707
1708struct i915_context_param_engines {
1709 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1710#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1711#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1712 struct i915_engine_class_instance engines[0];
1713} __attribute__((packed));
1714
1715#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1716 __u64 extensions; \
1717 struct i915_engine_class_instance engines[N__]; \
1718} __attribute__((packed)) name__
1719
1720struct drm_i915_gem_context_create_ext_setparam {
1721#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1722 struct i915_user_extension base;
1723 struct drm_i915_gem_context_param param;
1724};
1725
1726struct drm_i915_gem_context_create_ext_clone {
1727#define I915_CONTEXT_CREATE_EXT_CLONE 1
1728 struct i915_user_extension base;
1729 __u32 clone_id;
1730 __u32 flags;
1731#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1732#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1733#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1734#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1735#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1736#define I915_CONTEXT_CLONE_VM (1u << 5)
1737#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1738 __u64 rsvd;
1739};
1740
1741struct drm_i915_gem_context_destroy {
1742 __u32 ctx_id;
1743 __u32 pad;
1744};
1745
1746/*
1747 * DRM_I915_GEM_VM_CREATE -
1748 *
1749 * Create a new virtual memory address space (ppGTT) for use within a context
1750 * on the same file. Extensions can be provided to configure exactly how the
1751 * address space is setup upon creation.
1752 *
1753 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1754 * returned in the outparam @id.
1755 *
1756 * No flags are defined, with all bits reserved and must be zero.
1757 *
1758 * An extension chain maybe provided, starting with @extensions, and terminated
1759 * by the @next_extension being 0. Currently, no extensions are defined.
1760 *
1761 * DRM_I915_GEM_VM_DESTROY -
1762 *
1763 * Destroys a previously created VM id, specified in @id.
1764 *
1765 * No extensions or flags are allowed currently, and so must be zero.
1766 */
1767struct drm_i915_gem_vm_control {
1768 __u64 extensions;
1769 __u32 flags;
1770 __u32 vm_id;
1771};
1772
1773struct drm_i915_reg_read {
1774 /*
1775 * Register offset.
1776 * For 64bit wide registers where the upper 32bits don't immediately
1777 * follow the lower 32bits, the offset of the lower 32bits must
1778 * be specified
1779 */
1780 __u64 offset;
1781#define I915_REG_READ_8B_WA (1ul << 0)
1782
1783 __u64 val; /* Return value */
1784};
1785
1786/* Known registers:
1787 *
1788 * Render engine timestamp - 0x2358 + 64bit - gen7+
1789 * - Note this register returns an invalid value if using the default
1790 * single instruction 8byte read, in order to workaround that pass
1791 * flag I915_REG_READ_8B_WA in offset field.
1792 *
1793 */
1794
1795struct drm_i915_reset_stats {
1796 __u32 ctx_id;
1797 __u32 flags;
1798
1799 /* All resets since boot/module reload, for all contexts */
1800 __u32 reset_count;
1801
1802 /* Number of batches lost when active in GPU, for this context */
1803 __u32 batch_active;
1804
1805 /* Number of batches lost pending for execution, for this context */
1806 __u32 batch_pending;
1807
1808 __u32 pad;
1809};
1810
1811struct drm_i915_gem_userptr {
1812 __u64 user_ptr;
1813 __u64 user_size;
1814 __u32 flags;
1815#define I915_USERPTR_READ_ONLY 0x1
1816#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1817 /**
1818 * Returned handle for the object.
1819 *
1820 * Object handles are nonzero.
1821 */
1822 __u32 handle;
1823};
1824
1825enum drm_i915_oa_format {
1826 I915_OA_FORMAT_A13 = 1, /* HSW only */
1827 I915_OA_FORMAT_A29, /* HSW only */
1828 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
1829 I915_OA_FORMAT_B4_C8, /* HSW only */
1830 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
1831 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
1832 I915_OA_FORMAT_C4_B8, /* HSW+ */
1833
1834 /* Gen8+ */
1835 I915_OA_FORMAT_A12,
1836 I915_OA_FORMAT_A12_B8_C8,
1837 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1838
1839 I915_OA_FORMAT_MAX /* non-ABI */
1840};
1841
1842enum drm_i915_perf_property_id {
1843 /**
1844 * Open the stream for a specific context handle (as used with
1845 * execbuffer2). A stream opened for a specific context this way
1846 * won't typically require root privileges.
1847 */
1848 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1849
1850 /**
1851 * A value of 1 requests the inclusion of raw OA unit reports as
1852 * part of stream samples.
1853 */
1854 DRM_I915_PERF_PROP_SAMPLE_OA,
1855
1856 /**
1857 * The value specifies which set of OA unit metrics should be
1858 * be configured, defining the contents of any OA unit reports.
1859 */
1860 DRM_I915_PERF_PROP_OA_METRICS_SET,
1861
1862 /**
1863 * The value specifies the size and layout of OA unit reports.
1864 */
1865 DRM_I915_PERF_PROP_OA_FORMAT,
1866
1867 /**
1868 * Specifying this property implicitly requests periodic OA unit
1869 * sampling and (at least on Haswell) the sampling frequency is derived
1870 * from this exponent as follows:
1871 *
1872 * 80ns * 2^(period_exponent + 1)
1873 */
1874 DRM_I915_PERF_PROP_OA_EXPONENT,
1875
1876 DRM_I915_PERF_PROP_MAX /* non-ABI */
1877};
1878
1879struct drm_i915_perf_open_param {
1880 __u32 flags;
1881#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1882#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1883#define I915_PERF_FLAG_DISABLED (1<<2)
1884
1885 /** The number of u64 (id, value) pairs */
1886 __u32 num_properties;
1887
1888 /**
1889 * Pointer to array of u64 (id, value) pairs configuring the stream
1890 * to open.
1891 */
1892 __u64 properties_ptr;
1893};
1894
1895/**
1896 * Enable data capture for a stream that was either opened in a disabled state
1897 * via I915_PERF_FLAG_DISABLED or was later disabled via
1898 * I915_PERF_IOCTL_DISABLE.
1899 *
1900 * It is intended to be cheaper to disable and enable a stream than it may be
1901 * to close and re-open a stream with the same configuration.
1902 *
1903 * It's undefined whether any pending data for the stream will be lost.
1904 */
1905#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1906
1907/**
1908 * Disable data capture for a stream.
1909 *
1910 * It is an error to try and read a stream that is disabled.
1911 */
1912#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1913
1914/**
1915 * Common to all i915 perf records
1916 */
1917struct drm_i915_perf_record_header {
1918 __u32 type;
1919 __u16 pad;
1920 __u16 size;
1921};
1922
1923enum drm_i915_perf_record_type {
1924
1925 /**
1926 * Samples are the work horse record type whose contents are extensible
1927 * and defined when opening an i915 perf stream based on the given
1928 * properties.
1929 *
1930 * Boolean properties following the naming convention
1931 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1932 * every sample.
1933 *
1934 * The order of these sample properties given by userspace has no
1935 * affect on the ordering of data within a sample. The order is
1936 * documented here.
1937 *
1938 * struct {
1939 * struct drm_i915_perf_record_header header;
1940 *
1941 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1942 * };
1943 */
1944 DRM_I915_PERF_RECORD_SAMPLE = 1,
1945
1946 /*
1947 * Indicates that one or more OA reports were not written by the
1948 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1949 * command collides with periodic sampling - which would be more likely
1950 * at higher sampling frequencies.
1951 */
1952 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1953
1954 /**
1955 * An error occurred that resulted in all pending OA reports being lost.
1956 */
1957 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1958
1959 DRM_I915_PERF_RECORD_MAX /* non-ABI */
1960};
1961
1962/**
1963 * Structure to upload perf dynamic configuration into the kernel.
1964 */
1965struct drm_i915_perf_oa_config {
1966 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
1967 char uuid[36];
1968
1969 __u32 n_mux_regs;
1970 __u32 n_boolean_regs;
1971 __u32 n_flex_regs;
1972
1973 /*
1974 * These fields are pointers to tuples of u32 values (register address,
1975 * value). For example the expected length of the buffer pointed by
1976 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
1977 */
1978 __u64 mux_regs_ptr;
1979 __u64 boolean_regs_ptr;
1980 __u64 flex_regs_ptr;
1981};
1982
1983struct drm_i915_query_item {
1984 __u64 query_id;
1985#define DRM_I915_QUERY_TOPOLOGY_INFO 1
1986#define DRM_I915_QUERY_ENGINE_INFO 2
1987/* Must be kept compact -- no holes and well documented */
1988
1989 /*
1990 * When set to zero by userspace, this is filled with the size of the
1991 * data to be written at the data_ptr pointer. The kernel sets this
1992 * value to a negative value to signal an error on a particular query
1993 * item.
1994 */
1995 __s32 length;
1996
1997 /*
1998 * Unused for now. Must be cleared to zero.
1999 */
2000 __u32 flags;
2001
2002 /*
2003 * Data will be written at the location pointed by data_ptr when the
2004 * value of length matches the length of the data to be written by the
2005 * kernel.
2006 */
2007 __u64 data_ptr;
2008};
2009
2010struct drm_i915_query {
2011 __u32 num_items;
2012
2013 /*
2014 * Unused for now. Must be cleared to zero.
2015 */
2016 __u32 flags;
2017
2018 /*
2019 * This points to an array of num_items drm_i915_query_item structures.
2020 */
2021 __u64 items_ptr;
2022};
2023
2024/*
2025 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2026 *
2027 * data: contains the 3 pieces of information :
2028 *
2029 * - the slice mask with one bit per slice telling whether a slice is
2030 * available. The availability of slice X can be queried with the following
2031 * formula :
2032 *
2033 * (data[X / 8] >> (X % 8)) & 1
2034 *
2035 * - the subslice mask for each slice with one bit per subslice telling
2036 * whether a subslice is available. The availability of subslice Y in slice
2037 * X can be queried with the following formula :
2038 *
2039 * (data[subslice_offset +
2040 * X * subslice_stride +
2041 * Y / 8] >> (Y % 8)) & 1
2042 *
2043 * - the EU mask for each subslice in each slice with one bit per EU telling
2044 * whether an EU is available. The availability of EU Z in subslice Y in
2045 * slice X can be queried with the following formula :
2046 *
2047 * (data[eu_offset +
2048 * (X * max_subslices + Y) * eu_stride +
2049 * Z / 8] >> (Z % 8)) & 1
2050 */
2051struct drm_i915_query_topology_info {
2052 /*
2053 * Unused for now. Must be cleared to zero.
2054 */
2055 __u16 flags;
2056
2057 __u16 max_slices;
2058 __u16 max_subslices;
2059 __u16 max_eus_per_subslice;
2060
2061 /*
2062 * Offset in data[] at which the subslice masks are stored.
2063 */
2064 __u16 subslice_offset;
2065
2066 /*
2067 * Stride at which each of the subslice masks for each slice are
2068 * stored.
2069 */
2070 __u16 subslice_stride;
2071
2072 /*
2073 * Offset in data[] at which the EU masks are stored.
2074 */
2075 __u16 eu_offset;
2076
2077 /*
2078 * Stride at which each of the EU masks for each subslice are stored.
2079 */
2080 __u16 eu_stride;
2081
2082 __u8 data[];
2083};
2084
2085/**
2086 * struct drm_i915_engine_info
2087 *
2088 * Describes one engine and it's capabilities as known to the driver.
2089 */
2090struct drm_i915_engine_info {
2091 /** Engine class and instance. */
2092 struct i915_engine_class_instance engine;
2093
2094 /** Reserved field. */
2095 __u32 rsvd0;
2096
2097 /** Engine flags. */
2098 __u64 flags;
2099
2100 /** Capabilities of this engine. */
2101 __u64 capabilities;
2102#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2103#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2104
2105 /** Reserved fields. */
2106 __u64 rsvd1[4];
2107};
2108
2109/**
2110 * struct drm_i915_query_engine_info
2111 *
2112 * Engine info query enumerates all engines known to the driver by filling in
2113 * an array of struct drm_i915_engine_info structures.
2114 */
2115struct drm_i915_query_engine_info {
2116 /** Number of struct drm_i915_engine_info structs following. */
2117 __u32 num_engines;
2118
2119 /** MBZ */
2120 __u32 rsvd[3];
2121
2122 /** Marker for drm_i915_engine_info structures. */
2123 struct drm_i915_engine_info engines[];
2124};
2125
2126#if defined(__cplusplus)
2127}
2128#endif
2129
2130#endif /* _UAPI_I915_DRM_H_ */
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36/* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
38 */
39
40/**
41 * DOC: uevents generated by i915 on it's device node
42 *
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
49 *
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
56 *
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
60 */
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65/**
66 * struct i915_user_extension - Base class for defining a chain of extensions
67 *
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
73 *
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
79 *
80 * Example chaining:
81 *
82 * .. code-block:: C
83 *
84 * struct i915_user_extension ext3 {
85 * .next_extension = 0, // end
86 * .name = ...,
87 * };
88 * struct i915_user_extension ext2 {
89 * .next_extension = (uintptr_t)&ext3,
90 * .name = ...,
91 * };
92 * struct i915_user_extension ext1 {
93 * .next_extension = (uintptr_t)&ext2,
94 * .name = ...,
95 * };
96 *
97 * Typically the struct i915_user_extension would be embedded in some uAPI
98 * struct, and in this case we would feed it the head of the chain(i.e ext1),
99 * which would then apply all of the above extensions.
100 *
101 */
102struct i915_user_extension {
103 /**
104 * @next_extension:
105 *
106 * Pointer to the next struct i915_user_extension, or zero if the end.
107 */
108 __u64 next_extension;
109 /**
110 * @name: Name of the extension.
111 *
112 * Note that the name here is just some integer.
113 *
114 * Also note that the name space for this is not global for the whole
115 * driver, but rather its scope/meaning is limited to the specific piece
116 * of uAPI which has embedded the struct i915_user_extension.
117 */
118 __u32 name;
119 /**
120 * @flags: MBZ
121 *
122 * All undefined bits must be zero.
123 */
124 __u32 flags;
125 /**
126 * @rsvd: MBZ
127 *
128 * Reserved for future use; must be zero.
129 */
130 __u32 rsvd[4];
131};
132
133/*
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
136 */
137enum i915_mocs_table_index {
138 /*
139 * Not cached anywhere, coherency between CPU and GPU accesses is
140 * guaranteed.
141 */
142 I915_MOCS_UNCACHED,
143 /*
144 * Cacheability and coherency controlled by the kernel automatically
145 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
146 * usage of the surface (used for display scanout or not).
147 */
148 I915_MOCS_PTE,
149 /*
150 * Cached in all GPU caches available on the platform.
151 * Coherency between CPU and GPU accesses to the surface is not
152 * guaranteed without extra synchronization.
153 */
154 I915_MOCS_CACHED,
155};
156
157/**
158 * enum drm_i915_gem_engine_class - uapi engine type enumeration
159 *
160 * Different engines serve different roles, and there may be more than one
161 * engine serving each role. This enum provides a classification of the role
162 * of the engine, which may be used when requesting operations to be performed
163 * on a certain subset of engines, or for providing information about that
164 * group.
165 */
166enum drm_i915_gem_engine_class {
167 /**
168 * @I915_ENGINE_CLASS_RENDER:
169 *
170 * Render engines support instructions used for 3D, Compute (GPGPU),
171 * and programmable media workloads. These instructions fetch data and
172 * dispatch individual work items to threads that operate in parallel.
173 * The threads run small programs (called "kernels" or "shaders") on
174 * the GPU's execution units (EUs).
175 */
176 I915_ENGINE_CLASS_RENDER = 0,
177
178 /**
179 * @I915_ENGINE_CLASS_COPY:
180 *
181 * Copy engines (also referred to as "blitters") support instructions
182 * that move blocks of data from one location in memory to another,
183 * or that fill a specified location of memory with fixed data.
184 * Copy engines can perform pre-defined logical or bitwise operations
185 * on the source, destination, or pattern data.
186 */
187 I915_ENGINE_CLASS_COPY = 1,
188
189 /**
190 * @I915_ENGINE_CLASS_VIDEO:
191 *
192 * Video engines (also referred to as "bit stream decode" (BSD) or
193 * "vdbox") support instructions that perform fixed-function media
194 * decode and encode.
195 */
196 I915_ENGINE_CLASS_VIDEO = 2,
197
198 /**
199 * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
200 *
201 * Video enhancement engines (also referred to as "vebox") support
202 * instructions related to image enhancement.
203 */
204 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
205
206 /**
207 * @I915_ENGINE_CLASS_COMPUTE:
208 *
209 * Compute engines support a subset of the instructions available
210 * on render engines: compute engines support Compute (GPGPU) and
211 * programmable media workloads, but do not support the 3D pipeline.
212 */
213 I915_ENGINE_CLASS_COMPUTE = 4,
214
215 /* Values in this enum should be kept compact. */
216
217 /**
218 * @I915_ENGINE_CLASS_INVALID:
219 *
220 * Placeholder value to represent an invalid engine class assignment.
221 */
222 I915_ENGINE_CLASS_INVALID = -1
223};
224
225/**
226 * struct i915_engine_class_instance - Engine class/instance identifier
227 *
228 * There may be more than one engine fulfilling any role within the system.
229 * Each engine of a class is given a unique instance number and therefore
230 * any engine can be specified by its class:instance tuplet. APIs that allow
231 * access to any engine in the system will use struct i915_engine_class_instance
232 * for this identification.
233 */
234struct i915_engine_class_instance {
235 /**
236 * @engine_class:
237 *
238 * Engine class from enum drm_i915_gem_engine_class
239 */
240 __u16 engine_class;
241#define I915_ENGINE_CLASS_INVALID_NONE -1
242#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
243
244 /**
245 * @engine_instance:
246 *
247 * Engine instance.
248 */
249 __u16 engine_instance;
250};
251
252/**
253 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
254 *
255 */
256
257enum drm_i915_pmu_engine_sample {
258 I915_SAMPLE_BUSY = 0,
259 I915_SAMPLE_WAIT = 1,
260 I915_SAMPLE_SEMA = 2
261};
262
263#define I915_PMU_SAMPLE_BITS (4)
264#define I915_PMU_SAMPLE_MASK (0xf)
265#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
266#define I915_PMU_CLASS_SHIFT \
267 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
268
269#define __I915_PMU_ENGINE(class, instance, sample) \
270 ((class) << I915_PMU_CLASS_SHIFT | \
271 (instance) << I915_PMU_SAMPLE_BITS | \
272 (sample))
273
274#define I915_PMU_ENGINE_BUSY(class, instance) \
275 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
276
277#define I915_PMU_ENGINE_WAIT(class, instance) \
278 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
279
280#define I915_PMU_ENGINE_SEMA(class, instance) \
281 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
282
283#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
284
285#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
286#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
287#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
288#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
289#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
290
291#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
292
293/* Each region is a minimum of 16k, and there are at most 255 of them.
294 */
295#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
296 * of chars for next/prev indices */
297#define I915_LOG_MIN_TEX_REGION_SIZE 14
298
299typedef struct _drm_i915_init {
300 enum {
301 I915_INIT_DMA = 0x01,
302 I915_CLEANUP_DMA = 0x02,
303 I915_RESUME_DMA = 0x03
304 } func;
305 unsigned int mmio_offset;
306 int sarea_priv_offset;
307 unsigned int ring_start;
308 unsigned int ring_end;
309 unsigned int ring_size;
310 unsigned int front_offset;
311 unsigned int back_offset;
312 unsigned int depth_offset;
313 unsigned int w;
314 unsigned int h;
315 unsigned int pitch;
316 unsigned int pitch_bits;
317 unsigned int back_pitch;
318 unsigned int depth_pitch;
319 unsigned int cpp;
320 unsigned int chipset;
321} drm_i915_init_t;
322
323typedef struct _drm_i915_sarea {
324 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
325 int last_upload; /* last time texture was uploaded */
326 int last_enqueue; /* last time a buffer was enqueued */
327 int last_dispatch; /* age of the most recently dispatched buffer */
328 int ctxOwner; /* last context to upload state */
329 int texAge;
330 int pf_enabled; /* is pageflipping allowed? */
331 int pf_active;
332 int pf_current_page; /* which buffer is being displayed? */
333 int perf_boxes; /* performance boxes to be displayed */
334 int width, height; /* screen size in pixels */
335
336 drm_handle_t front_handle;
337 int front_offset;
338 int front_size;
339
340 drm_handle_t back_handle;
341 int back_offset;
342 int back_size;
343
344 drm_handle_t depth_handle;
345 int depth_offset;
346 int depth_size;
347
348 drm_handle_t tex_handle;
349 int tex_offset;
350 int tex_size;
351 int log_tex_granularity;
352 int pitch;
353 int rotation; /* 0, 90, 180 or 270 */
354 int rotated_offset;
355 int rotated_size;
356 int rotated_pitch;
357 int virtualX, virtualY;
358
359 unsigned int front_tiled;
360 unsigned int back_tiled;
361 unsigned int depth_tiled;
362 unsigned int rotated_tiled;
363 unsigned int rotated2_tiled;
364
365 int pipeA_x;
366 int pipeA_y;
367 int pipeA_w;
368 int pipeA_h;
369 int pipeB_x;
370 int pipeB_y;
371 int pipeB_w;
372 int pipeB_h;
373
374 /* fill out some space for old userspace triple buffer */
375 drm_handle_t unused_handle;
376 __u32 unused1, unused2, unused3;
377
378 /* buffer object handles for static buffers. May change
379 * over the lifetime of the client.
380 */
381 __u32 front_bo_handle;
382 __u32 back_bo_handle;
383 __u32 unused_bo_handle;
384 __u32 depth_bo_handle;
385
386} drm_i915_sarea_t;
387
388/* due to userspace building against these headers we need some compat here */
389#define planeA_x pipeA_x
390#define planeA_y pipeA_y
391#define planeA_w pipeA_w
392#define planeA_h pipeA_h
393#define planeB_x pipeB_x
394#define planeB_y pipeB_y
395#define planeB_w pipeB_w
396#define planeB_h pipeB_h
397
398/* Flags for perf_boxes
399 */
400#define I915_BOX_RING_EMPTY 0x1
401#define I915_BOX_FLIP 0x2
402#define I915_BOX_WAIT 0x4
403#define I915_BOX_TEXTURE_LOAD 0x8
404#define I915_BOX_LOST_CONTEXT 0x10
405
406/*
407 * i915 specific ioctls.
408 *
409 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
410 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
411 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
412 */
413#define DRM_I915_INIT 0x00
414#define DRM_I915_FLUSH 0x01
415#define DRM_I915_FLIP 0x02
416#define DRM_I915_BATCHBUFFER 0x03
417#define DRM_I915_IRQ_EMIT 0x04
418#define DRM_I915_IRQ_WAIT 0x05
419#define DRM_I915_GETPARAM 0x06
420#define DRM_I915_SETPARAM 0x07
421#define DRM_I915_ALLOC 0x08
422#define DRM_I915_FREE 0x09
423#define DRM_I915_INIT_HEAP 0x0a
424#define DRM_I915_CMDBUFFER 0x0b
425#define DRM_I915_DESTROY_HEAP 0x0c
426#define DRM_I915_SET_VBLANK_PIPE 0x0d
427#define DRM_I915_GET_VBLANK_PIPE 0x0e
428#define DRM_I915_VBLANK_SWAP 0x0f
429#define DRM_I915_HWS_ADDR 0x11
430#define DRM_I915_GEM_INIT 0x13
431#define DRM_I915_GEM_EXECBUFFER 0x14
432#define DRM_I915_GEM_PIN 0x15
433#define DRM_I915_GEM_UNPIN 0x16
434#define DRM_I915_GEM_BUSY 0x17
435#define DRM_I915_GEM_THROTTLE 0x18
436#define DRM_I915_GEM_ENTERVT 0x19
437#define DRM_I915_GEM_LEAVEVT 0x1a
438#define DRM_I915_GEM_CREATE 0x1b
439#define DRM_I915_GEM_PREAD 0x1c
440#define DRM_I915_GEM_PWRITE 0x1d
441#define DRM_I915_GEM_MMAP 0x1e
442#define DRM_I915_GEM_SET_DOMAIN 0x1f
443#define DRM_I915_GEM_SW_FINISH 0x20
444#define DRM_I915_GEM_SET_TILING 0x21
445#define DRM_I915_GEM_GET_TILING 0x22
446#define DRM_I915_GEM_GET_APERTURE 0x23
447#define DRM_I915_GEM_MMAP_GTT 0x24
448#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
449#define DRM_I915_GEM_MADVISE 0x26
450#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
451#define DRM_I915_OVERLAY_ATTRS 0x28
452#define DRM_I915_GEM_EXECBUFFER2 0x29
453#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
454#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
455#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
456#define DRM_I915_GEM_WAIT 0x2c
457#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
458#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
459#define DRM_I915_GEM_SET_CACHING 0x2f
460#define DRM_I915_GEM_GET_CACHING 0x30
461#define DRM_I915_REG_READ 0x31
462#define DRM_I915_GET_RESET_STATS 0x32
463#define DRM_I915_GEM_USERPTR 0x33
464#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
465#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
466#define DRM_I915_PERF_OPEN 0x36
467#define DRM_I915_PERF_ADD_CONFIG 0x37
468#define DRM_I915_PERF_REMOVE_CONFIG 0x38
469#define DRM_I915_QUERY 0x39
470#define DRM_I915_GEM_VM_CREATE 0x3a
471#define DRM_I915_GEM_VM_DESTROY 0x3b
472#define DRM_I915_GEM_CREATE_EXT 0x3c
473/* Must be kept compact -- no holes */
474
475#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
476#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
477#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
478#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
479#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
480#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
481#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
482#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
483#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
484#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
485#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
486#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
487#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
488#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
489#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
490#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
491#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
492#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
493#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
494#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
495#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
496#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
497#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
498#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
499#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
500#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
501#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
502#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
503#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
504#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
505#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
506#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
507#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
508#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
509#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
510#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
511#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
512#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
513#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
514#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
515#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
516#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
517#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
518#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
519#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
520#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
521#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
522#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
523#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
524#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
525#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
526#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
527#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
528#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
529#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
530#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
531#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
532#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
533#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
534#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
535#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
536#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
537
538/* Allow drivers to submit batchbuffers directly to hardware, relying
539 * on the security mechanisms provided by hardware.
540 */
541typedef struct drm_i915_batchbuffer {
542 int start; /* agp offset */
543 int used; /* nr bytes in use */
544 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
545 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
546 int num_cliprects; /* mulitpass with multiple cliprects? */
547 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
548} drm_i915_batchbuffer_t;
549
550/* As above, but pass a pointer to userspace buffer which can be
551 * validated by the kernel prior to sending to hardware.
552 */
553typedef struct _drm_i915_cmdbuffer {
554 char __user *buf; /* pointer to userspace command buffer */
555 int sz; /* nr bytes in buf */
556 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
557 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
558 int num_cliprects; /* mulitpass with multiple cliprects? */
559 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
560} drm_i915_cmdbuffer_t;
561
562/* Userspace can request & wait on irq's:
563 */
564typedef struct drm_i915_irq_emit {
565 int __user *irq_seq;
566} drm_i915_irq_emit_t;
567
568typedef struct drm_i915_irq_wait {
569 int irq_seq;
570} drm_i915_irq_wait_t;
571
572/*
573 * Different modes of per-process Graphics Translation Table,
574 * see I915_PARAM_HAS_ALIASING_PPGTT
575 */
576#define I915_GEM_PPGTT_NONE 0
577#define I915_GEM_PPGTT_ALIASING 1
578#define I915_GEM_PPGTT_FULL 2
579
580/* Ioctl to query kernel params:
581 */
582#define I915_PARAM_IRQ_ACTIVE 1
583#define I915_PARAM_ALLOW_BATCHBUFFER 2
584#define I915_PARAM_LAST_DISPATCH 3
585#define I915_PARAM_CHIPSET_ID 4
586#define I915_PARAM_HAS_GEM 5
587#define I915_PARAM_NUM_FENCES_AVAIL 6
588#define I915_PARAM_HAS_OVERLAY 7
589#define I915_PARAM_HAS_PAGEFLIPPING 8
590#define I915_PARAM_HAS_EXECBUF2 9
591#define I915_PARAM_HAS_BSD 10
592#define I915_PARAM_HAS_BLT 11
593#define I915_PARAM_HAS_RELAXED_FENCING 12
594#define I915_PARAM_HAS_COHERENT_RINGS 13
595#define I915_PARAM_HAS_EXEC_CONSTANTS 14
596#define I915_PARAM_HAS_RELAXED_DELTA 15
597#define I915_PARAM_HAS_GEN7_SOL_RESET 16
598#define I915_PARAM_HAS_LLC 17
599#define I915_PARAM_HAS_ALIASING_PPGTT 18
600#define I915_PARAM_HAS_WAIT_TIMEOUT 19
601#define I915_PARAM_HAS_SEMAPHORES 20
602#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
603#define I915_PARAM_HAS_VEBOX 22
604#define I915_PARAM_HAS_SECURE_BATCHES 23
605#define I915_PARAM_HAS_PINNED_BATCHES 24
606#define I915_PARAM_HAS_EXEC_NO_RELOC 25
607#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
608#define I915_PARAM_HAS_WT 27
609#define I915_PARAM_CMD_PARSER_VERSION 28
610#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
611#define I915_PARAM_MMAP_VERSION 30
612#define I915_PARAM_HAS_BSD2 31
613#define I915_PARAM_REVISION 32
614#define I915_PARAM_SUBSLICE_TOTAL 33
615#define I915_PARAM_EU_TOTAL 34
616#define I915_PARAM_HAS_GPU_RESET 35
617#define I915_PARAM_HAS_RESOURCE_STREAMER 36
618#define I915_PARAM_HAS_EXEC_SOFTPIN 37
619#define I915_PARAM_HAS_POOLED_EU 38
620#define I915_PARAM_MIN_EU_IN_POOL 39
621#define I915_PARAM_MMAP_GTT_VERSION 40
622
623/*
624 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
625 * priorities and the driver will attempt to execute batches in priority order.
626 * The param returns a capability bitmask, nonzero implies that the scheduler
627 * is enabled, with different features present according to the mask.
628 *
629 * The initial priority for each batch is supplied by the context and is
630 * controlled via I915_CONTEXT_PARAM_PRIORITY.
631 */
632#define I915_PARAM_HAS_SCHEDULER 41
633#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
634#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
635#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
636#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
637#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
638/*
639 * Indicates the 2k user priority levels are statically mapped into 3 buckets as
640 * follows:
641 *
642 * -1k to -1 Low priority
643 * 0 Normal priority
644 * 1 to 1k Highest priority
645 */
646#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
647
648/*
649 * Query the status of HuC load.
650 *
651 * The query can fail in the following scenarios with the listed error codes:
652 * -ENODEV if HuC is not present on this platform,
653 * -EOPNOTSUPP if HuC firmware usage is disabled,
654 * -ENOPKG if HuC firmware fetch failed,
655 * -ENOEXEC if HuC firmware is invalid or mismatched,
656 * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
657 * -EIO if the FW transfer or the FW authentication failed.
658 *
659 * If the IOCTL is successful, the returned parameter will be set to one of the
660 * following values:
661 * * 0 if HuC firmware load is not complete,
662 * * 1 if HuC firmware is authenticated and running.
663 */
664#define I915_PARAM_HUC_STATUS 42
665
666/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
667 * synchronisation with implicit fencing on individual objects.
668 * See EXEC_OBJECT_ASYNC.
669 */
670#define I915_PARAM_HAS_EXEC_ASYNC 43
671
672/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
673 * both being able to pass in a sync_file fd to wait upon before executing,
674 * and being able to return a new sync_file fd that is signaled when the
675 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
676 */
677#define I915_PARAM_HAS_EXEC_FENCE 44
678
679/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
680 * user specified bufffers for post-mortem debugging of GPU hangs. See
681 * EXEC_OBJECT_CAPTURE.
682 */
683#define I915_PARAM_HAS_EXEC_CAPTURE 45
684
685#define I915_PARAM_SLICE_MASK 46
686
687/* Assuming it's uniform for each slice, this queries the mask of subslices
688 * per-slice for this system.
689 */
690#define I915_PARAM_SUBSLICE_MASK 47
691
692/*
693 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
694 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
695 */
696#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
697
698/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
699 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
700 */
701#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
702
703/*
704 * Query whether every context (both per-file default and user created) is
705 * isolated (insofar as HW supports). If this parameter is not true, then
706 * freshly created contexts may inherit values from an existing context,
707 * rather than default HW values. If true, it also ensures (insofar as HW
708 * supports) that all state set by this context will not leak to any other
709 * context.
710 *
711 * As not every engine across every gen support contexts, the returned
712 * value reports the support of context isolation for individual engines by
713 * returning a bitmask of each engine class set to true if that class supports
714 * isolation.
715 */
716#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
717
718/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
719 * registers. This used to be fixed per platform but from CNL onwards, this
720 * might vary depending on the parts.
721 */
722#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
723
724/*
725 * Once upon a time we supposed that writes through the GGTT would be
726 * immediately in physical memory (once flushed out of the CPU path). However,
727 * on a few different processors and chipsets, this is not necessarily the case
728 * as the writes appear to be buffered internally. Thus a read of the backing
729 * storage (physical memory) via a different path (with different physical tags
730 * to the indirect write via the GGTT) will see stale values from before
731 * the GGTT write. Inside the kernel, we can for the most part keep track of
732 * the different read/write domains in use (e.g. set-domain), but the assumption
733 * of coherency is baked into the ABI, hence reporting its true state in this
734 * parameter.
735 *
736 * Reports true when writes via mmap_gtt are immediately visible following an
737 * lfence to flush the WCB.
738 *
739 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
740 * internal buffer and are _not_ immediately visible to third parties accessing
741 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
742 * communications channel when reporting false is strongly disadvised.
743 */
744#define I915_PARAM_MMAP_GTT_COHERENT 52
745
746/*
747 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
748 * execution through use of explicit fence support.
749 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
750 */
751#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
752
753/*
754 * Revision of the i915-perf uAPI. The value returned helps determine what
755 * i915-perf features are available. See drm_i915_perf_property_id.
756 */
757#define I915_PARAM_PERF_REVISION 54
758
759/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
760 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
761 * I915_EXEC_USE_EXTENSIONS.
762 */
763#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
764
765/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
766#define I915_PARAM_HAS_USERPTR_PROBE 56
767
768/*
769 * Frequency of the timestamps in OA reports. This used to be the same as the CS
770 * timestamp frequency, but differs on some platforms.
771 */
772#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
773
774/* Must be kept compact -- no holes and well documented */
775
776/**
777 * struct drm_i915_getparam - Driver parameter query structure.
778 */
779struct drm_i915_getparam {
780 /** @param: Driver parameter to query. */
781 __s32 param;
782
783 /**
784 * @value: Address of memory where queried value should be put.
785 *
786 * WARNING: Using pointers instead of fixed-size u64 means we need to write
787 * compat32 code. Don't repeat this mistake.
788 */
789 int __user *value;
790};
791
792/**
793 * typedef drm_i915_getparam_t - Driver parameter query structure.
794 * See struct drm_i915_getparam.
795 */
796typedef struct drm_i915_getparam drm_i915_getparam_t;
797
798/* Ioctl to set kernel params:
799 */
800#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
801#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
802#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
803#define I915_SETPARAM_NUM_USED_FENCES 4
804/* Must be kept compact -- no holes */
805
806typedef struct drm_i915_setparam {
807 int param;
808 int value;
809} drm_i915_setparam_t;
810
811/* A memory manager for regions of shared memory:
812 */
813#define I915_MEM_REGION_AGP 1
814
815typedef struct drm_i915_mem_alloc {
816 int region;
817 int alignment;
818 int size;
819 int __user *region_offset; /* offset from start of fb or agp */
820} drm_i915_mem_alloc_t;
821
822typedef struct drm_i915_mem_free {
823 int region;
824 int region_offset;
825} drm_i915_mem_free_t;
826
827typedef struct drm_i915_mem_init_heap {
828 int region;
829 int size;
830 int start;
831} drm_i915_mem_init_heap_t;
832
833/* Allow memory manager to be torn down and re-initialized (eg on
834 * rotate):
835 */
836typedef struct drm_i915_mem_destroy_heap {
837 int region;
838} drm_i915_mem_destroy_heap_t;
839
840/* Allow X server to configure which pipes to monitor for vblank signals
841 */
842#define DRM_I915_VBLANK_PIPE_A 1
843#define DRM_I915_VBLANK_PIPE_B 2
844
845typedef struct drm_i915_vblank_pipe {
846 int pipe;
847} drm_i915_vblank_pipe_t;
848
849/* Schedule buffer swap at given vertical blank:
850 */
851typedef struct drm_i915_vblank_swap {
852 drm_drawable_t drawable;
853 enum drm_vblank_seq_type seqtype;
854 unsigned int sequence;
855} drm_i915_vblank_swap_t;
856
857typedef struct drm_i915_hws_addr {
858 __u64 addr;
859} drm_i915_hws_addr_t;
860
861struct drm_i915_gem_init {
862 /**
863 * Beginning offset in the GTT to be managed by the DRM memory
864 * manager.
865 */
866 __u64 gtt_start;
867 /**
868 * Ending offset in the GTT to be managed by the DRM memory
869 * manager.
870 */
871 __u64 gtt_end;
872};
873
874struct drm_i915_gem_create {
875 /**
876 * Requested size for the object.
877 *
878 * The (page-aligned) allocated size for the object will be returned.
879 */
880 __u64 size;
881 /**
882 * Returned handle for the object.
883 *
884 * Object handles are nonzero.
885 */
886 __u32 handle;
887 __u32 pad;
888};
889
890struct drm_i915_gem_pread {
891 /** Handle for the object being read. */
892 __u32 handle;
893 __u32 pad;
894 /** Offset into the object to read from */
895 __u64 offset;
896 /** Length of data to read */
897 __u64 size;
898 /**
899 * Pointer to write the data into.
900 *
901 * This is a fixed-size type for 32/64 compatibility.
902 */
903 __u64 data_ptr;
904};
905
906struct drm_i915_gem_pwrite {
907 /** Handle for the object being written to. */
908 __u32 handle;
909 __u32 pad;
910 /** Offset into the object to write to */
911 __u64 offset;
912 /** Length of data to write */
913 __u64 size;
914 /**
915 * Pointer to read the data from.
916 *
917 * This is a fixed-size type for 32/64 compatibility.
918 */
919 __u64 data_ptr;
920};
921
922struct drm_i915_gem_mmap {
923 /** Handle for the object being mapped. */
924 __u32 handle;
925 __u32 pad;
926 /** Offset in the object to map. */
927 __u64 offset;
928 /**
929 * Length of data to map.
930 *
931 * The value will be page-aligned.
932 */
933 __u64 size;
934 /**
935 * Returned pointer the data was mapped at.
936 *
937 * This is a fixed-size type for 32/64 compatibility.
938 */
939 __u64 addr_ptr;
940
941 /**
942 * Flags for extended behaviour.
943 *
944 * Added in version 2.
945 */
946 __u64 flags;
947#define I915_MMAP_WC 0x1
948};
949
950struct drm_i915_gem_mmap_gtt {
951 /** Handle for the object being mapped. */
952 __u32 handle;
953 __u32 pad;
954 /**
955 * Fake offset to use for subsequent mmap call
956 *
957 * This is a fixed-size type for 32/64 compatibility.
958 */
959 __u64 offset;
960};
961
962/**
963 * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
964 *
965 * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
966 * and is used to retrieve the fake offset to mmap an object specified by &handle.
967 *
968 * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
969 * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
970 * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
971 */
972struct drm_i915_gem_mmap_offset {
973 /** @handle: Handle for the object being mapped. */
974 __u32 handle;
975 /** @pad: Must be zero */
976 __u32 pad;
977 /**
978 * @offset: The fake offset to use for subsequent mmap call
979 *
980 * This is a fixed-size type for 32/64 compatibility.
981 */
982 __u64 offset;
983
984 /**
985 * @flags: Flags for extended behaviour.
986 *
987 * It is mandatory that one of the `MMAP_OFFSET` types
988 * should be included:
989 *
990 * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
991 * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
992 * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
993 * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
994 *
995 * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
996 * type. On devices without local memory, this caching mode is invalid.
997 *
998 * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
999 * be used, depending on the object placement on creation. WB will be used
1000 * when the object can only exist in system memory, WC otherwise.
1001 */
1002 __u64 flags;
1003
1004#define I915_MMAP_OFFSET_GTT 0
1005#define I915_MMAP_OFFSET_WC 1
1006#define I915_MMAP_OFFSET_WB 2
1007#define I915_MMAP_OFFSET_UC 3
1008#define I915_MMAP_OFFSET_FIXED 4
1009
1010 /**
1011 * @extensions: Zero-terminated chain of extensions.
1012 *
1013 * No current extensions defined; mbz.
1014 */
1015 __u64 extensions;
1016};
1017
1018/**
1019 * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
1020 * preparation for accessing the pages via some CPU domain.
1021 *
1022 * Specifying a new write or read domain will flush the object out of the
1023 * previous domain(if required), before then updating the objects domain
1024 * tracking with the new domain.
1025 *
1026 * Note this might involve waiting for the object first if it is still active on
1027 * the GPU.
1028 *
1029 * Supported values for @read_domains and @write_domain:
1030 *
1031 * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
1032 * - I915_GEM_DOMAIN_CPU: CPU cache domain
1033 * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
1034 *
1035 * All other domains are rejected.
1036 *
1037 * Note that for discrete, starting from DG1, this is no longer supported, and
1038 * is instead rejected. On such platforms the CPU domain is effectively static,
1039 * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
1040 * which can't be set explicitly and instead depends on the object placements,
1041 * as per the below.
1042 *
1043 * Implicit caching rules, starting from DG1:
1044 *
1045 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
1046 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
1047 * mapped as write-combined only.
1048 *
1049 * - Everything else is always allocated and mapped as write-back, with the
1050 * guarantee that everything is also coherent with the GPU.
1051 *
1052 * Note that this is likely to change in the future again, where we might need
1053 * more flexibility on future devices, so making this all explicit as part of a
1054 * new &drm_i915_gem_create_ext extension is probable.
1055 */
1056struct drm_i915_gem_set_domain {
1057 /** @handle: Handle for the object. */
1058 __u32 handle;
1059
1060 /** @read_domains: New read domains. */
1061 __u32 read_domains;
1062
1063 /**
1064 * @write_domain: New write domain.
1065 *
1066 * Note that having something in the write domain implies it's in the
1067 * read domain, and only that read domain.
1068 */
1069 __u32 write_domain;
1070};
1071
1072struct drm_i915_gem_sw_finish {
1073 /** Handle for the object */
1074 __u32 handle;
1075};
1076
1077struct drm_i915_gem_relocation_entry {
1078 /**
1079 * Handle of the buffer being pointed to by this relocation entry.
1080 *
1081 * It's appealing to make this be an index into the mm_validate_entry
1082 * list to refer to the buffer, but this allows the driver to create
1083 * a relocation list for state buffers and not re-write it per
1084 * exec using the buffer.
1085 */
1086 __u32 target_handle;
1087
1088 /**
1089 * Value to be added to the offset of the target buffer to make up
1090 * the relocation entry.
1091 */
1092 __u32 delta;
1093
1094 /** Offset in the buffer the relocation entry will be written into */
1095 __u64 offset;
1096
1097 /**
1098 * Offset value of the target buffer that the relocation entry was last
1099 * written as.
1100 *
1101 * If the buffer has the same offset as last time, we can skip syncing
1102 * and writing the relocation. This value is written back out by
1103 * the execbuffer ioctl when the relocation is written.
1104 */
1105 __u64 presumed_offset;
1106
1107 /**
1108 * Target memory domains read by this operation.
1109 */
1110 __u32 read_domains;
1111
1112 /**
1113 * Target memory domains written by this operation.
1114 *
1115 * Note that only one domain may be written by the whole
1116 * execbuffer operation, so that where there are conflicts,
1117 * the application will get -EINVAL back.
1118 */
1119 __u32 write_domain;
1120};
1121
1122/** @{
1123 * Intel memory domains
1124 *
1125 * Most of these just align with the various caches in
1126 * the system and are used to flush and invalidate as
1127 * objects end up cached in different domains.
1128 */
1129/** CPU cache */
1130#define I915_GEM_DOMAIN_CPU 0x00000001
1131/** Render cache, used by 2D and 3D drawing */
1132#define I915_GEM_DOMAIN_RENDER 0x00000002
1133/** Sampler cache, used by texture engine */
1134#define I915_GEM_DOMAIN_SAMPLER 0x00000004
1135/** Command queue, used to load batch buffers */
1136#define I915_GEM_DOMAIN_COMMAND 0x00000008
1137/** Instruction cache, used by shader programs */
1138#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
1139/** Vertex address cache */
1140#define I915_GEM_DOMAIN_VERTEX 0x00000020
1141/** GTT domain - aperture and scanout */
1142#define I915_GEM_DOMAIN_GTT 0x00000040
1143/** WC domain - uncached access */
1144#define I915_GEM_DOMAIN_WC 0x00000080
1145/** @} */
1146
1147struct drm_i915_gem_exec_object {
1148 /**
1149 * User's handle for a buffer to be bound into the GTT for this
1150 * operation.
1151 */
1152 __u32 handle;
1153
1154 /** Number of relocations to be performed on this buffer */
1155 __u32 relocation_count;
1156 /**
1157 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1158 * the relocations to be performed in this buffer.
1159 */
1160 __u64 relocs_ptr;
1161
1162 /** Required alignment in graphics aperture */
1163 __u64 alignment;
1164
1165 /**
1166 * Returned value of the updated offset of the object, for future
1167 * presumed_offset writes.
1168 */
1169 __u64 offset;
1170};
1171
1172/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
1173struct drm_i915_gem_execbuffer {
1174 /**
1175 * List of buffers to be validated with their relocations to be
1176 * performend on them.
1177 *
1178 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
1179 *
1180 * These buffers must be listed in an order such that all relocations
1181 * a buffer is performing refer to buffers that have already appeared
1182 * in the validate list.
1183 */
1184 __u64 buffers_ptr;
1185 __u32 buffer_count;
1186
1187 /** Offset in the batchbuffer to start execution from. */
1188 __u32 batch_start_offset;
1189 /** Bytes used in batchbuffer from batch_start_offset */
1190 __u32 batch_len;
1191 __u32 DR1;
1192 __u32 DR4;
1193 __u32 num_cliprects;
1194 /** This is a struct drm_clip_rect *cliprects */
1195 __u64 cliprects_ptr;
1196};
1197
1198struct drm_i915_gem_exec_object2 {
1199 /**
1200 * User's handle for a buffer to be bound into the GTT for this
1201 * operation.
1202 */
1203 __u32 handle;
1204
1205 /** Number of relocations to be performed on this buffer */
1206 __u32 relocation_count;
1207 /**
1208 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1209 * the relocations to be performed in this buffer.
1210 */
1211 __u64 relocs_ptr;
1212
1213 /** Required alignment in graphics aperture */
1214 __u64 alignment;
1215
1216 /**
1217 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
1218 * the user with the GTT offset at which this object will be pinned.
1219 *
1220 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
1221 * presumed_offset of the object.
1222 *
1223 * During execbuffer2 the kernel populates it with the value of the
1224 * current GTT offset of the object, for future presumed_offset writes.
1225 *
1226 * See struct drm_i915_gem_create_ext for the rules when dealing with
1227 * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
1228 * minimum page sizes, like DG2.
1229 */
1230 __u64 offset;
1231
1232#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
1233#define EXEC_OBJECT_NEEDS_GTT (1<<1)
1234#define EXEC_OBJECT_WRITE (1<<2)
1235#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
1236#define EXEC_OBJECT_PINNED (1<<4)
1237#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
1238/* The kernel implicitly tracks GPU activity on all GEM objects, and
1239 * synchronises operations with outstanding rendering. This includes
1240 * rendering on other devices if exported via dma-buf. However, sometimes
1241 * this tracking is too coarse and the user knows better. For example,
1242 * if the object is split into non-overlapping ranges shared between different
1243 * clients or engines (i.e. suballocating objects), the implicit tracking
1244 * by kernel assumes that each operation affects the whole object rather
1245 * than an individual range, causing needless synchronisation between clients.
1246 * The kernel will also forgo any CPU cache flushes prior to rendering from
1247 * the object as the client is expected to be also handling such domain
1248 * tracking.
1249 *
1250 * The kernel maintains the implicit tracking in order to manage resources
1251 * used by the GPU - this flag only disables the synchronisation prior to
1252 * rendering with this object in this execbuf.
1253 *
1254 * Opting out of implicit synhronisation requires the user to do its own
1255 * explicit tracking to avoid rendering corruption. See, for example,
1256 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1257 */
1258#define EXEC_OBJECT_ASYNC (1<<6)
1259/* Request that the contents of this execobject be copied into the error
1260 * state upon a GPU hang involving this batch for post-mortem debugging.
1261 * These buffers are recorded in no particular order as "user" in
1262 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1263 * if the kernel supports this flag.
1264 */
1265#define EXEC_OBJECT_CAPTURE (1<<7)
1266/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1267#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1268 __u64 flags;
1269
1270 union {
1271 __u64 rsvd1;
1272 __u64 pad_to_size;
1273 };
1274 __u64 rsvd2;
1275};
1276
1277/**
1278 * struct drm_i915_gem_exec_fence - An input or output fence for the execbuf
1279 * ioctl.
1280 *
1281 * The request will wait for input fence to signal before submission.
1282 *
1283 * The returned output fence will be signaled after the completion of the
1284 * request.
1285 */
1286struct drm_i915_gem_exec_fence {
1287 /** @handle: User's handle for a drm_syncobj to wait on or signal. */
1288 __u32 handle;
1289
1290 /**
1291 * @flags: Supported flags are:
1292 *
1293 * I915_EXEC_FENCE_WAIT:
1294 * Wait for the input fence before request submission.
1295 *
1296 * I915_EXEC_FENCE_SIGNAL:
1297 * Return request completion fence as output
1298 */
1299 __u32 flags;
1300#define I915_EXEC_FENCE_WAIT (1<<0)
1301#define I915_EXEC_FENCE_SIGNAL (1<<1)
1302#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1303};
1304
1305/**
1306 * struct drm_i915_gem_execbuffer_ext_timeline_fences - Timeline fences
1307 * for execbuf ioctl.
1308 *
1309 * This structure describes an array of drm_syncobj and associated points for
1310 * timeline variants of drm_syncobj. It is invalid to append this structure to
1311 * the execbuf if I915_EXEC_FENCE_ARRAY is set.
1312 */
1313struct drm_i915_gem_execbuffer_ext_timeline_fences {
1314#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
1315 /** @base: Extension link. See struct i915_user_extension. */
1316 struct i915_user_extension base;
1317
1318 /**
1319 * @fence_count: Number of elements in the @handles_ptr & @value_ptr
1320 * arrays.
1321 */
1322 __u64 fence_count;
1323
1324 /**
1325 * @handles_ptr: Pointer to an array of struct drm_i915_gem_exec_fence
1326 * of length @fence_count.
1327 */
1328 __u64 handles_ptr;
1329
1330 /**
1331 * @values_ptr: Pointer to an array of u64 values of length
1332 * @fence_count.
1333 * Values must be 0 for a binary drm_syncobj. A Value of 0 for a
1334 * timeline drm_syncobj is invalid as it turns a drm_syncobj into a
1335 * binary one.
1336 */
1337 __u64 values_ptr;
1338};
1339
1340/**
1341 * struct drm_i915_gem_execbuffer2 - Structure for DRM_I915_GEM_EXECBUFFER2
1342 * ioctl.
1343 */
1344struct drm_i915_gem_execbuffer2 {
1345 /** @buffers_ptr: Pointer to a list of gem_exec_object2 structs */
1346 __u64 buffers_ptr;
1347
1348 /** @buffer_count: Number of elements in @buffers_ptr array */
1349 __u32 buffer_count;
1350
1351 /**
1352 * @batch_start_offset: Offset in the batchbuffer to start execution
1353 * from.
1354 */
1355 __u32 batch_start_offset;
1356
1357 /**
1358 * @batch_len: Length in bytes of the batch buffer, starting from the
1359 * @batch_start_offset. If 0, length is assumed to be the batch buffer
1360 * object size.
1361 */
1362 __u32 batch_len;
1363
1364 /** @DR1: deprecated */
1365 __u32 DR1;
1366
1367 /** @DR4: deprecated */
1368 __u32 DR4;
1369
1370 /** @num_cliprects: See @cliprects_ptr */
1371 __u32 num_cliprects;
1372
1373 /**
1374 * @cliprects_ptr: Kernel clipping was a DRI1 misfeature.
1375 *
1376 * It is invalid to use this field if I915_EXEC_FENCE_ARRAY or
1377 * I915_EXEC_USE_EXTENSIONS flags are not set.
1378 *
1379 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
1380 * of &drm_i915_gem_exec_fence and @num_cliprects is the length of the
1381 * array.
1382 *
1383 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
1384 * single &i915_user_extension and num_cliprects is 0.
1385 */
1386 __u64 cliprects_ptr;
1387
1388 /** @flags: Execbuf flags */
1389 __u64 flags;
1390#define I915_EXEC_RING_MASK (0x3f)
1391#define I915_EXEC_DEFAULT (0<<0)
1392#define I915_EXEC_RENDER (1<<0)
1393#define I915_EXEC_BSD (2<<0)
1394#define I915_EXEC_BLT (3<<0)
1395#define I915_EXEC_VEBOX (4<<0)
1396
1397/* Used for switching the constants addressing mode on gen4+ RENDER ring.
1398 * Gen6+ only supports relative addressing to dynamic state (default) and
1399 * absolute addressing.
1400 *
1401 * These flags are ignored for the BSD and BLT rings.
1402 */
1403#define I915_EXEC_CONSTANTS_MASK (3<<6)
1404#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1405#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1406#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1407
1408/** Resets the SO write offset registers for transform feedback on gen7. */
1409#define I915_EXEC_GEN7_SOL_RESET (1<<8)
1410
1411/** Request a privileged ("secure") batch buffer. Note only available for
1412 * DRM_ROOT_ONLY | DRM_MASTER processes.
1413 */
1414#define I915_EXEC_SECURE (1<<9)
1415
1416/** Inform the kernel that the batch is and will always be pinned. This
1417 * negates the requirement for a workaround to be performed to avoid
1418 * an incoherent CS (such as can be found on 830/845). If this flag is
1419 * not passed, the kernel will endeavour to make sure the batch is
1420 * coherent with the CS before execution. If this flag is passed,
1421 * userspace assumes the responsibility for ensuring the same.
1422 */
1423#define I915_EXEC_IS_PINNED (1<<10)
1424
1425/** Provide a hint to the kernel that the command stream and auxiliary
1426 * state buffers already holds the correct presumed addresses and so the
1427 * relocation process may be skipped if no buffers need to be moved in
1428 * preparation for the execbuffer.
1429 */
1430#define I915_EXEC_NO_RELOC (1<<11)
1431
1432/** Use the reloc.handle as an index into the exec object array rather
1433 * than as the per-file handle.
1434 */
1435#define I915_EXEC_HANDLE_LUT (1<<12)
1436
1437/** Used for switching BSD rings on the platforms with two BSD rings */
1438#define I915_EXEC_BSD_SHIFT (13)
1439#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1440/* default ping-pong mode */
1441#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1442#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1443#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1444
1445/** Tell the kernel that the batchbuffer is processed by
1446 * the resource streamer.
1447 */
1448#define I915_EXEC_RESOURCE_STREAMER (1<<15)
1449
1450/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1451 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1452 * the batch.
1453 *
1454 * Returns -EINVAL if the sync_file fd cannot be found.
1455 */
1456#define I915_EXEC_FENCE_IN (1<<16)
1457
1458/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1459 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1460 * to the caller, and it should be close() after use. (The fd is a regular
1461 * file descriptor and will be cleaned up on process termination. It holds
1462 * a reference to the request, but nothing else.)
1463 *
1464 * The sync_file fd can be combined with other sync_file and passed either
1465 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1466 * will only occur after this request completes), or to other devices.
1467 *
1468 * Using I915_EXEC_FENCE_OUT requires use of
1469 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1470 * back to userspace. Failure to do so will cause the out-fence to always
1471 * be reported as zero, and the real fence fd to be leaked.
1472 */
1473#define I915_EXEC_FENCE_OUT (1<<17)
1474
1475/*
1476 * Traditionally the execbuf ioctl has only considered the final element in
1477 * the execobject[] to be the executable batch. Often though, the client
1478 * will known the batch object prior to construction and being able to place
1479 * it into the execobject[] array first can simplify the relocation tracking.
1480 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1481 * execobject[] as the * batch instead (the default is to use the last
1482 * element).
1483 */
1484#define I915_EXEC_BATCH_FIRST (1<<18)
1485
1486/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1487 * define an array of i915_gem_exec_fence structures which specify a set of
1488 * dma fences to wait upon or signal.
1489 */
1490#define I915_EXEC_FENCE_ARRAY (1<<19)
1491
1492/*
1493 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1494 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1495 * the batch.
1496 *
1497 * Returns -EINVAL if the sync_file fd cannot be found.
1498 */
1499#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1500
1501/*
1502 * Setting I915_EXEC_USE_EXTENSIONS implies that
1503 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
1504 * list of i915_user_extension. Each i915_user_extension node is the base of a
1505 * larger structure. The list of supported structures are listed in the
1506 * drm_i915_gem_execbuffer_ext enum.
1507 */
1508#define I915_EXEC_USE_EXTENSIONS (1 << 21)
1509#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1510
1511 /** @rsvd1: Context id */
1512 __u64 rsvd1;
1513
1514 /**
1515 * @rsvd2: in and out sync_file file descriptors.
1516 *
1517 * When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the
1518 * lower 32 bits of this field will have the in sync_file fd (input).
1519 *
1520 * When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this
1521 * field will have the out sync_file fd (output).
1522 */
1523 __u64 rsvd2;
1524};
1525
1526#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1527#define i915_execbuffer2_set_context_id(eb2, context) \
1528 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1529#define i915_execbuffer2_get_context_id(eb2) \
1530 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1531
1532struct drm_i915_gem_pin {
1533 /** Handle of the buffer to be pinned. */
1534 __u32 handle;
1535 __u32 pad;
1536
1537 /** alignment required within the aperture */
1538 __u64 alignment;
1539
1540 /** Returned GTT offset of the buffer. */
1541 __u64 offset;
1542};
1543
1544struct drm_i915_gem_unpin {
1545 /** Handle of the buffer to be unpinned. */
1546 __u32 handle;
1547 __u32 pad;
1548};
1549
1550struct drm_i915_gem_busy {
1551 /** Handle of the buffer to check for busy */
1552 __u32 handle;
1553
1554 /** Return busy status
1555 *
1556 * A return of 0 implies that the object is idle (after
1557 * having flushed any pending activity), and a non-zero return that
1558 * the object is still in-flight on the GPU. (The GPU has not yet
1559 * signaled completion for all pending requests that reference the
1560 * object.) An object is guaranteed to become idle eventually (so
1561 * long as no new GPU commands are executed upon it). Due to the
1562 * asynchronous nature of the hardware, an object reported
1563 * as busy may become idle before the ioctl is completed.
1564 *
1565 * Furthermore, if the object is busy, which engine is busy is only
1566 * provided as a guide and only indirectly by reporting its class
1567 * (there may be more than one engine in each class). There are race
1568 * conditions which prevent the report of which engines are busy from
1569 * being always accurate. However, the converse is not true. If the
1570 * object is idle, the result of the ioctl, that all engines are idle,
1571 * is accurate.
1572 *
1573 * The returned dword is split into two fields to indicate both
1574 * the engine classess on which the object is being read, and the
1575 * engine class on which it is currently being written (if any).
1576 *
1577 * The low word (bits 0:15) indicate if the object is being written
1578 * to by any engine (there can only be one, as the GEM implicit
1579 * synchronisation rules force writes to be serialised). Only the
1580 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1581 * 1 not 0 etc) for the last write is reported.
1582 *
1583 * The high word (bits 16:31) are a bitmask of which engines classes
1584 * are currently reading from the object. Multiple engines may be
1585 * reading from the object simultaneously.
1586 *
1587 * The value of each engine class is the same as specified in the
1588 * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
1589 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1590 * Some hardware may have parallel execution engines, e.g. multiple
1591 * media engines, which are mapped to the same class identifier and so
1592 * are not separately reported for busyness.
1593 *
1594 * Caveat emptor:
1595 * Only the boolean result of this query is reliable; that is whether
1596 * the object is idle or busy. The report of which engines are busy
1597 * should be only used as a heuristic.
1598 */
1599 __u32 busy;
1600};
1601
1602/**
1603 * struct drm_i915_gem_caching - Set or get the caching for given object
1604 * handle.
1605 *
1606 * Allow userspace to control the GTT caching bits for a given object when the
1607 * object is later mapped through the ppGTT(or GGTT on older platforms lacking
1608 * ppGTT support, or if the object is used for scanout). Note that this might
1609 * require unbinding the object from the GTT first, if its current caching value
1610 * doesn't match.
1611 *
1612 * Note that this all changes on discrete platforms, starting from DG1, the
1613 * set/get caching is no longer supported, and is now rejected. Instead the CPU
1614 * caching attributes(WB vs WC) will become an immutable creation time property
1615 * for the object, along with the GTT caching level. For now we don't expose any
1616 * new uAPI for this, instead on DG1 this is all implicit, although this largely
1617 * shouldn't matter since DG1 is coherent by default(without any way of
1618 * controlling it).
1619 *
1620 * Implicit caching rules, starting from DG1:
1621 *
1622 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
1623 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
1624 * mapped as write-combined only.
1625 *
1626 * - Everything else is always allocated and mapped as write-back, with the
1627 * guarantee that everything is also coherent with the GPU.
1628 *
1629 * Note that this is likely to change in the future again, where we might need
1630 * more flexibility on future devices, so making this all explicit as part of a
1631 * new &drm_i915_gem_create_ext extension is probable.
1632 *
1633 * Side note: Part of the reason for this is that changing the at-allocation-time CPU
1634 * caching attributes for the pages might be required(and is expensive) if we
1635 * need to then CPU map the pages later with different caching attributes. This
1636 * inconsistent caching behaviour, while supported on x86, is not universally
1637 * supported on other architectures. So for simplicity we opt for setting
1638 * everything at creation time, whilst also making it immutable, on discrete
1639 * platforms.
1640 */
1641struct drm_i915_gem_caching {
1642 /**
1643 * @handle: Handle of the buffer to set/get the caching level.
1644 */
1645 __u32 handle;
1646
1647 /**
1648 * @caching: The GTT caching level to apply or possible return value.
1649 *
1650 * The supported @caching values:
1651 *
1652 * I915_CACHING_NONE:
1653 *
1654 * GPU access is not coherent with CPU caches. Default for machines
1655 * without an LLC. This means manual flushing might be needed, if we
1656 * want GPU access to be coherent.
1657 *
1658 * I915_CACHING_CACHED:
1659 *
1660 * GPU access is coherent with CPU caches and furthermore the data is
1661 * cached in last-level caches shared between CPU cores and the GPU GT.
1662 *
1663 * I915_CACHING_DISPLAY:
1664 *
1665 * Special GPU caching mode which is coherent with the scanout engines.
1666 * Transparently falls back to I915_CACHING_NONE on platforms where no
1667 * special cache mode (like write-through or gfdt flushing) is
1668 * available. The kernel automatically sets this mode when using a
1669 * buffer as a scanout target. Userspace can manually set this mode to
1670 * avoid a costly stall and clflush in the hotpath of drawing the first
1671 * frame.
1672 */
1673#define I915_CACHING_NONE 0
1674#define I915_CACHING_CACHED 1
1675#define I915_CACHING_DISPLAY 2
1676 __u32 caching;
1677};
1678
1679#define I915_TILING_NONE 0
1680#define I915_TILING_X 1
1681#define I915_TILING_Y 2
1682/*
1683 * Do not add new tiling types here. The I915_TILING_* values are for
1684 * de-tiling fence registers that no longer exist on modern platforms. Although
1685 * the hardware may support new types of tiling in general (e.g., Tile4), we
1686 * do not need to add them to the uapi that is specific to now-defunct ioctls.
1687 */
1688#define I915_TILING_LAST I915_TILING_Y
1689
1690#define I915_BIT_6_SWIZZLE_NONE 0
1691#define I915_BIT_6_SWIZZLE_9 1
1692#define I915_BIT_6_SWIZZLE_9_10 2
1693#define I915_BIT_6_SWIZZLE_9_11 3
1694#define I915_BIT_6_SWIZZLE_9_10_11 4
1695/* Not seen by userland */
1696#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1697/* Seen by userland. */
1698#define I915_BIT_6_SWIZZLE_9_17 6
1699#define I915_BIT_6_SWIZZLE_9_10_17 7
1700
1701struct drm_i915_gem_set_tiling {
1702 /** Handle of the buffer to have its tiling state updated */
1703 __u32 handle;
1704
1705 /**
1706 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1707 * I915_TILING_Y).
1708 *
1709 * This value is to be set on request, and will be updated by the
1710 * kernel on successful return with the actual chosen tiling layout.
1711 *
1712 * The tiling mode may be demoted to I915_TILING_NONE when the system
1713 * has bit 6 swizzling that can't be managed correctly by GEM.
1714 *
1715 * Buffer contents become undefined when changing tiling_mode.
1716 */
1717 __u32 tiling_mode;
1718
1719 /**
1720 * Stride in bytes for the object when in I915_TILING_X or
1721 * I915_TILING_Y.
1722 */
1723 __u32 stride;
1724
1725 /**
1726 * Returned address bit 6 swizzling required for CPU access through
1727 * mmap mapping.
1728 */
1729 __u32 swizzle_mode;
1730};
1731
1732struct drm_i915_gem_get_tiling {
1733 /** Handle of the buffer to get tiling state for. */
1734 __u32 handle;
1735
1736 /**
1737 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1738 * I915_TILING_Y).
1739 */
1740 __u32 tiling_mode;
1741
1742 /**
1743 * Returned address bit 6 swizzling required for CPU access through
1744 * mmap mapping.
1745 */
1746 __u32 swizzle_mode;
1747
1748 /**
1749 * Returned address bit 6 swizzling required for CPU access through
1750 * mmap mapping whilst bound.
1751 */
1752 __u32 phys_swizzle_mode;
1753};
1754
1755struct drm_i915_gem_get_aperture {
1756 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1757 __u64 aper_size;
1758
1759 /**
1760 * Available space in the aperture used by i915_gem_execbuffer, in
1761 * bytes
1762 */
1763 __u64 aper_available_size;
1764};
1765
1766struct drm_i915_get_pipe_from_crtc_id {
1767 /** ID of CRTC being requested **/
1768 __u32 crtc_id;
1769
1770 /** pipe of requested CRTC **/
1771 __u32 pipe;
1772};
1773
1774#define I915_MADV_WILLNEED 0
1775#define I915_MADV_DONTNEED 1
1776#define __I915_MADV_PURGED 2 /* internal state */
1777
1778struct drm_i915_gem_madvise {
1779 /** Handle of the buffer to change the backing store advice */
1780 __u32 handle;
1781
1782 /* Advice: either the buffer will be needed again in the near future,
1783 * or wont be and could be discarded under memory pressure.
1784 */
1785 __u32 madv;
1786
1787 /** Whether the backing store still exists. */
1788 __u32 retained;
1789};
1790
1791/* flags */
1792#define I915_OVERLAY_TYPE_MASK 0xff
1793#define I915_OVERLAY_YUV_PLANAR 0x01
1794#define I915_OVERLAY_YUV_PACKED 0x02
1795#define I915_OVERLAY_RGB 0x03
1796
1797#define I915_OVERLAY_DEPTH_MASK 0xff00
1798#define I915_OVERLAY_RGB24 0x1000
1799#define I915_OVERLAY_RGB16 0x2000
1800#define I915_OVERLAY_RGB15 0x3000
1801#define I915_OVERLAY_YUV422 0x0100
1802#define I915_OVERLAY_YUV411 0x0200
1803#define I915_OVERLAY_YUV420 0x0300
1804#define I915_OVERLAY_YUV410 0x0400
1805
1806#define I915_OVERLAY_SWAP_MASK 0xff0000
1807#define I915_OVERLAY_NO_SWAP 0x000000
1808#define I915_OVERLAY_UV_SWAP 0x010000
1809#define I915_OVERLAY_Y_SWAP 0x020000
1810#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1811
1812#define I915_OVERLAY_FLAGS_MASK 0xff000000
1813#define I915_OVERLAY_ENABLE 0x01000000
1814
1815struct drm_intel_overlay_put_image {
1816 /* various flags and src format description */
1817 __u32 flags;
1818 /* source picture description */
1819 __u32 bo_handle;
1820 /* stride values and offsets are in bytes, buffer relative */
1821 __u16 stride_Y; /* stride for packed formats */
1822 __u16 stride_UV;
1823 __u32 offset_Y; /* offset for packet formats */
1824 __u32 offset_U;
1825 __u32 offset_V;
1826 /* in pixels */
1827 __u16 src_width;
1828 __u16 src_height;
1829 /* to compensate the scaling factors for partially covered surfaces */
1830 __u16 src_scan_width;
1831 __u16 src_scan_height;
1832 /* output crtc description */
1833 __u32 crtc_id;
1834 __u16 dst_x;
1835 __u16 dst_y;
1836 __u16 dst_width;
1837 __u16 dst_height;
1838};
1839
1840/* flags */
1841#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1842#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1843#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1844struct drm_intel_overlay_attrs {
1845 __u32 flags;
1846 __u32 color_key;
1847 __s32 brightness;
1848 __u32 contrast;
1849 __u32 saturation;
1850 __u32 gamma0;
1851 __u32 gamma1;
1852 __u32 gamma2;
1853 __u32 gamma3;
1854 __u32 gamma4;
1855 __u32 gamma5;
1856};
1857
1858/*
1859 * Intel sprite handling
1860 *
1861 * Color keying works with a min/mask/max tuple. Both source and destination
1862 * color keying is allowed.
1863 *
1864 * Source keying:
1865 * Sprite pixels within the min & max values, masked against the color channels
1866 * specified in the mask field, will be transparent. All other pixels will
1867 * be displayed on top of the primary plane. For RGB surfaces, only the min
1868 * and mask fields will be used; ranged compares are not allowed.
1869 *
1870 * Destination keying:
1871 * Primary plane pixels that match the min value, masked against the color
1872 * channels specified in the mask field, will be replaced by corresponding
1873 * pixels from the sprite plane.
1874 *
1875 * Note that source & destination keying are exclusive; only one can be
1876 * active on a given plane.
1877 */
1878
1879#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1880 * flags==0 to disable colorkeying.
1881 */
1882#define I915_SET_COLORKEY_DESTINATION (1<<1)
1883#define I915_SET_COLORKEY_SOURCE (1<<2)
1884struct drm_intel_sprite_colorkey {
1885 __u32 plane_id;
1886 __u32 min_value;
1887 __u32 channel_mask;
1888 __u32 max_value;
1889 __u32 flags;
1890};
1891
1892struct drm_i915_gem_wait {
1893 /** Handle of BO we shall wait on */
1894 __u32 bo_handle;
1895 __u32 flags;
1896 /** Number of nanoseconds to wait, Returns time remaining. */
1897 __s64 timeout_ns;
1898};
1899
1900struct drm_i915_gem_context_create {
1901 __u32 ctx_id; /* output: id of new context*/
1902 __u32 pad;
1903};
1904
1905/**
1906 * struct drm_i915_gem_context_create_ext - Structure for creating contexts.
1907 */
1908struct drm_i915_gem_context_create_ext {
1909 /** @ctx_id: Id of the created context (output) */
1910 __u32 ctx_id;
1911
1912 /**
1913 * @flags: Supported flags are:
1914 *
1915 * I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:
1916 *
1917 * Extensions may be appended to this structure and driver must check
1918 * for those. See @extensions.
1919 *
1920 * I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE
1921 *
1922 * Created context will have single timeline.
1923 */
1924 __u32 flags;
1925#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1926#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1927#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1928 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1929
1930 /**
1931 * @extensions: Zero-terminated chain of extensions.
1932 *
1933 * I915_CONTEXT_CREATE_EXT_SETPARAM:
1934 * Context parameter to set or query during context creation.
1935 * See struct drm_i915_gem_context_create_ext_setparam.
1936 *
1937 * I915_CONTEXT_CREATE_EXT_CLONE:
1938 * This extension has been removed. On the off chance someone somewhere
1939 * has attempted to use it, never re-use this extension number.
1940 */
1941 __u64 extensions;
1942#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1943#define I915_CONTEXT_CREATE_EXT_CLONE 1
1944};
1945
1946/**
1947 * struct drm_i915_gem_context_param - Context parameter to set or query.
1948 */
1949struct drm_i915_gem_context_param {
1950 /** @ctx_id: Context id */
1951 __u32 ctx_id;
1952
1953 /** @size: Size of the parameter @value */
1954 __u32 size;
1955
1956 /** @param: Parameter to set or query */
1957 __u64 param;
1958#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1959/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
1960 * someone somewhere has attempted to use it, never re-use this context
1961 * param number.
1962 */
1963#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1964#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1965#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1966#define I915_CONTEXT_PARAM_BANNABLE 0x5
1967#define I915_CONTEXT_PARAM_PRIORITY 0x6
1968#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1969#define I915_CONTEXT_DEFAULT_PRIORITY 0
1970#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1971 /*
1972 * When using the following param, value should be a pointer to
1973 * drm_i915_gem_context_param_sseu.
1974 */
1975#define I915_CONTEXT_PARAM_SSEU 0x7
1976
1977/*
1978 * Not all clients may want to attempt automatic recover of a context after
1979 * a hang (for example, some clients may only submit very small incremental
1980 * batches relying on known logical state of previous batches which will never
1981 * recover correctly and each attempt will hang), and so would prefer that
1982 * the context is forever banned instead.
1983 *
1984 * If set to false (0), after a reset, subsequent (and in flight) rendering
1985 * from this context is discarded, and the client will need to create a new
1986 * context to use instead.
1987 *
1988 * If set to true (1), the kernel will automatically attempt to recover the
1989 * context by skipping the hanging batch and executing the next batch starting
1990 * from the default context state (discarding the incomplete logical context
1991 * state lost due to the reset).
1992 *
1993 * On creation, all new contexts are marked as recoverable.
1994 */
1995#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1996
1997 /*
1998 * The id of the associated virtual memory address space (ppGTT) of
1999 * this context. Can be retrieved and passed to another context
2000 * (on the same fd) for both to use the same ppGTT and so share
2001 * address layouts, and avoid reloading the page tables on context
2002 * switches between themselves.
2003 *
2004 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
2005 */
2006#define I915_CONTEXT_PARAM_VM 0x9
2007
2008/*
2009 * I915_CONTEXT_PARAM_ENGINES:
2010 *
2011 * Bind this context to operate on this subset of available engines. Henceforth,
2012 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
2013 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
2014 * and upwards. Slots 0...N are filled in using the specified (class, instance).
2015 * Use
2016 * engine_class: I915_ENGINE_CLASS_INVALID,
2017 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
2018 * to specify a gap in the array that can be filled in later, e.g. by a
2019 * virtual engine used for load balancing.
2020 *
2021 * Setting the number of engines bound to the context to 0, by passing a zero
2022 * sized argument, will revert back to default settings.
2023 *
2024 * See struct i915_context_param_engines.
2025 *
2026 * Extensions:
2027 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
2028 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
2029 * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
2030 */
2031#define I915_CONTEXT_PARAM_ENGINES 0xa
2032
2033/*
2034 * I915_CONTEXT_PARAM_PERSISTENCE:
2035 *
2036 * Allow the context and active rendering to survive the process until
2037 * completion. Persistence allows fire-and-forget clients to queue up a
2038 * bunch of work, hand the output over to a display server and then quit.
2039 * If the context is marked as not persistent, upon closing (either via
2040 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
2041 * or process termination), the context and any outstanding requests will be
2042 * cancelled (and exported fences for cancelled requests marked as -EIO).
2043 *
2044 * By default, new contexts allow persistence.
2045 */
2046#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
2047
2048/* This API has been removed. On the off chance someone somewhere has
2049 * attempted to use it, never re-use this context param number.
2050 */
2051#define I915_CONTEXT_PARAM_RINGSIZE 0xc
2052
2053/*
2054 * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
2055 *
2056 * Mark that the context makes use of protected content, which will result
2057 * in the context being invalidated when the protected content session is.
2058 * Given that the protected content session is killed on suspend, the device
2059 * is kept awake for the lifetime of a protected context, so the user should
2060 * make sure to dispose of them once done.
2061 * This flag can only be set at context creation time and, when set to true,
2062 * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
2063 * to false. This flag can't be set to true in conjunction with setting the
2064 * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
2065 *
2066 * .. code-block:: C
2067 *
2068 * struct drm_i915_gem_context_create_ext_setparam p_protected = {
2069 * .base = {
2070 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
2071 * },
2072 * .param = {
2073 * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
2074 * .value = 1,
2075 * }
2076 * };
2077 * struct drm_i915_gem_context_create_ext_setparam p_norecover = {
2078 * .base = {
2079 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
2080 * .next_extension = to_user_pointer(&p_protected),
2081 * },
2082 * .param = {
2083 * .param = I915_CONTEXT_PARAM_RECOVERABLE,
2084 * .value = 0,
2085 * }
2086 * };
2087 * struct drm_i915_gem_context_create_ext create = {
2088 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
2089 * .extensions = to_user_pointer(&p_norecover);
2090 * };
2091 *
2092 * ctx_id = gem_context_create_ext(drm_fd, &create);
2093 *
2094 * In addition to the normal failure cases, setting this flag during context
2095 * creation can result in the following errors:
2096 *
2097 * -ENODEV: feature not available
2098 * -EPERM: trying to mark a recoverable or not bannable context as protected
2099 */
2100#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
2101/* Must be kept compact -- no holes and well documented */
2102
2103 /** @value: Context parameter value to be set or queried */
2104 __u64 value;
2105};
2106
2107/*
2108 * Context SSEU programming
2109 *
2110 * It may be necessary for either functional or performance reason to configure
2111 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
2112 * Sub-slice/EU).
2113 *
2114 * This is done by configuring SSEU configuration using the below
2115 * @struct drm_i915_gem_context_param_sseu for every supported engine which
2116 * userspace intends to use.
2117 *
2118 * Not all GPUs or engines support this functionality in which case an error
2119 * code -ENODEV will be returned.
2120 *
2121 * Also, flexibility of possible SSEU configuration permutations varies between
2122 * GPU generations and software imposed limitations. Requesting such a
2123 * combination will return an error code of -EINVAL.
2124 *
2125 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
2126 * favour of a single global setting.
2127 */
2128struct drm_i915_gem_context_param_sseu {
2129 /*
2130 * Engine class & instance to be configured or queried.
2131 */
2132 struct i915_engine_class_instance engine;
2133
2134 /*
2135 * Unknown flags must be cleared to zero.
2136 */
2137 __u32 flags;
2138#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
2139
2140 /*
2141 * Mask of slices to enable for the context. Valid values are a subset
2142 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
2143 */
2144 __u64 slice_mask;
2145
2146 /*
2147 * Mask of subslices to enable for the context. Valid values are a
2148 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
2149 */
2150 __u64 subslice_mask;
2151
2152 /*
2153 * Minimum/Maximum number of EUs to enable per subslice for the
2154 * context. min_eus_per_subslice must be inferior or equal to
2155 * max_eus_per_subslice.
2156 */
2157 __u16 min_eus_per_subslice;
2158 __u16 max_eus_per_subslice;
2159
2160 /*
2161 * Unused for now. Must be cleared to zero.
2162 */
2163 __u32 rsvd;
2164};
2165
2166/**
2167 * DOC: Virtual Engine uAPI
2168 *
2169 * Virtual engine is a concept where userspace is able to configure a set of
2170 * physical engines, submit a batch buffer, and let the driver execute it on any
2171 * engine from the set as it sees fit.
2172 *
2173 * This is primarily useful on parts which have multiple instances of a same
2174 * class engine, like for example GT3+ Skylake parts with their two VCS engines.
2175 *
2176 * For instance userspace can enumerate all engines of a certain class using the
2177 * previously described `Engine Discovery uAPI`_. After that userspace can
2178 * create a GEM context with a placeholder slot for the virtual engine (using
2179 * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
2180 * and instance respectively) and finally using the
2181 * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
2182 * the same reserved slot.
2183 *
2184 * Example of creating a virtual engine and submitting a batch buffer to it:
2185 *
2186 * .. code-block:: C
2187 *
2188 * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
2189 * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
2190 * .engine_index = 0, // Place this virtual engine into engine map slot 0
2191 * .num_siblings = 2,
2192 * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
2193 * { I915_ENGINE_CLASS_VIDEO, 1 }, },
2194 * };
2195 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
2196 * .engines = { { I915_ENGINE_CLASS_INVALID,
2197 * I915_ENGINE_CLASS_INVALID_NONE } },
2198 * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
2199 * };
2200 * struct drm_i915_gem_context_create_ext_setparam p_engines = {
2201 * .base = {
2202 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
2203 * },
2204 * .param = {
2205 * .param = I915_CONTEXT_PARAM_ENGINES,
2206 * .value = to_user_pointer(&engines),
2207 * .size = sizeof(engines),
2208 * },
2209 * };
2210 * struct drm_i915_gem_context_create_ext create = {
2211 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
2212 * .extensions = to_user_pointer(&p_engines);
2213 * };
2214 *
2215 * ctx_id = gem_context_create_ext(drm_fd, &create);
2216 *
2217 * // Now we have created a GEM context with its engine map containing a
2218 * // single virtual engine. Submissions to this slot can go either to
2219 * // vcs0 or vcs1, depending on the load balancing algorithm used inside
2220 * // the driver. The load balancing is dynamic from one batch buffer to
2221 * // another and transparent to userspace.
2222 *
2223 * ...
2224 * execbuf.rsvd1 = ctx_id;
2225 * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
2226 * gem_execbuf(drm_fd, &execbuf);
2227 */
2228
2229/*
2230 * i915_context_engines_load_balance:
2231 *
2232 * Enable load balancing across this set of engines.
2233 *
2234 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
2235 * used will proxy the execbuffer request onto one of the set of engines
2236 * in such a way as to distribute the load evenly across the set.
2237 *
2238 * The set of engines must be compatible (e.g. the same HW class) as they
2239 * will share the same logical GPU context and ring.
2240 *
2241 * To intermix rendering with the virtual engine and direct rendering onto
2242 * the backing engines (bypassing the load balancing proxy), the context must
2243 * be defined to use a single timeline for all engines.
2244 */
2245struct i915_context_engines_load_balance {
2246 struct i915_user_extension base;
2247
2248 __u16 engine_index;
2249 __u16 num_siblings;
2250 __u32 flags; /* all undefined flags must be zero */
2251
2252 __u64 mbz64; /* reserved for future use; must be zero */
2253
2254 struct i915_engine_class_instance engines[];
2255} __attribute__((packed));
2256
2257#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
2258 struct i915_user_extension base; \
2259 __u16 engine_index; \
2260 __u16 num_siblings; \
2261 __u32 flags; \
2262 __u64 mbz64; \
2263 struct i915_engine_class_instance engines[N__]; \
2264} __attribute__((packed)) name__
2265
2266/*
2267 * i915_context_engines_bond:
2268 *
2269 * Constructed bonded pairs for execution within a virtual engine.
2270 *
2271 * All engines are equal, but some are more equal than others. Given
2272 * the distribution of resources in the HW, it may be preferable to run
2273 * a request on a given subset of engines in parallel to a request on a
2274 * specific engine. We enable this selection of engines within a virtual
2275 * engine by specifying bonding pairs, for any given master engine we will
2276 * only execute on one of the corresponding siblings within the virtual engine.
2277 *
2278 * To execute a request in parallel on the master engine and a sibling requires
2279 * coordination with a I915_EXEC_FENCE_SUBMIT.
2280 */
2281struct i915_context_engines_bond {
2282 struct i915_user_extension base;
2283
2284 struct i915_engine_class_instance master;
2285
2286 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
2287 __u16 num_bonds;
2288
2289 __u64 flags; /* all undefined flags must be zero */
2290 __u64 mbz64[4]; /* reserved for future use; must be zero */
2291
2292 struct i915_engine_class_instance engines[];
2293} __attribute__((packed));
2294
2295#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
2296 struct i915_user_extension base; \
2297 struct i915_engine_class_instance master; \
2298 __u16 virtual_index; \
2299 __u16 num_bonds; \
2300 __u64 flags; \
2301 __u64 mbz64[4]; \
2302 struct i915_engine_class_instance engines[N__]; \
2303} __attribute__((packed)) name__
2304
2305/**
2306 * struct i915_context_engines_parallel_submit - Configure engine for
2307 * parallel submission.
2308 *
2309 * Setup a slot in the context engine map to allow multiple BBs to be submitted
2310 * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
2311 * in parallel. Multiple hardware contexts are created internally in the i915 to
2312 * run these BBs. Once a slot is configured for N BBs only N BBs can be
2313 * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
2314 * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
2315 * many BBs there are based on the slot's configuration. The N BBs are the last
2316 * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
2317 *
2318 * The default placement behavior is to create implicit bonds between each
2319 * context if each context maps to more than 1 physical engine (e.g. context is
2320 * a virtual engine). Also we only allow contexts of same engine class and these
2321 * contexts must be in logically contiguous order. Examples of the placement
2322 * behavior are described below. Lastly, the default is to not allow BBs to be
2323 * preempted mid-batch. Rather insert coordinated preemption points on all
2324 * hardware contexts between each set of BBs. Flags could be added in the future
2325 * to change both of these default behaviors.
2326 *
2327 * Returns -EINVAL if hardware context placement configuration is invalid or if
2328 * the placement configuration isn't supported on the platform / submission
2329 * interface.
2330 * Returns -ENODEV if extension isn't supported on the platform / submission
2331 * interface.
2332 *
2333 * .. code-block:: none
2334 *
2335 * Examples syntax:
2336 * CS[X] = generic engine of same class, logical instance X
2337 * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
2338 *
2339 * Example 1 pseudo code:
2340 * set_engines(INVALID)
2341 * set_parallel(engine_index=0, width=2, num_siblings=1,
2342 * engines=CS[0],CS[1])
2343 *
2344 * Results in the following valid placement:
2345 * CS[0], CS[1]
2346 *
2347 * Example 2 pseudo code:
2348 * set_engines(INVALID)
2349 * set_parallel(engine_index=0, width=2, num_siblings=2,
2350 * engines=CS[0],CS[2],CS[1],CS[3])
2351 *
2352 * Results in the following valid placements:
2353 * CS[0], CS[1]
2354 * CS[2], CS[3]
2355 *
2356 * This can be thought of as two virtual engines, each containing two
2357 * engines thereby making a 2D array. However, there are bonds tying the
2358 * entries together and placing restrictions on how they can be scheduled.
2359 * Specifically, the scheduler can choose only vertical columns from the 2D
2360 * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
2361 * scheduler wants to submit to CS[0], it must also choose CS[1] and vice
2362 * versa. Same for CS[2] requires also using CS[3].
2363 * VE[0] = CS[0], CS[2]
2364 * VE[1] = CS[1], CS[3]
2365 *
2366 * Example 3 pseudo code:
2367 * set_engines(INVALID)
2368 * set_parallel(engine_index=0, width=2, num_siblings=2,
2369 * engines=CS[0],CS[1],CS[1],CS[3])
2370 *
2371 * Results in the following valid and invalid placements:
2372 * CS[0], CS[1]
2373 * CS[1], CS[3] - Not logically contiguous, return -EINVAL
2374 */
2375struct i915_context_engines_parallel_submit {
2376 /**
2377 * @base: base user extension.
2378 */
2379 struct i915_user_extension base;
2380
2381 /**
2382 * @engine_index: slot for parallel engine
2383 */
2384 __u16 engine_index;
2385
2386 /**
2387 * @width: number of contexts per parallel engine or in other words the
2388 * number of batches in each submission
2389 */
2390 __u16 width;
2391
2392 /**
2393 * @num_siblings: number of siblings per context or in other words the
2394 * number of possible placements for each submission
2395 */
2396 __u16 num_siblings;
2397
2398 /**
2399 * @mbz16: reserved for future use; must be zero
2400 */
2401 __u16 mbz16;
2402
2403 /**
2404 * @flags: all undefined flags must be zero, currently not defined flags
2405 */
2406 __u64 flags;
2407
2408 /**
2409 * @mbz64: reserved for future use; must be zero
2410 */
2411 __u64 mbz64[3];
2412
2413 /**
2414 * @engines: 2-d array of engine instances to configure parallel engine
2415 *
2416 * length = width (i) * num_siblings (j)
2417 * index = j + i * num_siblings
2418 */
2419 struct i915_engine_class_instance engines[];
2420
2421} __packed;
2422
2423#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
2424 struct i915_user_extension base; \
2425 __u16 engine_index; \
2426 __u16 width; \
2427 __u16 num_siblings; \
2428 __u16 mbz16; \
2429 __u64 flags; \
2430 __u64 mbz64[3]; \
2431 struct i915_engine_class_instance engines[N__]; \
2432} __attribute__((packed)) name__
2433
2434/**
2435 * DOC: Context Engine Map uAPI
2436 *
2437 * Context engine map is a new way of addressing engines when submitting batch-
2438 * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
2439 * inside the flags field of `struct drm_i915_gem_execbuffer2`.
2440 *
2441 * To use it created GEM contexts need to be configured with a list of engines
2442 * the user is intending to submit to. This is accomplished using the
2443 * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
2444 * i915_context_param_engines`.
2445 *
2446 * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
2447 * configured map.
2448 *
2449 * Example of creating such context and submitting against it:
2450 *
2451 * .. code-block:: C
2452 *
2453 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
2454 * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
2455 * { I915_ENGINE_CLASS_COPY, 0 } }
2456 * };
2457 * struct drm_i915_gem_context_create_ext_setparam p_engines = {
2458 * .base = {
2459 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
2460 * },
2461 * .param = {
2462 * .param = I915_CONTEXT_PARAM_ENGINES,
2463 * .value = to_user_pointer(&engines),
2464 * .size = sizeof(engines),
2465 * },
2466 * };
2467 * struct drm_i915_gem_context_create_ext create = {
2468 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
2469 * .extensions = to_user_pointer(&p_engines);
2470 * };
2471 *
2472 * ctx_id = gem_context_create_ext(drm_fd, &create);
2473 *
2474 * // We have now created a GEM context with two engines in the map:
2475 * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
2476 * // will not be accessible from this context.
2477 *
2478 * ...
2479 * execbuf.rsvd1 = ctx_id;
2480 * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
2481 * gem_execbuf(drm_fd, &execbuf);
2482 *
2483 * ...
2484 * execbuf.rsvd1 = ctx_id;
2485 * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
2486 * gem_execbuf(drm_fd, &execbuf);
2487 */
2488
2489struct i915_context_param_engines {
2490 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
2491#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
2492#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
2493#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
2494 struct i915_engine_class_instance engines[0];
2495} __attribute__((packed));
2496
2497#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
2498 __u64 extensions; \
2499 struct i915_engine_class_instance engines[N__]; \
2500} __attribute__((packed)) name__
2501
2502/**
2503 * struct drm_i915_gem_context_create_ext_setparam - Context parameter
2504 * to set or query during context creation.
2505 */
2506struct drm_i915_gem_context_create_ext_setparam {
2507 /** @base: Extension link. See struct i915_user_extension. */
2508 struct i915_user_extension base;
2509
2510 /**
2511 * @param: Context parameter to set or query.
2512 * See struct drm_i915_gem_context_param.
2513 */
2514 struct drm_i915_gem_context_param param;
2515};
2516
2517struct drm_i915_gem_context_destroy {
2518 __u32 ctx_id;
2519 __u32 pad;
2520};
2521
2522/**
2523 * struct drm_i915_gem_vm_control - Structure to create or destroy VM.
2524 *
2525 * DRM_I915_GEM_VM_CREATE -
2526 *
2527 * Create a new virtual memory address space (ppGTT) for use within a context
2528 * on the same file. Extensions can be provided to configure exactly how the
2529 * address space is setup upon creation.
2530 *
2531 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
2532 * returned in the outparam @id.
2533 *
2534 * An extension chain maybe provided, starting with @extensions, and terminated
2535 * by the @next_extension being 0. Currently, no extensions are defined.
2536 *
2537 * DRM_I915_GEM_VM_DESTROY -
2538 *
2539 * Destroys a previously created VM id, specified in @vm_id.
2540 *
2541 * No extensions or flags are allowed currently, and so must be zero.
2542 */
2543struct drm_i915_gem_vm_control {
2544 /** @extensions: Zero-terminated chain of extensions. */
2545 __u64 extensions;
2546
2547 /** @flags: reserved for future usage, currently MBZ */
2548 __u32 flags;
2549
2550 /** @vm_id: Id of the VM created or to be destroyed */
2551 __u32 vm_id;
2552};
2553
2554struct drm_i915_reg_read {
2555 /*
2556 * Register offset.
2557 * For 64bit wide registers where the upper 32bits don't immediately
2558 * follow the lower 32bits, the offset of the lower 32bits must
2559 * be specified
2560 */
2561 __u64 offset;
2562#define I915_REG_READ_8B_WA (1ul << 0)
2563
2564 __u64 val; /* Return value */
2565};
2566
2567/* Known registers:
2568 *
2569 * Render engine timestamp - 0x2358 + 64bit - gen7+
2570 * - Note this register returns an invalid value if using the default
2571 * single instruction 8byte read, in order to workaround that pass
2572 * flag I915_REG_READ_8B_WA in offset field.
2573 *
2574 */
2575
2576struct drm_i915_reset_stats {
2577 __u32 ctx_id;
2578 __u32 flags;
2579
2580 /* All resets since boot/module reload, for all contexts */
2581 __u32 reset_count;
2582
2583 /* Number of batches lost when active in GPU, for this context */
2584 __u32 batch_active;
2585
2586 /* Number of batches lost pending for execution, for this context */
2587 __u32 batch_pending;
2588
2589 __u32 pad;
2590};
2591
2592/**
2593 * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
2594 *
2595 * Userptr objects have several restrictions on what ioctls can be used with the
2596 * object handle.
2597 */
2598struct drm_i915_gem_userptr {
2599 /**
2600 * @user_ptr: The pointer to the allocated memory.
2601 *
2602 * Needs to be aligned to PAGE_SIZE.
2603 */
2604 __u64 user_ptr;
2605
2606 /**
2607 * @user_size:
2608 *
2609 * The size in bytes for the allocated memory. This will also become the
2610 * object size.
2611 *
2612 * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
2613 * or larger.
2614 */
2615 __u64 user_size;
2616
2617 /**
2618 * @flags:
2619 *
2620 * Supported flags:
2621 *
2622 * I915_USERPTR_READ_ONLY:
2623 *
2624 * Mark the object as readonly, this also means GPU access can only be
2625 * readonly. This is only supported on HW which supports readonly access
2626 * through the GTT. If the HW can't support readonly access, an error is
2627 * returned.
2628 *
2629 * I915_USERPTR_PROBE:
2630 *
2631 * Probe the provided @user_ptr range and validate that the @user_ptr is
2632 * indeed pointing to normal memory and that the range is also valid.
2633 * For example if some garbage address is given to the kernel, then this
2634 * should complain.
2635 *
2636 * Returns -EFAULT if the probe failed.
2637 *
2638 * Note that this doesn't populate the backing pages, and also doesn't
2639 * guarantee that the object will remain valid when the object is
2640 * eventually used.
2641 *
2642 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
2643 * returns a non-zero value.
2644 *
2645 * I915_USERPTR_UNSYNCHRONIZED:
2646 *
2647 * NOT USED. Setting this flag will result in an error.
2648 */
2649 __u32 flags;
2650#define I915_USERPTR_READ_ONLY 0x1
2651#define I915_USERPTR_PROBE 0x2
2652#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
2653 /**
2654 * @handle: Returned handle for the object.
2655 *
2656 * Object handles are nonzero.
2657 */
2658 __u32 handle;
2659};
2660
2661enum drm_i915_oa_format {
2662 I915_OA_FORMAT_A13 = 1, /* HSW only */
2663 I915_OA_FORMAT_A29, /* HSW only */
2664 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
2665 I915_OA_FORMAT_B4_C8, /* HSW only */
2666 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
2667 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
2668 I915_OA_FORMAT_C4_B8, /* HSW+ */
2669
2670 /* Gen8+ */
2671 I915_OA_FORMAT_A12,
2672 I915_OA_FORMAT_A12_B8_C8,
2673 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
2674
2675 /* DG2 */
2676 I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
2677 I915_OA_FORMAT_A24u40_A14u32_B8_C8,
2678
2679 I915_OA_FORMAT_MAX /* non-ABI */
2680};
2681
2682enum drm_i915_perf_property_id {
2683 /**
2684 * Open the stream for a specific context handle (as used with
2685 * execbuffer2). A stream opened for a specific context this way
2686 * won't typically require root privileges.
2687 *
2688 * This property is available in perf revision 1.
2689 */
2690 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
2691
2692 /**
2693 * A value of 1 requests the inclusion of raw OA unit reports as
2694 * part of stream samples.
2695 *
2696 * This property is available in perf revision 1.
2697 */
2698 DRM_I915_PERF_PROP_SAMPLE_OA,
2699
2700 /**
2701 * The value specifies which set of OA unit metrics should be
2702 * configured, defining the contents of any OA unit reports.
2703 *
2704 * This property is available in perf revision 1.
2705 */
2706 DRM_I915_PERF_PROP_OA_METRICS_SET,
2707
2708 /**
2709 * The value specifies the size and layout of OA unit reports.
2710 *
2711 * This property is available in perf revision 1.
2712 */
2713 DRM_I915_PERF_PROP_OA_FORMAT,
2714
2715 /**
2716 * Specifying this property implicitly requests periodic OA unit
2717 * sampling and (at least on Haswell) the sampling frequency is derived
2718 * from this exponent as follows:
2719 *
2720 * 80ns * 2^(period_exponent + 1)
2721 *
2722 * This property is available in perf revision 1.
2723 */
2724 DRM_I915_PERF_PROP_OA_EXPONENT,
2725
2726 /**
2727 * Specifying this property is only valid when specify a context to
2728 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
2729 * will hold preemption of the particular context we want to gather
2730 * performance data about. The execbuf2 submissions must include a
2731 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
2732 *
2733 * This property is available in perf revision 3.
2734 */
2735 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
2736
2737 /**
2738 * Specifying this pins all contexts to the specified SSEU power
2739 * configuration for the duration of the recording.
2740 *
2741 * This parameter's value is a pointer to a struct
2742 * drm_i915_gem_context_param_sseu.
2743 *
2744 * This property is available in perf revision 4.
2745 */
2746 DRM_I915_PERF_PROP_GLOBAL_SSEU,
2747
2748 /**
2749 * This optional parameter specifies the timer interval in nanoseconds
2750 * at which the i915 driver will check the OA buffer for available data.
2751 * Minimum allowed value is 100 microseconds. A default value is used by
2752 * the driver if this parameter is not specified. Note that larger timer
2753 * values will reduce cpu consumption during OA perf captures. However,
2754 * excessively large values would potentially result in OA buffer
2755 * overwrites as captures reach end of the OA buffer.
2756 *
2757 * This property is available in perf revision 5.
2758 */
2759 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
2760
2761 DRM_I915_PERF_PROP_MAX /* non-ABI */
2762};
2763
2764struct drm_i915_perf_open_param {
2765 __u32 flags;
2766#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2767#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2768#define I915_PERF_FLAG_DISABLED (1<<2)
2769
2770 /** The number of u64 (id, value) pairs */
2771 __u32 num_properties;
2772
2773 /**
2774 * Pointer to array of u64 (id, value) pairs configuring the stream
2775 * to open.
2776 */
2777 __u64 properties_ptr;
2778};
2779
2780/*
2781 * Enable data capture for a stream that was either opened in a disabled state
2782 * via I915_PERF_FLAG_DISABLED or was later disabled via
2783 * I915_PERF_IOCTL_DISABLE.
2784 *
2785 * It is intended to be cheaper to disable and enable a stream than it may be
2786 * to close and re-open a stream with the same configuration.
2787 *
2788 * It's undefined whether any pending data for the stream will be lost.
2789 *
2790 * This ioctl is available in perf revision 1.
2791 */
2792#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2793
2794/*
2795 * Disable data capture for a stream.
2796 *
2797 * It is an error to try and read a stream that is disabled.
2798 *
2799 * This ioctl is available in perf revision 1.
2800 */
2801#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2802
2803/*
2804 * Change metrics_set captured by a stream.
2805 *
2806 * If the stream is bound to a specific context, the configuration change
2807 * will performed inline with that context such that it takes effect before
2808 * the next execbuf submission.
2809 *
2810 * Returns the previously bound metrics set id, or a negative error code.
2811 *
2812 * This ioctl is available in perf revision 2.
2813 */
2814#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2815
2816/*
2817 * Common to all i915 perf records
2818 */
2819struct drm_i915_perf_record_header {
2820 __u32 type;
2821 __u16 pad;
2822 __u16 size;
2823};
2824
2825enum drm_i915_perf_record_type {
2826
2827 /**
2828 * Samples are the work horse record type whose contents are extensible
2829 * and defined when opening an i915 perf stream based on the given
2830 * properties.
2831 *
2832 * Boolean properties following the naming convention
2833 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2834 * every sample.
2835 *
2836 * The order of these sample properties given by userspace has no
2837 * affect on the ordering of data within a sample. The order is
2838 * documented here.
2839 *
2840 * struct {
2841 * struct drm_i915_perf_record_header header;
2842 *
2843 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2844 * };
2845 */
2846 DRM_I915_PERF_RECORD_SAMPLE = 1,
2847
2848 /*
2849 * Indicates that one or more OA reports were not written by the
2850 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2851 * command collides with periodic sampling - which would be more likely
2852 * at higher sampling frequencies.
2853 */
2854 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2855
2856 /**
2857 * An error occurred that resulted in all pending OA reports being lost.
2858 */
2859 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2860
2861 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2862};
2863
2864/**
2865 * struct drm_i915_perf_oa_config
2866 *
2867 * Structure to upload perf dynamic configuration into the kernel.
2868 */
2869struct drm_i915_perf_oa_config {
2870 /**
2871 * @uuid:
2872 *
2873 * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
2874 */
2875 char uuid[36];
2876
2877 /**
2878 * @n_mux_regs:
2879 *
2880 * Number of mux regs in &mux_regs_ptr.
2881 */
2882 __u32 n_mux_regs;
2883
2884 /**
2885 * @n_boolean_regs:
2886 *
2887 * Number of boolean regs in &boolean_regs_ptr.
2888 */
2889 __u32 n_boolean_regs;
2890
2891 /**
2892 * @n_flex_regs:
2893 *
2894 * Number of flex regs in &flex_regs_ptr.
2895 */
2896 __u32 n_flex_regs;
2897
2898 /**
2899 * @mux_regs_ptr:
2900 *
2901 * Pointer to tuples of u32 values (register address, value) for mux
2902 * registers. Expected length of buffer is (2 * sizeof(u32) *
2903 * &n_mux_regs).
2904 */
2905 __u64 mux_regs_ptr;
2906
2907 /**
2908 * @boolean_regs_ptr:
2909 *
2910 * Pointer to tuples of u32 values (register address, value) for mux
2911 * registers. Expected length of buffer is (2 * sizeof(u32) *
2912 * &n_boolean_regs).
2913 */
2914 __u64 boolean_regs_ptr;
2915
2916 /**
2917 * @flex_regs_ptr:
2918 *
2919 * Pointer to tuples of u32 values (register address, value) for mux
2920 * registers. Expected length of buffer is (2 * sizeof(u32) *
2921 * &n_flex_regs).
2922 */
2923 __u64 flex_regs_ptr;
2924};
2925
2926/**
2927 * struct drm_i915_query_item - An individual query for the kernel to process.
2928 *
2929 * The behaviour is determined by the @query_id. Note that exactly what
2930 * @data_ptr is also depends on the specific @query_id.
2931 */
2932struct drm_i915_query_item {
2933 /**
2934 * @query_id:
2935 *
2936 * The id for this query. Currently accepted query IDs are:
2937 * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
2938 * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
2939 * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
2940 * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
2941 * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
2942 * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
2943 */
2944 __u64 query_id;
2945#define DRM_I915_QUERY_TOPOLOGY_INFO 1
2946#define DRM_I915_QUERY_ENGINE_INFO 2
2947#define DRM_I915_QUERY_PERF_CONFIG 3
2948#define DRM_I915_QUERY_MEMORY_REGIONS 4
2949#define DRM_I915_QUERY_HWCONFIG_BLOB 5
2950#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
2951/* Must be kept compact -- no holes and well documented */
2952
2953 /**
2954 * @length:
2955 *
2956 * When set to zero by userspace, this is filled with the size of the
2957 * data to be written at the @data_ptr pointer. The kernel sets this
2958 * value to a negative value to signal an error on a particular query
2959 * item.
2960 */
2961 __s32 length;
2962
2963 /**
2964 * @flags:
2965 *
2966 * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2967 *
2968 * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
2969 * following:
2970 *
2971 * - %DRM_I915_QUERY_PERF_CONFIG_LIST
2972 * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2973 * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2974 *
2975 * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
2976 * a struct i915_engine_class_instance that references a render engine.
2977 */
2978 __u32 flags;
2979#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2980#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2981#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2982
2983 /**
2984 * @data_ptr:
2985 *
2986 * Data will be written at the location pointed by @data_ptr when the
2987 * value of @length matches the length of the data to be written by the
2988 * kernel.
2989 */
2990 __u64 data_ptr;
2991};
2992
2993/**
2994 * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
2995 * kernel to fill out.
2996 *
2997 * Note that this is generally a two step process for each struct
2998 * drm_i915_query_item in the array:
2999 *
3000 * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
3001 * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
3002 * kernel will then fill in the size, in bytes, which tells userspace how
3003 * memory it needs to allocate for the blob(say for an array of properties).
3004 *
3005 * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
3006 * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
3007 * the &drm_i915_query_item.length should still be the same as what the
3008 * kernel previously set. At this point the kernel can fill in the blob.
3009 *
3010 * Note that for some query items it can make sense for userspace to just pass
3011 * in a buffer/blob equal to or larger than the required size. In this case only
3012 * a single ioctl call is needed. For some smaller query items this can work
3013 * quite well.
3014 *
3015 */
3016struct drm_i915_query {
3017 /** @num_items: The number of elements in the @items_ptr array */
3018 __u32 num_items;
3019
3020 /**
3021 * @flags: Unused for now. Must be cleared to zero.
3022 */
3023 __u32 flags;
3024
3025 /**
3026 * @items_ptr:
3027 *
3028 * Pointer to an array of struct drm_i915_query_item. The number of
3029 * array elements is @num_items.
3030 */
3031 __u64 items_ptr;
3032};
3033
3034/**
3035 * struct drm_i915_query_topology_info
3036 *
3037 * Describes slice/subslice/EU information queried by
3038 * %DRM_I915_QUERY_TOPOLOGY_INFO
3039 */
3040struct drm_i915_query_topology_info {
3041 /**
3042 * @flags:
3043 *
3044 * Unused for now. Must be cleared to zero.
3045 */
3046 __u16 flags;
3047
3048 /**
3049 * @max_slices:
3050 *
3051 * The number of bits used to express the slice mask.
3052 */
3053 __u16 max_slices;
3054
3055 /**
3056 * @max_subslices:
3057 *
3058 * The number of bits used to express the subslice mask.
3059 */
3060 __u16 max_subslices;
3061
3062 /**
3063 * @max_eus_per_subslice:
3064 *
3065 * The number of bits in the EU mask that correspond to a single
3066 * subslice's EUs.
3067 */
3068 __u16 max_eus_per_subslice;
3069
3070 /**
3071 * @subslice_offset:
3072 *
3073 * Offset in data[] at which the subslice masks are stored.
3074 */
3075 __u16 subslice_offset;
3076
3077 /**
3078 * @subslice_stride:
3079 *
3080 * Stride at which each of the subslice masks for each slice are
3081 * stored.
3082 */
3083 __u16 subslice_stride;
3084
3085 /**
3086 * @eu_offset:
3087 *
3088 * Offset in data[] at which the EU masks are stored.
3089 */
3090 __u16 eu_offset;
3091
3092 /**
3093 * @eu_stride:
3094 *
3095 * Stride at which each of the EU masks for each subslice are stored.
3096 */
3097 __u16 eu_stride;
3098
3099 /**
3100 * @data:
3101 *
3102 * Contains 3 pieces of information :
3103 *
3104 * - The slice mask with one bit per slice telling whether a slice is
3105 * available. The availability of slice X can be queried with the
3106 * following formula :
3107 *
3108 * .. code:: c
3109 *
3110 * (data[X / 8] >> (X % 8)) & 1
3111 *
3112 * Starting with Xe_HP platforms, Intel hardware no longer has
3113 * traditional slices so i915 will always report a single slice
3114 * (hardcoded slicemask = 0x1) which contains all of the platform's
3115 * subslices. I.e., the mask here does not reflect any of the newer
3116 * hardware concepts such as "gslices" or "cslices" since userspace
3117 * is capable of inferring those from the subslice mask.
3118 *
3119 * - The subslice mask for each slice with one bit per subslice telling
3120 * whether a subslice is available. Starting with Gen12 we use the
3121 * term "subslice" to refer to what the hardware documentation
3122 * describes as a "dual-subslices." The availability of subslice Y
3123 * in slice X can be queried with the following formula :
3124 *
3125 * .. code:: c
3126 *
3127 * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
3128 *
3129 * - The EU mask for each subslice in each slice, with one bit per EU
3130 * telling whether an EU is available. The availability of EU Z in
3131 * subslice Y in slice X can be queried with the following formula :
3132 *
3133 * .. code:: c
3134 *
3135 * (data[eu_offset +
3136 * (X * max_subslices + Y) * eu_stride +
3137 * Z / 8
3138 * ] >> (Z % 8)) & 1
3139 */
3140 __u8 data[];
3141};
3142
3143/**
3144 * DOC: Engine Discovery uAPI
3145 *
3146 * Engine discovery uAPI is a way of enumerating physical engines present in a
3147 * GPU associated with an open i915 DRM file descriptor. This supersedes the old
3148 * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
3149 * `I915_PARAM_HAS_BLT`.
3150 *
3151 * The need for this interface came starting with Icelake and newer GPUs, which
3152 * started to establish a pattern of having multiple engines of a same class,
3153 * where not all instances were always completely functionally equivalent.
3154 *
3155 * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
3156 * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
3157 *
3158 * Example for getting the list of engines:
3159 *
3160 * .. code-block:: C
3161 *
3162 * struct drm_i915_query_engine_info *info;
3163 * struct drm_i915_query_item item = {
3164 * .query_id = DRM_I915_QUERY_ENGINE_INFO;
3165 * };
3166 * struct drm_i915_query query = {
3167 * .num_items = 1,
3168 * .items_ptr = (uintptr_t)&item,
3169 * };
3170 * int err, i;
3171 *
3172 * // First query the size of the blob we need, this needs to be large
3173 * // enough to hold our array of engines. The kernel will fill out the
3174 * // item.length for us, which is the number of bytes we need.
3175 * //
3176 * // Alternatively a large buffer can be allocated straight away enabling
3177 * // querying in one pass, in which case item.length should contain the
3178 * // length of the provided buffer.
3179 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
3180 * if (err) ...
3181 *
3182 * info = calloc(1, item.length);
3183 * // Now that we allocated the required number of bytes, we call the ioctl
3184 * // again, this time with the data_ptr pointing to our newly allocated
3185 * // blob, which the kernel can then populate with info on all engines.
3186 * item.data_ptr = (uintptr_t)&info,
3187 *
3188 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
3189 * if (err) ...
3190 *
3191 * // We can now access each engine in the array
3192 * for (i = 0; i < info->num_engines; i++) {
3193 * struct drm_i915_engine_info einfo = info->engines[i];
3194 * u16 class = einfo.engine.class;
3195 * u16 instance = einfo.engine.instance;
3196 * ....
3197 * }
3198 *
3199 * free(info);
3200 *
3201 * Each of the enumerated engines, apart from being defined by its class and
3202 * instance (see `struct i915_engine_class_instance`), also can have flags and
3203 * capabilities defined as documented in i915_drm.h.
3204 *
3205 * For instance video engines which support HEVC encoding will have the
3206 * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
3207 *
3208 * Engine discovery only fully comes to its own when combined with the new way
3209 * of addressing engines when submitting batch buffers using contexts with
3210 * engine maps configured.
3211 */
3212
3213/**
3214 * struct drm_i915_engine_info
3215 *
3216 * Describes one engine and it's capabilities as known to the driver.
3217 */
3218struct drm_i915_engine_info {
3219 /** @engine: Engine class and instance. */
3220 struct i915_engine_class_instance engine;
3221
3222 /** @rsvd0: Reserved field. */
3223 __u32 rsvd0;
3224
3225 /** @flags: Engine flags. */
3226 __u64 flags;
3227#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
3228
3229 /** @capabilities: Capabilities of this engine. */
3230 __u64 capabilities;
3231#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
3232#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
3233
3234 /** @logical_instance: Logical instance of engine */
3235 __u16 logical_instance;
3236
3237 /** @rsvd1: Reserved fields. */
3238 __u16 rsvd1[3];
3239 /** @rsvd2: Reserved fields. */
3240 __u64 rsvd2[3];
3241};
3242
3243/**
3244 * struct drm_i915_query_engine_info
3245 *
3246 * Engine info query enumerates all engines known to the driver by filling in
3247 * an array of struct drm_i915_engine_info structures.
3248 */
3249struct drm_i915_query_engine_info {
3250 /** @num_engines: Number of struct drm_i915_engine_info structs following. */
3251 __u32 num_engines;
3252
3253 /** @rsvd: MBZ */
3254 __u32 rsvd[3];
3255
3256 /** @engines: Marker for drm_i915_engine_info structures. */
3257 struct drm_i915_engine_info engines[];
3258};
3259
3260/**
3261 * struct drm_i915_query_perf_config
3262 *
3263 * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
3264 * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
3265 */
3266struct drm_i915_query_perf_config {
3267 union {
3268 /**
3269 * @n_configs:
3270 *
3271 * When &drm_i915_query_item.flags ==
3272 * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
3273 * the number of configurations available.
3274 */
3275 __u64 n_configs;
3276
3277 /**
3278 * @config:
3279 *
3280 * When &drm_i915_query_item.flags ==
3281 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
3282 * value in this field as configuration identifier to decide
3283 * what data to write into config_ptr.
3284 */
3285 __u64 config;
3286
3287 /**
3288 * @uuid:
3289 *
3290 * When &drm_i915_query_item.flags ==
3291 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
3292 * value in this field as configuration identifier to decide
3293 * what data to write into config_ptr.
3294 *
3295 * String formatted like "%08x-%04x-%04x-%04x-%012x"
3296 */
3297 char uuid[36];
3298 };
3299
3300 /**
3301 * @flags:
3302 *
3303 * Unused for now. Must be cleared to zero.
3304 */
3305 __u32 flags;
3306
3307 /**
3308 * @data:
3309 *
3310 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
3311 * i915 will write an array of __u64 of configuration identifiers.
3312 *
3313 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
3314 * i915 will write a struct drm_i915_perf_oa_config. If the following
3315 * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
3316 * write into the associated pointers the values of submitted when the
3317 * configuration was created :
3318 *
3319 * - &drm_i915_perf_oa_config.n_mux_regs
3320 * - &drm_i915_perf_oa_config.n_boolean_regs
3321 * - &drm_i915_perf_oa_config.n_flex_regs
3322 */
3323 __u8 data[];
3324};
3325
3326/**
3327 * enum drm_i915_gem_memory_class - Supported memory classes
3328 */
3329enum drm_i915_gem_memory_class {
3330 /** @I915_MEMORY_CLASS_SYSTEM: System memory */
3331 I915_MEMORY_CLASS_SYSTEM = 0,
3332 /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
3333 I915_MEMORY_CLASS_DEVICE,
3334};
3335
3336/**
3337 * struct drm_i915_gem_memory_class_instance - Identify particular memory region
3338 */
3339struct drm_i915_gem_memory_class_instance {
3340 /** @memory_class: See enum drm_i915_gem_memory_class */
3341 __u16 memory_class;
3342
3343 /** @memory_instance: Which instance */
3344 __u16 memory_instance;
3345};
3346
3347/**
3348 * struct drm_i915_memory_region_info - Describes one region as known to the
3349 * driver.
3350 *
3351 * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
3352 * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
3353 * at &drm_i915_query_item.query_id.
3354 */
3355struct drm_i915_memory_region_info {
3356 /** @region: The class:instance pair encoding */
3357 struct drm_i915_gem_memory_class_instance region;
3358
3359 /** @rsvd0: MBZ */
3360 __u32 rsvd0;
3361
3362 /**
3363 * @probed_size: Memory probed by the driver
3364 *
3365 * Note that it should not be possible to ever encounter a zero value
3366 * here, also note that no current region type will ever return -1 here.
3367 * Although for future region types, this might be a possibility. The
3368 * same applies to the other size fields.
3369 */
3370 __u64 probed_size;
3371
3372 /**
3373 * @unallocated_size: Estimate of memory remaining
3374 *
3375 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting.
3376 * Without this (or if this is an older kernel) the value here will
3377 * always equal the @probed_size. Note this is only currently tracked
3378 * for I915_MEMORY_CLASS_DEVICE regions (for other types the value here
3379 * will always equal the @probed_size).
3380 */
3381 __u64 unallocated_size;
3382
3383 union {
3384 /** @rsvd1: MBZ */
3385 __u64 rsvd1[8];
3386 struct {
3387 /**
3388 * @probed_cpu_visible_size: Memory probed by the driver
3389 * that is CPU accessible.
3390 *
3391 * This will be always be <= @probed_size, and the
3392 * remainder (if there is any) will not be CPU
3393 * accessible.
3394 *
3395 * On systems without small BAR, the @probed_size will
3396 * always equal the @probed_cpu_visible_size, since all
3397 * of it will be CPU accessible.
3398 *
3399 * Note this is only tracked for
3400 * I915_MEMORY_CLASS_DEVICE regions (for other types the
3401 * value here will always equal the @probed_size).
3402 *
3403 * Note that if the value returned here is zero, then
3404 * this must be an old kernel which lacks the relevant
3405 * small-bar uAPI support (including
3406 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on
3407 * such systems we should never actually end up with a
3408 * small BAR configuration, assuming we are able to load
3409 * the kernel module. Hence it should be safe to treat
3410 * this the same as when @probed_cpu_visible_size ==
3411 * @probed_size.
3412 */
3413 __u64 probed_cpu_visible_size;
3414
3415 /**
3416 * @unallocated_cpu_visible_size: Estimate of CPU
3417 * visible memory remaining.
3418 *
3419 * Note this is only tracked for
3420 * I915_MEMORY_CLASS_DEVICE regions (for other types the
3421 * value here will always equal the
3422 * @probed_cpu_visible_size).
3423 *
3424 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
3425 * accounting. Without this the value here will always
3426 * equal the @probed_cpu_visible_size. Note this is only
3427 * currently tracked for I915_MEMORY_CLASS_DEVICE
3428 * regions (for other types the value here will also
3429 * always equal the @probed_cpu_visible_size).
3430 *
3431 * If this is an older kernel the value here will be
3432 * zero, see also @probed_cpu_visible_size.
3433 */
3434 __u64 unallocated_cpu_visible_size;
3435 };
3436 };
3437};
3438
3439/**
3440 * struct drm_i915_query_memory_regions
3441 *
3442 * The region info query enumerates all regions known to the driver by filling
3443 * in an array of struct drm_i915_memory_region_info structures.
3444 *
3445 * Example for getting the list of supported regions:
3446 *
3447 * .. code-block:: C
3448 *
3449 * struct drm_i915_query_memory_regions *info;
3450 * struct drm_i915_query_item item = {
3451 * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
3452 * };
3453 * struct drm_i915_query query = {
3454 * .num_items = 1,
3455 * .items_ptr = (uintptr_t)&item,
3456 * };
3457 * int err, i;
3458 *
3459 * // First query the size of the blob we need, this needs to be large
3460 * // enough to hold our array of regions. The kernel will fill out the
3461 * // item.length for us, which is the number of bytes we need.
3462 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
3463 * if (err) ...
3464 *
3465 * info = calloc(1, item.length);
3466 * // Now that we allocated the required number of bytes, we call the ioctl
3467 * // again, this time with the data_ptr pointing to our newly allocated
3468 * // blob, which the kernel can then populate with the all the region info.
3469 * item.data_ptr = (uintptr_t)&info,
3470 *
3471 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
3472 * if (err) ...
3473 *
3474 * // We can now access each region in the array
3475 * for (i = 0; i < info->num_regions; i++) {
3476 * struct drm_i915_memory_region_info mr = info->regions[i];
3477 * u16 class = mr.region.class;
3478 * u16 instance = mr.region.instance;
3479 *
3480 * ....
3481 * }
3482 *
3483 * free(info);
3484 */
3485struct drm_i915_query_memory_regions {
3486 /** @num_regions: Number of supported regions */
3487 __u32 num_regions;
3488
3489 /** @rsvd: MBZ */
3490 __u32 rsvd[3];
3491
3492 /** @regions: Info about each supported region */
3493 struct drm_i915_memory_region_info regions[];
3494};
3495
3496/**
3497 * DOC: GuC HWCONFIG blob uAPI
3498 *
3499 * The GuC produces a blob with information about the current device.
3500 * i915 reads this blob from GuC and makes it available via this uAPI.
3501 *
3502 * The format and meaning of the blob content are documented in the
3503 * Programmer's Reference Manual.
3504 */
3505
3506/**
3507 * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
3508 * extension support using struct i915_user_extension.
3509 *
3510 * Note that new buffer flags should be added here, at least for the stuff that
3511 * is immutable. Previously we would have two ioctls, one to create the object
3512 * with gem_create, and another to apply various parameters, however this
3513 * creates some ambiguity for the params which are considered immutable. Also in
3514 * general we're phasing out the various SET/GET ioctls.
3515 */
3516struct drm_i915_gem_create_ext {
3517 /**
3518 * @size: Requested size for the object.
3519 *
3520 * The (page-aligned) allocated size for the object will be returned.
3521 *
3522 * On platforms like DG2/ATS the kernel will always use 64K or larger
3523 * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
3524 * minimum of 64K GTT alignment for such objects.
3525 *
3526 * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
3527 * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
3528 * where we had the following complications:
3529 *
3530 * 1) The entire PDE (which covers a 2MB virtual address range), must
3531 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
3532 * PDE is forbidden by the hardware.
3533 *
3534 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
3535 * objects.
3536 *
3537 * However on actual production HW this was completely changed to now
3538 * allow setting a TLB hint at the PTE level (see PS64), which is a lot
3539 * more flexible than the above. With this the 2M restriction was
3540 * dropped where we now only require 64K.
3541 */
3542 __u64 size;
3543
3544 /**
3545 * @handle: Returned handle for the object.
3546 *
3547 * Object handles are nonzero.
3548 */
3549 __u32 handle;
3550
3551 /**
3552 * @flags: Optional flags.
3553 *
3554 * Supported values:
3555 *
3556 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that
3557 * the object will need to be accessed via the CPU.
3558 *
3559 * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
3560 * strictly required on configurations where some subset of the device
3561 * memory is directly visible/mappable through the CPU (which we also
3562 * call small BAR), like on some DG2+ systems. Note that this is quite
3563 * undesirable, but due to various factors like the client CPU, BIOS etc
3564 * it's something we can expect to see in the wild. See
3565 * &drm_i915_memory_region_info.probed_cpu_visible_size for how to
3566 * determine if this system applies.
3567 *
3568 * Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to
3569 * ensure the kernel can always spill the allocation to system memory,
3570 * if the object can't be allocated in the mappable part of
3571 * I915_MEMORY_CLASS_DEVICE.
3572 *
3573 * Also note that since the kernel only supports flat-CCS on objects
3574 * that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore
3575 * don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with
3576 * flat-CCS.
3577 *
3578 * Without this hint, the kernel will assume that non-mappable
3579 * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
3580 * kernel can still migrate the object to the mappable part, as a last
3581 * resort, if userspace ever CPU faults this object, but this might be
3582 * expensive, and so ideally should be avoided.
3583 *
3584 * On older kernels which lack the relevant small-bar uAPI support (see
3585 * also &drm_i915_memory_region_info.probed_cpu_visible_size),
3586 * usage of the flag will result in an error, but it should NEVER be
3587 * possible to end up with a small BAR configuration, assuming we can
3588 * also successfully load the i915 kernel module. In such cases the
3589 * entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as
3590 * such there are zero restrictions on where the object can be placed.
3591 */
3592#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
3593 __u32 flags;
3594
3595 /**
3596 * @extensions: The chain of extensions to apply to this object.
3597 *
3598 * This will be useful in the future when we need to support several
3599 * different extensions, and we need to apply more than one when
3600 * creating the object. See struct i915_user_extension.
3601 *
3602 * If we don't supply any extensions then we get the same old gem_create
3603 * behaviour.
3604 *
3605 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
3606 * struct drm_i915_gem_create_ext_memory_regions.
3607 *
3608 * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
3609 * struct drm_i915_gem_create_ext_protected_content.
3610 */
3611#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
3612#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
3613 __u64 extensions;
3614};
3615
3616/**
3617 * struct drm_i915_gem_create_ext_memory_regions - The
3618 * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
3619 *
3620 * Set the object with the desired set of placements/regions in priority
3621 * order. Each entry must be unique and supported by the device.
3622 *
3623 * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
3624 * an equivalent layout of class:instance pair encodings. See struct
3625 * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
3626 * query the supported regions for a device.
3627 *
3628 * As an example, on discrete devices, if we wish to set the placement as
3629 * device local-memory we can do something like:
3630 *
3631 * .. code-block:: C
3632 *
3633 * struct drm_i915_gem_memory_class_instance region_lmem = {
3634 * .memory_class = I915_MEMORY_CLASS_DEVICE,
3635 * .memory_instance = 0,
3636 * };
3637 * struct drm_i915_gem_create_ext_memory_regions regions = {
3638 * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
3639 * .regions = (uintptr_t)®ion_lmem,
3640 * .num_regions = 1,
3641 * };
3642 * struct drm_i915_gem_create_ext create_ext = {
3643 * .size = 16 * PAGE_SIZE,
3644 * .extensions = (uintptr_t)®ions,
3645 * };
3646 *
3647 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
3648 * if (err) ...
3649 *
3650 * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
3651 * along with the final object size in &drm_i915_gem_create_ext.size, which
3652 * should account for any rounding up, if required.
3653 *
3654 * Note that userspace has no means of knowing the current backing region
3655 * for objects where @num_regions is larger than one. The kernel will only
3656 * ensure that the priority order of the @regions array is honoured, either
3657 * when initially placing the object, or when moving memory around due to
3658 * memory pressure
3659 *
3660 * On Flat-CCS capable HW, compression is supported for the objects residing
3661 * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other
3662 * memory class in @regions and migrated (by i915, due to memory
3663 * constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to
3664 * decompress the content. But i915 doesn't have the required information to
3665 * decompress the userspace compressed objects.
3666 *
3667 * So i915 supports Flat-CCS, on the objects which can reside only on
3668 * I915_MEMORY_CLASS_DEVICE regions.
3669 */
3670struct drm_i915_gem_create_ext_memory_regions {
3671 /** @base: Extension link. See struct i915_user_extension. */
3672 struct i915_user_extension base;
3673
3674 /** @pad: MBZ */
3675 __u32 pad;
3676 /** @num_regions: Number of elements in the @regions array. */
3677 __u32 num_regions;
3678 /**
3679 * @regions: The regions/placements array.
3680 *
3681 * An array of struct drm_i915_gem_memory_class_instance.
3682 */
3683 __u64 regions;
3684};
3685
3686/**
3687 * struct drm_i915_gem_create_ext_protected_content - The
3688 * I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
3689 *
3690 * If this extension is provided, buffer contents are expected to be protected
3691 * by PXP encryption and require decryption for scan out and processing. This
3692 * is only possible on platforms that have PXP enabled, on all other scenarios
3693 * using this extension will cause the ioctl to fail and return -ENODEV. The
3694 * flags parameter is reserved for future expansion and must currently be set
3695 * to zero.
3696 *
3697 * The buffer contents are considered invalid after a PXP session teardown.
3698 *
3699 * The encryption is guaranteed to be processed correctly only if the object
3700 * is submitted with a context created using the
3701 * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
3702 * at submission time on the validity of the objects involved.
3703 *
3704 * Below is an example on how to create a protected object:
3705 *
3706 * .. code-block:: C
3707 *
3708 * struct drm_i915_gem_create_ext_protected_content protected_ext = {
3709 * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
3710 * .flags = 0,
3711 * };
3712 * struct drm_i915_gem_create_ext create_ext = {
3713 * .size = PAGE_SIZE,
3714 * .extensions = (uintptr_t)&protected_ext,
3715 * };
3716 *
3717 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
3718 * if (err) ...
3719 */
3720struct drm_i915_gem_create_ext_protected_content {
3721 /** @base: Extension link. See struct i915_user_extension. */
3722 struct i915_user_extension base;
3723 /** @flags: reserved for future usage, currently MBZ */
3724 __u32 flags;
3725};
3726
3727/* ID of the protected content session managed by i915 when PXP is active */
3728#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
3729
3730#if defined(__cplusplus)
3731}
3732#endif
3733
3734#endif /* _UAPI_I915_DRM_H_ */