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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MGSL_MAGIC 0x5401
95#define MAX_DEVICES 32
96
97static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103};
104MODULE_DEVICE_TABLE(pci, pci_table);
105
106static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107static void remove_one(struct pci_dev *dev);
108static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
112 .remove = remove_one,
113};
114
115static bool pci_registered;
116
117/*
118 * module configuration and status
119 */
120static struct slgt_info *slgt_device_list;
121static int slgt_device_count;
122
123static int ttymajor;
124static int debug_level;
125static int maxframe[MAX_DEVICES];
126
127module_param(ttymajor, int, 0);
128module_param(debug_level, int, 0);
129module_param_array(maxframe, int, NULL, 0);
130
131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
134
135/*
136 * tty support and callbacks
137 */
138static struct tty_driver *serial_driver;
139
140static int open(struct tty_struct *tty, struct file * filp);
141static void close(struct tty_struct *tty, struct file * filp);
142static void hangup(struct tty_struct *tty);
143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
144
145static int write(struct tty_struct *tty, const unsigned char *buf, int count);
146static int put_char(struct tty_struct *tty, unsigned char ch);
147static void send_xchar(struct tty_struct *tty, char ch);
148static void wait_until_sent(struct tty_struct *tty, int timeout);
149static int write_room(struct tty_struct *tty);
150static void flush_chars(struct tty_struct *tty);
151static void flush_buffer(struct tty_struct *tty);
152static void tx_hold(struct tty_struct *tty);
153static void tx_release(struct tty_struct *tty);
154
155static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
156static int chars_in_buffer(struct tty_struct *tty);
157static void throttle(struct tty_struct * tty);
158static void unthrottle(struct tty_struct * tty);
159static int set_break(struct tty_struct *tty, int break_state);
160
161/*
162 * generic HDLC support and callbacks
163 */
164#if SYNCLINK_GENERIC_HDLC
165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
166static void hdlcdev_tx_done(struct slgt_info *info);
167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
168static int hdlcdev_init(struct slgt_info *info);
169static void hdlcdev_exit(struct slgt_info *info);
170#endif
171
172
173/*
174 * device specific structures, macros and functions
175 */
176
177#define SLGT_MAX_PORTS 4
178#define SLGT_REG_SIZE 256
179
180/*
181 * conditional wait facility
182 */
183struct cond_wait {
184 struct cond_wait *next;
185 wait_queue_head_t q;
186 wait_queue_entry_t wait;
187 unsigned int data;
188};
189static void init_cond_wait(struct cond_wait *w, unsigned int data);
190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void flush_cond_wait(struct cond_wait **head);
193
194/*
195 * DMA buffer descriptor and access macros
196 */
197struct slgt_desc
198{
199 __le16 count;
200 __le16 status;
201 __le32 pbuf; /* physical address of data buffer */
202 __le32 next; /* physical address of next descriptor */
203
204 /* driver book keeping */
205 char *buf; /* virtual address of data buffer */
206 unsigned int pdesc; /* physical address of this descriptor */
207 dma_addr_t buf_dma_addr;
208 unsigned short buf_count;
209};
210
211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
212#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
213#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
214#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
216#define desc_count(a) (le16_to_cpu((a).count))
217#define desc_status(a) (le16_to_cpu((a).status))
218#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
219#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
220#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
221#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
222#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
223
224struct _input_signal_events {
225 int ri_up;
226 int ri_down;
227 int dsr_up;
228 int dsr_down;
229 int dcd_up;
230 int dcd_down;
231 int cts_up;
232 int cts_down;
233};
234
235/*
236 * device instance data structure
237 */
238struct slgt_info {
239 void *if_ptr; /* General purpose pointer (used by SPPP) */
240 struct tty_port port;
241
242 struct slgt_info *next_device; /* device list link */
243
244 int magic;
245
246 char device_name[25];
247 struct pci_dev *pdev;
248
249 int port_count; /* count of ports on adapter */
250 int adapter_num; /* adapter instance number */
251 int port_num; /* port instance number */
252
253 /* array of pointers to port contexts on this adapter */
254 struct slgt_info *port_array[SLGT_MAX_PORTS];
255
256 int line; /* tty line instance number */
257
258 struct mgsl_icount icount;
259
260 int timeout;
261 int x_char; /* xon/xoff character */
262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
265 wait_queue_head_t status_event_wait_q;
266 wait_queue_head_t event_wait_q;
267 struct timer_list tx_timer;
268 struct timer_list rx_timer;
269
270 unsigned int gpio_present;
271 struct cond_wait *gpio_wait_q;
272
273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
277 bool bh_requested;
278 bool bh_running;
279
280 int isr_overflow;
281 bool irq_requested; /* true if IRQ requested */
282 bool irq_occurred; /* for diagnostics use */
283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
292 bool reg_addr_requested;
293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
298 unsigned int rbuf_fill_level;
299 unsigned int rx_pio;
300 unsigned int if_mode;
301 unsigned int base_clock;
302 unsigned int xsync;
303 unsigned int xctrl;
304
305 /* device status */
306
307 bool rx_enabled;
308 bool rx_restart;
309
310 bool tx_enabled;
311 bool tx_active;
312
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
315
316 unsigned char *tx_buf;
317 int tx_count;
318
319 char *flag_buf;
320 bool drop_rts_on_tx_done;
321 struct _input_signal_events input_signal_events;
322
323 int dcd_chkcount; /* check counts to prevent */
324 int cts_chkcount; /* too many IRQs if a signal */
325 int dsr_chkcount; /* is floating */
326 int ri_chkcount;
327
328 char *bufs; /* virtual address of DMA buffer lists */
329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
330
331 unsigned int rbuf_count;
332 struct slgt_desc *rbufs;
333 unsigned int rbuf_current;
334 unsigned int rbuf_index;
335 unsigned int rbuf_fill_index;
336 unsigned short rbuf_fill_count;
337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
349 spinlock_t netlock;
350#if SYNCLINK_GENERIC_HDLC
351 struct net_device *netdev;
352#endif
353
354};
355
356static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370};
371
372
373#define BH_RECEIVE 1
374#define BH_TRANSMIT 2
375#define BH_STATUS 4
376#define IO_PIN_SHUTDOWN_LIMIT 100
377
378#define DMABUFSIZE 256
379#define DESC_LIST_SIZE 4096
380
381#define MASK_PARITY BIT1
382#define MASK_FRAMING BIT0
383#define MASK_BREAK BIT14
384#define MASK_OVERRUN BIT4
385
386#define GSR 0x00 /* global status */
387#define JCR 0x04 /* JTAG control */
388#define IODR 0x08 /* GPIO direction */
389#define IOER 0x0c /* GPIO interrupt enable */
390#define IOVR 0x10 /* GPIO value */
391#define IOSR 0x14 /* GPIO interrupt status */
392#define TDR 0x80 /* tx data */
393#define RDR 0x80 /* rx data */
394#define TCR 0x82 /* tx control */
395#define TIR 0x84 /* tx idle */
396#define TPR 0x85 /* tx preamble */
397#define RCR 0x86 /* rx control */
398#define VCR 0x88 /* V.24 control */
399#define CCR 0x89 /* clock control */
400#define BDR 0x8a /* baud divisor */
401#define SCR 0x8c /* serial control */
402#define SSR 0x8e /* serial status */
403#define RDCSR 0x90 /* rx DMA control/status */
404#define TDCSR 0x94 /* tx DMA control/status */
405#define RDDAR 0x98 /* rx DMA descriptor address */
406#define TDDAR 0x9c /* tx DMA descriptor address */
407#define XSR 0x40 /* extended sync pattern */
408#define XCR 0x44 /* extended control */
409
410#define RXIDLE BIT14
411#define RXBREAK BIT14
412#define IRQ_TXDATA BIT13
413#define IRQ_TXIDLE BIT12
414#define IRQ_TXUNDER BIT11 /* HDLC */
415#define IRQ_RXDATA BIT10
416#define IRQ_RXIDLE BIT9 /* HDLC */
417#define IRQ_RXBREAK BIT9 /* async */
418#define IRQ_RXOVER BIT8
419#define IRQ_DSR BIT7
420#define IRQ_CTS BIT6
421#define IRQ_DCD BIT5
422#define IRQ_RI BIT4
423#define IRQ_ALL 0x3ff0
424#define IRQ_MASTER BIT0
425
426#define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428#define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438static void msc_set_vcr(struct slgt_info *info);
439
440static int startup(struct slgt_info *info);
441static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442static void shutdown(struct slgt_info *info);
443static void program_hw(struct slgt_info *info);
444static void change_params(struct slgt_info *info);
445
446static int register_test(struct slgt_info *info);
447static int irq_test(struct slgt_info *info);
448static int loopback_test(struct slgt_info *info);
449static int adapter_test(struct slgt_info *info);
450
451static void reset_adapter(struct slgt_info *info);
452static void reset_port(struct slgt_info *info);
453static void async_mode(struct slgt_info *info);
454static void sync_mode(struct slgt_info *info);
455
456static void rx_stop(struct slgt_info *info);
457static void rx_start(struct slgt_info *info);
458static void reset_rbufs(struct slgt_info *info);
459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460static void rdma_reset(struct slgt_info *info);
461static bool rx_get_frame(struct slgt_info *info);
462static bool rx_get_buf(struct slgt_info *info);
463
464static void tx_start(struct slgt_info *info);
465static void tx_stop(struct slgt_info *info);
466static void tx_set_idle(struct slgt_info *info);
467static unsigned int free_tbuf_count(struct slgt_info *info);
468static unsigned int tbuf_bytes(struct slgt_info *info);
469static void reset_tbufs(struct slgt_info *info);
470static void tdma_reset(struct slgt_info *info);
471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472
473static void get_signals(struct slgt_info *info);
474static void set_signals(struct slgt_info *info);
475static void enable_loopback(struct slgt_info *info);
476static void set_rate(struct slgt_info *info, u32 data_rate);
477
478static int bh_action(struct slgt_info *info);
479static void bh_handler(struct work_struct *work);
480static void bh_transmit(struct slgt_info *info);
481static void isr_serial(struct slgt_info *info);
482static void isr_rdma(struct slgt_info *info);
483static void isr_txeom(struct slgt_info *info, unsigned short status);
484static void isr_tdma(struct slgt_info *info);
485
486static int alloc_dma_bufs(struct slgt_info *info);
487static void free_dma_bufs(struct slgt_info *info);
488static int alloc_desc(struct slgt_info *info);
489static void free_desc(struct slgt_info *info);
490static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493static int alloc_tmp_rbuf(struct slgt_info *info);
494static void free_tmp_rbuf(struct slgt_info *info);
495
496static void tx_timeout(struct timer_list *t);
497static void rx_timeout(struct timer_list *t);
498
499/*
500 * ioctl handlers
501 */
502static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506static int set_txidle(struct slgt_info *info, int idle_mode);
507static int tx_enable(struct slgt_info *info, int enable);
508static int tx_abort(struct slgt_info *info);
509static int rx_enable(struct slgt_info *info, int enable);
510static int modem_input_wait(struct slgt_info *info,int arg);
511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
512static int tiocmget(struct tty_struct *tty);
513static int tiocmset(struct tty_struct *tty,
514 unsigned int set, unsigned int clear);
515static int set_break(struct tty_struct *tty, int break_state);
516static int get_interface(struct slgt_info *info, int __user *if_mode);
517static int set_interface(struct slgt_info *info, int if_mode);
518static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int get_xsync(struct slgt_info *info, int __user *if_mode);
522static int set_xsync(struct slgt_info *info, int if_mode);
523static int get_xctrl(struct slgt_info *info, int __user *if_mode);
524static int set_xctrl(struct slgt_info *info, int if_mode);
525
526/*
527 * driver functions
528 */
529static void add_device(struct slgt_info *info);
530static void device_init(int adapter_num, struct pci_dev *pdev);
531static int claim_resources(struct slgt_info *info);
532static void release_resources(struct slgt_info *info);
533
534/*
535 * DEBUG OUTPUT CODE
536 */
537#ifndef DBGINFO
538#define DBGINFO(fmt)
539#endif
540#ifndef DBGERR
541#define DBGERR(fmt)
542#endif
543#ifndef DBGBH
544#define DBGBH(fmt)
545#endif
546#ifndef DBGISR
547#define DBGISR(fmt)
548#endif
549
550#ifdef DBGDATA
551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
552{
553 int i;
554 int linecount;
555 printk("%s %s data:\n",info->device_name, label);
556 while(count) {
557 linecount = (count > 16) ? 16 : count;
558 for(i=0; i < linecount; i++)
559 printk("%02X ",(unsigned char)data[i]);
560 for(;i<17;i++)
561 printk(" ");
562 for(i=0;i<linecount;i++) {
563 if (data[i]>=040 && data[i]<=0176)
564 printk("%c",data[i]);
565 else
566 printk(".");
567 }
568 printk("\n");
569 data += linecount;
570 count -= linecount;
571 }
572}
573#else
574#define DBGDATA(info, buf, size, label)
575#endif
576
577#ifdef DBGTBUF
578static void dump_tbufs(struct slgt_info *info)
579{
580 int i;
581 printk("tbuf_current=%d\n", info->tbuf_current);
582 for (i=0 ; i < info->tbuf_count ; i++) {
583 printk("%d: count=%04X status=%04X\n",
584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
585 }
586}
587#else
588#define DBGTBUF(info)
589#endif
590
591#ifdef DBGRBUF
592static void dump_rbufs(struct slgt_info *info)
593{
594 int i;
595 printk("rbuf_current=%d\n", info->rbuf_current);
596 for (i=0 ; i < info->rbuf_count ; i++) {
597 printk("%d: count=%04X status=%04X\n",
598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
599 }
600}
601#else
602#define DBGRBUF(info)
603#endif
604
605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
606{
607#ifdef SANITY_CHECK
608 if (!info) {
609 printk("null struct slgt_info for (%s) in %s\n", devname, name);
610 return 1;
611 }
612 if (info->magic != MGSL_MAGIC) {
613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
614 return 1;
615 }
616#else
617 if (!info)
618 return 1;
619#endif
620 return 0;
621}
622
623/**
624 * line discipline callback wrappers
625 *
626 * The wrappers maintain line discipline references
627 * while calling into the line discipline.
628 *
629 * ldisc_receive_buf - pass receive data to line discipline
630 */
631static void ldisc_receive_buf(struct tty_struct *tty,
632 const __u8 *data, char *flags, int count)
633{
634 struct tty_ldisc *ld;
635 if (!tty)
636 return;
637 ld = tty_ldisc_ref(tty);
638 if (ld) {
639 if (ld->ops->receive_buf)
640 ld->ops->receive_buf(tty, data, flags, count);
641 tty_ldisc_deref(ld);
642 }
643}
644
645/* tty callbacks */
646
647static int open(struct tty_struct *tty, struct file *filp)
648{
649 struct slgt_info *info;
650 int retval, line;
651 unsigned long flags;
652
653 line = tty->index;
654 if (line >= slgt_device_count) {
655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
656 return -ENODEV;
657 }
658
659 info = slgt_device_list;
660 while(info && info->line != line)
661 info = info->next_device;
662 if (sanity_check(info, tty->name, "open"))
663 return -ENODEV;
664 if (info->init_error) {
665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
666 return -ENODEV;
667 }
668
669 tty->driver_data = info;
670 info->port.tty = tty;
671
672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
673
674 mutex_lock(&info->port.mutex);
675 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
676
677 spin_lock_irqsave(&info->netlock, flags);
678 if (info->netcount) {
679 retval = -EBUSY;
680 spin_unlock_irqrestore(&info->netlock, flags);
681 mutex_unlock(&info->port.mutex);
682 goto cleanup;
683 }
684 info->port.count++;
685 spin_unlock_irqrestore(&info->netlock, flags);
686
687 if (info->port.count == 1) {
688 /* 1st open on this device, init hardware */
689 retval = startup(info);
690 if (retval < 0) {
691 mutex_unlock(&info->port.mutex);
692 goto cleanup;
693 }
694 }
695 mutex_unlock(&info->port.mutex);
696 retval = block_til_ready(tty, filp, info);
697 if (retval) {
698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
699 goto cleanup;
700 }
701
702 retval = 0;
703
704cleanup:
705 if (retval) {
706 if (tty->count == 1)
707 info->port.tty = NULL; /* tty layer will release tty struct */
708 if(info->port.count)
709 info->port.count--;
710 }
711
712 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
713 return retval;
714}
715
716static void close(struct tty_struct *tty, struct file *filp)
717{
718 struct slgt_info *info = tty->driver_data;
719
720 if (sanity_check(info, tty->name, "close"))
721 return;
722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
723
724 if (tty_port_close_start(&info->port, tty, filp) == 0)
725 goto cleanup;
726
727 mutex_lock(&info->port.mutex);
728 if (tty_port_initialized(&info->port))
729 wait_until_sent(tty, info->timeout);
730 flush_buffer(tty);
731 tty_ldisc_flush(tty);
732
733 shutdown(info);
734 mutex_unlock(&info->port.mutex);
735
736 tty_port_close_end(&info->port, tty);
737 info->port.tty = NULL;
738cleanup:
739 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
740}
741
742static void hangup(struct tty_struct *tty)
743{
744 struct slgt_info *info = tty->driver_data;
745 unsigned long flags;
746
747 if (sanity_check(info, tty->name, "hangup"))
748 return;
749 DBGINFO(("%s hangup\n", info->device_name));
750
751 flush_buffer(tty);
752
753 mutex_lock(&info->port.mutex);
754 shutdown(info);
755
756 spin_lock_irqsave(&info->port.lock, flags);
757 info->port.count = 0;
758 info->port.tty = NULL;
759 spin_unlock_irqrestore(&info->port.lock, flags);
760 tty_port_set_active(&info->port, 0);
761 mutex_unlock(&info->port.mutex);
762
763 wake_up_interruptible(&info->port.open_wait);
764}
765
766static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
767{
768 struct slgt_info *info = tty->driver_data;
769 unsigned long flags;
770
771 DBGINFO(("%s set_termios\n", tty->driver->name));
772
773 change_params(info);
774
775 /* Handle transition to B0 status */
776 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
777 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
778 spin_lock_irqsave(&info->lock,flags);
779 set_signals(info);
780 spin_unlock_irqrestore(&info->lock,flags);
781 }
782
783 /* Handle transition away from B0 status */
784 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
785 info->signals |= SerialSignal_DTR;
786 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
787 info->signals |= SerialSignal_RTS;
788 spin_lock_irqsave(&info->lock,flags);
789 set_signals(info);
790 spin_unlock_irqrestore(&info->lock,flags);
791 }
792
793 /* Handle turning off CRTSCTS */
794 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
795 tty->hw_stopped = 0;
796 tx_release(tty);
797 }
798}
799
800static void update_tx_timer(struct slgt_info *info)
801{
802 /*
803 * use worst case speed of 1200bps to calculate transmit timeout
804 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
805 */
806 if (info->params.mode == MGSL_MODE_HDLC) {
807 int timeout = (tbuf_bytes(info) * 7) + 1000;
808 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
809 }
810}
811
812static int write(struct tty_struct *tty,
813 const unsigned char *buf, int count)
814{
815 int ret = 0;
816 struct slgt_info *info = tty->driver_data;
817 unsigned long flags;
818
819 if (sanity_check(info, tty->name, "write"))
820 return -EIO;
821
822 DBGINFO(("%s write count=%d\n", info->device_name, count));
823
824 if (!info->tx_buf || (count > info->max_frame_size))
825 return -EIO;
826
827 if (!count || tty->stopped || tty->hw_stopped)
828 return 0;
829
830 spin_lock_irqsave(&info->lock, flags);
831
832 if (info->tx_count) {
833 /* send accumulated data from send_char() */
834 if (!tx_load(info, info->tx_buf, info->tx_count))
835 goto cleanup;
836 info->tx_count = 0;
837 }
838
839 if (tx_load(info, buf, count))
840 ret = count;
841
842cleanup:
843 spin_unlock_irqrestore(&info->lock, flags);
844 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
845 return ret;
846}
847
848static int put_char(struct tty_struct *tty, unsigned char ch)
849{
850 struct slgt_info *info = tty->driver_data;
851 unsigned long flags;
852 int ret = 0;
853
854 if (sanity_check(info, tty->name, "put_char"))
855 return 0;
856 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
857 if (!info->tx_buf)
858 return 0;
859 spin_lock_irqsave(&info->lock,flags);
860 if (info->tx_count < info->max_frame_size) {
861 info->tx_buf[info->tx_count++] = ch;
862 ret = 1;
863 }
864 spin_unlock_irqrestore(&info->lock,flags);
865 return ret;
866}
867
868static void send_xchar(struct tty_struct *tty, char ch)
869{
870 struct slgt_info *info = tty->driver_data;
871 unsigned long flags;
872
873 if (sanity_check(info, tty->name, "send_xchar"))
874 return;
875 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
876 info->x_char = ch;
877 if (ch) {
878 spin_lock_irqsave(&info->lock,flags);
879 if (!info->tx_enabled)
880 tx_start(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883}
884
885static void wait_until_sent(struct tty_struct *tty, int timeout)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long orig_jiffies, char_time;
889
890 if (!info )
891 return;
892 if (sanity_check(info, tty->name, "wait_until_sent"))
893 return;
894 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
895 if (!tty_port_initialized(&info->port))
896 goto exit;
897
898 orig_jiffies = jiffies;
899
900 /* Set check interval to 1/5 of estimated time to
901 * send a character, and make it at least 1. The check
902 * interval should also be less than the timeout.
903 * Note: use tight timings here to satisfy the NIST-PCTS.
904 */
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923exit:
924 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
925}
926
927static int write_room(struct tty_struct *tty)
928{
929 struct slgt_info *info = tty->driver_data;
930 int ret;
931
932 if (sanity_check(info, tty->name, "write_room"))
933 return 0;
934 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
935 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
936 return ret;
937}
938
939static void flush_chars(struct tty_struct *tty)
940{
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "flush_chars"))
945 return;
946 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
947
948 if (info->tx_count <= 0 || tty->stopped ||
949 tty->hw_stopped || !info->tx_buf)
950 return;
951
952 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
953
954 spin_lock_irqsave(&info->lock,flags);
955 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
956 info->tx_count = 0;
957 spin_unlock_irqrestore(&info->lock,flags);
958}
959
960static void flush_buffer(struct tty_struct *tty)
961{
962 struct slgt_info *info = tty->driver_data;
963 unsigned long flags;
964
965 if (sanity_check(info, tty->name, "flush_buffer"))
966 return;
967 DBGINFO(("%s flush_buffer\n", info->device_name));
968
969 spin_lock_irqsave(&info->lock, flags);
970 info->tx_count = 0;
971 spin_unlock_irqrestore(&info->lock, flags);
972
973 tty_wakeup(tty);
974}
975
976/*
977 * throttle (stop) transmitter
978 */
979static void tx_hold(struct tty_struct *tty)
980{
981 struct slgt_info *info = tty->driver_data;
982 unsigned long flags;
983
984 if (sanity_check(info, tty->name, "tx_hold"))
985 return;
986 DBGINFO(("%s tx_hold\n", info->device_name));
987 spin_lock_irqsave(&info->lock,flags);
988 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
989 tx_stop(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991}
992
993/*
994 * release (start) transmitter
995 */
996static void tx_release(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_release"))
1002 return;
1003 DBGINFO(("%s tx_release\n", info->device_name));
1004 spin_lock_irqsave(&info->lock, flags);
1005 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006 info->tx_count = 0;
1007 spin_unlock_irqrestore(&info->lock, flags);
1008}
1009
1010/*
1011 * Service an IOCTL request
1012 *
1013 * Arguments
1014 *
1015 * tty pointer to tty instance data
1016 * cmd IOCTL command code
1017 * arg command argument/context
1018 *
1019 * Return 0 if success, otherwise error code
1020 */
1021static int ioctl(struct tty_struct *tty,
1022 unsigned int cmd, unsigned long arg)
1023{
1024 struct slgt_info *info = tty->driver_data;
1025 void __user *argp = (void __user *)arg;
1026 int ret;
1027
1028 if (sanity_check(info, tty->name, "ioctl"))
1029 return -ENODEV;
1030 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032 if (cmd != TIOCMIWAIT) {
1033 if (tty_io_error(tty))
1034 return -EIO;
1035 }
1036
1037 switch (cmd) {
1038 case MGSL_IOCWAITEVENT:
1039 return wait_mgsl_event(info, argp);
1040 case TIOCMIWAIT:
1041 return modem_input_wait(info,(int)arg);
1042 case MGSL_IOCSGPIO:
1043 return set_gpio(info, argp);
1044 case MGSL_IOCGGPIO:
1045 return get_gpio(info, argp);
1046 case MGSL_IOCWAITGPIO:
1047 return wait_gpio(info, argp);
1048 case MGSL_IOCGXSYNC:
1049 return get_xsync(info, argp);
1050 case MGSL_IOCSXSYNC:
1051 return set_xsync(info, (int)arg);
1052 case MGSL_IOCGXCTRL:
1053 return get_xctrl(info, argp);
1054 case MGSL_IOCSXCTRL:
1055 return set_xctrl(info, (int)arg);
1056 }
1057 mutex_lock(&info->port.mutex);
1058 switch (cmd) {
1059 case MGSL_IOCGPARAMS:
1060 ret = get_params(info, argp);
1061 break;
1062 case MGSL_IOCSPARAMS:
1063 ret = set_params(info, argp);
1064 break;
1065 case MGSL_IOCGTXIDLE:
1066 ret = get_txidle(info, argp);
1067 break;
1068 case MGSL_IOCSTXIDLE:
1069 ret = set_txidle(info, (int)arg);
1070 break;
1071 case MGSL_IOCTXENABLE:
1072 ret = tx_enable(info, (int)arg);
1073 break;
1074 case MGSL_IOCRXENABLE:
1075 ret = rx_enable(info, (int)arg);
1076 break;
1077 case MGSL_IOCTXABORT:
1078 ret = tx_abort(info);
1079 break;
1080 case MGSL_IOCGSTATS:
1081 ret = get_stats(info, argp);
1082 break;
1083 case MGSL_IOCGIF:
1084 ret = get_interface(info, argp);
1085 break;
1086 case MGSL_IOCSIF:
1087 ret = set_interface(info,(int)arg);
1088 break;
1089 default:
1090 ret = -ENOIOCTLCMD;
1091 }
1092 mutex_unlock(&info->port.mutex);
1093 return ret;
1094}
1095
1096static int get_icount(struct tty_struct *tty,
1097 struct serial_icounter_struct *icount)
1098
1099{
1100 struct slgt_info *info = tty->driver_data;
1101 struct mgsl_icount cnow; /* kernel counter temps */
1102 unsigned long flags;
1103
1104 spin_lock_irqsave(&info->lock,flags);
1105 cnow = info->icount;
1106 spin_unlock_irqrestore(&info->lock,flags);
1107
1108 icount->cts = cnow.cts;
1109 icount->dsr = cnow.dsr;
1110 icount->rng = cnow.rng;
1111 icount->dcd = cnow.dcd;
1112 icount->rx = cnow.rx;
1113 icount->tx = cnow.tx;
1114 icount->frame = cnow.frame;
1115 icount->overrun = cnow.overrun;
1116 icount->parity = cnow.parity;
1117 icount->brk = cnow.brk;
1118 icount->buf_overrun = cnow.buf_overrun;
1119
1120 return 0;
1121}
1122
1123/*
1124 * support for 32 bit ioctl calls on 64 bit systems
1125 */
1126#ifdef CONFIG_COMPAT
1127static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1128{
1129 struct MGSL_PARAMS32 tmp_params;
1130
1131 DBGINFO(("%s get_params32\n", info->device_name));
1132 memset(&tmp_params, 0, sizeof(tmp_params));
1133 tmp_params.mode = (compat_ulong_t)info->params.mode;
1134 tmp_params.loopback = info->params.loopback;
1135 tmp_params.flags = info->params.flags;
1136 tmp_params.encoding = info->params.encoding;
1137 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1138 tmp_params.addr_filter = info->params.addr_filter;
1139 tmp_params.crc_type = info->params.crc_type;
1140 tmp_params.preamble_length = info->params.preamble_length;
1141 tmp_params.preamble = info->params.preamble;
1142 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1143 tmp_params.data_bits = info->params.data_bits;
1144 tmp_params.stop_bits = info->params.stop_bits;
1145 tmp_params.parity = info->params.parity;
1146 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1147 return -EFAULT;
1148 return 0;
1149}
1150
1151static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1152{
1153 struct MGSL_PARAMS32 tmp_params;
1154
1155 DBGINFO(("%s set_params32\n", info->device_name));
1156 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1157 return -EFAULT;
1158
1159 spin_lock(&info->lock);
1160 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1161 info->base_clock = tmp_params.clock_speed;
1162 } else {
1163 info->params.mode = tmp_params.mode;
1164 info->params.loopback = tmp_params.loopback;
1165 info->params.flags = tmp_params.flags;
1166 info->params.encoding = tmp_params.encoding;
1167 info->params.clock_speed = tmp_params.clock_speed;
1168 info->params.addr_filter = tmp_params.addr_filter;
1169 info->params.crc_type = tmp_params.crc_type;
1170 info->params.preamble_length = tmp_params.preamble_length;
1171 info->params.preamble = tmp_params.preamble;
1172 info->params.data_rate = tmp_params.data_rate;
1173 info->params.data_bits = tmp_params.data_bits;
1174 info->params.stop_bits = tmp_params.stop_bits;
1175 info->params.parity = tmp_params.parity;
1176 }
1177 spin_unlock(&info->lock);
1178
1179 program_hw(info);
1180
1181 return 0;
1182}
1183
1184static long slgt_compat_ioctl(struct tty_struct *tty,
1185 unsigned int cmd, unsigned long arg)
1186{
1187 struct slgt_info *info = tty->driver_data;
1188 int rc;
1189
1190 if (sanity_check(info, tty->name, "compat_ioctl"))
1191 return -ENODEV;
1192 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1193
1194 switch (cmd) {
1195 case MGSL_IOCSPARAMS32:
1196 rc = set_params32(info, compat_ptr(arg));
1197 break;
1198
1199 case MGSL_IOCGPARAMS32:
1200 rc = get_params32(info, compat_ptr(arg));
1201 break;
1202
1203 case MGSL_IOCGPARAMS:
1204 case MGSL_IOCSPARAMS:
1205 case MGSL_IOCGTXIDLE:
1206 case MGSL_IOCGSTATS:
1207 case MGSL_IOCWAITEVENT:
1208 case MGSL_IOCGIF:
1209 case MGSL_IOCSGPIO:
1210 case MGSL_IOCGGPIO:
1211 case MGSL_IOCWAITGPIO:
1212 case MGSL_IOCGXSYNC:
1213 case MGSL_IOCGXCTRL:
1214 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1215 break;
1216 default:
1217 rc = ioctl(tty, cmd, arg);
1218 }
1219 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1220 return rc;
1221}
1222#else
1223#define slgt_compat_ioctl NULL
1224#endif /* ifdef CONFIG_COMPAT */
1225
1226/*
1227 * proc fs support
1228 */
1229static inline void line_info(struct seq_file *m, struct slgt_info *info)
1230{
1231 char stat_buf[30];
1232 unsigned long flags;
1233
1234 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1235 info->device_name, info->phys_reg_addr,
1236 info->irq_level, info->max_frame_size);
1237
1238 /* output current serial signal states */
1239 spin_lock_irqsave(&info->lock,flags);
1240 get_signals(info);
1241 spin_unlock_irqrestore(&info->lock,flags);
1242
1243 stat_buf[0] = 0;
1244 stat_buf[1] = 0;
1245 if (info->signals & SerialSignal_RTS)
1246 strcat(stat_buf, "|RTS");
1247 if (info->signals & SerialSignal_CTS)
1248 strcat(stat_buf, "|CTS");
1249 if (info->signals & SerialSignal_DTR)
1250 strcat(stat_buf, "|DTR");
1251 if (info->signals & SerialSignal_DSR)
1252 strcat(stat_buf, "|DSR");
1253 if (info->signals & SerialSignal_DCD)
1254 strcat(stat_buf, "|CD");
1255 if (info->signals & SerialSignal_RI)
1256 strcat(stat_buf, "|RI");
1257
1258 if (info->params.mode != MGSL_MODE_ASYNC) {
1259 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1260 info->icount.txok, info->icount.rxok);
1261 if (info->icount.txunder)
1262 seq_printf(m, " txunder:%d", info->icount.txunder);
1263 if (info->icount.txabort)
1264 seq_printf(m, " txabort:%d", info->icount.txabort);
1265 if (info->icount.rxshort)
1266 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1267 if (info->icount.rxlong)
1268 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1269 if (info->icount.rxover)
1270 seq_printf(m, " rxover:%d", info->icount.rxover);
1271 if (info->icount.rxcrc)
1272 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1273 } else {
1274 seq_printf(m, "\tASYNC tx:%d rx:%d",
1275 info->icount.tx, info->icount.rx);
1276 if (info->icount.frame)
1277 seq_printf(m, " fe:%d", info->icount.frame);
1278 if (info->icount.parity)
1279 seq_printf(m, " pe:%d", info->icount.parity);
1280 if (info->icount.brk)
1281 seq_printf(m, " brk:%d", info->icount.brk);
1282 if (info->icount.overrun)
1283 seq_printf(m, " oe:%d", info->icount.overrun);
1284 }
1285
1286 /* Append serial signal status to end */
1287 seq_printf(m, " %s\n", stat_buf+1);
1288
1289 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1290 info->tx_active,info->bh_requested,info->bh_running,
1291 info->pending_bh);
1292}
1293
1294/* Called to print information about devices
1295 */
1296static int synclink_gt_proc_show(struct seq_file *m, void *v)
1297{
1298 struct slgt_info *info;
1299
1300 seq_puts(m, "synclink_gt driver\n");
1301
1302 info = slgt_device_list;
1303 while( info ) {
1304 line_info(m, info);
1305 info = info->next_device;
1306 }
1307 return 0;
1308}
1309
1310/*
1311 * return count of bytes in transmit buffer
1312 */
1313static int chars_in_buffer(struct tty_struct *tty)
1314{
1315 struct slgt_info *info = tty->driver_data;
1316 int count;
1317 if (sanity_check(info, tty->name, "chars_in_buffer"))
1318 return 0;
1319 count = tbuf_bytes(info);
1320 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1321 return count;
1322}
1323
1324/*
1325 * signal remote device to throttle send data (our receive data)
1326 */
1327static void throttle(struct tty_struct * tty)
1328{
1329 struct slgt_info *info = tty->driver_data;
1330 unsigned long flags;
1331
1332 if (sanity_check(info, tty->name, "throttle"))
1333 return;
1334 DBGINFO(("%s throttle\n", info->device_name));
1335 if (I_IXOFF(tty))
1336 send_xchar(tty, STOP_CHAR(tty));
1337 if (C_CRTSCTS(tty)) {
1338 spin_lock_irqsave(&info->lock,flags);
1339 info->signals &= ~SerialSignal_RTS;
1340 set_signals(info);
1341 spin_unlock_irqrestore(&info->lock,flags);
1342 }
1343}
1344
1345/*
1346 * signal remote device to stop throttling send data (our receive data)
1347 */
1348static void unthrottle(struct tty_struct * tty)
1349{
1350 struct slgt_info *info = tty->driver_data;
1351 unsigned long flags;
1352
1353 if (sanity_check(info, tty->name, "unthrottle"))
1354 return;
1355 DBGINFO(("%s unthrottle\n", info->device_name));
1356 if (I_IXOFF(tty)) {
1357 if (info->x_char)
1358 info->x_char = 0;
1359 else
1360 send_xchar(tty, START_CHAR(tty));
1361 }
1362 if (C_CRTSCTS(tty)) {
1363 spin_lock_irqsave(&info->lock,flags);
1364 info->signals |= SerialSignal_RTS;
1365 set_signals(info);
1366 spin_unlock_irqrestore(&info->lock,flags);
1367 }
1368}
1369
1370/*
1371 * set or clear transmit break condition
1372 * break_state -1=set break condition, 0=clear
1373 */
1374static int set_break(struct tty_struct *tty, int break_state)
1375{
1376 struct slgt_info *info = tty->driver_data;
1377 unsigned short value;
1378 unsigned long flags;
1379
1380 if (sanity_check(info, tty->name, "set_break"))
1381 return -EINVAL;
1382 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1383
1384 spin_lock_irqsave(&info->lock,flags);
1385 value = rd_reg16(info, TCR);
1386 if (break_state == -1)
1387 value |= BIT6;
1388 else
1389 value &= ~BIT6;
1390 wr_reg16(info, TCR, value);
1391 spin_unlock_irqrestore(&info->lock,flags);
1392 return 0;
1393}
1394
1395#if SYNCLINK_GENERIC_HDLC
1396
1397/**
1398 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1399 * set encoding and frame check sequence (FCS) options
1400 *
1401 * dev pointer to network device structure
1402 * encoding serial encoding setting
1403 * parity FCS setting
1404 *
1405 * returns 0 if success, otherwise error code
1406 */
1407static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1408 unsigned short parity)
1409{
1410 struct slgt_info *info = dev_to_port(dev);
1411 unsigned char new_encoding;
1412 unsigned short new_crctype;
1413
1414 /* return error if TTY interface open */
1415 if (info->port.count)
1416 return -EBUSY;
1417
1418 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1419
1420 switch (encoding)
1421 {
1422 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1423 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1424 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1425 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1426 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1427 default: return -EINVAL;
1428 }
1429
1430 switch (parity)
1431 {
1432 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1433 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1434 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1435 default: return -EINVAL;
1436 }
1437
1438 info->params.encoding = new_encoding;
1439 info->params.crc_type = new_crctype;
1440
1441 /* if network interface up, reprogram hardware */
1442 if (info->netcount)
1443 program_hw(info);
1444
1445 return 0;
1446}
1447
1448/**
1449 * called by generic HDLC layer to send frame
1450 *
1451 * skb socket buffer containing HDLC frame
1452 * dev pointer to network device structure
1453 */
1454static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1455 struct net_device *dev)
1456{
1457 struct slgt_info *info = dev_to_port(dev);
1458 unsigned long flags;
1459
1460 DBGINFO(("%s hdlc_xmit\n", dev->name));
1461
1462 if (!skb->len)
1463 return NETDEV_TX_OK;
1464
1465 /* stop sending until this frame completes */
1466 netif_stop_queue(dev);
1467
1468 /* update network statistics */
1469 dev->stats.tx_packets++;
1470 dev->stats.tx_bytes += skb->len;
1471
1472 /* save start time for transmit timeout detection */
1473 netif_trans_update(dev);
1474
1475 spin_lock_irqsave(&info->lock, flags);
1476 tx_load(info, skb->data, skb->len);
1477 spin_unlock_irqrestore(&info->lock, flags);
1478
1479 /* done with socket buffer, so free it */
1480 dev_kfree_skb(skb);
1481
1482 return NETDEV_TX_OK;
1483}
1484
1485/**
1486 * called by network layer when interface enabled
1487 * claim resources and initialize hardware
1488 *
1489 * dev pointer to network device structure
1490 *
1491 * returns 0 if success, otherwise error code
1492 */
1493static int hdlcdev_open(struct net_device *dev)
1494{
1495 struct slgt_info *info = dev_to_port(dev);
1496 int rc;
1497 unsigned long flags;
1498
1499 if (!try_module_get(THIS_MODULE))
1500 return -EBUSY;
1501
1502 DBGINFO(("%s hdlcdev_open\n", dev->name));
1503
1504 /* generic HDLC layer open processing */
1505 rc = hdlc_open(dev);
1506 if (rc)
1507 return rc;
1508
1509 /* arbitrate between network and tty opens */
1510 spin_lock_irqsave(&info->netlock, flags);
1511 if (info->port.count != 0 || info->netcount != 0) {
1512 DBGINFO(("%s hdlc_open busy\n", dev->name));
1513 spin_unlock_irqrestore(&info->netlock, flags);
1514 return -EBUSY;
1515 }
1516 info->netcount=1;
1517 spin_unlock_irqrestore(&info->netlock, flags);
1518
1519 /* claim resources and init adapter */
1520 if ((rc = startup(info)) != 0) {
1521 spin_lock_irqsave(&info->netlock, flags);
1522 info->netcount=0;
1523 spin_unlock_irqrestore(&info->netlock, flags);
1524 return rc;
1525 }
1526
1527 /* assert RTS and DTR, apply hardware settings */
1528 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1529 program_hw(info);
1530
1531 /* enable network layer transmit */
1532 netif_trans_update(dev);
1533 netif_start_queue(dev);
1534
1535 /* inform generic HDLC layer of current DCD status */
1536 spin_lock_irqsave(&info->lock, flags);
1537 get_signals(info);
1538 spin_unlock_irqrestore(&info->lock, flags);
1539 if (info->signals & SerialSignal_DCD)
1540 netif_carrier_on(dev);
1541 else
1542 netif_carrier_off(dev);
1543 return 0;
1544}
1545
1546/**
1547 * called by network layer when interface is disabled
1548 * shutdown hardware and release resources
1549 *
1550 * dev pointer to network device structure
1551 *
1552 * returns 0 if success, otherwise error code
1553 */
1554static int hdlcdev_close(struct net_device *dev)
1555{
1556 struct slgt_info *info = dev_to_port(dev);
1557 unsigned long flags;
1558
1559 DBGINFO(("%s hdlcdev_close\n", dev->name));
1560
1561 netif_stop_queue(dev);
1562
1563 /* shutdown adapter and release resources */
1564 shutdown(info);
1565
1566 hdlc_close(dev);
1567
1568 spin_lock_irqsave(&info->netlock, flags);
1569 info->netcount=0;
1570 spin_unlock_irqrestore(&info->netlock, flags);
1571
1572 module_put(THIS_MODULE);
1573 return 0;
1574}
1575
1576/**
1577 * called by network layer to process IOCTL call to network device
1578 *
1579 * dev pointer to network device structure
1580 * ifr pointer to network interface request structure
1581 * cmd IOCTL command code
1582 *
1583 * returns 0 if success, otherwise error code
1584 */
1585static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1586{
1587 const size_t size = sizeof(sync_serial_settings);
1588 sync_serial_settings new_line;
1589 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1590 struct slgt_info *info = dev_to_port(dev);
1591 unsigned int flags;
1592
1593 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1594
1595 /* return error if TTY interface open */
1596 if (info->port.count)
1597 return -EBUSY;
1598
1599 if (cmd != SIOCWANDEV)
1600 return hdlc_ioctl(dev, ifr, cmd);
1601
1602 memset(&new_line, 0, sizeof(new_line));
1603
1604 switch(ifr->ifr_settings.type) {
1605 case IF_GET_IFACE: /* return current sync_serial_settings */
1606
1607 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1608 if (ifr->ifr_settings.size < size) {
1609 ifr->ifr_settings.size = size; /* data size wanted */
1610 return -ENOBUFS;
1611 }
1612
1613 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1614 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1615 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1616 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1617
1618 switch (flags){
1619 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1620 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1621 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1622 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1623 default: new_line.clock_type = CLOCK_DEFAULT;
1624 }
1625
1626 new_line.clock_rate = info->params.clock_speed;
1627 new_line.loopback = info->params.loopback ? 1:0;
1628
1629 if (copy_to_user(line, &new_line, size))
1630 return -EFAULT;
1631 return 0;
1632
1633 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1634
1635 if(!capable(CAP_NET_ADMIN))
1636 return -EPERM;
1637 if (copy_from_user(&new_line, line, size))
1638 return -EFAULT;
1639
1640 switch (new_line.clock_type)
1641 {
1642 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1643 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1644 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1645 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1646 case CLOCK_DEFAULT: flags = info->params.flags &
1647 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1648 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1649 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1650 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1651 default: return -EINVAL;
1652 }
1653
1654 if (new_line.loopback != 0 && new_line.loopback != 1)
1655 return -EINVAL;
1656
1657 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1658 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1659 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1660 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1661 info->params.flags |= flags;
1662
1663 info->params.loopback = new_line.loopback;
1664
1665 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1666 info->params.clock_speed = new_line.clock_rate;
1667 else
1668 info->params.clock_speed = 0;
1669
1670 /* if network interface up, reprogram hardware */
1671 if (info->netcount)
1672 program_hw(info);
1673 return 0;
1674
1675 default:
1676 return hdlc_ioctl(dev, ifr, cmd);
1677 }
1678}
1679
1680/**
1681 * called by network layer when transmit timeout is detected
1682 *
1683 * dev pointer to network device structure
1684 */
1685static void hdlcdev_tx_timeout(struct net_device *dev)
1686{
1687 struct slgt_info *info = dev_to_port(dev);
1688 unsigned long flags;
1689
1690 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1691
1692 dev->stats.tx_errors++;
1693 dev->stats.tx_aborted_errors++;
1694
1695 spin_lock_irqsave(&info->lock,flags);
1696 tx_stop(info);
1697 spin_unlock_irqrestore(&info->lock,flags);
1698
1699 netif_wake_queue(dev);
1700}
1701
1702/**
1703 * called by device driver when transmit completes
1704 * reenable network layer transmit if stopped
1705 *
1706 * info pointer to device instance information
1707 */
1708static void hdlcdev_tx_done(struct slgt_info *info)
1709{
1710 if (netif_queue_stopped(info->netdev))
1711 netif_wake_queue(info->netdev);
1712}
1713
1714/**
1715 * called by device driver when frame received
1716 * pass frame to network layer
1717 *
1718 * info pointer to device instance information
1719 * buf pointer to buffer contianing frame data
1720 * size count of data bytes in buf
1721 */
1722static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1723{
1724 struct sk_buff *skb = dev_alloc_skb(size);
1725 struct net_device *dev = info->netdev;
1726
1727 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1728
1729 if (skb == NULL) {
1730 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1731 dev->stats.rx_dropped++;
1732 return;
1733 }
1734
1735 skb_put_data(skb, buf, size);
1736
1737 skb->protocol = hdlc_type_trans(skb, dev);
1738
1739 dev->stats.rx_packets++;
1740 dev->stats.rx_bytes += size;
1741
1742 netif_rx(skb);
1743}
1744
1745static const struct net_device_ops hdlcdev_ops = {
1746 .ndo_open = hdlcdev_open,
1747 .ndo_stop = hdlcdev_close,
1748 .ndo_start_xmit = hdlc_start_xmit,
1749 .ndo_do_ioctl = hdlcdev_ioctl,
1750 .ndo_tx_timeout = hdlcdev_tx_timeout,
1751};
1752
1753/**
1754 * called by device driver when adding device instance
1755 * do generic HDLC initialization
1756 *
1757 * info pointer to device instance information
1758 *
1759 * returns 0 if success, otherwise error code
1760 */
1761static int hdlcdev_init(struct slgt_info *info)
1762{
1763 int rc;
1764 struct net_device *dev;
1765 hdlc_device *hdlc;
1766
1767 /* allocate and initialize network and HDLC layer objects */
1768
1769 dev = alloc_hdlcdev(info);
1770 if (!dev) {
1771 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1772 return -ENOMEM;
1773 }
1774
1775 /* for network layer reporting purposes only */
1776 dev->mem_start = info->phys_reg_addr;
1777 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1778 dev->irq = info->irq_level;
1779
1780 /* network layer callbacks and settings */
1781 dev->netdev_ops = &hdlcdev_ops;
1782 dev->watchdog_timeo = 10 * HZ;
1783 dev->tx_queue_len = 50;
1784
1785 /* generic HDLC layer callbacks and settings */
1786 hdlc = dev_to_hdlc(dev);
1787 hdlc->attach = hdlcdev_attach;
1788 hdlc->xmit = hdlcdev_xmit;
1789
1790 /* register objects with HDLC layer */
1791 rc = register_hdlc_device(dev);
1792 if (rc) {
1793 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1794 free_netdev(dev);
1795 return rc;
1796 }
1797
1798 info->netdev = dev;
1799 return 0;
1800}
1801
1802/**
1803 * called by device driver when removing device instance
1804 * do generic HDLC cleanup
1805 *
1806 * info pointer to device instance information
1807 */
1808static void hdlcdev_exit(struct slgt_info *info)
1809{
1810 unregister_hdlc_device(info->netdev);
1811 free_netdev(info->netdev);
1812 info->netdev = NULL;
1813}
1814
1815#endif /* ifdef CONFIG_HDLC */
1816
1817/*
1818 * get async data from rx DMA buffers
1819 */
1820static void rx_async(struct slgt_info *info)
1821{
1822 struct mgsl_icount *icount = &info->icount;
1823 unsigned int start, end;
1824 unsigned char *p;
1825 unsigned char status;
1826 struct slgt_desc *bufs = info->rbufs;
1827 int i, count;
1828 int chars = 0;
1829 int stat;
1830 unsigned char ch;
1831
1832 start = end = info->rbuf_current;
1833
1834 while(desc_complete(bufs[end])) {
1835 count = desc_count(bufs[end]) - info->rbuf_index;
1836 p = bufs[end].buf + info->rbuf_index;
1837
1838 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1839 DBGDATA(info, p, count, "rx");
1840
1841 for(i=0 ; i < count; i+=2, p+=2) {
1842 ch = *p;
1843 icount->rx++;
1844
1845 stat = 0;
1846
1847 status = *(p + 1) & (BIT1 + BIT0);
1848 if (status) {
1849 if (status & BIT1)
1850 icount->parity++;
1851 else if (status & BIT0)
1852 icount->frame++;
1853 /* discard char if tty control flags say so */
1854 if (status & info->ignore_status_mask)
1855 continue;
1856 if (status & BIT1)
1857 stat = TTY_PARITY;
1858 else if (status & BIT0)
1859 stat = TTY_FRAME;
1860 }
1861 tty_insert_flip_char(&info->port, ch, stat);
1862 chars++;
1863 }
1864
1865 if (i < count) {
1866 /* receive buffer not completed */
1867 info->rbuf_index += i;
1868 mod_timer(&info->rx_timer, jiffies + 1);
1869 break;
1870 }
1871
1872 info->rbuf_index = 0;
1873 free_rbufs(info, end, end);
1874
1875 if (++end == info->rbuf_count)
1876 end = 0;
1877
1878 /* if entire list searched then no frame available */
1879 if (end == start)
1880 break;
1881 }
1882
1883 if (chars)
1884 tty_flip_buffer_push(&info->port);
1885}
1886
1887/*
1888 * return next bottom half action to perform
1889 */
1890static int bh_action(struct slgt_info *info)
1891{
1892 unsigned long flags;
1893 int rc;
1894
1895 spin_lock_irqsave(&info->lock,flags);
1896
1897 if (info->pending_bh & BH_RECEIVE) {
1898 info->pending_bh &= ~BH_RECEIVE;
1899 rc = BH_RECEIVE;
1900 } else if (info->pending_bh & BH_TRANSMIT) {
1901 info->pending_bh &= ~BH_TRANSMIT;
1902 rc = BH_TRANSMIT;
1903 } else if (info->pending_bh & BH_STATUS) {
1904 info->pending_bh &= ~BH_STATUS;
1905 rc = BH_STATUS;
1906 } else {
1907 /* Mark BH routine as complete */
1908 info->bh_running = false;
1909 info->bh_requested = false;
1910 rc = 0;
1911 }
1912
1913 spin_unlock_irqrestore(&info->lock,flags);
1914
1915 return rc;
1916}
1917
1918/*
1919 * perform bottom half processing
1920 */
1921static void bh_handler(struct work_struct *work)
1922{
1923 struct slgt_info *info = container_of(work, struct slgt_info, task);
1924 int action;
1925
1926 info->bh_running = true;
1927
1928 while((action = bh_action(info))) {
1929 switch (action) {
1930 case BH_RECEIVE:
1931 DBGBH(("%s bh receive\n", info->device_name));
1932 switch(info->params.mode) {
1933 case MGSL_MODE_ASYNC:
1934 rx_async(info);
1935 break;
1936 case MGSL_MODE_HDLC:
1937 while(rx_get_frame(info));
1938 break;
1939 case MGSL_MODE_RAW:
1940 case MGSL_MODE_MONOSYNC:
1941 case MGSL_MODE_BISYNC:
1942 case MGSL_MODE_XSYNC:
1943 while(rx_get_buf(info));
1944 break;
1945 }
1946 /* restart receiver if rx DMA buffers exhausted */
1947 if (info->rx_restart)
1948 rx_start(info);
1949 break;
1950 case BH_TRANSMIT:
1951 bh_transmit(info);
1952 break;
1953 case BH_STATUS:
1954 DBGBH(("%s bh status\n", info->device_name));
1955 info->ri_chkcount = 0;
1956 info->dsr_chkcount = 0;
1957 info->dcd_chkcount = 0;
1958 info->cts_chkcount = 0;
1959 break;
1960 default:
1961 DBGBH(("%s unknown action\n", info->device_name));
1962 break;
1963 }
1964 }
1965 DBGBH(("%s bh_handler exit\n", info->device_name));
1966}
1967
1968static void bh_transmit(struct slgt_info *info)
1969{
1970 struct tty_struct *tty = info->port.tty;
1971
1972 DBGBH(("%s bh_transmit\n", info->device_name));
1973 if (tty)
1974 tty_wakeup(tty);
1975}
1976
1977static void dsr_change(struct slgt_info *info, unsigned short status)
1978{
1979 if (status & BIT3) {
1980 info->signals |= SerialSignal_DSR;
1981 info->input_signal_events.dsr_up++;
1982 } else {
1983 info->signals &= ~SerialSignal_DSR;
1984 info->input_signal_events.dsr_down++;
1985 }
1986 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1987 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1988 slgt_irq_off(info, IRQ_DSR);
1989 return;
1990 }
1991 info->icount.dsr++;
1992 wake_up_interruptible(&info->status_event_wait_q);
1993 wake_up_interruptible(&info->event_wait_q);
1994 info->pending_bh |= BH_STATUS;
1995}
1996
1997static void cts_change(struct slgt_info *info, unsigned short status)
1998{
1999 if (status & BIT2) {
2000 info->signals |= SerialSignal_CTS;
2001 info->input_signal_events.cts_up++;
2002 } else {
2003 info->signals &= ~SerialSignal_CTS;
2004 info->input_signal_events.cts_down++;
2005 }
2006 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2007 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2008 slgt_irq_off(info, IRQ_CTS);
2009 return;
2010 }
2011 info->icount.cts++;
2012 wake_up_interruptible(&info->status_event_wait_q);
2013 wake_up_interruptible(&info->event_wait_q);
2014 info->pending_bh |= BH_STATUS;
2015
2016 if (tty_port_cts_enabled(&info->port)) {
2017 if (info->port.tty) {
2018 if (info->port.tty->hw_stopped) {
2019 if (info->signals & SerialSignal_CTS) {
2020 info->port.tty->hw_stopped = 0;
2021 info->pending_bh |= BH_TRANSMIT;
2022 return;
2023 }
2024 } else {
2025 if (!(info->signals & SerialSignal_CTS))
2026 info->port.tty->hw_stopped = 1;
2027 }
2028 }
2029 }
2030}
2031
2032static void dcd_change(struct slgt_info *info, unsigned short status)
2033{
2034 if (status & BIT1) {
2035 info->signals |= SerialSignal_DCD;
2036 info->input_signal_events.dcd_up++;
2037 } else {
2038 info->signals &= ~SerialSignal_DCD;
2039 info->input_signal_events.dcd_down++;
2040 }
2041 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2042 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2043 slgt_irq_off(info, IRQ_DCD);
2044 return;
2045 }
2046 info->icount.dcd++;
2047#if SYNCLINK_GENERIC_HDLC
2048 if (info->netcount) {
2049 if (info->signals & SerialSignal_DCD)
2050 netif_carrier_on(info->netdev);
2051 else
2052 netif_carrier_off(info->netdev);
2053 }
2054#endif
2055 wake_up_interruptible(&info->status_event_wait_q);
2056 wake_up_interruptible(&info->event_wait_q);
2057 info->pending_bh |= BH_STATUS;
2058
2059 if (tty_port_check_carrier(&info->port)) {
2060 if (info->signals & SerialSignal_DCD)
2061 wake_up_interruptible(&info->port.open_wait);
2062 else {
2063 if (info->port.tty)
2064 tty_hangup(info->port.tty);
2065 }
2066 }
2067}
2068
2069static void ri_change(struct slgt_info *info, unsigned short status)
2070{
2071 if (status & BIT0) {
2072 info->signals |= SerialSignal_RI;
2073 info->input_signal_events.ri_up++;
2074 } else {
2075 info->signals &= ~SerialSignal_RI;
2076 info->input_signal_events.ri_down++;
2077 }
2078 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2079 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2080 slgt_irq_off(info, IRQ_RI);
2081 return;
2082 }
2083 info->icount.rng++;
2084 wake_up_interruptible(&info->status_event_wait_q);
2085 wake_up_interruptible(&info->event_wait_q);
2086 info->pending_bh |= BH_STATUS;
2087}
2088
2089static void isr_rxdata(struct slgt_info *info)
2090{
2091 unsigned int count = info->rbuf_fill_count;
2092 unsigned int i = info->rbuf_fill_index;
2093 unsigned short reg;
2094
2095 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2096 reg = rd_reg16(info, RDR);
2097 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2098 if (desc_complete(info->rbufs[i])) {
2099 /* all buffers full */
2100 rx_stop(info);
2101 info->rx_restart = 1;
2102 continue;
2103 }
2104 info->rbufs[i].buf[count++] = (unsigned char)reg;
2105 /* async mode saves status byte to buffer for each data byte */
2106 if (info->params.mode == MGSL_MODE_ASYNC)
2107 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2108 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2109 /* buffer full or end of frame */
2110 set_desc_count(info->rbufs[i], count);
2111 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2112 info->rbuf_fill_count = count = 0;
2113 if (++i == info->rbuf_count)
2114 i = 0;
2115 info->pending_bh |= BH_RECEIVE;
2116 }
2117 }
2118
2119 info->rbuf_fill_index = i;
2120 info->rbuf_fill_count = count;
2121}
2122
2123static void isr_serial(struct slgt_info *info)
2124{
2125 unsigned short status = rd_reg16(info, SSR);
2126
2127 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2128
2129 wr_reg16(info, SSR, status); /* clear pending */
2130
2131 info->irq_occurred = true;
2132
2133 if (info->params.mode == MGSL_MODE_ASYNC) {
2134 if (status & IRQ_TXIDLE) {
2135 if (info->tx_active)
2136 isr_txeom(info, status);
2137 }
2138 if (info->rx_pio && (status & IRQ_RXDATA))
2139 isr_rxdata(info);
2140 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2141 info->icount.brk++;
2142 /* process break detection if tty control allows */
2143 if (info->port.tty) {
2144 if (!(status & info->ignore_status_mask)) {
2145 if (info->read_status_mask & MASK_BREAK) {
2146 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2147 if (info->port.flags & ASYNC_SAK)
2148 do_SAK(info->port.tty);
2149 }
2150 }
2151 }
2152 }
2153 } else {
2154 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2155 isr_txeom(info, status);
2156 if (info->rx_pio && (status & IRQ_RXDATA))
2157 isr_rxdata(info);
2158 if (status & IRQ_RXIDLE) {
2159 if (status & RXIDLE)
2160 info->icount.rxidle++;
2161 else
2162 info->icount.exithunt++;
2163 wake_up_interruptible(&info->event_wait_q);
2164 }
2165
2166 if (status & IRQ_RXOVER)
2167 rx_start(info);
2168 }
2169
2170 if (status & IRQ_DSR)
2171 dsr_change(info, status);
2172 if (status & IRQ_CTS)
2173 cts_change(info, status);
2174 if (status & IRQ_DCD)
2175 dcd_change(info, status);
2176 if (status & IRQ_RI)
2177 ri_change(info, status);
2178}
2179
2180static void isr_rdma(struct slgt_info *info)
2181{
2182 unsigned int status = rd_reg32(info, RDCSR);
2183
2184 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2185
2186 /* RDCSR (rx DMA control/status)
2187 *
2188 * 31..07 reserved
2189 * 06 save status byte to DMA buffer
2190 * 05 error
2191 * 04 eol (end of list)
2192 * 03 eob (end of buffer)
2193 * 02 IRQ enable
2194 * 01 reset
2195 * 00 enable
2196 */
2197 wr_reg32(info, RDCSR, status); /* clear pending */
2198
2199 if (status & (BIT5 + BIT4)) {
2200 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2201 info->rx_restart = true;
2202 }
2203 info->pending_bh |= BH_RECEIVE;
2204}
2205
2206static void isr_tdma(struct slgt_info *info)
2207{
2208 unsigned int status = rd_reg32(info, TDCSR);
2209
2210 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2211
2212 /* TDCSR (tx DMA control/status)
2213 *
2214 * 31..06 reserved
2215 * 05 error
2216 * 04 eol (end of list)
2217 * 03 eob (end of buffer)
2218 * 02 IRQ enable
2219 * 01 reset
2220 * 00 enable
2221 */
2222 wr_reg32(info, TDCSR, status); /* clear pending */
2223
2224 if (status & (BIT5 + BIT4 + BIT3)) {
2225 // another transmit buffer has completed
2226 // run bottom half to get more send data from user
2227 info->pending_bh |= BH_TRANSMIT;
2228 }
2229}
2230
2231/*
2232 * return true if there are unsent tx DMA buffers, otherwise false
2233 *
2234 * if there are unsent buffers then info->tbuf_start
2235 * is set to index of first unsent buffer
2236 */
2237static bool unsent_tbufs(struct slgt_info *info)
2238{
2239 unsigned int i = info->tbuf_current;
2240 bool rc = false;
2241
2242 /*
2243 * search backwards from last loaded buffer (precedes tbuf_current)
2244 * for first unsent buffer (desc_count > 0)
2245 */
2246
2247 do {
2248 if (i)
2249 i--;
2250 else
2251 i = info->tbuf_count - 1;
2252 if (!desc_count(info->tbufs[i]))
2253 break;
2254 info->tbuf_start = i;
2255 rc = true;
2256 } while (i != info->tbuf_current);
2257
2258 return rc;
2259}
2260
2261static void isr_txeom(struct slgt_info *info, unsigned short status)
2262{
2263 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2264
2265 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2266 tdma_reset(info);
2267 if (status & IRQ_TXUNDER) {
2268 unsigned short val = rd_reg16(info, TCR);
2269 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2270 wr_reg16(info, TCR, val); /* clear reset bit */
2271 }
2272
2273 if (info->tx_active) {
2274 if (info->params.mode != MGSL_MODE_ASYNC) {
2275 if (status & IRQ_TXUNDER)
2276 info->icount.txunder++;
2277 else if (status & IRQ_TXIDLE)
2278 info->icount.txok++;
2279 }
2280
2281 if (unsent_tbufs(info)) {
2282 tx_start(info);
2283 update_tx_timer(info);
2284 return;
2285 }
2286 info->tx_active = false;
2287
2288 del_timer(&info->tx_timer);
2289
2290 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2291 info->signals &= ~SerialSignal_RTS;
2292 info->drop_rts_on_tx_done = false;
2293 set_signals(info);
2294 }
2295
2296#if SYNCLINK_GENERIC_HDLC
2297 if (info->netcount)
2298 hdlcdev_tx_done(info);
2299 else
2300#endif
2301 {
2302 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2303 tx_stop(info);
2304 return;
2305 }
2306 info->pending_bh |= BH_TRANSMIT;
2307 }
2308 }
2309}
2310
2311static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2312{
2313 struct cond_wait *w, *prev;
2314
2315 /* wake processes waiting for specific transitions */
2316 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2317 if (w->data & changed) {
2318 w->data = state;
2319 wake_up_interruptible(&w->q);
2320 if (prev != NULL)
2321 prev->next = w->next;
2322 else
2323 info->gpio_wait_q = w->next;
2324 } else
2325 prev = w;
2326 }
2327}
2328
2329/* interrupt service routine
2330 *
2331 * irq interrupt number
2332 * dev_id device ID supplied during interrupt registration
2333 */
2334static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2335{
2336 struct slgt_info *info = dev_id;
2337 unsigned int gsr;
2338 unsigned int i;
2339
2340 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2341
2342 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2343 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2344 info->irq_occurred = true;
2345 for(i=0; i < info->port_count ; i++) {
2346 if (info->port_array[i] == NULL)
2347 continue;
2348 spin_lock(&info->port_array[i]->lock);
2349 if (gsr & (BIT8 << i))
2350 isr_serial(info->port_array[i]);
2351 if (gsr & (BIT16 << (i*2)))
2352 isr_rdma(info->port_array[i]);
2353 if (gsr & (BIT17 << (i*2)))
2354 isr_tdma(info->port_array[i]);
2355 spin_unlock(&info->port_array[i]->lock);
2356 }
2357 }
2358
2359 if (info->gpio_present) {
2360 unsigned int state;
2361 unsigned int changed;
2362 spin_lock(&info->lock);
2363 while ((changed = rd_reg32(info, IOSR)) != 0) {
2364 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2365 /* read latched state of GPIO signals */
2366 state = rd_reg32(info, IOVR);
2367 /* clear pending GPIO interrupt bits */
2368 wr_reg32(info, IOSR, changed);
2369 for (i=0 ; i < info->port_count ; i++) {
2370 if (info->port_array[i] != NULL)
2371 isr_gpio(info->port_array[i], changed, state);
2372 }
2373 }
2374 spin_unlock(&info->lock);
2375 }
2376
2377 for(i=0; i < info->port_count ; i++) {
2378 struct slgt_info *port = info->port_array[i];
2379 if (port == NULL)
2380 continue;
2381 spin_lock(&port->lock);
2382 if ((port->port.count || port->netcount) &&
2383 port->pending_bh && !port->bh_running &&
2384 !port->bh_requested) {
2385 DBGISR(("%s bh queued\n", port->device_name));
2386 schedule_work(&port->task);
2387 port->bh_requested = true;
2388 }
2389 spin_unlock(&port->lock);
2390 }
2391
2392 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2393 return IRQ_HANDLED;
2394}
2395
2396static int startup(struct slgt_info *info)
2397{
2398 DBGINFO(("%s startup\n", info->device_name));
2399
2400 if (tty_port_initialized(&info->port))
2401 return 0;
2402
2403 if (!info->tx_buf) {
2404 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2405 if (!info->tx_buf) {
2406 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2407 return -ENOMEM;
2408 }
2409 }
2410
2411 info->pending_bh = 0;
2412
2413 memset(&info->icount, 0, sizeof(info->icount));
2414
2415 /* program hardware for current parameters */
2416 change_params(info);
2417
2418 if (info->port.tty)
2419 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2420
2421 tty_port_set_initialized(&info->port, 1);
2422
2423 return 0;
2424}
2425
2426/*
2427 * called by close() and hangup() to shutdown hardware
2428 */
2429static void shutdown(struct slgt_info *info)
2430{
2431 unsigned long flags;
2432
2433 if (!tty_port_initialized(&info->port))
2434 return;
2435
2436 DBGINFO(("%s shutdown\n", info->device_name));
2437
2438 /* clear status wait queue because status changes */
2439 /* can't happen after shutting down the hardware */
2440 wake_up_interruptible(&info->status_event_wait_q);
2441 wake_up_interruptible(&info->event_wait_q);
2442
2443 del_timer_sync(&info->tx_timer);
2444 del_timer_sync(&info->rx_timer);
2445
2446 kfree(info->tx_buf);
2447 info->tx_buf = NULL;
2448
2449 spin_lock_irqsave(&info->lock,flags);
2450
2451 tx_stop(info);
2452 rx_stop(info);
2453
2454 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2455
2456 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2457 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2458 set_signals(info);
2459 }
2460
2461 flush_cond_wait(&info->gpio_wait_q);
2462
2463 spin_unlock_irqrestore(&info->lock,flags);
2464
2465 if (info->port.tty)
2466 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2467
2468 tty_port_set_initialized(&info->port, 0);
2469}
2470
2471static void program_hw(struct slgt_info *info)
2472{
2473 unsigned long flags;
2474
2475 spin_lock_irqsave(&info->lock,flags);
2476
2477 rx_stop(info);
2478 tx_stop(info);
2479
2480 if (info->params.mode != MGSL_MODE_ASYNC ||
2481 info->netcount)
2482 sync_mode(info);
2483 else
2484 async_mode(info);
2485
2486 set_signals(info);
2487
2488 info->dcd_chkcount = 0;
2489 info->cts_chkcount = 0;
2490 info->ri_chkcount = 0;
2491 info->dsr_chkcount = 0;
2492
2493 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2494 get_signals(info);
2495
2496 if (info->netcount ||
2497 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2498 rx_start(info);
2499
2500 spin_unlock_irqrestore(&info->lock,flags);
2501}
2502
2503/*
2504 * reconfigure adapter based on new parameters
2505 */
2506static void change_params(struct slgt_info *info)
2507{
2508 unsigned cflag;
2509 int bits_per_char;
2510
2511 if (!info->port.tty)
2512 return;
2513 DBGINFO(("%s change_params\n", info->device_name));
2514
2515 cflag = info->port.tty->termios.c_cflag;
2516
2517 /* if B0 rate (hangup) specified then negate RTS and DTR */
2518 /* otherwise assert RTS and DTR */
2519 if (cflag & CBAUD)
2520 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2521 else
2522 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2523
2524 /* byte size and parity */
2525
2526 switch (cflag & CSIZE) {
2527 case CS5: info->params.data_bits = 5; break;
2528 case CS6: info->params.data_bits = 6; break;
2529 case CS7: info->params.data_bits = 7; break;
2530 case CS8: info->params.data_bits = 8; break;
2531 default: info->params.data_bits = 7; break;
2532 }
2533
2534 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2535
2536 if (cflag & PARENB)
2537 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2538 else
2539 info->params.parity = ASYNC_PARITY_NONE;
2540
2541 /* calculate number of jiffies to transmit a full
2542 * FIFO (32 bytes) at specified data rate
2543 */
2544 bits_per_char = info->params.data_bits +
2545 info->params.stop_bits + 1;
2546
2547 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2548
2549 if (info->params.data_rate) {
2550 info->timeout = (32*HZ*bits_per_char) /
2551 info->params.data_rate;
2552 }
2553 info->timeout += HZ/50; /* Add .02 seconds of slop */
2554
2555 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2556 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2557
2558 /* process tty input control flags */
2559
2560 info->read_status_mask = IRQ_RXOVER;
2561 if (I_INPCK(info->port.tty))
2562 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2563 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2564 info->read_status_mask |= MASK_BREAK;
2565 if (I_IGNPAR(info->port.tty))
2566 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2567 if (I_IGNBRK(info->port.tty)) {
2568 info->ignore_status_mask |= MASK_BREAK;
2569 /* If ignoring parity and break indicators, ignore
2570 * overruns too. (For real raw support).
2571 */
2572 if (I_IGNPAR(info->port.tty))
2573 info->ignore_status_mask |= MASK_OVERRUN;
2574 }
2575
2576 program_hw(info);
2577}
2578
2579static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2580{
2581 DBGINFO(("%s get_stats\n", info->device_name));
2582 if (!user_icount) {
2583 memset(&info->icount, 0, sizeof(info->icount));
2584 } else {
2585 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2586 return -EFAULT;
2587 }
2588 return 0;
2589}
2590
2591static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2592{
2593 DBGINFO(("%s get_params\n", info->device_name));
2594 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2595 return -EFAULT;
2596 return 0;
2597}
2598
2599static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2600{
2601 unsigned long flags;
2602 MGSL_PARAMS tmp_params;
2603
2604 DBGINFO(("%s set_params\n", info->device_name));
2605 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2606 return -EFAULT;
2607
2608 spin_lock_irqsave(&info->lock, flags);
2609 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2610 info->base_clock = tmp_params.clock_speed;
2611 else
2612 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2613 spin_unlock_irqrestore(&info->lock, flags);
2614
2615 program_hw(info);
2616
2617 return 0;
2618}
2619
2620static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2621{
2622 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2623 if (put_user(info->idle_mode, idle_mode))
2624 return -EFAULT;
2625 return 0;
2626}
2627
2628static int set_txidle(struct slgt_info *info, int idle_mode)
2629{
2630 unsigned long flags;
2631 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2632 spin_lock_irqsave(&info->lock,flags);
2633 info->idle_mode = idle_mode;
2634 if (info->params.mode != MGSL_MODE_ASYNC)
2635 tx_set_idle(info);
2636 spin_unlock_irqrestore(&info->lock,flags);
2637 return 0;
2638}
2639
2640static int tx_enable(struct slgt_info *info, int enable)
2641{
2642 unsigned long flags;
2643 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2644 spin_lock_irqsave(&info->lock,flags);
2645 if (enable) {
2646 if (!info->tx_enabled)
2647 tx_start(info);
2648 } else {
2649 if (info->tx_enabled)
2650 tx_stop(info);
2651 }
2652 spin_unlock_irqrestore(&info->lock,flags);
2653 return 0;
2654}
2655
2656/*
2657 * abort transmit HDLC frame
2658 */
2659static int tx_abort(struct slgt_info *info)
2660{
2661 unsigned long flags;
2662 DBGINFO(("%s tx_abort\n", info->device_name));
2663 spin_lock_irqsave(&info->lock,flags);
2664 tdma_reset(info);
2665 spin_unlock_irqrestore(&info->lock,flags);
2666 return 0;
2667}
2668
2669static int rx_enable(struct slgt_info *info, int enable)
2670{
2671 unsigned long flags;
2672 unsigned int rbuf_fill_level;
2673 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2674 spin_lock_irqsave(&info->lock,flags);
2675 /*
2676 * enable[31..16] = receive DMA buffer fill level
2677 * 0 = noop (leave fill level unchanged)
2678 * fill level must be multiple of 4 and <= buffer size
2679 */
2680 rbuf_fill_level = ((unsigned int)enable) >> 16;
2681 if (rbuf_fill_level) {
2682 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2683 spin_unlock_irqrestore(&info->lock, flags);
2684 return -EINVAL;
2685 }
2686 info->rbuf_fill_level = rbuf_fill_level;
2687 if (rbuf_fill_level < 128)
2688 info->rx_pio = 1; /* PIO mode */
2689 else
2690 info->rx_pio = 0; /* DMA mode */
2691 rx_stop(info); /* restart receiver to use new fill level */
2692 }
2693
2694 /*
2695 * enable[1..0] = receiver enable command
2696 * 0 = disable
2697 * 1 = enable
2698 * 2 = enable or force hunt mode if already enabled
2699 */
2700 enable &= 3;
2701 if (enable) {
2702 if (!info->rx_enabled)
2703 rx_start(info);
2704 else if (enable == 2) {
2705 /* force hunt mode (write 1 to RCR[3]) */
2706 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2707 }
2708 } else {
2709 if (info->rx_enabled)
2710 rx_stop(info);
2711 }
2712 spin_unlock_irqrestore(&info->lock,flags);
2713 return 0;
2714}
2715
2716/*
2717 * wait for specified event to occur
2718 */
2719static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2720{
2721 unsigned long flags;
2722 int s;
2723 int rc=0;
2724 struct mgsl_icount cprev, cnow;
2725 int events;
2726 int mask;
2727 struct _input_signal_events oldsigs, newsigs;
2728 DECLARE_WAITQUEUE(wait, current);
2729
2730 if (get_user(mask, mask_ptr))
2731 return -EFAULT;
2732
2733 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2734
2735 spin_lock_irqsave(&info->lock,flags);
2736
2737 /* return immediately if state matches requested events */
2738 get_signals(info);
2739 s = info->signals;
2740
2741 events = mask &
2742 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2743 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2744 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2745 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2746 if (events) {
2747 spin_unlock_irqrestore(&info->lock,flags);
2748 goto exit;
2749 }
2750
2751 /* save current irq counts */
2752 cprev = info->icount;
2753 oldsigs = info->input_signal_events;
2754
2755 /* enable hunt and idle irqs if needed */
2756 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2757 unsigned short val = rd_reg16(info, SCR);
2758 if (!(val & IRQ_RXIDLE))
2759 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2760 }
2761
2762 set_current_state(TASK_INTERRUPTIBLE);
2763 add_wait_queue(&info->event_wait_q, &wait);
2764
2765 spin_unlock_irqrestore(&info->lock,flags);
2766
2767 for(;;) {
2768 schedule();
2769 if (signal_pending(current)) {
2770 rc = -ERESTARTSYS;
2771 break;
2772 }
2773
2774 /* get current irq counts */
2775 spin_lock_irqsave(&info->lock,flags);
2776 cnow = info->icount;
2777 newsigs = info->input_signal_events;
2778 set_current_state(TASK_INTERRUPTIBLE);
2779 spin_unlock_irqrestore(&info->lock,flags);
2780
2781 /* if no change, wait aborted for some reason */
2782 if (newsigs.dsr_up == oldsigs.dsr_up &&
2783 newsigs.dsr_down == oldsigs.dsr_down &&
2784 newsigs.dcd_up == oldsigs.dcd_up &&
2785 newsigs.dcd_down == oldsigs.dcd_down &&
2786 newsigs.cts_up == oldsigs.cts_up &&
2787 newsigs.cts_down == oldsigs.cts_down &&
2788 newsigs.ri_up == oldsigs.ri_up &&
2789 newsigs.ri_down == oldsigs.ri_down &&
2790 cnow.exithunt == cprev.exithunt &&
2791 cnow.rxidle == cprev.rxidle) {
2792 rc = -EIO;
2793 break;
2794 }
2795
2796 events = mask &
2797 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2798 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2799 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2800 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2801 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2802 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2803 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2804 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2805 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2806 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2807 if (events)
2808 break;
2809
2810 cprev = cnow;
2811 oldsigs = newsigs;
2812 }
2813
2814 remove_wait_queue(&info->event_wait_q, &wait);
2815 set_current_state(TASK_RUNNING);
2816
2817
2818 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2819 spin_lock_irqsave(&info->lock,flags);
2820 if (!waitqueue_active(&info->event_wait_q)) {
2821 /* disable enable exit hunt mode/idle rcvd IRQs */
2822 wr_reg16(info, SCR,
2823 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2824 }
2825 spin_unlock_irqrestore(&info->lock,flags);
2826 }
2827exit:
2828 if (rc == 0)
2829 rc = put_user(events, mask_ptr);
2830 return rc;
2831}
2832
2833static int get_interface(struct slgt_info *info, int __user *if_mode)
2834{
2835 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2836 if (put_user(info->if_mode, if_mode))
2837 return -EFAULT;
2838 return 0;
2839}
2840
2841static int set_interface(struct slgt_info *info, int if_mode)
2842{
2843 unsigned long flags;
2844 unsigned short val;
2845
2846 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2847 spin_lock_irqsave(&info->lock,flags);
2848 info->if_mode = if_mode;
2849
2850 msc_set_vcr(info);
2851
2852 /* TCR (tx control) 07 1=RTS driver control */
2853 val = rd_reg16(info, TCR);
2854 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2855 val |= BIT7;
2856 else
2857 val &= ~BIT7;
2858 wr_reg16(info, TCR, val);
2859
2860 spin_unlock_irqrestore(&info->lock,flags);
2861 return 0;
2862}
2863
2864static int get_xsync(struct slgt_info *info, int __user *xsync)
2865{
2866 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2867 if (put_user(info->xsync, xsync))
2868 return -EFAULT;
2869 return 0;
2870}
2871
2872/*
2873 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2874 *
2875 * sync pattern is contained in least significant bytes of value
2876 * most significant byte of sync pattern is oldest (1st sent/detected)
2877 */
2878static int set_xsync(struct slgt_info *info, int xsync)
2879{
2880 unsigned long flags;
2881
2882 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2883 spin_lock_irqsave(&info->lock, flags);
2884 info->xsync = xsync;
2885 wr_reg32(info, XSR, xsync);
2886 spin_unlock_irqrestore(&info->lock, flags);
2887 return 0;
2888}
2889
2890static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2891{
2892 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2893 if (put_user(info->xctrl, xctrl))
2894 return -EFAULT;
2895 return 0;
2896}
2897
2898/*
2899 * set extended control options
2900 *
2901 * xctrl[31:19] reserved, must be zero
2902 * xctrl[18:17] extended sync pattern length in bytes
2903 * 00 = 1 byte in xsr[7:0]
2904 * 01 = 2 bytes in xsr[15:0]
2905 * 10 = 3 bytes in xsr[23:0]
2906 * 11 = 4 bytes in xsr[31:0]
2907 * xctrl[16] 1 = enable terminal count, 0=disabled
2908 * xctrl[15:0] receive terminal count for fixed length packets
2909 * value is count minus one (0 = 1 byte packet)
2910 * when terminal count is reached, receiver
2911 * automatically returns to hunt mode and receive
2912 * FIFO contents are flushed to DMA buffers with
2913 * end of frame (EOF) status
2914 */
2915static int set_xctrl(struct slgt_info *info, int xctrl)
2916{
2917 unsigned long flags;
2918
2919 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2920 spin_lock_irqsave(&info->lock, flags);
2921 info->xctrl = xctrl;
2922 wr_reg32(info, XCR, xctrl);
2923 spin_unlock_irqrestore(&info->lock, flags);
2924 return 0;
2925}
2926
2927/*
2928 * set general purpose IO pin state and direction
2929 *
2930 * user_gpio fields:
2931 * state each bit indicates a pin state
2932 * smask set bit indicates pin state to set
2933 * dir each bit indicates a pin direction (0=input, 1=output)
2934 * dmask set bit indicates pin direction to set
2935 */
2936static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2937{
2938 unsigned long flags;
2939 struct gpio_desc gpio;
2940 __u32 data;
2941
2942 if (!info->gpio_present)
2943 return -EINVAL;
2944 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2945 return -EFAULT;
2946 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2947 info->device_name, gpio.state, gpio.smask,
2948 gpio.dir, gpio.dmask));
2949
2950 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2951 if (gpio.dmask) {
2952 data = rd_reg32(info, IODR);
2953 data |= gpio.dmask & gpio.dir;
2954 data &= ~(gpio.dmask & ~gpio.dir);
2955 wr_reg32(info, IODR, data);
2956 }
2957 if (gpio.smask) {
2958 data = rd_reg32(info, IOVR);
2959 data |= gpio.smask & gpio.state;
2960 data &= ~(gpio.smask & ~gpio.state);
2961 wr_reg32(info, IOVR, data);
2962 }
2963 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2964
2965 return 0;
2966}
2967
2968/*
2969 * get general purpose IO pin state and direction
2970 */
2971static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2972{
2973 struct gpio_desc gpio;
2974 if (!info->gpio_present)
2975 return -EINVAL;
2976 gpio.state = rd_reg32(info, IOVR);
2977 gpio.smask = 0xffffffff;
2978 gpio.dir = rd_reg32(info, IODR);
2979 gpio.dmask = 0xffffffff;
2980 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2981 return -EFAULT;
2982 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2983 info->device_name, gpio.state, gpio.dir));
2984 return 0;
2985}
2986
2987/*
2988 * conditional wait facility
2989 */
2990static void init_cond_wait(struct cond_wait *w, unsigned int data)
2991{
2992 init_waitqueue_head(&w->q);
2993 init_waitqueue_entry(&w->wait, current);
2994 w->data = data;
2995}
2996
2997static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2998{
2999 set_current_state(TASK_INTERRUPTIBLE);
3000 add_wait_queue(&w->q, &w->wait);
3001 w->next = *head;
3002 *head = w;
3003}
3004
3005static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3006{
3007 struct cond_wait *w, *prev;
3008 remove_wait_queue(&cw->q, &cw->wait);
3009 set_current_state(TASK_RUNNING);
3010 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3011 if (w == cw) {
3012 if (prev != NULL)
3013 prev->next = w->next;
3014 else
3015 *head = w->next;
3016 break;
3017 }
3018 }
3019}
3020
3021static void flush_cond_wait(struct cond_wait **head)
3022{
3023 while (*head != NULL) {
3024 wake_up_interruptible(&(*head)->q);
3025 *head = (*head)->next;
3026 }
3027}
3028
3029/*
3030 * wait for general purpose I/O pin(s) to enter specified state
3031 *
3032 * user_gpio fields:
3033 * state - bit indicates target pin state
3034 * smask - set bit indicates watched pin
3035 *
3036 * The wait ends when at least one watched pin enters the specified
3037 * state. When 0 (no error) is returned, user_gpio->state is set to the
3038 * state of all GPIO pins when the wait ends.
3039 *
3040 * Note: Each pin may be a dedicated input, dedicated output, or
3041 * configurable input/output. The number and configuration of pins
3042 * varies with the specific adapter model. Only input pins (dedicated
3043 * or configured) can be monitored with this function.
3044 */
3045static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3046{
3047 unsigned long flags;
3048 int rc = 0;
3049 struct gpio_desc gpio;
3050 struct cond_wait wait;
3051 u32 state;
3052
3053 if (!info->gpio_present)
3054 return -EINVAL;
3055 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3056 return -EFAULT;
3057 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3058 info->device_name, gpio.state, gpio.smask));
3059 /* ignore output pins identified by set IODR bit */
3060 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3061 return -EINVAL;
3062 init_cond_wait(&wait, gpio.smask);
3063
3064 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3065 /* enable interrupts for watched pins */
3066 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3067 /* get current pin states */
3068 state = rd_reg32(info, IOVR);
3069
3070 if (gpio.smask & ~(state ^ gpio.state)) {
3071 /* already in target state */
3072 gpio.state = state;
3073 } else {
3074 /* wait for target state */
3075 add_cond_wait(&info->gpio_wait_q, &wait);
3076 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3077 schedule();
3078 if (signal_pending(current))
3079 rc = -ERESTARTSYS;
3080 else
3081 gpio.state = wait.data;
3082 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3083 remove_cond_wait(&info->gpio_wait_q, &wait);
3084 }
3085
3086 /* disable all GPIO interrupts if no waiting processes */
3087 if (info->gpio_wait_q == NULL)
3088 wr_reg32(info, IOER, 0);
3089 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3090
3091 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3092 rc = -EFAULT;
3093 return rc;
3094}
3095
3096static int modem_input_wait(struct slgt_info *info,int arg)
3097{
3098 unsigned long flags;
3099 int rc;
3100 struct mgsl_icount cprev, cnow;
3101 DECLARE_WAITQUEUE(wait, current);
3102
3103 /* save current irq counts */
3104 spin_lock_irqsave(&info->lock,flags);
3105 cprev = info->icount;
3106 add_wait_queue(&info->status_event_wait_q, &wait);
3107 set_current_state(TASK_INTERRUPTIBLE);
3108 spin_unlock_irqrestore(&info->lock,flags);
3109
3110 for(;;) {
3111 schedule();
3112 if (signal_pending(current)) {
3113 rc = -ERESTARTSYS;
3114 break;
3115 }
3116
3117 /* get new irq counts */
3118 spin_lock_irqsave(&info->lock,flags);
3119 cnow = info->icount;
3120 set_current_state(TASK_INTERRUPTIBLE);
3121 spin_unlock_irqrestore(&info->lock,flags);
3122
3123 /* if no change, wait aborted for some reason */
3124 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3125 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3126 rc = -EIO;
3127 break;
3128 }
3129
3130 /* check for change in caller specified modem input */
3131 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3132 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3133 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3134 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3135 rc = 0;
3136 break;
3137 }
3138
3139 cprev = cnow;
3140 }
3141 remove_wait_queue(&info->status_event_wait_q, &wait);
3142 set_current_state(TASK_RUNNING);
3143 return rc;
3144}
3145
3146/*
3147 * return state of serial control and status signals
3148 */
3149static int tiocmget(struct tty_struct *tty)
3150{
3151 struct slgt_info *info = tty->driver_data;
3152 unsigned int result;
3153 unsigned long flags;
3154
3155 spin_lock_irqsave(&info->lock,flags);
3156 get_signals(info);
3157 spin_unlock_irqrestore(&info->lock,flags);
3158
3159 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3160 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3161 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3162 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3163 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3164 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3165
3166 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3167 return result;
3168}
3169
3170/*
3171 * set modem control signals (DTR/RTS)
3172 *
3173 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3174 * TIOCMSET = set/clear signal values
3175 * value bit mask for command
3176 */
3177static int tiocmset(struct tty_struct *tty,
3178 unsigned int set, unsigned int clear)
3179{
3180 struct slgt_info *info = tty->driver_data;
3181 unsigned long flags;
3182
3183 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3184
3185 if (set & TIOCM_RTS)
3186 info->signals |= SerialSignal_RTS;
3187 if (set & TIOCM_DTR)
3188 info->signals |= SerialSignal_DTR;
3189 if (clear & TIOCM_RTS)
3190 info->signals &= ~SerialSignal_RTS;
3191 if (clear & TIOCM_DTR)
3192 info->signals &= ~SerialSignal_DTR;
3193
3194 spin_lock_irqsave(&info->lock,flags);
3195 set_signals(info);
3196 spin_unlock_irqrestore(&info->lock,flags);
3197 return 0;
3198}
3199
3200static int carrier_raised(struct tty_port *port)
3201{
3202 unsigned long flags;
3203 struct slgt_info *info = container_of(port, struct slgt_info, port);
3204
3205 spin_lock_irqsave(&info->lock,flags);
3206 get_signals(info);
3207 spin_unlock_irqrestore(&info->lock,flags);
3208 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3209}
3210
3211static void dtr_rts(struct tty_port *port, int on)
3212{
3213 unsigned long flags;
3214 struct slgt_info *info = container_of(port, struct slgt_info, port);
3215
3216 spin_lock_irqsave(&info->lock,flags);
3217 if (on)
3218 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3219 else
3220 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3221 set_signals(info);
3222 spin_unlock_irqrestore(&info->lock,flags);
3223}
3224
3225
3226/*
3227 * block current process until the device is ready to open
3228 */
3229static int block_til_ready(struct tty_struct *tty, struct file *filp,
3230 struct slgt_info *info)
3231{
3232 DECLARE_WAITQUEUE(wait, current);
3233 int retval;
3234 bool do_clocal = false;
3235 unsigned long flags;
3236 int cd;
3237 struct tty_port *port = &info->port;
3238
3239 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3240
3241 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3242 /* nonblock mode is set or port is not enabled */
3243 tty_port_set_active(port, 1);
3244 return 0;
3245 }
3246
3247 if (C_CLOCAL(tty))
3248 do_clocal = true;
3249
3250 /* Wait for carrier detect and the line to become
3251 * free (i.e., not in use by the callout). While we are in
3252 * this loop, port->count is dropped by one, so that
3253 * close() knows when to free things. We restore it upon
3254 * exit, either normal or abnormal.
3255 */
3256
3257 retval = 0;
3258 add_wait_queue(&port->open_wait, &wait);
3259
3260 spin_lock_irqsave(&info->lock, flags);
3261 port->count--;
3262 spin_unlock_irqrestore(&info->lock, flags);
3263 port->blocked_open++;
3264
3265 while (1) {
3266 if (C_BAUD(tty) && tty_port_initialized(port))
3267 tty_port_raise_dtr_rts(port);
3268
3269 set_current_state(TASK_INTERRUPTIBLE);
3270
3271 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3272 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3273 -EAGAIN : -ERESTARTSYS;
3274 break;
3275 }
3276
3277 cd = tty_port_carrier_raised(port);
3278 if (do_clocal || cd)
3279 break;
3280
3281 if (signal_pending(current)) {
3282 retval = -ERESTARTSYS;
3283 break;
3284 }
3285
3286 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3287 tty_unlock(tty);
3288 schedule();
3289 tty_lock(tty);
3290 }
3291
3292 set_current_state(TASK_RUNNING);
3293 remove_wait_queue(&port->open_wait, &wait);
3294
3295 if (!tty_hung_up_p(filp))
3296 port->count++;
3297 port->blocked_open--;
3298
3299 if (!retval)
3300 tty_port_set_active(port, 1);
3301
3302 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3303 return retval;
3304}
3305
3306/*
3307 * allocate buffers used for calling line discipline receive_buf
3308 * directly in synchronous mode
3309 * note: add 5 bytes to max frame size to allow appending
3310 * 32-bit CRC and status byte when configured to do so
3311 */
3312static int alloc_tmp_rbuf(struct slgt_info *info)
3313{
3314 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3315 if (info->tmp_rbuf == NULL)
3316 return -ENOMEM;
3317 /* unused flag buffer to satisfy receive_buf calling interface */
3318 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3319 if (!info->flag_buf) {
3320 kfree(info->tmp_rbuf);
3321 info->tmp_rbuf = NULL;
3322 return -ENOMEM;
3323 }
3324 return 0;
3325}
3326
3327static void free_tmp_rbuf(struct slgt_info *info)
3328{
3329 kfree(info->tmp_rbuf);
3330 info->tmp_rbuf = NULL;
3331 kfree(info->flag_buf);
3332 info->flag_buf = NULL;
3333}
3334
3335/*
3336 * allocate DMA descriptor lists.
3337 */
3338static int alloc_desc(struct slgt_info *info)
3339{
3340 unsigned int i;
3341 unsigned int pbufs;
3342
3343 /* allocate memory to hold descriptor lists */
3344 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3345 &info->bufs_dma_addr);
3346 if (info->bufs == NULL)
3347 return -ENOMEM;
3348
3349 info->rbufs = (struct slgt_desc*)info->bufs;
3350 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3351
3352 pbufs = (unsigned int)info->bufs_dma_addr;
3353
3354 /*
3355 * Build circular lists of descriptors
3356 */
3357
3358 for (i=0; i < info->rbuf_count; i++) {
3359 /* physical address of this descriptor */
3360 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3361
3362 /* physical address of next descriptor */
3363 if (i == info->rbuf_count - 1)
3364 info->rbufs[i].next = cpu_to_le32(pbufs);
3365 else
3366 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3367 set_desc_count(info->rbufs[i], DMABUFSIZE);
3368 }
3369
3370 for (i=0; i < info->tbuf_count; i++) {
3371 /* physical address of this descriptor */
3372 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3373
3374 /* physical address of next descriptor */
3375 if (i == info->tbuf_count - 1)
3376 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3377 else
3378 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3379 }
3380
3381 return 0;
3382}
3383
3384static void free_desc(struct slgt_info *info)
3385{
3386 if (info->bufs != NULL) {
3387 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3388 info->bufs = NULL;
3389 info->rbufs = NULL;
3390 info->tbufs = NULL;
3391 }
3392}
3393
3394static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3395{
3396 int i;
3397 for (i=0; i < count; i++) {
3398 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3399 return -ENOMEM;
3400 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3401 }
3402 return 0;
3403}
3404
3405static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3406{
3407 int i;
3408 for (i=0; i < count; i++) {
3409 if (bufs[i].buf == NULL)
3410 continue;
3411 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3412 bufs[i].buf = NULL;
3413 }
3414}
3415
3416static int alloc_dma_bufs(struct slgt_info *info)
3417{
3418 info->rbuf_count = 32;
3419 info->tbuf_count = 32;
3420
3421 if (alloc_desc(info) < 0 ||
3422 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3423 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3424 alloc_tmp_rbuf(info) < 0) {
3425 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3426 return -ENOMEM;
3427 }
3428 reset_rbufs(info);
3429 return 0;
3430}
3431
3432static void free_dma_bufs(struct slgt_info *info)
3433{
3434 if (info->bufs) {
3435 free_bufs(info, info->rbufs, info->rbuf_count);
3436 free_bufs(info, info->tbufs, info->tbuf_count);
3437 free_desc(info);
3438 }
3439 free_tmp_rbuf(info);
3440}
3441
3442static int claim_resources(struct slgt_info *info)
3443{
3444 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3445 DBGERR(("%s reg addr conflict, addr=%08X\n",
3446 info->device_name, info->phys_reg_addr));
3447 info->init_error = DiagStatus_AddressConflict;
3448 goto errout;
3449 }
3450 else
3451 info->reg_addr_requested = true;
3452
3453 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3454 if (!info->reg_addr) {
3455 DBGERR(("%s can't map device registers, addr=%08X\n",
3456 info->device_name, info->phys_reg_addr));
3457 info->init_error = DiagStatus_CantAssignPciResources;
3458 goto errout;
3459 }
3460 return 0;
3461
3462errout:
3463 release_resources(info);
3464 return -ENODEV;
3465}
3466
3467static void release_resources(struct slgt_info *info)
3468{
3469 if (info->irq_requested) {
3470 free_irq(info->irq_level, info);
3471 info->irq_requested = false;
3472 }
3473
3474 if (info->reg_addr_requested) {
3475 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3476 info->reg_addr_requested = false;
3477 }
3478
3479 if (info->reg_addr) {
3480 iounmap(info->reg_addr);
3481 info->reg_addr = NULL;
3482 }
3483}
3484
3485/* Add the specified device instance data structure to the
3486 * global linked list of devices and increment the device count.
3487 */
3488static void add_device(struct slgt_info *info)
3489{
3490 char *devstr;
3491
3492 info->next_device = NULL;
3493 info->line = slgt_device_count;
3494 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3495
3496 if (info->line < MAX_DEVICES) {
3497 if (maxframe[info->line])
3498 info->max_frame_size = maxframe[info->line];
3499 }
3500
3501 slgt_device_count++;
3502
3503 if (!slgt_device_list)
3504 slgt_device_list = info;
3505 else {
3506 struct slgt_info *current_dev = slgt_device_list;
3507 while(current_dev->next_device)
3508 current_dev = current_dev->next_device;
3509 current_dev->next_device = info;
3510 }
3511
3512 if (info->max_frame_size < 4096)
3513 info->max_frame_size = 4096;
3514 else if (info->max_frame_size > 65535)
3515 info->max_frame_size = 65535;
3516
3517 switch(info->pdev->device) {
3518 case SYNCLINK_GT_DEVICE_ID:
3519 devstr = "GT";
3520 break;
3521 case SYNCLINK_GT2_DEVICE_ID:
3522 devstr = "GT2";
3523 break;
3524 case SYNCLINK_GT4_DEVICE_ID:
3525 devstr = "GT4";
3526 break;
3527 case SYNCLINK_AC_DEVICE_ID:
3528 devstr = "AC";
3529 info->params.mode = MGSL_MODE_ASYNC;
3530 break;
3531 default:
3532 devstr = "(unknown model)";
3533 }
3534 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3535 devstr, info->device_name, info->phys_reg_addr,
3536 info->irq_level, info->max_frame_size);
3537
3538#if SYNCLINK_GENERIC_HDLC
3539 hdlcdev_init(info);
3540#endif
3541}
3542
3543static const struct tty_port_operations slgt_port_ops = {
3544 .carrier_raised = carrier_raised,
3545 .dtr_rts = dtr_rts,
3546};
3547
3548/*
3549 * allocate device instance structure, return NULL on failure
3550 */
3551static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3552{
3553 struct slgt_info *info;
3554
3555 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3556
3557 if (!info) {
3558 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3559 driver_name, adapter_num, port_num));
3560 } else {
3561 tty_port_init(&info->port);
3562 info->port.ops = &slgt_port_ops;
3563 info->magic = MGSL_MAGIC;
3564 INIT_WORK(&info->task, bh_handler);
3565 info->max_frame_size = 4096;
3566 info->base_clock = 14745600;
3567 info->rbuf_fill_level = DMABUFSIZE;
3568 info->port.close_delay = 5*HZ/10;
3569 info->port.closing_wait = 30*HZ;
3570 init_waitqueue_head(&info->status_event_wait_q);
3571 init_waitqueue_head(&info->event_wait_q);
3572 spin_lock_init(&info->netlock);
3573 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3574 info->idle_mode = HDLC_TXIDLE_FLAGS;
3575 info->adapter_num = adapter_num;
3576 info->port_num = port_num;
3577
3578 timer_setup(&info->tx_timer, tx_timeout, 0);
3579 timer_setup(&info->rx_timer, rx_timeout, 0);
3580
3581 /* Copy configuration info to device instance data */
3582 info->pdev = pdev;
3583 info->irq_level = pdev->irq;
3584 info->phys_reg_addr = pci_resource_start(pdev,0);
3585
3586 info->bus_type = MGSL_BUS_TYPE_PCI;
3587 info->irq_flags = IRQF_SHARED;
3588
3589 info->init_error = -1; /* assume error, set to 0 on successful init */
3590 }
3591
3592 return info;
3593}
3594
3595static void device_init(int adapter_num, struct pci_dev *pdev)
3596{
3597 struct slgt_info *port_array[SLGT_MAX_PORTS];
3598 int i;
3599 int port_count = 1;
3600
3601 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3602 port_count = 2;
3603 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3604 port_count = 4;
3605
3606 /* allocate device instances for all ports */
3607 for (i=0; i < port_count; ++i) {
3608 port_array[i] = alloc_dev(adapter_num, i, pdev);
3609 if (port_array[i] == NULL) {
3610 for (--i; i >= 0; --i) {
3611 tty_port_destroy(&port_array[i]->port);
3612 kfree(port_array[i]);
3613 }
3614 return;
3615 }
3616 }
3617
3618 /* give copy of port_array to all ports and add to device list */
3619 for (i=0; i < port_count; ++i) {
3620 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3621 add_device(port_array[i]);
3622 port_array[i]->port_count = port_count;
3623 spin_lock_init(&port_array[i]->lock);
3624 }
3625
3626 /* Allocate and claim adapter resources */
3627 if (!claim_resources(port_array[0])) {
3628
3629 alloc_dma_bufs(port_array[0]);
3630
3631 /* copy resource information from first port to others */
3632 for (i = 1; i < port_count; ++i) {
3633 port_array[i]->irq_level = port_array[0]->irq_level;
3634 port_array[i]->reg_addr = port_array[0]->reg_addr;
3635 alloc_dma_bufs(port_array[i]);
3636 }
3637
3638 if (request_irq(port_array[0]->irq_level,
3639 slgt_interrupt,
3640 port_array[0]->irq_flags,
3641 port_array[0]->device_name,
3642 port_array[0]) < 0) {
3643 DBGERR(("%s request_irq failed IRQ=%d\n",
3644 port_array[0]->device_name,
3645 port_array[0]->irq_level));
3646 } else {
3647 port_array[0]->irq_requested = true;
3648 adapter_test(port_array[0]);
3649 for (i=1 ; i < port_count ; i++) {
3650 port_array[i]->init_error = port_array[0]->init_error;
3651 port_array[i]->gpio_present = port_array[0]->gpio_present;
3652 }
3653 }
3654 }
3655
3656 for (i = 0; i < port_count; ++i) {
3657 struct slgt_info *info = port_array[i];
3658 tty_port_register_device(&info->port, serial_driver, info->line,
3659 &info->pdev->dev);
3660 }
3661}
3662
3663static int init_one(struct pci_dev *dev,
3664 const struct pci_device_id *ent)
3665{
3666 if (pci_enable_device(dev)) {
3667 printk("error enabling pci device %p\n", dev);
3668 return -EIO;
3669 }
3670 pci_set_master(dev);
3671 device_init(slgt_device_count, dev);
3672 return 0;
3673}
3674
3675static void remove_one(struct pci_dev *dev)
3676{
3677}
3678
3679static const struct tty_operations ops = {
3680 .open = open,
3681 .close = close,
3682 .write = write,
3683 .put_char = put_char,
3684 .flush_chars = flush_chars,
3685 .write_room = write_room,
3686 .chars_in_buffer = chars_in_buffer,
3687 .flush_buffer = flush_buffer,
3688 .ioctl = ioctl,
3689 .compat_ioctl = slgt_compat_ioctl,
3690 .throttle = throttle,
3691 .unthrottle = unthrottle,
3692 .send_xchar = send_xchar,
3693 .break_ctl = set_break,
3694 .wait_until_sent = wait_until_sent,
3695 .set_termios = set_termios,
3696 .stop = tx_hold,
3697 .start = tx_release,
3698 .hangup = hangup,
3699 .tiocmget = tiocmget,
3700 .tiocmset = tiocmset,
3701 .get_icount = get_icount,
3702 .proc_show = synclink_gt_proc_show,
3703};
3704
3705static void slgt_cleanup(void)
3706{
3707 int rc;
3708 struct slgt_info *info;
3709 struct slgt_info *tmp;
3710
3711 printk(KERN_INFO "unload %s\n", driver_name);
3712
3713 if (serial_driver) {
3714 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3715 tty_unregister_device(serial_driver, info->line);
3716 rc = tty_unregister_driver(serial_driver);
3717 if (rc)
3718 DBGERR(("tty_unregister_driver error=%d\n", rc));
3719 put_tty_driver(serial_driver);
3720 }
3721
3722 /* reset devices */
3723 info = slgt_device_list;
3724 while(info) {
3725 reset_port(info);
3726 info = info->next_device;
3727 }
3728
3729 /* release devices */
3730 info = slgt_device_list;
3731 while(info) {
3732#if SYNCLINK_GENERIC_HDLC
3733 hdlcdev_exit(info);
3734#endif
3735 free_dma_bufs(info);
3736 free_tmp_rbuf(info);
3737 if (info->port_num == 0)
3738 release_resources(info);
3739 tmp = info;
3740 info = info->next_device;
3741 tty_port_destroy(&tmp->port);
3742 kfree(tmp);
3743 }
3744
3745 if (pci_registered)
3746 pci_unregister_driver(&pci_driver);
3747}
3748
3749/*
3750 * Driver initialization entry point.
3751 */
3752static int __init slgt_init(void)
3753{
3754 int rc;
3755
3756 printk(KERN_INFO "%s\n", driver_name);
3757
3758 serial_driver = alloc_tty_driver(MAX_DEVICES);
3759 if (!serial_driver) {
3760 printk("%s can't allocate tty driver\n", driver_name);
3761 return -ENOMEM;
3762 }
3763
3764 /* Initialize the tty_driver structure */
3765
3766 serial_driver->driver_name = slgt_driver_name;
3767 serial_driver->name = tty_dev_prefix;
3768 serial_driver->major = ttymajor;
3769 serial_driver->minor_start = 64;
3770 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3771 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3772 serial_driver->init_termios = tty_std_termios;
3773 serial_driver->init_termios.c_cflag =
3774 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3775 serial_driver->init_termios.c_ispeed = 9600;
3776 serial_driver->init_termios.c_ospeed = 9600;
3777 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3778 tty_set_operations(serial_driver, &ops);
3779 if ((rc = tty_register_driver(serial_driver)) < 0) {
3780 DBGERR(("%s can't register serial driver\n", driver_name));
3781 put_tty_driver(serial_driver);
3782 serial_driver = NULL;
3783 goto error;
3784 }
3785
3786 printk(KERN_INFO "%s, tty major#%d\n",
3787 driver_name, serial_driver->major);
3788
3789 slgt_device_count = 0;
3790 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3791 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3792 goto error;
3793 }
3794 pci_registered = true;
3795
3796 if (!slgt_device_list)
3797 printk("%s no devices found\n",driver_name);
3798
3799 return 0;
3800
3801error:
3802 slgt_cleanup();
3803 return rc;
3804}
3805
3806static void __exit slgt_exit(void)
3807{
3808 slgt_cleanup();
3809}
3810
3811module_init(slgt_init);
3812module_exit(slgt_exit);
3813
3814/*
3815 * register access routines
3816 */
3817
3818#define CALC_REGADDR() \
3819 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3820 if (addr >= 0x80) \
3821 reg_addr += (info->port_num) * 32; \
3822 else if (addr >= 0x40) \
3823 reg_addr += (info->port_num) * 16;
3824
3825static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3826{
3827 CALC_REGADDR();
3828 return readb((void __iomem *)reg_addr);
3829}
3830
3831static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3832{
3833 CALC_REGADDR();
3834 writeb(value, (void __iomem *)reg_addr);
3835}
3836
3837static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3838{
3839 CALC_REGADDR();
3840 return readw((void __iomem *)reg_addr);
3841}
3842
3843static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3844{
3845 CALC_REGADDR();
3846 writew(value, (void __iomem *)reg_addr);
3847}
3848
3849static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3850{
3851 CALC_REGADDR();
3852 return readl((void __iomem *)reg_addr);
3853}
3854
3855static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3856{
3857 CALC_REGADDR();
3858 writel(value, (void __iomem *)reg_addr);
3859}
3860
3861static void rdma_reset(struct slgt_info *info)
3862{
3863 unsigned int i;
3864
3865 /* set reset bit */
3866 wr_reg32(info, RDCSR, BIT1);
3867
3868 /* wait for enable bit cleared */
3869 for(i=0 ; i < 1000 ; i++)
3870 if (!(rd_reg32(info, RDCSR) & BIT0))
3871 break;
3872}
3873
3874static void tdma_reset(struct slgt_info *info)
3875{
3876 unsigned int i;
3877
3878 /* set reset bit */
3879 wr_reg32(info, TDCSR, BIT1);
3880
3881 /* wait for enable bit cleared */
3882 for(i=0 ; i < 1000 ; i++)
3883 if (!(rd_reg32(info, TDCSR) & BIT0))
3884 break;
3885}
3886
3887/*
3888 * enable internal loopback
3889 * TxCLK and RxCLK are generated from BRG
3890 * and TxD is looped back to RxD internally.
3891 */
3892static void enable_loopback(struct slgt_info *info)
3893{
3894 /* SCR (serial control) BIT2=loopback enable */
3895 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 /* CCR (clock control)
3899 * 07..05 tx clock source (010 = BRG)
3900 * 04..02 rx clock source (010 = BRG)
3901 * 01 auxclk enable (0 = disable)
3902 * 00 BRG enable (1 = enable)
3903 *
3904 * 0100 1001
3905 */
3906 wr_reg8(info, CCR, 0x49);
3907
3908 /* set speed if available, otherwise use default */
3909 if (info->params.clock_speed)
3910 set_rate(info, info->params.clock_speed);
3911 else
3912 set_rate(info, 3686400);
3913 }
3914}
3915
3916/*
3917 * set baud rate generator to specified rate
3918 */
3919static void set_rate(struct slgt_info *info, u32 rate)
3920{
3921 unsigned int div;
3922 unsigned int osc = info->base_clock;
3923
3924 /* div = osc/rate - 1
3925 *
3926 * Round div up if osc/rate is not integer to
3927 * force to next slowest rate.
3928 */
3929
3930 if (rate) {
3931 div = osc/rate;
3932 if (!(osc % rate) && div)
3933 div--;
3934 wr_reg16(info, BDR, (unsigned short)div);
3935 }
3936}
3937
3938static void rx_stop(struct slgt_info *info)
3939{
3940 unsigned short val;
3941
3942 /* disable and reset receiver */
3943 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3944 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3945 wr_reg16(info, RCR, val); /* clear reset bit */
3946
3947 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3948
3949 /* clear pending rx interrupts */
3950 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3951
3952 rdma_reset(info);
3953
3954 info->rx_enabled = false;
3955 info->rx_restart = false;
3956}
3957
3958static void rx_start(struct slgt_info *info)
3959{
3960 unsigned short val;
3961
3962 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3963
3964 /* clear pending rx overrun IRQ */
3965 wr_reg16(info, SSR, IRQ_RXOVER);
3966
3967 /* reset and disable receiver */
3968 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3969 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3970 wr_reg16(info, RCR, val); /* clear reset bit */
3971
3972 rdma_reset(info);
3973 reset_rbufs(info);
3974
3975 if (info->rx_pio) {
3976 /* rx request when rx FIFO not empty */
3977 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3978 slgt_irq_on(info, IRQ_RXDATA);
3979 if (info->params.mode == MGSL_MODE_ASYNC) {
3980 /* enable saving of rx status */
3981 wr_reg32(info, RDCSR, BIT6);
3982 }
3983 } else {
3984 /* rx request when rx FIFO half full */
3985 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3986 /* set 1st descriptor address */
3987 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3988
3989 if (info->params.mode != MGSL_MODE_ASYNC) {
3990 /* enable rx DMA and DMA interrupt */
3991 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3992 } else {
3993 /* enable saving of rx status, rx DMA and DMA interrupt */
3994 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3995 }
3996 }
3997
3998 slgt_irq_on(info, IRQ_RXOVER);
3999
4000 /* enable receiver */
4001 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4002
4003 info->rx_restart = false;
4004 info->rx_enabled = true;
4005}
4006
4007static void tx_start(struct slgt_info *info)
4008{
4009 if (!info->tx_enabled) {
4010 wr_reg16(info, TCR,
4011 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4012 info->tx_enabled = true;
4013 }
4014
4015 if (desc_count(info->tbufs[info->tbuf_start])) {
4016 info->drop_rts_on_tx_done = false;
4017
4018 if (info->params.mode != MGSL_MODE_ASYNC) {
4019 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4020 get_signals(info);
4021 if (!(info->signals & SerialSignal_RTS)) {
4022 info->signals |= SerialSignal_RTS;
4023 set_signals(info);
4024 info->drop_rts_on_tx_done = true;
4025 }
4026 }
4027
4028 slgt_irq_off(info, IRQ_TXDATA);
4029 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4030 /* clear tx idle and underrun status bits */
4031 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4032 } else {
4033 slgt_irq_off(info, IRQ_TXDATA);
4034 slgt_irq_on(info, IRQ_TXIDLE);
4035 /* clear tx idle status bit */
4036 wr_reg16(info, SSR, IRQ_TXIDLE);
4037 }
4038 /* set 1st descriptor address and start DMA */
4039 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4040 wr_reg32(info, TDCSR, BIT2 + BIT0);
4041 info->tx_active = true;
4042 }
4043}
4044
4045static void tx_stop(struct slgt_info *info)
4046{
4047 unsigned short val;
4048
4049 del_timer(&info->tx_timer);
4050
4051 tdma_reset(info);
4052
4053 /* reset and disable transmitter */
4054 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4055 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4056
4057 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4058
4059 /* clear tx idle and underrun status bit */
4060 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4061
4062 reset_tbufs(info);
4063
4064 info->tx_enabled = false;
4065 info->tx_active = false;
4066}
4067
4068static void reset_port(struct slgt_info *info)
4069{
4070 if (!info->reg_addr)
4071 return;
4072
4073 tx_stop(info);
4074 rx_stop(info);
4075
4076 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4077 set_signals(info);
4078
4079 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4080}
4081
4082static void reset_adapter(struct slgt_info *info)
4083{
4084 int i;
4085 for (i=0; i < info->port_count; ++i) {
4086 if (info->port_array[i])
4087 reset_port(info->port_array[i]);
4088 }
4089}
4090
4091static void async_mode(struct slgt_info *info)
4092{
4093 unsigned short val;
4094
4095 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4096 tx_stop(info);
4097 rx_stop(info);
4098
4099 /* TCR (tx control)
4100 *
4101 * 15..13 mode, 010=async
4102 * 12..10 encoding, 000=NRZ
4103 * 09 parity enable
4104 * 08 1=odd parity, 0=even parity
4105 * 07 1=RTS driver control
4106 * 06 1=break enable
4107 * 05..04 character length
4108 * 00=5 bits
4109 * 01=6 bits
4110 * 10=7 bits
4111 * 11=8 bits
4112 * 03 0=1 stop bit, 1=2 stop bits
4113 * 02 reset
4114 * 01 enable
4115 * 00 auto-CTS enable
4116 */
4117 val = 0x4000;
4118
4119 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4120 val |= BIT7;
4121
4122 if (info->params.parity != ASYNC_PARITY_NONE) {
4123 val |= BIT9;
4124 if (info->params.parity == ASYNC_PARITY_ODD)
4125 val |= BIT8;
4126 }
4127
4128 switch (info->params.data_bits)
4129 {
4130 case 6: val |= BIT4; break;
4131 case 7: val |= BIT5; break;
4132 case 8: val |= BIT5 + BIT4; break;
4133 }
4134
4135 if (info->params.stop_bits != 1)
4136 val |= BIT3;
4137
4138 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4139 val |= BIT0;
4140
4141 wr_reg16(info, TCR, val);
4142
4143 /* RCR (rx control)
4144 *
4145 * 15..13 mode, 010=async
4146 * 12..10 encoding, 000=NRZ
4147 * 09 parity enable
4148 * 08 1=odd parity, 0=even parity
4149 * 07..06 reserved, must be 0
4150 * 05..04 character length
4151 * 00=5 bits
4152 * 01=6 bits
4153 * 10=7 bits
4154 * 11=8 bits
4155 * 03 reserved, must be zero
4156 * 02 reset
4157 * 01 enable
4158 * 00 auto-DCD enable
4159 */
4160 val = 0x4000;
4161
4162 if (info->params.parity != ASYNC_PARITY_NONE) {
4163 val |= BIT9;
4164 if (info->params.parity == ASYNC_PARITY_ODD)
4165 val |= BIT8;
4166 }
4167
4168 switch (info->params.data_bits)
4169 {
4170 case 6: val |= BIT4; break;
4171 case 7: val |= BIT5; break;
4172 case 8: val |= BIT5 + BIT4; break;
4173 }
4174
4175 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4176 val |= BIT0;
4177
4178 wr_reg16(info, RCR, val);
4179
4180 /* CCR (clock control)
4181 *
4182 * 07..05 011 = tx clock source is BRG/16
4183 * 04..02 010 = rx clock source is BRG
4184 * 01 0 = auxclk disabled
4185 * 00 1 = BRG enabled
4186 *
4187 * 0110 1001
4188 */
4189 wr_reg8(info, CCR, 0x69);
4190
4191 msc_set_vcr(info);
4192
4193 /* SCR (serial control)
4194 *
4195 * 15 1=tx req on FIFO half empty
4196 * 14 1=rx req on FIFO half full
4197 * 13 tx data IRQ enable
4198 * 12 tx idle IRQ enable
4199 * 11 rx break on IRQ enable
4200 * 10 rx data IRQ enable
4201 * 09 rx break off IRQ enable
4202 * 08 overrun IRQ enable
4203 * 07 DSR IRQ enable
4204 * 06 CTS IRQ enable
4205 * 05 DCD IRQ enable
4206 * 04 RI IRQ enable
4207 * 03 0=16x sampling, 1=8x sampling
4208 * 02 1=txd->rxd internal loopback enable
4209 * 01 reserved, must be zero
4210 * 00 1=master IRQ enable
4211 */
4212 val = BIT15 + BIT14 + BIT0;
4213 /* JCR[8] : 1 = x8 async mode feature available */
4214 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4215 ((info->base_clock < (info->params.data_rate * 16)) ||
4216 (info->base_clock % (info->params.data_rate * 16)))) {
4217 /* use 8x sampling */
4218 val |= BIT3;
4219 set_rate(info, info->params.data_rate * 8);
4220 } else {
4221 /* use 16x sampling */
4222 set_rate(info, info->params.data_rate * 16);
4223 }
4224 wr_reg16(info, SCR, val);
4225
4226 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4227
4228 if (info->params.loopback)
4229 enable_loopback(info);
4230}
4231
4232static void sync_mode(struct slgt_info *info)
4233{
4234 unsigned short val;
4235
4236 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4237 tx_stop(info);
4238 rx_stop(info);
4239
4240 /* TCR (tx control)
4241 *
4242 * 15..13 mode
4243 * 000=HDLC/SDLC
4244 * 001=raw bit synchronous
4245 * 010=asynchronous/isochronous
4246 * 011=monosync byte synchronous
4247 * 100=bisync byte synchronous
4248 * 101=xsync byte synchronous
4249 * 12..10 encoding
4250 * 09 CRC enable
4251 * 08 CRC32
4252 * 07 1=RTS driver control
4253 * 06 preamble enable
4254 * 05..04 preamble length
4255 * 03 share open/close flag
4256 * 02 reset
4257 * 01 enable
4258 * 00 auto-CTS enable
4259 */
4260 val = BIT2;
4261
4262 switch(info->params.mode) {
4263 case MGSL_MODE_XSYNC:
4264 val |= BIT15 + BIT13;
4265 break;
4266 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4267 case MGSL_MODE_BISYNC: val |= BIT15; break;
4268 case MGSL_MODE_RAW: val |= BIT13; break;
4269 }
4270 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4271 val |= BIT7;
4272
4273 switch(info->params.encoding)
4274 {
4275 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4276 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4277 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4278 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4279 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4280 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4281 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4282 }
4283
4284 switch (info->params.crc_type & HDLC_CRC_MASK)
4285 {
4286 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4287 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4288 }
4289
4290 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4291 val |= BIT6;
4292
4293 switch (info->params.preamble_length)
4294 {
4295 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4296 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4297 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4298 }
4299
4300 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4301 val |= BIT0;
4302
4303 wr_reg16(info, TCR, val);
4304
4305 /* TPR (transmit preamble) */
4306
4307 switch (info->params.preamble)
4308 {
4309 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4310 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4311 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4312 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4313 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4314 default: val = 0x7e; break;
4315 }
4316 wr_reg8(info, TPR, (unsigned char)val);
4317
4318 /* RCR (rx control)
4319 *
4320 * 15..13 mode
4321 * 000=HDLC/SDLC
4322 * 001=raw bit synchronous
4323 * 010=asynchronous/isochronous
4324 * 011=monosync byte synchronous
4325 * 100=bisync byte synchronous
4326 * 101=xsync byte synchronous
4327 * 12..10 encoding
4328 * 09 CRC enable
4329 * 08 CRC32
4330 * 07..03 reserved, must be 0
4331 * 02 reset
4332 * 01 enable
4333 * 00 auto-DCD enable
4334 */
4335 val = 0;
4336
4337 switch(info->params.mode) {
4338 case MGSL_MODE_XSYNC:
4339 val |= BIT15 + BIT13;
4340 break;
4341 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4342 case MGSL_MODE_BISYNC: val |= BIT15; break;
4343 case MGSL_MODE_RAW: val |= BIT13; break;
4344 }
4345
4346 switch(info->params.encoding)
4347 {
4348 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4349 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4350 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4351 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4352 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4353 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4354 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4355 }
4356
4357 switch (info->params.crc_type & HDLC_CRC_MASK)
4358 {
4359 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4360 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4361 }
4362
4363 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4364 val |= BIT0;
4365
4366 wr_reg16(info, RCR, val);
4367
4368 /* CCR (clock control)
4369 *
4370 * 07..05 tx clock source
4371 * 04..02 rx clock source
4372 * 01 auxclk enable
4373 * 00 BRG enable
4374 */
4375 val = 0;
4376
4377 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4378 {
4379 // when RxC source is DPLL, BRG generates 16X DPLL
4380 // reference clock, so take TxC from BRG/16 to get
4381 // transmit clock at actual data rate
4382 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4383 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4384 else
4385 val |= BIT6; /* 010, txclk = BRG */
4386 }
4387 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4388 val |= BIT7; /* 100, txclk = DPLL Input */
4389 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4390 val |= BIT5; /* 001, txclk = RXC Input */
4391
4392 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4393 val |= BIT3; /* 010, rxclk = BRG */
4394 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4395 val |= BIT4; /* 100, rxclk = DPLL */
4396 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4397 val |= BIT2; /* 001, rxclk = TXC Input */
4398
4399 if (info->params.clock_speed)
4400 val |= BIT1 + BIT0;
4401
4402 wr_reg8(info, CCR, (unsigned char)val);
4403
4404 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4405 {
4406 // program DPLL mode
4407 switch(info->params.encoding)
4408 {
4409 case HDLC_ENCODING_BIPHASE_MARK:
4410 case HDLC_ENCODING_BIPHASE_SPACE:
4411 val = BIT7; break;
4412 case HDLC_ENCODING_BIPHASE_LEVEL:
4413 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4414 val = BIT7 + BIT6; break;
4415 default: val = BIT6; // NRZ encodings
4416 }
4417 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4418
4419 // DPLL requires a 16X reference clock from BRG
4420 set_rate(info, info->params.clock_speed * 16);
4421 }
4422 else
4423 set_rate(info, info->params.clock_speed);
4424
4425 tx_set_idle(info);
4426
4427 msc_set_vcr(info);
4428
4429 /* SCR (serial control)
4430 *
4431 * 15 1=tx req on FIFO half empty
4432 * 14 1=rx req on FIFO half full
4433 * 13 tx data IRQ enable
4434 * 12 tx idle IRQ enable
4435 * 11 underrun IRQ enable
4436 * 10 rx data IRQ enable
4437 * 09 rx idle IRQ enable
4438 * 08 overrun IRQ enable
4439 * 07 DSR IRQ enable
4440 * 06 CTS IRQ enable
4441 * 05 DCD IRQ enable
4442 * 04 RI IRQ enable
4443 * 03 reserved, must be zero
4444 * 02 1=txd->rxd internal loopback enable
4445 * 01 reserved, must be zero
4446 * 00 1=master IRQ enable
4447 */
4448 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4449
4450 if (info->params.loopback)
4451 enable_loopback(info);
4452}
4453
4454/*
4455 * set transmit idle mode
4456 */
4457static void tx_set_idle(struct slgt_info *info)
4458{
4459 unsigned char val;
4460 unsigned short tcr;
4461
4462 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4463 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4464 */
4465 tcr = rd_reg16(info, TCR);
4466 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4467 /* disable preamble, set idle size to 16 bits */
4468 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4469 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4470 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4471 } else if (!(tcr & BIT6)) {
4472 /* preamble is disabled, set idle size to 8 bits */
4473 tcr &= ~(BIT5 + BIT4);
4474 }
4475 wr_reg16(info, TCR, tcr);
4476
4477 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4478 /* LSB of custom tx idle specified in tx idle register */
4479 val = (unsigned char)(info->idle_mode & 0xff);
4480 } else {
4481 /* standard 8 bit idle patterns */
4482 switch(info->idle_mode)
4483 {
4484 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4485 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4486 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4487 case HDLC_TXIDLE_ZEROS:
4488 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4489 default: val = 0xff;
4490 }
4491 }
4492
4493 wr_reg8(info, TIR, val);
4494}
4495
4496/*
4497 * get state of V24 status (input) signals
4498 */
4499static void get_signals(struct slgt_info *info)
4500{
4501 unsigned short status = rd_reg16(info, SSR);
4502
4503 /* clear all serial signals except RTS and DTR */
4504 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4505
4506 if (status & BIT3)
4507 info->signals |= SerialSignal_DSR;
4508 if (status & BIT2)
4509 info->signals |= SerialSignal_CTS;
4510 if (status & BIT1)
4511 info->signals |= SerialSignal_DCD;
4512 if (status & BIT0)
4513 info->signals |= SerialSignal_RI;
4514}
4515
4516/*
4517 * set V.24 Control Register based on current configuration
4518 */
4519static void msc_set_vcr(struct slgt_info *info)
4520{
4521 unsigned char val = 0;
4522
4523 /* VCR (V.24 control)
4524 *
4525 * 07..04 serial IF select
4526 * 03 DTR
4527 * 02 RTS
4528 * 01 LL
4529 * 00 RL
4530 */
4531
4532 switch(info->if_mode & MGSL_INTERFACE_MASK)
4533 {
4534 case MGSL_INTERFACE_RS232:
4535 val |= BIT5; /* 0010 */
4536 break;
4537 case MGSL_INTERFACE_V35:
4538 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4539 break;
4540 case MGSL_INTERFACE_RS422:
4541 val |= BIT6; /* 0100 */
4542 break;
4543 }
4544
4545 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4546 val |= BIT4;
4547 if (info->signals & SerialSignal_DTR)
4548 val |= BIT3;
4549 if (info->signals & SerialSignal_RTS)
4550 val |= BIT2;
4551 if (info->if_mode & MGSL_INTERFACE_LL)
4552 val |= BIT1;
4553 if (info->if_mode & MGSL_INTERFACE_RL)
4554 val |= BIT0;
4555 wr_reg8(info, VCR, val);
4556}
4557
4558/*
4559 * set state of V24 control (output) signals
4560 */
4561static void set_signals(struct slgt_info *info)
4562{
4563 unsigned char val = rd_reg8(info, VCR);
4564 if (info->signals & SerialSignal_DTR)
4565 val |= BIT3;
4566 else
4567 val &= ~BIT3;
4568 if (info->signals & SerialSignal_RTS)
4569 val |= BIT2;
4570 else
4571 val &= ~BIT2;
4572 wr_reg8(info, VCR, val);
4573}
4574
4575/*
4576 * free range of receive DMA buffers (i to last)
4577 */
4578static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4579{
4580 int done = 0;
4581
4582 while(!done) {
4583 /* reset current buffer for reuse */
4584 info->rbufs[i].status = 0;
4585 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4586 if (i == last)
4587 done = 1;
4588 if (++i == info->rbuf_count)
4589 i = 0;
4590 }
4591 info->rbuf_current = i;
4592}
4593
4594/*
4595 * mark all receive DMA buffers as free
4596 */
4597static void reset_rbufs(struct slgt_info *info)
4598{
4599 free_rbufs(info, 0, info->rbuf_count - 1);
4600 info->rbuf_fill_index = 0;
4601 info->rbuf_fill_count = 0;
4602}
4603
4604/*
4605 * pass receive HDLC frame to upper layer
4606 *
4607 * return true if frame available, otherwise false
4608 */
4609static bool rx_get_frame(struct slgt_info *info)
4610{
4611 unsigned int start, end;
4612 unsigned short status;
4613 unsigned int framesize = 0;
4614 unsigned long flags;
4615 struct tty_struct *tty = info->port.tty;
4616 unsigned char addr_field = 0xff;
4617 unsigned int crc_size = 0;
4618
4619 switch (info->params.crc_type & HDLC_CRC_MASK) {
4620 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4621 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4622 }
4623
4624check_again:
4625
4626 framesize = 0;
4627 addr_field = 0xff;
4628 start = end = info->rbuf_current;
4629
4630 for (;;) {
4631 if (!desc_complete(info->rbufs[end]))
4632 goto cleanup;
4633
4634 if (framesize == 0 && info->params.addr_filter != 0xff)
4635 addr_field = info->rbufs[end].buf[0];
4636
4637 framesize += desc_count(info->rbufs[end]);
4638
4639 if (desc_eof(info->rbufs[end]))
4640 break;
4641
4642 if (++end == info->rbuf_count)
4643 end = 0;
4644
4645 if (end == info->rbuf_current) {
4646 if (info->rx_enabled){
4647 spin_lock_irqsave(&info->lock,flags);
4648 rx_start(info);
4649 spin_unlock_irqrestore(&info->lock,flags);
4650 }
4651 goto cleanup;
4652 }
4653 }
4654
4655 /* status
4656 *
4657 * 15 buffer complete
4658 * 14..06 reserved
4659 * 05..04 residue
4660 * 02 eof (end of frame)
4661 * 01 CRC error
4662 * 00 abort
4663 */
4664 status = desc_status(info->rbufs[end]);
4665
4666 /* ignore CRC bit if not using CRC (bit is undefined) */
4667 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4668 status &= ~BIT1;
4669
4670 if (framesize == 0 ||
4671 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4672 free_rbufs(info, start, end);
4673 goto check_again;
4674 }
4675
4676 if (framesize < (2 + crc_size) || status & BIT0) {
4677 info->icount.rxshort++;
4678 framesize = 0;
4679 } else if (status & BIT1) {
4680 info->icount.rxcrc++;
4681 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4682 framesize = 0;
4683 }
4684
4685#if SYNCLINK_GENERIC_HDLC
4686 if (framesize == 0) {
4687 info->netdev->stats.rx_errors++;
4688 info->netdev->stats.rx_frame_errors++;
4689 }
4690#endif
4691
4692 DBGBH(("%s rx frame status=%04X size=%d\n",
4693 info->device_name, status, framesize));
4694 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4695
4696 if (framesize) {
4697 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4698 framesize -= crc_size;
4699 crc_size = 0;
4700 }
4701
4702 if (framesize > info->max_frame_size + crc_size)
4703 info->icount.rxlong++;
4704 else {
4705 /* copy dma buffer(s) to contiguous temp buffer */
4706 int copy_count = framesize;
4707 int i = start;
4708 unsigned char *p = info->tmp_rbuf;
4709 info->tmp_rbuf_count = framesize;
4710
4711 info->icount.rxok++;
4712
4713 while(copy_count) {
4714 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4715 memcpy(p, info->rbufs[i].buf, partial_count);
4716 p += partial_count;
4717 copy_count -= partial_count;
4718 if (++i == info->rbuf_count)
4719 i = 0;
4720 }
4721
4722 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4723 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4724 framesize++;
4725 }
4726
4727#if SYNCLINK_GENERIC_HDLC
4728 if (info->netcount)
4729 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4730 else
4731#endif
4732 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4733 }
4734 }
4735 free_rbufs(info, start, end);
4736 return true;
4737
4738cleanup:
4739 return false;
4740}
4741
4742/*
4743 * pass receive buffer (RAW synchronous mode) to tty layer
4744 * return true if buffer available, otherwise false
4745 */
4746static bool rx_get_buf(struct slgt_info *info)
4747{
4748 unsigned int i = info->rbuf_current;
4749 unsigned int count;
4750
4751 if (!desc_complete(info->rbufs[i]))
4752 return false;
4753 count = desc_count(info->rbufs[i]);
4754 switch(info->params.mode) {
4755 case MGSL_MODE_MONOSYNC:
4756 case MGSL_MODE_BISYNC:
4757 case MGSL_MODE_XSYNC:
4758 /* ignore residue in byte synchronous modes */
4759 if (desc_residue(info->rbufs[i]))
4760 count--;
4761 break;
4762 }
4763 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4764 DBGINFO(("rx_get_buf size=%d\n", count));
4765 if (count)
4766 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4767 info->flag_buf, count);
4768 free_rbufs(info, i, i);
4769 return true;
4770}
4771
4772static void reset_tbufs(struct slgt_info *info)
4773{
4774 unsigned int i;
4775 info->tbuf_current = 0;
4776 for (i=0 ; i < info->tbuf_count ; i++) {
4777 info->tbufs[i].status = 0;
4778 info->tbufs[i].count = 0;
4779 }
4780}
4781
4782/*
4783 * return number of free transmit DMA buffers
4784 */
4785static unsigned int free_tbuf_count(struct slgt_info *info)
4786{
4787 unsigned int count = 0;
4788 unsigned int i = info->tbuf_current;
4789
4790 do
4791 {
4792 if (desc_count(info->tbufs[i]))
4793 break; /* buffer in use */
4794 ++count;
4795 if (++i == info->tbuf_count)
4796 i=0;
4797 } while (i != info->tbuf_current);
4798
4799 /* if tx DMA active, last zero count buffer is in use */
4800 if (count && (rd_reg32(info, TDCSR) & BIT0))
4801 --count;
4802
4803 return count;
4804}
4805
4806/*
4807 * return number of bytes in unsent transmit DMA buffers
4808 * and the serial controller tx FIFO
4809 */
4810static unsigned int tbuf_bytes(struct slgt_info *info)
4811{
4812 unsigned int total_count = 0;
4813 unsigned int i = info->tbuf_current;
4814 unsigned int reg_value;
4815 unsigned int count;
4816 unsigned int active_buf_count = 0;
4817
4818 /*
4819 * Add descriptor counts for all tx DMA buffers.
4820 * If count is zero (cleared by DMA controller after read),
4821 * the buffer is complete or is actively being read from.
4822 *
4823 * Record buf_count of last buffer with zero count starting
4824 * from current ring position. buf_count is mirror
4825 * copy of count and is not cleared by serial controller.
4826 * If DMA controller is active, that buffer is actively
4827 * being read so add to total.
4828 */
4829 do {
4830 count = desc_count(info->tbufs[i]);
4831 if (count)
4832 total_count += count;
4833 else if (!total_count)
4834 active_buf_count = info->tbufs[i].buf_count;
4835 if (++i == info->tbuf_count)
4836 i = 0;
4837 } while (i != info->tbuf_current);
4838
4839 /* read tx DMA status register */
4840 reg_value = rd_reg32(info, TDCSR);
4841
4842 /* if tx DMA active, last zero count buffer is in use */
4843 if (reg_value & BIT0)
4844 total_count += active_buf_count;
4845
4846 /* add tx FIFO count = reg_value[15..8] */
4847 total_count += (reg_value >> 8) & 0xff;
4848
4849 /* if transmitter active add one byte for shift register */
4850 if (info->tx_active)
4851 total_count++;
4852
4853 return total_count;
4854}
4855
4856/*
4857 * load data into transmit DMA buffer ring and start transmitter if needed
4858 * return true if data accepted, otherwise false (buffers full)
4859 */
4860static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4861{
4862 unsigned short count;
4863 unsigned int i;
4864 struct slgt_desc *d;
4865
4866 /* check required buffer space */
4867 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4868 return false;
4869
4870 DBGDATA(info, buf, size, "tx");
4871
4872 /*
4873 * copy data to one or more DMA buffers in circular ring
4874 * tbuf_start = first buffer for this data
4875 * tbuf_current = next free buffer
4876 *
4877 * Copy all data before making data visible to DMA controller by
4878 * setting descriptor count of the first buffer.
4879 * This prevents an active DMA controller from reading the first DMA
4880 * buffers of a frame and stopping before the final buffers are filled.
4881 */
4882
4883 info->tbuf_start = i = info->tbuf_current;
4884
4885 while (size) {
4886 d = &info->tbufs[i];
4887
4888 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4889 memcpy(d->buf, buf, count);
4890
4891 size -= count;
4892 buf += count;
4893
4894 /*
4895 * set EOF bit for last buffer of HDLC frame or
4896 * for every buffer in raw mode
4897 */
4898 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4899 info->params.mode == MGSL_MODE_RAW)
4900 set_desc_eof(*d, 1);
4901 else
4902 set_desc_eof(*d, 0);
4903
4904 /* set descriptor count for all but first buffer */
4905 if (i != info->tbuf_start)
4906 set_desc_count(*d, count);
4907 d->buf_count = count;
4908
4909 if (++i == info->tbuf_count)
4910 i = 0;
4911 }
4912
4913 info->tbuf_current = i;
4914
4915 /* set first buffer count to make new data visible to DMA controller */
4916 d = &info->tbufs[info->tbuf_start];
4917 set_desc_count(*d, d->buf_count);
4918
4919 /* start transmitter if needed and update transmit timeout */
4920 if (!info->tx_active)
4921 tx_start(info);
4922 update_tx_timer(info);
4923
4924 return true;
4925}
4926
4927static int register_test(struct slgt_info *info)
4928{
4929 static unsigned short patterns[] =
4930 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4931 static unsigned int count = ARRAY_SIZE(patterns);
4932 unsigned int i;
4933 int rc = 0;
4934
4935 for (i=0 ; i < count ; i++) {
4936 wr_reg16(info, TIR, patterns[i]);
4937 wr_reg16(info, BDR, patterns[(i+1)%count]);
4938 if ((rd_reg16(info, TIR) != patterns[i]) ||
4939 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4940 rc = -ENODEV;
4941 break;
4942 }
4943 }
4944 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4945 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4946 return rc;
4947}
4948
4949static int irq_test(struct slgt_info *info)
4950{
4951 unsigned long timeout;
4952 unsigned long flags;
4953 struct tty_struct *oldtty = info->port.tty;
4954 u32 speed = info->params.data_rate;
4955
4956 info->params.data_rate = 921600;
4957 info->port.tty = NULL;
4958
4959 spin_lock_irqsave(&info->lock, flags);
4960 async_mode(info);
4961 slgt_irq_on(info, IRQ_TXIDLE);
4962
4963 /* enable transmitter */
4964 wr_reg16(info, TCR,
4965 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4966
4967 /* write one byte and wait for tx idle */
4968 wr_reg16(info, TDR, 0);
4969
4970 /* assume failure */
4971 info->init_error = DiagStatus_IrqFailure;
4972 info->irq_occurred = false;
4973
4974 spin_unlock_irqrestore(&info->lock, flags);
4975
4976 timeout=100;
4977 while(timeout-- && !info->irq_occurred)
4978 msleep_interruptible(10);
4979
4980 spin_lock_irqsave(&info->lock,flags);
4981 reset_port(info);
4982 spin_unlock_irqrestore(&info->lock,flags);
4983
4984 info->params.data_rate = speed;
4985 info->port.tty = oldtty;
4986
4987 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4988 return info->irq_occurred ? 0 : -ENODEV;
4989}
4990
4991static int loopback_test_rx(struct slgt_info *info)
4992{
4993 unsigned char *src, *dest;
4994 int count;
4995
4996 if (desc_complete(info->rbufs[0])) {
4997 count = desc_count(info->rbufs[0]);
4998 src = info->rbufs[0].buf;
4999 dest = info->tmp_rbuf;
5000
5001 for( ; count ; count-=2, src+=2) {
5002 /* src=data byte (src+1)=status byte */
5003 if (!(*(src+1) & (BIT9 + BIT8))) {
5004 *dest = *src;
5005 dest++;
5006 info->tmp_rbuf_count++;
5007 }
5008 }
5009 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5010 return 1;
5011 }
5012 return 0;
5013}
5014
5015static int loopback_test(struct slgt_info *info)
5016{
5017#define TESTFRAMESIZE 20
5018
5019 unsigned long timeout;
5020 u16 count = TESTFRAMESIZE;
5021 unsigned char buf[TESTFRAMESIZE];
5022 int rc = -ENODEV;
5023 unsigned long flags;
5024
5025 struct tty_struct *oldtty = info->port.tty;
5026 MGSL_PARAMS params;
5027
5028 memcpy(¶ms, &info->params, sizeof(params));
5029
5030 info->params.mode = MGSL_MODE_ASYNC;
5031 info->params.data_rate = 921600;
5032 info->params.loopback = 1;
5033 info->port.tty = NULL;
5034
5035 /* build and send transmit frame */
5036 for (count = 0; count < TESTFRAMESIZE; ++count)
5037 buf[count] = (unsigned char)count;
5038
5039 info->tmp_rbuf_count = 0;
5040 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5041
5042 /* program hardware for HDLC and enabled receiver */
5043 spin_lock_irqsave(&info->lock,flags);
5044 async_mode(info);
5045 rx_start(info);
5046 tx_load(info, buf, count);
5047 spin_unlock_irqrestore(&info->lock, flags);
5048
5049 /* wait for receive complete */
5050 for (timeout = 100; timeout; --timeout) {
5051 msleep_interruptible(10);
5052 if (loopback_test_rx(info)) {
5053 rc = 0;
5054 break;
5055 }
5056 }
5057
5058 /* verify received frame length and contents */
5059 if (!rc && (info->tmp_rbuf_count != count ||
5060 memcmp(buf, info->tmp_rbuf, count))) {
5061 rc = -ENODEV;
5062 }
5063
5064 spin_lock_irqsave(&info->lock,flags);
5065 reset_adapter(info);
5066 spin_unlock_irqrestore(&info->lock,flags);
5067
5068 memcpy(&info->params, ¶ms, sizeof(info->params));
5069 info->port.tty = oldtty;
5070
5071 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5072 return rc;
5073}
5074
5075static int adapter_test(struct slgt_info *info)
5076{
5077 DBGINFO(("testing %s\n", info->device_name));
5078 if (register_test(info) < 0) {
5079 printk("register test failure %s addr=%08X\n",
5080 info->device_name, info->phys_reg_addr);
5081 } else if (irq_test(info) < 0) {
5082 printk("IRQ test failure %s IRQ=%d\n",
5083 info->device_name, info->irq_level);
5084 } else if (loopback_test(info) < 0) {
5085 printk("loopback test failure %s\n", info->device_name);
5086 }
5087 return info->init_error;
5088}
5089
5090/*
5091 * transmit timeout handler
5092 */
5093static void tx_timeout(struct timer_list *t)
5094{
5095 struct slgt_info *info = from_timer(info, t, tx_timer);
5096 unsigned long flags;
5097
5098 DBGINFO(("%s tx_timeout\n", info->device_name));
5099 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5100 info->icount.txtimeout++;
5101 }
5102 spin_lock_irqsave(&info->lock,flags);
5103 tx_stop(info);
5104 spin_unlock_irqrestore(&info->lock,flags);
5105
5106#if SYNCLINK_GENERIC_HDLC
5107 if (info->netcount)
5108 hdlcdev_tx_done(info);
5109 else
5110#endif
5111 bh_transmit(info);
5112}
5113
5114/*
5115 * receive buffer polling timer
5116 */
5117static void rx_timeout(struct timer_list *t)
5118{
5119 struct slgt_info *info = from_timer(info, t, rx_timer);
5120 unsigned long flags;
5121
5122 DBGINFO(("%s rx_timeout\n", info->device_name));
5123 spin_lock_irqsave(&info->lock, flags);
5124 info->pending_bh |= BH_RECEIVE;
5125 spin_unlock_irqrestore(&info->lock, flags);
5126 bh_handler(&info->task);
5127}
5128
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MAX_DEVICES 32
95
96static const struct pci_device_id pci_table[] = {
97 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {0,}, /* terminate list */
102};
103MODULE_DEVICE_TABLE(pci, pci_table);
104
105static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
106static void remove_one(struct pci_dev *dev);
107static struct pci_driver pci_driver = {
108 .name = "synclink_gt",
109 .id_table = pci_table,
110 .probe = init_one,
111 .remove = remove_one,
112};
113
114static bool pci_registered;
115
116/*
117 * module configuration and status
118 */
119static struct slgt_info *slgt_device_list;
120static int slgt_device_count;
121
122static int ttymajor;
123static int debug_level;
124static int maxframe[MAX_DEVICES];
125
126module_param(ttymajor, int, 0);
127module_param(debug_level, int, 0);
128module_param_array(maxframe, int, NULL, 0);
129
130MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
131MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
132MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
133
134/*
135 * tty support and callbacks
136 */
137static struct tty_driver *serial_driver;
138
139static void wait_until_sent(struct tty_struct *tty, int timeout);
140static void flush_buffer(struct tty_struct *tty);
141static void tx_release(struct tty_struct *tty);
142
143/*
144 * generic HDLC support
145 */
146#define dev_to_port(D) (dev_to_hdlc(D)->priv)
147
148
149/*
150 * device specific structures, macros and functions
151 */
152
153#define SLGT_MAX_PORTS 4
154#define SLGT_REG_SIZE 256
155
156/*
157 * conditional wait facility
158 */
159struct cond_wait {
160 struct cond_wait *next;
161 wait_queue_head_t q;
162 wait_queue_entry_t wait;
163 unsigned int data;
164};
165static void flush_cond_wait(struct cond_wait **head);
166
167/*
168 * DMA buffer descriptor and access macros
169 */
170struct slgt_desc
171{
172 __le16 count;
173 __le16 status;
174 __le32 pbuf; /* physical address of data buffer */
175 __le32 next; /* physical address of next descriptor */
176
177 /* driver book keeping */
178 char *buf; /* virtual address of data buffer */
179 unsigned int pdesc; /* physical address of this descriptor */
180 dma_addr_t buf_dma_addr;
181 unsigned short buf_count;
182};
183
184#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
185#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
186#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
187#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
188#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
189#define desc_count(a) (le16_to_cpu((a).count))
190#define desc_status(a) (le16_to_cpu((a).status))
191#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
192#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
193#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
194#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
195#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
196
197struct _input_signal_events {
198 int ri_up;
199 int ri_down;
200 int dsr_up;
201 int dsr_down;
202 int dcd_up;
203 int dcd_down;
204 int cts_up;
205 int cts_down;
206};
207
208/*
209 * device instance data structure
210 */
211struct slgt_info {
212 void *if_ptr; /* General purpose pointer (used by SPPP) */
213 struct tty_port port;
214
215 struct slgt_info *next_device; /* device list link */
216
217 char device_name[25];
218 struct pci_dev *pdev;
219
220 int port_count; /* count of ports on adapter */
221 int adapter_num; /* adapter instance number */
222 int port_num; /* port instance number */
223
224 /* array of pointers to port contexts on this adapter */
225 struct slgt_info *port_array[SLGT_MAX_PORTS];
226
227 int line; /* tty line instance number */
228
229 struct mgsl_icount icount;
230
231 int timeout;
232 int x_char; /* xon/xoff character */
233 unsigned int read_status_mask;
234 unsigned int ignore_status_mask;
235
236 wait_queue_head_t status_event_wait_q;
237 wait_queue_head_t event_wait_q;
238 struct timer_list tx_timer;
239 struct timer_list rx_timer;
240
241 unsigned int gpio_present;
242 struct cond_wait *gpio_wait_q;
243
244 spinlock_t lock; /* spinlock for synchronizing with ISR */
245
246 struct work_struct task;
247 u32 pending_bh;
248 bool bh_requested;
249 bool bh_running;
250
251 int isr_overflow;
252 bool irq_requested; /* true if IRQ requested */
253 bool irq_occurred; /* for diagnostics use */
254
255 /* device configuration */
256
257 unsigned int bus_type;
258 unsigned int irq_level;
259 unsigned long irq_flags;
260
261 unsigned char __iomem * reg_addr; /* memory mapped registers address */
262 u32 phys_reg_addr;
263 bool reg_addr_requested;
264
265 MGSL_PARAMS params; /* communications parameters */
266 u32 idle_mode;
267 u32 max_frame_size; /* as set by device config */
268
269 unsigned int rbuf_fill_level;
270 unsigned int rx_pio;
271 unsigned int if_mode;
272 unsigned int base_clock;
273 unsigned int xsync;
274 unsigned int xctrl;
275
276 /* device status */
277
278 bool rx_enabled;
279 bool rx_restart;
280
281 bool tx_enabled;
282 bool tx_active;
283
284 unsigned char signals; /* serial signal states */
285 int init_error; /* initialization error */
286
287 unsigned char *tx_buf;
288 int tx_count;
289
290 char *flag_buf;
291 bool drop_rts_on_tx_done;
292 struct _input_signal_events input_signal_events;
293
294 int dcd_chkcount; /* check counts to prevent */
295 int cts_chkcount; /* too many IRQs if a signal */
296 int dsr_chkcount; /* is floating */
297 int ri_chkcount;
298
299 char *bufs; /* virtual address of DMA buffer lists */
300 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
301
302 unsigned int rbuf_count;
303 struct slgt_desc *rbufs;
304 unsigned int rbuf_current;
305 unsigned int rbuf_index;
306 unsigned int rbuf_fill_index;
307 unsigned short rbuf_fill_count;
308
309 unsigned int tbuf_count;
310 struct slgt_desc *tbufs;
311 unsigned int tbuf_current;
312 unsigned int tbuf_start;
313
314 unsigned char *tmp_rbuf;
315 unsigned int tmp_rbuf_count;
316
317 /* SPPP/Cisco HDLC device parts */
318
319 int netcount;
320 spinlock_t netlock;
321#if SYNCLINK_GENERIC_HDLC
322 struct net_device *netdev;
323#endif
324
325};
326
327static MGSL_PARAMS default_params = {
328 .mode = MGSL_MODE_HDLC,
329 .loopback = 0,
330 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
331 .encoding = HDLC_ENCODING_NRZI_SPACE,
332 .clock_speed = 0,
333 .addr_filter = 0xff,
334 .crc_type = HDLC_CRC_16_CCITT,
335 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
336 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
337 .data_rate = 9600,
338 .data_bits = 8,
339 .stop_bits = 1,
340 .parity = ASYNC_PARITY_NONE
341};
342
343
344#define BH_RECEIVE 1
345#define BH_TRANSMIT 2
346#define BH_STATUS 4
347#define IO_PIN_SHUTDOWN_LIMIT 100
348
349#define DMABUFSIZE 256
350#define DESC_LIST_SIZE 4096
351
352#define MASK_PARITY BIT1
353#define MASK_FRAMING BIT0
354#define MASK_BREAK BIT14
355#define MASK_OVERRUN BIT4
356
357#define GSR 0x00 /* global status */
358#define JCR 0x04 /* JTAG control */
359#define IODR 0x08 /* GPIO direction */
360#define IOER 0x0c /* GPIO interrupt enable */
361#define IOVR 0x10 /* GPIO value */
362#define IOSR 0x14 /* GPIO interrupt status */
363#define TDR 0x80 /* tx data */
364#define RDR 0x80 /* rx data */
365#define TCR 0x82 /* tx control */
366#define TIR 0x84 /* tx idle */
367#define TPR 0x85 /* tx preamble */
368#define RCR 0x86 /* rx control */
369#define VCR 0x88 /* V.24 control */
370#define CCR 0x89 /* clock control */
371#define BDR 0x8a /* baud divisor */
372#define SCR 0x8c /* serial control */
373#define SSR 0x8e /* serial status */
374#define RDCSR 0x90 /* rx DMA control/status */
375#define TDCSR 0x94 /* tx DMA control/status */
376#define RDDAR 0x98 /* rx DMA descriptor address */
377#define TDDAR 0x9c /* tx DMA descriptor address */
378#define XSR 0x40 /* extended sync pattern */
379#define XCR 0x44 /* extended control */
380
381#define RXIDLE BIT14
382#define RXBREAK BIT14
383#define IRQ_TXDATA BIT13
384#define IRQ_TXIDLE BIT12
385#define IRQ_TXUNDER BIT11 /* HDLC */
386#define IRQ_RXDATA BIT10
387#define IRQ_RXIDLE BIT9 /* HDLC */
388#define IRQ_RXBREAK BIT9 /* async */
389#define IRQ_RXOVER BIT8
390#define IRQ_DSR BIT7
391#define IRQ_CTS BIT6
392#define IRQ_DCD BIT5
393#define IRQ_RI BIT4
394#define IRQ_ALL 0x3ff0
395#define IRQ_MASTER BIT0
396
397#define slgt_irq_on(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
399#define slgt_irq_off(info, mask) \
400 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
401
402static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
403static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
404static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
405static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
406static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
407static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
408
409static void msc_set_vcr(struct slgt_info *info);
410
411static int startup(struct slgt_info *info);
412static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
413static void shutdown(struct slgt_info *info);
414static void program_hw(struct slgt_info *info);
415static void change_params(struct slgt_info *info);
416
417static int adapter_test(struct slgt_info *info);
418
419static void reset_port(struct slgt_info *info);
420static void async_mode(struct slgt_info *info);
421static void sync_mode(struct slgt_info *info);
422
423static void rx_stop(struct slgt_info *info);
424static void rx_start(struct slgt_info *info);
425static void reset_rbufs(struct slgt_info *info);
426static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
427static bool rx_get_frame(struct slgt_info *info);
428static bool rx_get_buf(struct slgt_info *info);
429
430static void tx_start(struct slgt_info *info);
431static void tx_stop(struct slgt_info *info);
432static void tx_set_idle(struct slgt_info *info);
433static unsigned int tbuf_bytes(struct slgt_info *info);
434static void reset_tbufs(struct slgt_info *info);
435static void tdma_reset(struct slgt_info *info);
436static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
437
438static void get_gtsignals(struct slgt_info *info);
439static void set_gtsignals(struct slgt_info *info);
440static void set_rate(struct slgt_info *info, u32 data_rate);
441
442static void bh_transmit(struct slgt_info *info);
443static void isr_txeom(struct slgt_info *info, unsigned short status);
444
445static void tx_timeout(struct timer_list *t);
446static void rx_timeout(struct timer_list *t);
447
448/*
449 * ioctl handlers
450 */
451static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
452static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
453static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
454static int get_txidle(struct slgt_info *info, int __user *idle_mode);
455static int set_txidle(struct slgt_info *info, int idle_mode);
456static int tx_enable(struct slgt_info *info, int enable);
457static int tx_abort(struct slgt_info *info);
458static int rx_enable(struct slgt_info *info, int enable);
459static int modem_input_wait(struct slgt_info *info,int arg);
460static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
461static int get_interface(struct slgt_info *info, int __user *if_mode);
462static int set_interface(struct slgt_info *info, int if_mode);
463static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
465static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
466static int get_xsync(struct slgt_info *info, int __user *if_mode);
467static int set_xsync(struct slgt_info *info, int if_mode);
468static int get_xctrl(struct slgt_info *info, int __user *if_mode);
469static int set_xctrl(struct slgt_info *info, int if_mode);
470
471/*
472 * driver functions
473 */
474static void release_resources(struct slgt_info *info);
475
476/*
477 * DEBUG OUTPUT CODE
478 */
479#ifndef DBGINFO
480#define DBGINFO(fmt)
481#endif
482#ifndef DBGERR
483#define DBGERR(fmt)
484#endif
485#ifndef DBGBH
486#define DBGBH(fmt)
487#endif
488#ifndef DBGISR
489#define DBGISR(fmt)
490#endif
491
492#ifdef DBGDATA
493static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
494{
495 int i;
496 int linecount;
497 printk("%s %s data:\n",info->device_name, label);
498 while(count) {
499 linecount = (count > 16) ? 16 : count;
500 for(i=0; i < linecount; i++)
501 printk("%02X ",(unsigned char)data[i]);
502 for(;i<17;i++)
503 printk(" ");
504 for(i=0;i<linecount;i++) {
505 if (data[i]>=040 && data[i]<=0176)
506 printk("%c",data[i]);
507 else
508 printk(".");
509 }
510 printk("\n");
511 data += linecount;
512 count -= linecount;
513 }
514}
515#else
516#define DBGDATA(info, buf, size, label)
517#endif
518
519#ifdef DBGTBUF
520static void dump_tbufs(struct slgt_info *info)
521{
522 int i;
523 printk("tbuf_current=%d\n", info->tbuf_current);
524 for (i=0 ; i < info->tbuf_count ; i++) {
525 printk("%d: count=%04X status=%04X\n",
526 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
527 }
528}
529#else
530#define DBGTBUF(info)
531#endif
532
533#ifdef DBGRBUF
534static void dump_rbufs(struct slgt_info *info)
535{
536 int i;
537 printk("rbuf_current=%d\n", info->rbuf_current);
538 for (i=0 ; i < info->rbuf_count ; i++) {
539 printk("%d: count=%04X status=%04X\n",
540 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
541 }
542}
543#else
544#define DBGRBUF(info)
545#endif
546
547static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
548{
549#ifdef SANITY_CHECK
550 if (!info) {
551 printk("null struct slgt_info for (%s) in %s\n", devname, name);
552 return 1;
553 }
554#else
555 if (!info)
556 return 1;
557#endif
558 return 0;
559}
560
561/*
562 * line discipline callback wrappers
563 *
564 * The wrappers maintain line discipline references
565 * while calling into the line discipline.
566 *
567 * ldisc_receive_buf - pass receive data to line discipline
568 */
569static void ldisc_receive_buf(struct tty_struct *tty,
570 const __u8 *data, char *flags, int count)
571{
572 struct tty_ldisc *ld;
573 if (!tty)
574 return;
575 ld = tty_ldisc_ref(tty);
576 if (ld) {
577 if (ld->ops->receive_buf)
578 ld->ops->receive_buf(tty, data, flags, count);
579 tty_ldisc_deref(ld);
580 }
581}
582
583/* tty callbacks */
584
585static int open(struct tty_struct *tty, struct file *filp)
586{
587 struct slgt_info *info;
588 int retval, line;
589 unsigned long flags;
590
591 line = tty->index;
592 if (line >= slgt_device_count) {
593 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
594 return -ENODEV;
595 }
596
597 info = slgt_device_list;
598 while(info && info->line != line)
599 info = info->next_device;
600 if (sanity_check(info, tty->name, "open"))
601 return -ENODEV;
602 if (info->init_error) {
603 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
604 return -ENODEV;
605 }
606
607 tty->driver_data = info;
608 info->port.tty = tty;
609
610 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
611
612 mutex_lock(&info->port.mutex);
613
614 spin_lock_irqsave(&info->netlock, flags);
615 if (info->netcount) {
616 retval = -EBUSY;
617 spin_unlock_irqrestore(&info->netlock, flags);
618 mutex_unlock(&info->port.mutex);
619 goto cleanup;
620 }
621 info->port.count++;
622 spin_unlock_irqrestore(&info->netlock, flags);
623
624 if (info->port.count == 1) {
625 /* 1st open on this device, init hardware */
626 retval = startup(info);
627 if (retval < 0) {
628 mutex_unlock(&info->port.mutex);
629 goto cleanup;
630 }
631 }
632 mutex_unlock(&info->port.mutex);
633 retval = block_til_ready(tty, filp, info);
634 if (retval) {
635 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
636 goto cleanup;
637 }
638
639 retval = 0;
640
641cleanup:
642 if (retval) {
643 if (tty->count == 1)
644 info->port.tty = NULL; /* tty layer will release tty struct */
645 if(info->port.count)
646 info->port.count--;
647 }
648
649 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
650 return retval;
651}
652
653static void close(struct tty_struct *tty, struct file *filp)
654{
655 struct slgt_info *info = tty->driver_data;
656
657 if (sanity_check(info, tty->name, "close"))
658 return;
659 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
660
661 if (tty_port_close_start(&info->port, tty, filp) == 0)
662 goto cleanup;
663
664 mutex_lock(&info->port.mutex);
665 if (tty_port_initialized(&info->port))
666 wait_until_sent(tty, info->timeout);
667 flush_buffer(tty);
668 tty_ldisc_flush(tty);
669
670 shutdown(info);
671 mutex_unlock(&info->port.mutex);
672
673 tty_port_close_end(&info->port, tty);
674 info->port.tty = NULL;
675cleanup:
676 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
677}
678
679static void hangup(struct tty_struct *tty)
680{
681 struct slgt_info *info = tty->driver_data;
682 unsigned long flags;
683
684 if (sanity_check(info, tty->name, "hangup"))
685 return;
686 DBGINFO(("%s hangup\n", info->device_name));
687
688 flush_buffer(tty);
689
690 mutex_lock(&info->port.mutex);
691 shutdown(info);
692
693 spin_lock_irqsave(&info->port.lock, flags);
694 info->port.count = 0;
695 info->port.tty = NULL;
696 spin_unlock_irqrestore(&info->port.lock, flags);
697 tty_port_set_active(&info->port, 0);
698 mutex_unlock(&info->port.mutex);
699
700 wake_up_interruptible(&info->port.open_wait);
701}
702
703static void set_termios(struct tty_struct *tty,
704 const struct ktermios *old_termios)
705{
706 struct slgt_info *info = tty->driver_data;
707 unsigned long flags;
708
709 DBGINFO(("%s set_termios\n", tty->driver->name));
710
711 change_params(info);
712
713 /* Handle transition to B0 status */
714 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
715 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
716 spin_lock_irqsave(&info->lock,flags);
717 set_gtsignals(info);
718 spin_unlock_irqrestore(&info->lock,flags);
719 }
720
721 /* Handle transition away from B0 status */
722 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
723 info->signals |= SerialSignal_DTR;
724 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
725 info->signals |= SerialSignal_RTS;
726 spin_lock_irqsave(&info->lock,flags);
727 set_gtsignals(info);
728 spin_unlock_irqrestore(&info->lock,flags);
729 }
730
731 /* Handle turning off CRTSCTS */
732 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
733 tty->hw_stopped = 0;
734 tx_release(tty);
735 }
736}
737
738static void update_tx_timer(struct slgt_info *info)
739{
740 /*
741 * use worst case speed of 1200bps to calculate transmit timeout
742 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
743 */
744 if (info->params.mode == MGSL_MODE_HDLC) {
745 int timeout = (tbuf_bytes(info) * 7) + 1000;
746 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
747 }
748}
749
750static int write(struct tty_struct *tty,
751 const unsigned char *buf, int count)
752{
753 int ret = 0;
754 struct slgt_info *info = tty->driver_data;
755 unsigned long flags;
756
757 if (sanity_check(info, tty->name, "write"))
758 return -EIO;
759
760 DBGINFO(("%s write count=%d\n", info->device_name, count));
761
762 if (!info->tx_buf || (count > info->max_frame_size))
763 return -EIO;
764
765 if (!count || tty->flow.stopped || tty->hw_stopped)
766 return 0;
767
768 spin_lock_irqsave(&info->lock, flags);
769
770 if (info->tx_count) {
771 /* send accumulated data from send_char() */
772 if (!tx_load(info, info->tx_buf, info->tx_count))
773 goto cleanup;
774 info->tx_count = 0;
775 }
776
777 if (tx_load(info, buf, count))
778 ret = count;
779
780cleanup:
781 spin_unlock_irqrestore(&info->lock, flags);
782 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
783 return ret;
784}
785
786static int put_char(struct tty_struct *tty, unsigned char ch)
787{
788 struct slgt_info *info = tty->driver_data;
789 unsigned long flags;
790 int ret = 0;
791
792 if (sanity_check(info, tty->name, "put_char"))
793 return 0;
794 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
795 if (!info->tx_buf)
796 return 0;
797 spin_lock_irqsave(&info->lock,flags);
798 if (info->tx_count < info->max_frame_size) {
799 info->tx_buf[info->tx_count++] = ch;
800 ret = 1;
801 }
802 spin_unlock_irqrestore(&info->lock,flags);
803 return ret;
804}
805
806static void send_xchar(struct tty_struct *tty, char ch)
807{
808 struct slgt_info *info = tty->driver_data;
809 unsigned long flags;
810
811 if (sanity_check(info, tty->name, "send_xchar"))
812 return;
813 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
814 info->x_char = ch;
815 if (ch) {
816 spin_lock_irqsave(&info->lock,flags);
817 if (!info->tx_enabled)
818 tx_start(info);
819 spin_unlock_irqrestore(&info->lock,flags);
820 }
821}
822
823static void wait_until_sent(struct tty_struct *tty, int timeout)
824{
825 struct slgt_info *info = tty->driver_data;
826 unsigned long orig_jiffies, char_time;
827
828 if (!info )
829 return;
830 if (sanity_check(info, tty->name, "wait_until_sent"))
831 return;
832 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
833 if (!tty_port_initialized(&info->port))
834 goto exit;
835
836 orig_jiffies = jiffies;
837
838 /* Set check interval to 1/5 of estimated time to
839 * send a character, and make it at least 1. The check
840 * interval should also be less than the timeout.
841 * Note: use tight timings here to satisfy the NIST-PCTS.
842 */
843
844 if (info->params.data_rate) {
845 char_time = info->timeout/(32 * 5);
846 if (!char_time)
847 char_time++;
848 } else
849 char_time = 1;
850
851 if (timeout)
852 char_time = min_t(unsigned long, char_time, timeout);
853
854 while (info->tx_active) {
855 msleep_interruptible(jiffies_to_msecs(char_time));
856 if (signal_pending(current))
857 break;
858 if (timeout && time_after(jiffies, orig_jiffies + timeout))
859 break;
860 }
861exit:
862 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
863}
864
865static unsigned int write_room(struct tty_struct *tty)
866{
867 struct slgt_info *info = tty->driver_data;
868 unsigned int ret;
869
870 if (sanity_check(info, tty->name, "write_room"))
871 return 0;
872 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
873 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
874 return ret;
875}
876
877static void flush_chars(struct tty_struct *tty)
878{
879 struct slgt_info *info = tty->driver_data;
880 unsigned long flags;
881
882 if (sanity_check(info, tty->name, "flush_chars"))
883 return;
884 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
885
886 if (info->tx_count <= 0 || tty->flow.stopped ||
887 tty->hw_stopped || !info->tx_buf)
888 return;
889
890 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
891
892 spin_lock_irqsave(&info->lock,flags);
893 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
894 info->tx_count = 0;
895 spin_unlock_irqrestore(&info->lock,flags);
896}
897
898static void flush_buffer(struct tty_struct *tty)
899{
900 struct slgt_info *info = tty->driver_data;
901 unsigned long flags;
902
903 if (sanity_check(info, tty->name, "flush_buffer"))
904 return;
905 DBGINFO(("%s flush_buffer\n", info->device_name));
906
907 spin_lock_irqsave(&info->lock, flags);
908 info->tx_count = 0;
909 spin_unlock_irqrestore(&info->lock, flags);
910
911 tty_wakeup(tty);
912}
913
914/*
915 * throttle (stop) transmitter
916 */
917static void tx_hold(struct tty_struct *tty)
918{
919 struct slgt_info *info = tty->driver_data;
920 unsigned long flags;
921
922 if (sanity_check(info, tty->name, "tx_hold"))
923 return;
924 DBGINFO(("%s tx_hold\n", info->device_name));
925 spin_lock_irqsave(&info->lock,flags);
926 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
927 tx_stop(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929}
930
931/*
932 * release (start) transmitter
933 */
934static void tx_release(struct tty_struct *tty)
935{
936 struct slgt_info *info = tty->driver_data;
937 unsigned long flags;
938
939 if (sanity_check(info, tty->name, "tx_release"))
940 return;
941 DBGINFO(("%s tx_release\n", info->device_name));
942 spin_lock_irqsave(&info->lock, flags);
943 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
944 info->tx_count = 0;
945 spin_unlock_irqrestore(&info->lock, flags);
946}
947
948/*
949 * Service an IOCTL request
950 *
951 * Arguments
952 *
953 * tty pointer to tty instance data
954 * cmd IOCTL command code
955 * arg command argument/context
956 *
957 * Return 0 if success, otherwise error code
958 */
959static int ioctl(struct tty_struct *tty,
960 unsigned int cmd, unsigned long arg)
961{
962 struct slgt_info *info = tty->driver_data;
963 void __user *argp = (void __user *)arg;
964 int ret;
965
966 if (sanity_check(info, tty->name, "ioctl"))
967 return -ENODEV;
968 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
969
970 if (cmd != TIOCMIWAIT) {
971 if (tty_io_error(tty))
972 return -EIO;
973 }
974
975 switch (cmd) {
976 case MGSL_IOCWAITEVENT:
977 return wait_mgsl_event(info, argp);
978 case TIOCMIWAIT:
979 return modem_input_wait(info,(int)arg);
980 case MGSL_IOCSGPIO:
981 return set_gpio(info, argp);
982 case MGSL_IOCGGPIO:
983 return get_gpio(info, argp);
984 case MGSL_IOCWAITGPIO:
985 return wait_gpio(info, argp);
986 case MGSL_IOCGXSYNC:
987 return get_xsync(info, argp);
988 case MGSL_IOCSXSYNC:
989 return set_xsync(info, (int)arg);
990 case MGSL_IOCGXCTRL:
991 return get_xctrl(info, argp);
992 case MGSL_IOCSXCTRL:
993 return set_xctrl(info, (int)arg);
994 }
995 mutex_lock(&info->port.mutex);
996 switch (cmd) {
997 case MGSL_IOCGPARAMS:
998 ret = get_params(info, argp);
999 break;
1000 case MGSL_IOCSPARAMS:
1001 ret = set_params(info, argp);
1002 break;
1003 case MGSL_IOCGTXIDLE:
1004 ret = get_txidle(info, argp);
1005 break;
1006 case MGSL_IOCSTXIDLE:
1007 ret = set_txidle(info, (int)arg);
1008 break;
1009 case MGSL_IOCTXENABLE:
1010 ret = tx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCRXENABLE:
1013 ret = rx_enable(info, (int)arg);
1014 break;
1015 case MGSL_IOCTXABORT:
1016 ret = tx_abort(info);
1017 break;
1018 case MGSL_IOCGSTATS:
1019 ret = get_stats(info, argp);
1020 break;
1021 case MGSL_IOCGIF:
1022 ret = get_interface(info, argp);
1023 break;
1024 case MGSL_IOCSIF:
1025 ret = set_interface(info,(int)arg);
1026 break;
1027 default:
1028 ret = -ENOIOCTLCMD;
1029 }
1030 mutex_unlock(&info->port.mutex);
1031 return ret;
1032}
1033
1034static int get_icount(struct tty_struct *tty,
1035 struct serial_icounter_struct *icount)
1036
1037{
1038 struct slgt_info *info = tty->driver_data;
1039 struct mgsl_icount cnow; /* kernel counter temps */
1040 unsigned long flags;
1041
1042 spin_lock_irqsave(&info->lock,flags);
1043 cnow = info->icount;
1044 spin_unlock_irqrestore(&info->lock,flags);
1045
1046 icount->cts = cnow.cts;
1047 icount->dsr = cnow.dsr;
1048 icount->rng = cnow.rng;
1049 icount->dcd = cnow.dcd;
1050 icount->rx = cnow.rx;
1051 icount->tx = cnow.tx;
1052 icount->frame = cnow.frame;
1053 icount->overrun = cnow.overrun;
1054 icount->parity = cnow.parity;
1055 icount->brk = cnow.brk;
1056 icount->buf_overrun = cnow.buf_overrun;
1057
1058 return 0;
1059}
1060
1061/*
1062 * support for 32 bit ioctl calls on 64 bit systems
1063 */
1064#ifdef CONFIG_COMPAT
1065static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1066{
1067 struct MGSL_PARAMS32 tmp_params;
1068
1069 DBGINFO(("%s get_params32\n", info->device_name));
1070 memset(&tmp_params, 0, sizeof(tmp_params));
1071 tmp_params.mode = (compat_ulong_t)info->params.mode;
1072 tmp_params.loopback = info->params.loopback;
1073 tmp_params.flags = info->params.flags;
1074 tmp_params.encoding = info->params.encoding;
1075 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1076 tmp_params.addr_filter = info->params.addr_filter;
1077 tmp_params.crc_type = info->params.crc_type;
1078 tmp_params.preamble_length = info->params.preamble_length;
1079 tmp_params.preamble = info->params.preamble;
1080 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1081 tmp_params.data_bits = info->params.data_bits;
1082 tmp_params.stop_bits = info->params.stop_bits;
1083 tmp_params.parity = info->params.parity;
1084 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1085 return -EFAULT;
1086 return 0;
1087}
1088
1089static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1090{
1091 struct MGSL_PARAMS32 tmp_params;
1092
1093 DBGINFO(("%s set_params32\n", info->device_name));
1094 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1095 return -EFAULT;
1096
1097 spin_lock(&info->lock);
1098 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1099 info->base_clock = tmp_params.clock_speed;
1100 } else {
1101 info->params.mode = tmp_params.mode;
1102 info->params.loopback = tmp_params.loopback;
1103 info->params.flags = tmp_params.flags;
1104 info->params.encoding = tmp_params.encoding;
1105 info->params.clock_speed = tmp_params.clock_speed;
1106 info->params.addr_filter = tmp_params.addr_filter;
1107 info->params.crc_type = tmp_params.crc_type;
1108 info->params.preamble_length = tmp_params.preamble_length;
1109 info->params.preamble = tmp_params.preamble;
1110 info->params.data_rate = tmp_params.data_rate;
1111 info->params.data_bits = tmp_params.data_bits;
1112 info->params.stop_bits = tmp_params.stop_bits;
1113 info->params.parity = tmp_params.parity;
1114 }
1115 spin_unlock(&info->lock);
1116
1117 program_hw(info);
1118
1119 return 0;
1120}
1121
1122static long slgt_compat_ioctl(struct tty_struct *tty,
1123 unsigned int cmd, unsigned long arg)
1124{
1125 struct slgt_info *info = tty->driver_data;
1126 int rc;
1127
1128 if (sanity_check(info, tty->name, "compat_ioctl"))
1129 return -ENODEV;
1130 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1131
1132 switch (cmd) {
1133 case MGSL_IOCSPARAMS32:
1134 rc = set_params32(info, compat_ptr(arg));
1135 break;
1136
1137 case MGSL_IOCGPARAMS32:
1138 rc = get_params32(info, compat_ptr(arg));
1139 break;
1140
1141 case MGSL_IOCGPARAMS:
1142 case MGSL_IOCSPARAMS:
1143 case MGSL_IOCGTXIDLE:
1144 case MGSL_IOCGSTATS:
1145 case MGSL_IOCWAITEVENT:
1146 case MGSL_IOCGIF:
1147 case MGSL_IOCSGPIO:
1148 case MGSL_IOCGGPIO:
1149 case MGSL_IOCWAITGPIO:
1150 case MGSL_IOCGXSYNC:
1151 case MGSL_IOCGXCTRL:
1152 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1153 break;
1154 default:
1155 rc = ioctl(tty, cmd, arg);
1156 }
1157 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1158 return rc;
1159}
1160#else
1161#define slgt_compat_ioctl NULL
1162#endif /* ifdef CONFIG_COMPAT */
1163
1164/*
1165 * proc fs support
1166 */
1167static inline void line_info(struct seq_file *m, struct slgt_info *info)
1168{
1169 char stat_buf[30];
1170 unsigned long flags;
1171
1172 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1173 info->device_name, info->phys_reg_addr,
1174 info->irq_level, info->max_frame_size);
1175
1176 /* output current serial signal states */
1177 spin_lock_irqsave(&info->lock,flags);
1178 get_gtsignals(info);
1179 spin_unlock_irqrestore(&info->lock,flags);
1180
1181 stat_buf[0] = 0;
1182 stat_buf[1] = 0;
1183 if (info->signals & SerialSignal_RTS)
1184 strcat(stat_buf, "|RTS");
1185 if (info->signals & SerialSignal_CTS)
1186 strcat(stat_buf, "|CTS");
1187 if (info->signals & SerialSignal_DTR)
1188 strcat(stat_buf, "|DTR");
1189 if (info->signals & SerialSignal_DSR)
1190 strcat(stat_buf, "|DSR");
1191 if (info->signals & SerialSignal_DCD)
1192 strcat(stat_buf, "|CD");
1193 if (info->signals & SerialSignal_RI)
1194 strcat(stat_buf, "|RI");
1195
1196 if (info->params.mode != MGSL_MODE_ASYNC) {
1197 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1198 info->icount.txok, info->icount.rxok);
1199 if (info->icount.txunder)
1200 seq_printf(m, " txunder:%d", info->icount.txunder);
1201 if (info->icount.txabort)
1202 seq_printf(m, " txabort:%d", info->icount.txabort);
1203 if (info->icount.rxshort)
1204 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1205 if (info->icount.rxlong)
1206 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1207 if (info->icount.rxover)
1208 seq_printf(m, " rxover:%d", info->icount.rxover);
1209 if (info->icount.rxcrc)
1210 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1211 } else {
1212 seq_printf(m, "\tASYNC tx:%d rx:%d",
1213 info->icount.tx, info->icount.rx);
1214 if (info->icount.frame)
1215 seq_printf(m, " fe:%d", info->icount.frame);
1216 if (info->icount.parity)
1217 seq_printf(m, " pe:%d", info->icount.parity);
1218 if (info->icount.brk)
1219 seq_printf(m, " brk:%d", info->icount.brk);
1220 if (info->icount.overrun)
1221 seq_printf(m, " oe:%d", info->icount.overrun);
1222 }
1223
1224 /* Append serial signal status to end */
1225 seq_printf(m, " %s\n", stat_buf+1);
1226
1227 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1228 info->tx_active,info->bh_requested,info->bh_running,
1229 info->pending_bh);
1230}
1231
1232/* Called to print information about devices
1233 */
1234static int synclink_gt_proc_show(struct seq_file *m, void *v)
1235{
1236 struct slgt_info *info;
1237
1238 seq_puts(m, "synclink_gt driver\n");
1239
1240 info = slgt_device_list;
1241 while( info ) {
1242 line_info(m, info);
1243 info = info->next_device;
1244 }
1245 return 0;
1246}
1247
1248/*
1249 * return count of bytes in transmit buffer
1250 */
1251static unsigned int chars_in_buffer(struct tty_struct *tty)
1252{
1253 struct slgt_info *info = tty->driver_data;
1254 unsigned int count;
1255 if (sanity_check(info, tty->name, "chars_in_buffer"))
1256 return 0;
1257 count = tbuf_bytes(info);
1258 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1259 return count;
1260}
1261
1262/*
1263 * signal remote device to throttle send data (our receive data)
1264 */
1265static void throttle(struct tty_struct * tty)
1266{
1267 struct slgt_info *info = tty->driver_data;
1268 unsigned long flags;
1269
1270 if (sanity_check(info, tty->name, "throttle"))
1271 return;
1272 DBGINFO(("%s throttle\n", info->device_name));
1273 if (I_IXOFF(tty))
1274 send_xchar(tty, STOP_CHAR(tty));
1275 if (C_CRTSCTS(tty)) {
1276 spin_lock_irqsave(&info->lock,flags);
1277 info->signals &= ~SerialSignal_RTS;
1278 set_gtsignals(info);
1279 spin_unlock_irqrestore(&info->lock,flags);
1280 }
1281}
1282
1283/*
1284 * signal remote device to stop throttling send data (our receive data)
1285 */
1286static void unthrottle(struct tty_struct * tty)
1287{
1288 struct slgt_info *info = tty->driver_data;
1289 unsigned long flags;
1290
1291 if (sanity_check(info, tty->name, "unthrottle"))
1292 return;
1293 DBGINFO(("%s unthrottle\n", info->device_name));
1294 if (I_IXOFF(tty)) {
1295 if (info->x_char)
1296 info->x_char = 0;
1297 else
1298 send_xchar(tty, START_CHAR(tty));
1299 }
1300 if (C_CRTSCTS(tty)) {
1301 spin_lock_irqsave(&info->lock,flags);
1302 info->signals |= SerialSignal_RTS;
1303 set_gtsignals(info);
1304 spin_unlock_irqrestore(&info->lock,flags);
1305 }
1306}
1307
1308/*
1309 * set or clear transmit break condition
1310 * break_state -1=set break condition, 0=clear
1311 */
1312static int set_break(struct tty_struct *tty, int break_state)
1313{
1314 struct slgt_info *info = tty->driver_data;
1315 unsigned short value;
1316 unsigned long flags;
1317
1318 if (sanity_check(info, tty->name, "set_break"))
1319 return -EINVAL;
1320 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1321
1322 spin_lock_irqsave(&info->lock,flags);
1323 value = rd_reg16(info, TCR);
1324 if (break_state == -1)
1325 value |= BIT6;
1326 else
1327 value &= ~BIT6;
1328 wr_reg16(info, TCR, value);
1329 spin_unlock_irqrestore(&info->lock,flags);
1330 return 0;
1331}
1332
1333#if SYNCLINK_GENERIC_HDLC
1334
1335/**
1336 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1337 * @dev: pointer to network device structure
1338 * @encoding: serial encoding setting
1339 * @parity: FCS setting
1340 *
1341 * Set encoding and frame check sequence (FCS) options.
1342 *
1343 * Return: 0 if success, otherwise error code
1344 */
1345static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1346 unsigned short parity)
1347{
1348 struct slgt_info *info = dev_to_port(dev);
1349 unsigned char new_encoding;
1350 unsigned short new_crctype;
1351
1352 /* return error if TTY interface open */
1353 if (info->port.count)
1354 return -EBUSY;
1355
1356 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1357
1358 switch (encoding)
1359 {
1360 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1361 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1362 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1363 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1364 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1365 default: return -EINVAL;
1366 }
1367
1368 switch (parity)
1369 {
1370 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1371 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1372 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1373 default: return -EINVAL;
1374 }
1375
1376 info->params.encoding = new_encoding;
1377 info->params.crc_type = new_crctype;
1378
1379 /* if network interface up, reprogram hardware */
1380 if (info->netcount)
1381 program_hw(info);
1382
1383 return 0;
1384}
1385
1386/**
1387 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1388 * @skb: socket buffer containing HDLC frame
1389 * @dev: pointer to network device structure
1390 */
1391static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1392 struct net_device *dev)
1393{
1394 struct slgt_info *info = dev_to_port(dev);
1395 unsigned long flags;
1396
1397 DBGINFO(("%s hdlc_xmit\n", dev->name));
1398
1399 if (!skb->len)
1400 return NETDEV_TX_OK;
1401
1402 /* stop sending until this frame completes */
1403 netif_stop_queue(dev);
1404
1405 /* update network statistics */
1406 dev->stats.tx_packets++;
1407 dev->stats.tx_bytes += skb->len;
1408
1409 /* save start time for transmit timeout detection */
1410 netif_trans_update(dev);
1411
1412 spin_lock_irqsave(&info->lock, flags);
1413 tx_load(info, skb->data, skb->len);
1414 spin_unlock_irqrestore(&info->lock, flags);
1415
1416 /* done with socket buffer, so free it */
1417 dev_kfree_skb(skb);
1418
1419 return NETDEV_TX_OK;
1420}
1421
1422/**
1423 * hdlcdev_open - called by network layer when interface enabled
1424 * @dev: pointer to network device structure
1425 *
1426 * Claim resources and initialize hardware.
1427 *
1428 * Return: 0 if success, otherwise error code
1429 */
1430static int hdlcdev_open(struct net_device *dev)
1431{
1432 struct slgt_info *info = dev_to_port(dev);
1433 int rc;
1434 unsigned long flags;
1435
1436 DBGINFO(("%s hdlcdev_open\n", dev->name));
1437
1438 /* arbitrate between network and tty opens */
1439 spin_lock_irqsave(&info->netlock, flags);
1440 if (info->port.count != 0 || info->netcount != 0) {
1441 DBGINFO(("%s hdlc_open busy\n", dev->name));
1442 spin_unlock_irqrestore(&info->netlock, flags);
1443 return -EBUSY;
1444 }
1445 info->netcount=1;
1446 spin_unlock_irqrestore(&info->netlock, flags);
1447
1448 /* claim resources and init adapter */
1449 if ((rc = startup(info)) != 0) {
1450 spin_lock_irqsave(&info->netlock, flags);
1451 info->netcount=0;
1452 spin_unlock_irqrestore(&info->netlock, flags);
1453 return rc;
1454 }
1455
1456 /* generic HDLC layer open processing */
1457 rc = hdlc_open(dev);
1458 if (rc) {
1459 shutdown(info);
1460 spin_lock_irqsave(&info->netlock, flags);
1461 info->netcount = 0;
1462 spin_unlock_irqrestore(&info->netlock, flags);
1463 return rc;
1464 }
1465
1466 /* assert RTS and DTR, apply hardware settings */
1467 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1468 program_hw(info);
1469
1470 /* enable network layer transmit */
1471 netif_trans_update(dev);
1472 netif_start_queue(dev);
1473
1474 /* inform generic HDLC layer of current DCD status */
1475 spin_lock_irqsave(&info->lock, flags);
1476 get_gtsignals(info);
1477 spin_unlock_irqrestore(&info->lock, flags);
1478 if (info->signals & SerialSignal_DCD)
1479 netif_carrier_on(dev);
1480 else
1481 netif_carrier_off(dev);
1482 return 0;
1483}
1484
1485/**
1486 * hdlcdev_close - called by network layer when interface is disabled
1487 * @dev: pointer to network device structure
1488 *
1489 * Shutdown hardware and release resources.
1490 *
1491 * Return: 0 if success, otherwise error code
1492 */
1493static int hdlcdev_close(struct net_device *dev)
1494{
1495 struct slgt_info *info = dev_to_port(dev);
1496 unsigned long flags;
1497
1498 DBGINFO(("%s hdlcdev_close\n", dev->name));
1499
1500 netif_stop_queue(dev);
1501
1502 /* shutdown adapter and release resources */
1503 shutdown(info);
1504
1505 hdlc_close(dev);
1506
1507 spin_lock_irqsave(&info->netlock, flags);
1508 info->netcount=0;
1509 spin_unlock_irqrestore(&info->netlock, flags);
1510
1511 return 0;
1512}
1513
1514/**
1515 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1516 * @dev: pointer to network device structure
1517 * @ifr: pointer to network interface request structure
1518 * @cmd: IOCTL command code
1519 *
1520 * Return: 0 if success, otherwise error code
1521 */
1522static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1523{
1524 const size_t size = sizeof(sync_serial_settings);
1525 sync_serial_settings new_line;
1526 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1527 struct slgt_info *info = dev_to_port(dev);
1528 unsigned int flags;
1529
1530 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1531
1532 /* return error if TTY interface open */
1533 if (info->port.count)
1534 return -EBUSY;
1535
1536 memset(&new_line, 0, sizeof(new_line));
1537
1538 switch (ifs->type) {
1539 case IF_GET_IFACE: /* return current sync_serial_settings */
1540
1541 ifs->type = IF_IFACE_SYNC_SERIAL;
1542 if (ifs->size < size) {
1543 ifs->size = size; /* data size wanted */
1544 return -ENOBUFS;
1545 }
1546
1547 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1548 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1549 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1550 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1551
1552 switch (flags){
1553 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1554 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1555 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1556 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1557 default: new_line.clock_type = CLOCK_DEFAULT;
1558 }
1559
1560 new_line.clock_rate = info->params.clock_speed;
1561 new_line.loopback = info->params.loopback ? 1:0;
1562
1563 if (copy_to_user(line, &new_line, size))
1564 return -EFAULT;
1565 return 0;
1566
1567 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1568
1569 if(!capable(CAP_NET_ADMIN))
1570 return -EPERM;
1571 if (copy_from_user(&new_line, line, size))
1572 return -EFAULT;
1573
1574 switch (new_line.clock_type)
1575 {
1576 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1577 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1578 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1579 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1580 case CLOCK_DEFAULT: flags = info->params.flags &
1581 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1582 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1583 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1584 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1585 default: return -EINVAL;
1586 }
1587
1588 if (new_line.loopback != 0 && new_line.loopback != 1)
1589 return -EINVAL;
1590
1591 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1592 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1593 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1594 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1595 info->params.flags |= flags;
1596
1597 info->params.loopback = new_line.loopback;
1598
1599 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1600 info->params.clock_speed = new_line.clock_rate;
1601 else
1602 info->params.clock_speed = 0;
1603
1604 /* if network interface up, reprogram hardware */
1605 if (info->netcount)
1606 program_hw(info);
1607 return 0;
1608
1609 default:
1610 return hdlc_ioctl(dev, ifs);
1611 }
1612}
1613
1614/**
1615 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1616 * @dev: pointer to network device structure
1617 * @txqueue: unused
1618 */
1619static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1620{
1621 struct slgt_info *info = dev_to_port(dev);
1622 unsigned long flags;
1623
1624 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1625
1626 dev->stats.tx_errors++;
1627 dev->stats.tx_aborted_errors++;
1628
1629 spin_lock_irqsave(&info->lock,flags);
1630 tx_stop(info);
1631 spin_unlock_irqrestore(&info->lock,flags);
1632
1633 netif_wake_queue(dev);
1634}
1635
1636/**
1637 * hdlcdev_tx_done - called by device driver when transmit completes
1638 * @info: pointer to device instance information
1639 *
1640 * Reenable network layer transmit if stopped.
1641 */
1642static void hdlcdev_tx_done(struct slgt_info *info)
1643{
1644 if (netif_queue_stopped(info->netdev))
1645 netif_wake_queue(info->netdev);
1646}
1647
1648/**
1649 * hdlcdev_rx - called by device driver when frame received
1650 * @info: pointer to device instance information
1651 * @buf: pointer to buffer contianing frame data
1652 * @size: count of data bytes in buf
1653 *
1654 * Pass frame to network layer.
1655 */
1656static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1657{
1658 struct sk_buff *skb = dev_alloc_skb(size);
1659 struct net_device *dev = info->netdev;
1660
1661 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1662
1663 if (skb == NULL) {
1664 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1665 dev->stats.rx_dropped++;
1666 return;
1667 }
1668
1669 skb_put_data(skb, buf, size);
1670
1671 skb->protocol = hdlc_type_trans(skb, dev);
1672
1673 dev->stats.rx_packets++;
1674 dev->stats.rx_bytes += size;
1675
1676 netif_rx(skb);
1677}
1678
1679static const struct net_device_ops hdlcdev_ops = {
1680 .ndo_open = hdlcdev_open,
1681 .ndo_stop = hdlcdev_close,
1682 .ndo_start_xmit = hdlc_start_xmit,
1683 .ndo_siocwandev = hdlcdev_ioctl,
1684 .ndo_tx_timeout = hdlcdev_tx_timeout,
1685};
1686
1687/**
1688 * hdlcdev_init - called by device driver when adding device instance
1689 * @info: pointer to device instance information
1690 *
1691 * Do generic HDLC initialization.
1692 *
1693 * Return: 0 if success, otherwise error code
1694 */
1695static int hdlcdev_init(struct slgt_info *info)
1696{
1697 int rc;
1698 struct net_device *dev;
1699 hdlc_device *hdlc;
1700
1701 /* allocate and initialize network and HDLC layer objects */
1702
1703 dev = alloc_hdlcdev(info);
1704 if (!dev) {
1705 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1706 return -ENOMEM;
1707 }
1708
1709 /* for network layer reporting purposes only */
1710 dev->mem_start = info->phys_reg_addr;
1711 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1712 dev->irq = info->irq_level;
1713
1714 /* network layer callbacks and settings */
1715 dev->netdev_ops = &hdlcdev_ops;
1716 dev->watchdog_timeo = 10 * HZ;
1717 dev->tx_queue_len = 50;
1718
1719 /* generic HDLC layer callbacks and settings */
1720 hdlc = dev_to_hdlc(dev);
1721 hdlc->attach = hdlcdev_attach;
1722 hdlc->xmit = hdlcdev_xmit;
1723
1724 /* register objects with HDLC layer */
1725 rc = register_hdlc_device(dev);
1726 if (rc) {
1727 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1728 free_netdev(dev);
1729 return rc;
1730 }
1731
1732 info->netdev = dev;
1733 return 0;
1734}
1735
1736/**
1737 * hdlcdev_exit - called by device driver when removing device instance
1738 * @info: pointer to device instance information
1739 *
1740 * Do generic HDLC cleanup.
1741 */
1742static void hdlcdev_exit(struct slgt_info *info)
1743{
1744 if (!info->netdev)
1745 return;
1746 unregister_hdlc_device(info->netdev);
1747 free_netdev(info->netdev);
1748 info->netdev = NULL;
1749}
1750
1751#endif /* ifdef CONFIG_HDLC */
1752
1753/*
1754 * get async data from rx DMA buffers
1755 */
1756static void rx_async(struct slgt_info *info)
1757{
1758 struct mgsl_icount *icount = &info->icount;
1759 unsigned int start, end;
1760 unsigned char *p;
1761 unsigned char status;
1762 struct slgt_desc *bufs = info->rbufs;
1763 int i, count;
1764 int chars = 0;
1765 int stat;
1766 unsigned char ch;
1767
1768 start = end = info->rbuf_current;
1769
1770 while(desc_complete(bufs[end])) {
1771 count = desc_count(bufs[end]) - info->rbuf_index;
1772 p = bufs[end].buf + info->rbuf_index;
1773
1774 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1775 DBGDATA(info, p, count, "rx");
1776
1777 for(i=0 ; i < count; i+=2, p+=2) {
1778 ch = *p;
1779 icount->rx++;
1780
1781 stat = 0;
1782
1783 status = *(p + 1) & (BIT1 + BIT0);
1784 if (status) {
1785 if (status & BIT1)
1786 icount->parity++;
1787 else if (status & BIT0)
1788 icount->frame++;
1789 /* discard char if tty control flags say so */
1790 if (status & info->ignore_status_mask)
1791 continue;
1792 if (status & BIT1)
1793 stat = TTY_PARITY;
1794 else if (status & BIT0)
1795 stat = TTY_FRAME;
1796 }
1797 tty_insert_flip_char(&info->port, ch, stat);
1798 chars++;
1799 }
1800
1801 if (i < count) {
1802 /* receive buffer not completed */
1803 info->rbuf_index += i;
1804 mod_timer(&info->rx_timer, jiffies + 1);
1805 break;
1806 }
1807
1808 info->rbuf_index = 0;
1809 free_rbufs(info, end, end);
1810
1811 if (++end == info->rbuf_count)
1812 end = 0;
1813
1814 /* if entire list searched then no frame available */
1815 if (end == start)
1816 break;
1817 }
1818
1819 if (chars)
1820 tty_flip_buffer_push(&info->port);
1821}
1822
1823/*
1824 * return next bottom half action to perform
1825 */
1826static int bh_action(struct slgt_info *info)
1827{
1828 unsigned long flags;
1829 int rc;
1830
1831 spin_lock_irqsave(&info->lock,flags);
1832
1833 if (info->pending_bh & BH_RECEIVE) {
1834 info->pending_bh &= ~BH_RECEIVE;
1835 rc = BH_RECEIVE;
1836 } else if (info->pending_bh & BH_TRANSMIT) {
1837 info->pending_bh &= ~BH_TRANSMIT;
1838 rc = BH_TRANSMIT;
1839 } else if (info->pending_bh & BH_STATUS) {
1840 info->pending_bh &= ~BH_STATUS;
1841 rc = BH_STATUS;
1842 } else {
1843 /* Mark BH routine as complete */
1844 info->bh_running = false;
1845 info->bh_requested = false;
1846 rc = 0;
1847 }
1848
1849 spin_unlock_irqrestore(&info->lock,flags);
1850
1851 return rc;
1852}
1853
1854/*
1855 * perform bottom half processing
1856 */
1857static void bh_handler(struct work_struct *work)
1858{
1859 struct slgt_info *info = container_of(work, struct slgt_info, task);
1860 int action;
1861
1862 info->bh_running = true;
1863
1864 while((action = bh_action(info))) {
1865 switch (action) {
1866 case BH_RECEIVE:
1867 DBGBH(("%s bh receive\n", info->device_name));
1868 switch(info->params.mode) {
1869 case MGSL_MODE_ASYNC:
1870 rx_async(info);
1871 break;
1872 case MGSL_MODE_HDLC:
1873 while(rx_get_frame(info));
1874 break;
1875 case MGSL_MODE_RAW:
1876 case MGSL_MODE_MONOSYNC:
1877 case MGSL_MODE_BISYNC:
1878 case MGSL_MODE_XSYNC:
1879 while(rx_get_buf(info));
1880 break;
1881 }
1882 /* restart receiver if rx DMA buffers exhausted */
1883 if (info->rx_restart)
1884 rx_start(info);
1885 break;
1886 case BH_TRANSMIT:
1887 bh_transmit(info);
1888 break;
1889 case BH_STATUS:
1890 DBGBH(("%s bh status\n", info->device_name));
1891 info->ri_chkcount = 0;
1892 info->dsr_chkcount = 0;
1893 info->dcd_chkcount = 0;
1894 info->cts_chkcount = 0;
1895 break;
1896 default:
1897 DBGBH(("%s unknown action\n", info->device_name));
1898 break;
1899 }
1900 }
1901 DBGBH(("%s bh_handler exit\n", info->device_name));
1902}
1903
1904static void bh_transmit(struct slgt_info *info)
1905{
1906 struct tty_struct *tty = info->port.tty;
1907
1908 DBGBH(("%s bh_transmit\n", info->device_name));
1909 if (tty)
1910 tty_wakeup(tty);
1911}
1912
1913static void dsr_change(struct slgt_info *info, unsigned short status)
1914{
1915 if (status & BIT3) {
1916 info->signals |= SerialSignal_DSR;
1917 info->input_signal_events.dsr_up++;
1918 } else {
1919 info->signals &= ~SerialSignal_DSR;
1920 info->input_signal_events.dsr_down++;
1921 }
1922 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1923 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1924 slgt_irq_off(info, IRQ_DSR);
1925 return;
1926 }
1927 info->icount.dsr++;
1928 wake_up_interruptible(&info->status_event_wait_q);
1929 wake_up_interruptible(&info->event_wait_q);
1930 info->pending_bh |= BH_STATUS;
1931}
1932
1933static void cts_change(struct slgt_info *info, unsigned short status)
1934{
1935 if (status & BIT2) {
1936 info->signals |= SerialSignal_CTS;
1937 info->input_signal_events.cts_up++;
1938 } else {
1939 info->signals &= ~SerialSignal_CTS;
1940 info->input_signal_events.cts_down++;
1941 }
1942 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1943 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1944 slgt_irq_off(info, IRQ_CTS);
1945 return;
1946 }
1947 info->icount.cts++;
1948 wake_up_interruptible(&info->status_event_wait_q);
1949 wake_up_interruptible(&info->event_wait_q);
1950 info->pending_bh |= BH_STATUS;
1951
1952 if (tty_port_cts_enabled(&info->port)) {
1953 if (info->port.tty) {
1954 if (info->port.tty->hw_stopped) {
1955 if (info->signals & SerialSignal_CTS) {
1956 info->port.tty->hw_stopped = 0;
1957 info->pending_bh |= BH_TRANSMIT;
1958 return;
1959 }
1960 } else {
1961 if (!(info->signals & SerialSignal_CTS))
1962 info->port.tty->hw_stopped = 1;
1963 }
1964 }
1965 }
1966}
1967
1968static void dcd_change(struct slgt_info *info, unsigned short status)
1969{
1970 if (status & BIT1) {
1971 info->signals |= SerialSignal_DCD;
1972 info->input_signal_events.dcd_up++;
1973 } else {
1974 info->signals &= ~SerialSignal_DCD;
1975 info->input_signal_events.dcd_down++;
1976 }
1977 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1978 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1979 slgt_irq_off(info, IRQ_DCD);
1980 return;
1981 }
1982 info->icount.dcd++;
1983#if SYNCLINK_GENERIC_HDLC
1984 if (info->netcount) {
1985 if (info->signals & SerialSignal_DCD)
1986 netif_carrier_on(info->netdev);
1987 else
1988 netif_carrier_off(info->netdev);
1989 }
1990#endif
1991 wake_up_interruptible(&info->status_event_wait_q);
1992 wake_up_interruptible(&info->event_wait_q);
1993 info->pending_bh |= BH_STATUS;
1994
1995 if (tty_port_check_carrier(&info->port)) {
1996 if (info->signals & SerialSignal_DCD)
1997 wake_up_interruptible(&info->port.open_wait);
1998 else {
1999 if (info->port.tty)
2000 tty_hangup(info->port.tty);
2001 }
2002 }
2003}
2004
2005static void ri_change(struct slgt_info *info, unsigned short status)
2006{
2007 if (status & BIT0) {
2008 info->signals |= SerialSignal_RI;
2009 info->input_signal_events.ri_up++;
2010 } else {
2011 info->signals &= ~SerialSignal_RI;
2012 info->input_signal_events.ri_down++;
2013 }
2014 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2015 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2016 slgt_irq_off(info, IRQ_RI);
2017 return;
2018 }
2019 info->icount.rng++;
2020 wake_up_interruptible(&info->status_event_wait_q);
2021 wake_up_interruptible(&info->event_wait_q);
2022 info->pending_bh |= BH_STATUS;
2023}
2024
2025static void isr_rxdata(struct slgt_info *info)
2026{
2027 unsigned int count = info->rbuf_fill_count;
2028 unsigned int i = info->rbuf_fill_index;
2029 unsigned short reg;
2030
2031 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2032 reg = rd_reg16(info, RDR);
2033 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2034 if (desc_complete(info->rbufs[i])) {
2035 /* all buffers full */
2036 rx_stop(info);
2037 info->rx_restart = true;
2038 continue;
2039 }
2040 info->rbufs[i].buf[count++] = (unsigned char)reg;
2041 /* async mode saves status byte to buffer for each data byte */
2042 if (info->params.mode == MGSL_MODE_ASYNC)
2043 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2044 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2045 /* buffer full or end of frame */
2046 set_desc_count(info->rbufs[i], count);
2047 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2048 info->rbuf_fill_count = count = 0;
2049 if (++i == info->rbuf_count)
2050 i = 0;
2051 info->pending_bh |= BH_RECEIVE;
2052 }
2053 }
2054
2055 info->rbuf_fill_index = i;
2056 info->rbuf_fill_count = count;
2057}
2058
2059static void isr_serial(struct slgt_info *info)
2060{
2061 unsigned short status = rd_reg16(info, SSR);
2062
2063 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2064
2065 wr_reg16(info, SSR, status); /* clear pending */
2066
2067 info->irq_occurred = true;
2068
2069 if (info->params.mode == MGSL_MODE_ASYNC) {
2070 if (status & IRQ_TXIDLE) {
2071 if (info->tx_active)
2072 isr_txeom(info, status);
2073 }
2074 if (info->rx_pio && (status & IRQ_RXDATA))
2075 isr_rxdata(info);
2076 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2077 info->icount.brk++;
2078 /* process break detection if tty control allows */
2079 if (info->port.tty) {
2080 if (!(status & info->ignore_status_mask)) {
2081 if (info->read_status_mask & MASK_BREAK) {
2082 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2083 if (info->port.flags & ASYNC_SAK)
2084 do_SAK(info->port.tty);
2085 }
2086 }
2087 }
2088 }
2089 } else {
2090 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2091 isr_txeom(info, status);
2092 if (info->rx_pio && (status & IRQ_RXDATA))
2093 isr_rxdata(info);
2094 if (status & IRQ_RXIDLE) {
2095 if (status & RXIDLE)
2096 info->icount.rxidle++;
2097 else
2098 info->icount.exithunt++;
2099 wake_up_interruptible(&info->event_wait_q);
2100 }
2101
2102 if (status & IRQ_RXOVER)
2103 rx_start(info);
2104 }
2105
2106 if (status & IRQ_DSR)
2107 dsr_change(info, status);
2108 if (status & IRQ_CTS)
2109 cts_change(info, status);
2110 if (status & IRQ_DCD)
2111 dcd_change(info, status);
2112 if (status & IRQ_RI)
2113 ri_change(info, status);
2114}
2115
2116static void isr_rdma(struct slgt_info *info)
2117{
2118 unsigned int status = rd_reg32(info, RDCSR);
2119
2120 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2121
2122 /* RDCSR (rx DMA control/status)
2123 *
2124 * 31..07 reserved
2125 * 06 save status byte to DMA buffer
2126 * 05 error
2127 * 04 eol (end of list)
2128 * 03 eob (end of buffer)
2129 * 02 IRQ enable
2130 * 01 reset
2131 * 00 enable
2132 */
2133 wr_reg32(info, RDCSR, status); /* clear pending */
2134
2135 if (status & (BIT5 + BIT4)) {
2136 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2137 info->rx_restart = true;
2138 }
2139 info->pending_bh |= BH_RECEIVE;
2140}
2141
2142static void isr_tdma(struct slgt_info *info)
2143{
2144 unsigned int status = rd_reg32(info, TDCSR);
2145
2146 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2147
2148 /* TDCSR (tx DMA control/status)
2149 *
2150 * 31..06 reserved
2151 * 05 error
2152 * 04 eol (end of list)
2153 * 03 eob (end of buffer)
2154 * 02 IRQ enable
2155 * 01 reset
2156 * 00 enable
2157 */
2158 wr_reg32(info, TDCSR, status); /* clear pending */
2159
2160 if (status & (BIT5 + BIT4 + BIT3)) {
2161 // another transmit buffer has completed
2162 // run bottom half to get more send data from user
2163 info->pending_bh |= BH_TRANSMIT;
2164 }
2165}
2166
2167/*
2168 * return true if there are unsent tx DMA buffers, otherwise false
2169 *
2170 * if there are unsent buffers then info->tbuf_start
2171 * is set to index of first unsent buffer
2172 */
2173static bool unsent_tbufs(struct slgt_info *info)
2174{
2175 unsigned int i = info->tbuf_current;
2176 bool rc = false;
2177
2178 /*
2179 * search backwards from last loaded buffer (precedes tbuf_current)
2180 * for first unsent buffer (desc_count > 0)
2181 */
2182
2183 do {
2184 if (i)
2185 i--;
2186 else
2187 i = info->tbuf_count - 1;
2188 if (!desc_count(info->tbufs[i]))
2189 break;
2190 info->tbuf_start = i;
2191 rc = true;
2192 } while (i != info->tbuf_current);
2193
2194 return rc;
2195}
2196
2197static void isr_txeom(struct slgt_info *info, unsigned short status)
2198{
2199 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2200
2201 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2202 tdma_reset(info);
2203 if (status & IRQ_TXUNDER) {
2204 unsigned short val = rd_reg16(info, TCR);
2205 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2206 wr_reg16(info, TCR, val); /* clear reset bit */
2207 }
2208
2209 if (info->tx_active) {
2210 if (info->params.mode != MGSL_MODE_ASYNC) {
2211 if (status & IRQ_TXUNDER)
2212 info->icount.txunder++;
2213 else if (status & IRQ_TXIDLE)
2214 info->icount.txok++;
2215 }
2216
2217 if (unsent_tbufs(info)) {
2218 tx_start(info);
2219 update_tx_timer(info);
2220 return;
2221 }
2222 info->tx_active = false;
2223
2224 del_timer(&info->tx_timer);
2225
2226 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2227 info->signals &= ~SerialSignal_RTS;
2228 info->drop_rts_on_tx_done = false;
2229 set_gtsignals(info);
2230 }
2231
2232#if SYNCLINK_GENERIC_HDLC
2233 if (info->netcount)
2234 hdlcdev_tx_done(info);
2235 else
2236#endif
2237 {
2238 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2239 tx_stop(info);
2240 return;
2241 }
2242 info->pending_bh |= BH_TRANSMIT;
2243 }
2244 }
2245}
2246
2247static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2248{
2249 struct cond_wait *w, *prev;
2250
2251 /* wake processes waiting for specific transitions */
2252 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2253 if (w->data & changed) {
2254 w->data = state;
2255 wake_up_interruptible(&w->q);
2256 if (prev != NULL)
2257 prev->next = w->next;
2258 else
2259 info->gpio_wait_q = w->next;
2260 } else
2261 prev = w;
2262 }
2263}
2264
2265/* interrupt service routine
2266 *
2267 * irq interrupt number
2268 * dev_id device ID supplied during interrupt registration
2269 */
2270static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2271{
2272 struct slgt_info *info = dev_id;
2273 unsigned int gsr;
2274 unsigned int i;
2275
2276 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2277
2278 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2279 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2280 info->irq_occurred = true;
2281 for(i=0; i < info->port_count ; i++) {
2282 if (info->port_array[i] == NULL)
2283 continue;
2284 spin_lock(&info->port_array[i]->lock);
2285 if (gsr & (BIT8 << i))
2286 isr_serial(info->port_array[i]);
2287 if (gsr & (BIT16 << (i*2)))
2288 isr_rdma(info->port_array[i]);
2289 if (gsr & (BIT17 << (i*2)))
2290 isr_tdma(info->port_array[i]);
2291 spin_unlock(&info->port_array[i]->lock);
2292 }
2293 }
2294
2295 if (info->gpio_present) {
2296 unsigned int state;
2297 unsigned int changed;
2298 spin_lock(&info->lock);
2299 while ((changed = rd_reg32(info, IOSR)) != 0) {
2300 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2301 /* read latched state of GPIO signals */
2302 state = rd_reg32(info, IOVR);
2303 /* clear pending GPIO interrupt bits */
2304 wr_reg32(info, IOSR, changed);
2305 for (i=0 ; i < info->port_count ; i++) {
2306 if (info->port_array[i] != NULL)
2307 isr_gpio(info->port_array[i], changed, state);
2308 }
2309 }
2310 spin_unlock(&info->lock);
2311 }
2312
2313 for(i=0; i < info->port_count ; i++) {
2314 struct slgt_info *port = info->port_array[i];
2315 if (port == NULL)
2316 continue;
2317 spin_lock(&port->lock);
2318 if ((port->port.count || port->netcount) &&
2319 port->pending_bh && !port->bh_running &&
2320 !port->bh_requested) {
2321 DBGISR(("%s bh queued\n", port->device_name));
2322 schedule_work(&port->task);
2323 port->bh_requested = true;
2324 }
2325 spin_unlock(&port->lock);
2326 }
2327
2328 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2329 return IRQ_HANDLED;
2330}
2331
2332static int startup(struct slgt_info *info)
2333{
2334 DBGINFO(("%s startup\n", info->device_name));
2335
2336 if (tty_port_initialized(&info->port))
2337 return 0;
2338
2339 if (!info->tx_buf) {
2340 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2341 if (!info->tx_buf) {
2342 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2343 return -ENOMEM;
2344 }
2345 }
2346
2347 info->pending_bh = 0;
2348
2349 memset(&info->icount, 0, sizeof(info->icount));
2350
2351 /* program hardware for current parameters */
2352 change_params(info);
2353
2354 if (info->port.tty)
2355 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2356
2357 tty_port_set_initialized(&info->port, 1);
2358
2359 return 0;
2360}
2361
2362/*
2363 * called by close() and hangup() to shutdown hardware
2364 */
2365static void shutdown(struct slgt_info *info)
2366{
2367 unsigned long flags;
2368
2369 if (!tty_port_initialized(&info->port))
2370 return;
2371
2372 DBGINFO(("%s shutdown\n", info->device_name));
2373
2374 /* clear status wait queue because status changes */
2375 /* can't happen after shutting down the hardware */
2376 wake_up_interruptible(&info->status_event_wait_q);
2377 wake_up_interruptible(&info->event_wait_q);
2378
2379 del_timer_sync(&info->tx_timer);
2380 del_timer_sync(&info->rx_timer);
2381
2382 kfree(info->tx_buf);
2383 info->tx_buf = NULL;
2384
2385 spin_lock_irqsave(&info->lock,flags);
2386
2387 tx_stop(info);
2388 rx_stop(info);
2389
2390 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2391
2392 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2393 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2394 set_gtsignals(info);
2395 }
2396
2397 flush_cond_wait(&info->gpio_wait_q);
2398
2399 spin_unlock_irqrestore(&info->lock,flags);
2400
2401 if (info->port.tty)
2402 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2403
2404 tty_port_set_initialized(&info->port, 0);
2405}
2406
2407static void program_hw(struct slgt_info *info)
2408{
2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&info->lock,flags);
2412
2413 rx_stop(info);
2414 tx_stop(info);
2415
2416 if (info->params.mode != MGSL_MODE_ASYNC ||
2417 info->netcount)
2418 sync_mode(info);
2419 else
2420 async_mode(info);
2421
2422 set_gtsignals(info);
2423
2424 info->dcd_chkcount = 0;
2425 info->cts_chkcount = 0;
2426 info->ri_chkcount = 0;
2427 info->dsr_chkcount = 0;
2428
2429 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2430 get_gtsignals(info);
2431
2432 if (info->netcount ||
2433 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2434 rx_start(info);
2435
2436 spin_unlock_irqrestore(&info->lock,flags);
2437}
2438
2439/*
2440 * reconfigure adapter based on new parameters
2441 */
2442static void change_params(struct slgt_info *info)
2443{
2444 unsigned cflag;
2445 int bits_per_char;
2446
2447 if (!info->port.tty)
2448 return;
2449 DBGINFO(("%s change_params\n", info->device_name));
2450
2451 cflag = info->port.tty->termios.c_cflag;
2452
2453 /* if B0 rate (hangup) specified then negate RTS and DTR */
2454 /* otherwise assert RTS and DTR */
2455 if (cflag & CBAUD)
2456 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2457 else
2458 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2459
2460 /* byte size and parity */
2461
2462 info->params.data_bits = tty_get_char_size(cflag);
2463 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2464
2465 if (cflag & PARENB)
2466 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2467 else
2468 info->params.parity = ASYNC_PARITY_NONE;
2469
2470 /* calculate number of jiffies to transmit a full
2471 * FIFO (32 bytes) at specified data rate
2472 */
2473 bits_per_char = info->params.data_bits +
2474 info->params.stop_bits + 1;
2475
2476 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2477
2478 if (info->params.data_rate) {
2479 info->timeout = (32*HZ*bits_per_char) /
2480 info->params.data_rate;
2481 }
2482 info->timeout += HZ/50; /* Add .02 seconds of slop */
2483
2484 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2485 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2486
2487 /* process tty input control flags */
2488
2489 info->read_status_mask = IRQ_RXOVER;
2490 if (I_INPCK(info->port.tty))
2491 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2492 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2493 info->read_status_mask |= MASK_BREAK;
2494 if (I_IGNPAR(info->port.tty))
2495 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2496 if (I_IGNBRK(info->port.tty)) {
2497 info->ignore_status_mask |= MASK_BREAK;
2498 /* If ignoring parity and break indicators, ignore
2499 * overruns too. (For real raw support).
2500 */
2501 if (I_IGNPAR(info->port.tty))
2502 info->ignore_status_mask |= MASK_OVERRUN;
2503 }
2504
2505 program_hw(info);
2506}
2507
2508static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2509{
2510 DBGINFO(("%s get_stats\n", info->device_name));
2511 if (!user_icount) {
2512 memset(&info->icount, 0, sizeof(info->icount));
2513 } else {
2514 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2515 return -EFAULT;
2516 }
2517 return 0;
2518}
2519
2520static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2521{
2522 DBGINFO(("%s get_params\n", info->device_name));
2523 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2524 return -EFAULT;
2525 return 0;
2526}
2527
2528static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2529{
2530 unsigned long flags;
2531 MGSL_PARAMS tmp_params;
2532
2533 DBGINFO(("%s set_params\n", info->device_name));
2534 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2535 return -EFAULT;
2536
2537 spin_lock_irqsave(&info->lock, flags);
2538 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2539 info->base_clock = tmp_params.clock_speed;
2540 else
2541 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2542 spin_unlock_irqrestore(&info->lock, flags);
2543
2544 program_hw(info);
2545
2546 return 0;
2547}
2548
2549static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2550{
2551 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2552 if (put_user(info->idle_mode, idle_mode))
2553 return -EFAULT;
2554 return 0;
2555}
2556
2557static int set_txidle(struct slgt_info *info, int idle_mode)
2558{
2559 unsigned long flags;
2560 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2561 spin_lock_irqsave(&info->lock,flags);
2562 info->idle_mode = idle_mode;
2563 if (info->params.mode != MGSL_MODE_ASYNC)
2564 tx_set_idle(info);
2565 spin_unlock_irqrestore(&info->lock,flags);
2566 return 0;
2567}
2568
2569static int tx_enable(struct slgt_info *info, int enable)
2570{
2571 unsigned long flags;
2572 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2573 spin_lock_irqsave(&info->lock,flags);
2574 if (enable) {
2575 if (!info->tx_enabled)
2576 tx_start(info);
2577 } else {
2578 if (info->tx_enabled)
2579 tx_stop(info);
2580 }
2581 spin_unlock_irqrestore(&info->lock,flags);
2582 return 0;
2583}
2584
2585/*
2586 * abort transmit HDLC frame
2587 */
2588static int tx_abort(struct slgt_info *info)
2589{
2590 unsigned long flags;
2591 DBGINFO(("%s tx_abort\n", info->device_name));
2592 spin_lock_irqsave(&info->lock,flags);
2593 tdma_reset(info);
2594 spin_unlock_irqrestore(&info->lock,flags);
2595 return 0;
2596}
2597
2598static int rx_enable(struct slgt_info *info, int enable)
2599{
2600 unsigned long flags;
2601 unsigned int rbuf_fill_level;
2602 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2603 spin_lock_irqsave(&info->lock,flags);
2604 /*
2605 * enable[31..16] = receive DMA buffer fill level
2606 * 0 = noop (leave fill level unchanged)
2607 * fill level must be multiple of 4 and <= buffer size
2608 */
2609 rbuf_fill_level = ((unsigned int)enable) >> 16;
2610 if (rbuf_fill_level) {
2611 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2612 spin_unlock_irqrestore(&info->lock, flags);
2613 return -EINVAL;
2614 }
2615 info->rbuf_fill_level = rbuf_fill_level;
2616 if (rbuf_fill_level < 128)
2617 info->rx_pio = 1; /* PIO mode */
2618 else
2619 info->rx_pio = 0; /* DMA mode */
2620 rx_stop(info); /* restart receiver to use new fill level */
2621 }
2622
2623 /*
2624 * enable[1..0] = receiver enable command
2625 * 0 = disable
2626 * 1 = enable
2627 * 2 = enable or force hunt mode if already enabled
2628 */
2629 enable &= 3;
2630 if (enable) {
2631 if (!info->rx_enabled)
2632 rx_start(info);
2633 else if (enable == 2) {
2634 /* force hunt mode (write 1 to RCR[3]) */
2635 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2636 }
2637 } else {
2638 if (info->rx_enabled)
2639 rx_stop(info);
2640 }
2641 spin_unlock_irqrestore(&info->lock,flags);
2642 return 0;
2643}
2644
2645/*
2646 * wait for specified event to occur
2647 */
2648static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2649{
2650 unsigned long flags;
2651 int s;
2652 int rc=0;
2653 struct mgsl_icount cprev, cnow;
2654 int events;
2655 int mask;
2656 struct _input_signal_events oldsigs, newsigs;
2657 DECLARE_WAITQUEUE(wait, current);
2658
2659 if (get_user(mask, mask_ptr))
2660 return -EFAULT;
2661
2662 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2663
2664 spin_lock_irqsave(&info->lock,flags);
2665
2666 /* return immediately if state matches requested events */
2667 get_gtsignals(info);
2668 s = info->signals;
2669
2670 events = mask &
2671 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2672 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2673 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2674 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2675 if (events) {
2676 spin_unlock_irqrestore(&info->lock,flags);
2677 goto exit;
2678 }
2679
2680 /* save current irq counts */
2681 cprev = info->icount;
2682 oldsigs = info->input_signal_events;
2683
2684 /* enable hunt and idle irqs if needed */
2685 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2686 unsigned short val = rd_reg16(info, SCR);
2687 if (!(val & IRQ_RXIDLE))
2688 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2689 }
2690
2691 set_current_state(TASK_INTERRUPTIBLE);
2692 add_wait_queue(&info->event_wait_q, &wait);
2693
2694 spin_unlock_irqrestore(&info->lock,flags);
2695
2696 for(;;) {
2697 schedule();
2698 if (signal_pending(current)) {
2699 rc = -ERESTARTSYS;
2700 break;
2701 }
2702
2703 /* get current irq counts */
2704 spin_lock_irqsave(&info->lock,flags);
2705 cnow = info->icount;
2706 newsigs = info->input_signal_events;
2707 set_current_state(TASK_INTERRUPTIBLE);
2708 spin_unlock_irqrestore(&info->lock,flags);
2709
2710 /* if no change, wait aborted for some reason */
2711 if (newsigs.dsr_up == oldsigs.dsr_up &&
2712 newsigs.dsr_down == oldsigs.dsr_down &&
2713 newsigs.dcd_up == oldsigs.dcd_up &&
2714 newsigs.dcd_down == oldsigs.dcd_down &&
2715 newsigs.cts_up == oldsigs.cts_up &&
2716 newsigs.cts_down == oldsigs.cts_down &&
2717 newsigs.ri_up == oldsigs.ri_up &&
2718 newsigs.ri_down == oldsigs.ri_down &&
2719 cnow.exithunt == cprev.exithunt &&
2720 cnow.rxidle == cprev.rxidle) {
2721 rc = -EIO;
2722 break;
2723 }
2724
2725 events = mask &
2726 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2727 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2728 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2729 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2730 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2731 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2732 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2733 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2734 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2735 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2736 if (events)
2737 break;
2738
2739 cprev = cnow;
2740 oldsigs = newsigs;
2741 }
2742
2743 remove_wait_queue(&info->event_wait_q, &wait);
2744 set_current_state(TASK_RUNNING);
2745
2746
2747 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2748 spin_lock_irqsave(&info->lock,flags);
2749 if (!waitqueue_active(&info->event_wait_q)) {
2750 /* disable enable exit hunt mode/idle rcvd IRQs */
2751 wr_reg16(info, SCR,
2752 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2753 }
2754 spin_unlock_irqrestore(&info->lock,flags);
2755 }
2756exit:
2757 if (rc == 0)
2758 rc = put_user(events, mask_ptr);
2759 return rc;
2760}
2761
2762static int get_interface(struct slgt_info *info, int __user *if_mode)
2763{
2764 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2765 if (put_user(info->if_mode, if_mode))
2766 return -EFAULT;
2767 return 0;
2768}
2769
2770static int set_interface(struct slgt_info *info, int if_mode)
2771{
2772 unsigned long flags;
2773 unsigned short val;
2774
2775 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2776 spin_lock_irqsave(&info->lock,flags);
2777 info->if_mode = if_mode;
2778
2779 msc_set_vcr(info);
2780
2781 /* TCR (tx control) 07 1=RTS driver control */
2782 val = rd_reg16(info, TCR);
2783 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2784 val |= BIT7;
2785 else
2786 val &= ~BIT7;
2787 wr_reg16(info, TCR, val);
2788
2789 spin_unlock_irqrestore(&info->lock,flags);
2790 return 0;
2791}
2792
2793static int get_xsync(struct slgt_info *info, int __user *xsync)
2794{
2795 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2796 if (put_user(info->xsync, xsync))
2797 return -EFAULT;
2798 return 0;
2799}
2800
2801/*
2802 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2803 *
2804 * sync pattern is contained in least significant bytes of value
2805 * most significant byte of sync pattern is oldest (1st sent/detected)
2806 */
2807static int set_xsync(struct slgt_info *info, int xsync)
2808{
2809 unsigned long flags;
2810
2811 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2812 spin_lock_irqsave(&info->lock, flags);
2813 info->xsync = xsync;
2814 wr_reg32(info, XSR, xsync);
2815 spin_unlock_irqrestore(&info->lock, flags);
2816 return 0;
2817}
2818
2819static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2820{
2821 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2822 if (put_user(info->xctrl, xctrl))
2823 return -EFAULT;
2824 return 0;
2825}
2826
2827/*
2828 * set extended control options
2829 *
2830 * xctrl[31:19] reserved, must be zero
2831 * xctrl[18:17] extended sync pattern length in bytes
2832 * 00 = 1 byte in xsr[7:0]
2833 * 01 = 2 bytes in xsr[15:0]
2834 * 10 = 3 bytes in xsr[23:0]
2835 * 11 = 4 bytes in xsr[31:0]
2836 * xctrl[16] 1 = enable terminal count, 0=disabled
2837 * xctrl[15:0] receive terminal count for fixed length packets
2838 * value is count minus one (0 = 1 byte packet)
2839 * when terminal count is reached, receiver
2840 * automatically returns to hunt mode and receive
2841 * FIFO contents are flushed to DMA buffers with
2842 * end of frame (EOF) status
2843 */
2844static int set_xctrl(struct slgt_info *info, int xctrl)
2845{
2846 unsigned long flags;
2847
2848 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2849 spin_lock_irqsave(&info->lock, flags);
2850 info->xctrl = xctrl;
2851 wr_reg32(info, XCR, xctrl);
2852 spin_unlock_irqrestore(&info->lock, flags);
2853 return 0;
2854}
2855
2856/*
2857 * set general purpose IO pin state and direction
2858 *
2859 * user_gpio fields:
2860 * state each bit indicates a pin state
2861 * smask set bit indicates pin state to set
2862 * dir each bit indicates a pin direction (0=input, 1=output)
2863 * dmask set bit indicates pin direction to set
2864 */
2865static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2866{
2867 unsigned long flags;
2868 struct gpio_desc gpio;
2869 __u32 data;
2870
2871 if (!info->gpio_present)
2872 return -EINVAL;
2873 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2874 return -EFAULT;
2875 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2876 info->device_name, gpio.state, gpio.smask,
2877 gpio.dir, gpio.dmask));
2878
2879 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2880 if (gpio.dmask) {
2881 data = rd_reg32(info, IODR);
2882 data |= gpio.dmask & gpio.dir;
2883 data &= ~(gpio.dmask & ~gpio.dir);
2884 wr_reg32(info, IODR, data);
2885 }
2886 if (gpio.smask) {
2887 data = rd_reg32(info, IOVR);
2888 data |= gpio.smask & gpio.state;
2889 data &= ~(gpio.smask & ~gpio.state);
2890 wr_reg32(info, IOVR, data);
2891 }
2892 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2893
2894 return 0;
2895}
2896
2897/*
2898 * get general purpose IO pin state and direction
2899 */
2900static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2901{
2902 struct gpio_desc gpio;
2903 if (!info->gpio_present)
2904 return -EINVAL;
2905 gpio.state = rd_reg32(info, IOVR);
2906 gpio.smask = 0xffffffff;
2907 gpio.dir = rd_reg32(info, IODR);
2908 gpio.dmask = 0xffffffff;
2909 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2910 return -EFAULT;
2911 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2912 info->device_name, gpio.state, gpio.dir));
2913 return 0;
2914}
2915
2916/*
2917 * conditional wait facility
2918 */
2919static void init_cond_wait(struct cond_wait *w, unsigned int data)
2920{
2921 init_waitqueue_head(&w->q);
2922 init_waitqueue_entry(&w->wait, current);
2923 w->data = data;
2924}
2925
2926static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2927{
2928 set_current_state(TASK_INTERRUPTIBLE);
2929 add_wait_queue(&w->q, &w->wait);
2930 w->next = *head;
2931 *head = w;
2932}
2933
2934static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2935{
2936 struct cond_wait *w, *prev;
2937 remove_wait_queue(&cw->q, &cw->wait);
2938 set_current_state(TASK_RUNNING);
2939 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2940 if (w == cw) {
2941 if (prev != NULL)
2942 prev->next = w->next;
2943 else
2944 *head = w->next;
2945 break;
2946 }
2947 }
2948}
2949
2950static void flush_cond_wait(struct cond_wait **head)
2951{
2952 while (*head != NULL) {
2953 wake_up_interruptible(&(*head)->q);
2954 *head = (*head)->next;
2955 }
2956}
2957
2958/*
2959 * wait for general purpose I/O pin(s) to enter specified state
2960 *
2961 * user_gpio fields:
2962 * state - bit indicates target pin state
2963 * smask - set bit indicates watched pin
2964 *
2965 * The wait ends when at least one watched pin enters the specified
2966 * state. When 0 (no error) is returned, user_gpio->state is set to the
2967 * state of all GPIO pins when the wait ends.
2968 *
2969 * Note: Each pin may be a dedicated input, dedicated output, or
2970 * configurable input/output. The number and configuration of pins
2971 * varies with the specific adapter model. Only input pins (dedicated
2972 * or configured) can be monitored with this function.
2973 */
2974static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2975{
2976 unsigned long flags;
2977 int rc = 0;
2978 struct gpio_desc gpio;
2979 struct cond_wait wait;
2980 u32 state;
2981
2982 if (!info->gpio_present)
2983 return -EINVAL;
2984 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2985 return -EFAULT;
2986 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2987 info->device_name, gpio.state, gpio.smask));
2988 /* ignore output pins identified by set IODR bit */
2989 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2990 return -EINVAL;
2991 init_cond_wait(&wait, gpio.smask);
2992
2993 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2994 /* enable interrupts for watched pins */
2995 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2996 /* get current pin states */
2997 state = rd_reg32(info, IOVR);
2998
2999 if (gpio.smask & ~(state ^ gpio.state)) {
3000 /* already in target state */
3001 gpio.state = state;
3002 } else {
3003 /* wait for target state */
3004 add_cond_wait(&info->gpio_wait_q, &wait);
3005 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3006 schedule();
3007 if (signal_pending(current))
3008 rc = -ERESTARTSYS;
3009 else
3010 gpio.state = wait.data;
3011 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3012 remove_cond_wait(&info->gpio_wait_q, &wait);
3013 }
3014
3015 /* disable all GPIO interrupts if no waiting processes */
3016 if (info->gpio_wait_q == NULL)
3017 wr_reg32(info, IOER, 0);
3018 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3019
3020 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3021 rc = -EFAULT;
3022 return rc;
3023}
3024
3025static int modem_input_wait(struct slgt_info *info,int arg)
3026{
3027 unsigned long flags;
3028 int rc;
3029 struct mgsl_icount cprev, cnow;
3030 DECLARE_WAITQUEUE(wait, current);
3031
3032 /* save current irq counts */
3033 spin_lock_irqsave(&info->lock,flags);
3034 cprev = info->icount;
3035 add_wait_queue(&info->status_event_wait_q, &wait);
3036 set_current_state(TASK_INTERRUPTIBLE);
3037 spin_unlock_irqrestore(&info->lock,flags);
3038
3039 for(;;) {
3040 schedule();
3041 if (signal_pending(current)) {
3042 rc = -ERESTARTSYS;
3043 break;
3044 }
3045
3046 /* get new irq counts */
3047 spin_lock_irqsave(&info->lock,flags);
3048 cnow = info->icount;
3049 set_current_state(TASK_INTERRUPTIBLE);
3050 spin_unlock_irqrestore(&info->lock,flags);
3051
3052 /* if no change, wait aborted for some reason */
3053 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3054 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3055 rc = -EIO;
3056 break;
3057 }
3058
3059 /* check for change in caller specified modem input */
3060 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3061 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3062 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3063 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3064 rc = 0;
3065 break;
3066 }
3067
3068 cprev = cnow;
3069 }
3070 remove_wait_queue(&info->status_event_wait_q, &wait);
3071 set_current_state(TASK_RUNNING);
3072 return rc;
3073}
3074
3075/*
3076 * return state of serial control and status signals
3077 */
3078static int tiocmget(struct tty_struct *tty)
3079{
3080 struct slgt_info *info = tty->driver_data;
3081 unsigned int result;
3082 unsigned long flags;
3083
3084 spin_lock_irqsave(&info->lock,flags);
3085 get_gtsignals(info);
3086 spin_unlock_irqrestore(&info->lock,flags);
3087
3088 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3089 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3090 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3091 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3092 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3093 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3094
3095 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3096 return result;
3097}
3098
3099/*
3100 * set modem control signals (DTR/RTS)
3101 *
3102 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3103 * TIOCMSET = set/clear signal values
3104 * value bit mask for command
3105 */
3106static int tiocmset(struct tty_struct *tty,
3107 unsigned int set, unsigned int clear)
3108{
3109 struct slgt_info *info = tty->driver_data;
3110 unsigned long flags;
3111
3112 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3113
3114 if (set & TIOCM_RTS)
3115 info->signals |= SerialSignal_RTS;
3116 if (set & TIOCM_DTR)
3117 info->signals |= SerialSignal_DTR;
3118 if (clear & TIOCM_RTS)
3119 info->signals &= ~SerialSignal_RTS;
3120 if (clear & TIOCM_DTR)
3121 info->signals &= ~SerialSignal_DTR;
3122
3123 spin_lock_irqsave(&info->lock,flags);
3124 set_gtsignals(info);
3125 spin_unlock_irqrestore(&info->lock,flags);
3126 return 0;
3127}
3128
3129static int carrier_raised(struct tty_port *port)
3130{
3131 unsigned long flags;
3132 struct slgt_info *info = container_of(port, struct slgt_info, port);
3133
3134 spin_lock_irqsave(&info->lock,flags);
3135 get_gtsignals(info);
3136 spin_unlock_irqrestore(&info->lock,flags);
3137 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3138}
3139
3140static void dtr_rts(struct tty_port *port, int on)
3141{
3142 unsigned long flags;
3143 struct slgt_info *info = container_of(port, struct slgt_info, port);
3144
3145 spin_lock_irqsave(&info->lock,flags);
3146 if (on)
3147 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3148 else
3149 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3150 set_gtsignals(info);
3151 spin_unlock_irqrestore(&info->lock,flags);
3152}
3153
3154
3155/*
3156 * block current process until the device is ready to open
3157 */
3158static int block_til_ready(struct tty_struct *tty, struct file *filp,
3159 struct slgt_info *info)
3160{
3161 DECLARE_WAITQUEUE(wait, current);
3162 int retval;
3163 bool do_clocal = false;
3164 unsigned long flags;
3165 int cd;
3166 struct tty_port *port = &info->port;
3167
3168 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3169
3170 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3171 /* nonblock mode is set or port is not enabled */
3172 tty_port_set_active(port, 1);
3173 return 0;
3174 }
3175
3176 if (C_CLOCAL(tty))
3177 do_clocal = true;
3178
3179 /* Wait for carrier detect and the line to become
3180 * free (i.e., not in use by the callout). While we are in
3181 * this loop, port->count is dropped by one, so that
3182 * close() knows when to free things. We restore it upon
3183 * exit, either normal or abnormal.
3184 */
3185
3186 retval = 0;
3187 add_wait_queue(&port->open_wait, &wait);
3188
3189 spin_lock_irqsave(&info->lock, flags);
3190 port->count--;
3191 spin_unlock_irqrestore(&info->lock, flags);
3192 port->blocked_open++;
3193
3194 while (1) {
3195 if (C_BAUD(tty) && tty_port_initialized(port))
3196 tty_port_raise_dtr_rts(port);
3197
3198 set_current_state(TASK_INTERRUPTIBLE);
3199
3200 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3201 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3202 -EAGAIN : -ERESTARTSYS;
3203 break;
3204 }
3205
3206 cd = tty_port_carrier_raised(port);
3207 if (do_clocal || cd)
3208 break;
3209
3210 if (signal_pending(current)) {
3211 retval = -ERESTARTSYS;
3212 break;
3213 }
3214
3215 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3216 tty_unlock(tty);
3217 schedule();
3218 tty_lock(tty);
3219 }
3220
3221 set_current_state(TASK_RUNNING);
3222 remove_wait_queue(&port->open_wait, &wait);
3223
3224 if (!tty_hung_up_p(filp))
3225 port->count++;
3226 port->blocked_open--;
3227
3228 if (!retval)
3229 tty_port_set_active(port, 1);
3230
3231 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3232 return retval;
3233}
3234
3235/*
3236 * allocate buffers used for calling line discipline receive_buf
3237 * directly in synchronous mode
3238 * note: add 5 bytes to max frame size to allow appending
3239 * 32-bit CRC and status byte when configured to do so
3240 */
3241static int alloc_tmp_rbuf(struct slgt_info *info)
3242{
3243 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3244 if (info->tmp_rbuf == NULL)
3245 return -ENOMEM;
3246 /* unused flag buffer to satisfy receive_buf calling interface */
3247 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3248 if (!info->flag_buf) {
3249 kfree(info->tmp_rbuf);
3250 info->tmp_rbuf = NULL;
3251 return -ENOMEM;
3252 }
3253 return 0;
3254}
3255
3256static void free_tmp_rbuf(struct slgt_info *info)
3257{
3258 kfree(info->tmp_rbuf);
3259 info->tmp_rbuf = NULL;
3260 kfree(info->flag_buf);
3261 info->flag_buf = NULL;
3262}
3263
3264/*
3265 * allocate DMA descriptor lists.
3266 */
3267static int alloc_desc(struct slgt_info *info)
3268{
3269 unsigned int i;
3270 unsigned int pbufs;
3271
3272 /* allocate memory to hold descriptor lists */
3273 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3274 &info->bufs_dma_addr, GFP_KERNEL);
3275 if (info->bufs == NULL)
3276 return -ENOMEM;
3277
3278 info->rbufs = (struct slgt_desc*)info->bufs;
3279 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3280
3281 pbufs = (unsigned int)info->bufs_dma_addr;
3282
3283 /*
3284 * Build circular lists of descriptors
3285 */
3286
3287 for (i=0; i < info->rbuf_count; i++) {
3288 /* physical address of this descriptor */
3289 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3290
3291 /* physical address of next descriptor */
3292 if (i == info->rbuf_count - 1)
3293 info->rbufs[i].next = cpu_to_le32(pbufs);
3294 else
3295 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3296 set_desc_count(info->rbufs[i], DMABUFSIZE);
3297 }
3298
3299 for (i=0; i < info->tbuf_count; i++) {
3300 /* physical address of this descriptor */
3301 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3302
3303 /* physical address of next descriptor */
3304 if (i == info->tbuf_count - 1)
3305 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3306 else
3307 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3308 }
3309
3310 return 0;
3311}
3312
3313static void free_desc(struct slgt_info *info)
3314{
3315 if (info->bufs != NULL) {
3316 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3317 info->bufs, info->bufs_dma_addr);
3318 info->bufs = NULL;
3319 info->rbufs = NULL;
3320 info->tbufs = NULL;
3321 }
3322}
3323
3324static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3325{
3326 int i;
3327 for (i=0; i < count; i++) {
3328 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3329 &bufs[i].buf_dma_addr, GFP_KERNEL);
3330 if (!bufs[i].buf)
3331 return -ENOMEM;
3332 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3333 }
3334 return 0;
3335}
3336
3337static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3338{
3339 int i;
3340 for (i=0; i < count; i++) {
3341 if (bufs[i].buf == NULL)
3342 continue;
3343 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3344 bufs[i].buf_dma_addr);
3345 bufs[i].buf = NULL;
3346 }
3347}
3348
3349static int alloc_dma_bufs(struct slgt_info *info)
3350{
3351 info->rbuf_count = 32;
3352 info->tbuf_count = 32;
3353
3354 if (alloc_desc(info) < 0 ||
3355 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3356 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3357 alloc_tmp_rbuf(info) < 0) {
3358 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3359 return -ENOMEM;
3360 }
3361 reset_rbufs(info);
3362 return 0;
3363}
3364
3365static void free_dma_bufs(struct slgt_info *info)
3366{
3367 if (info->bufs) {
3368 free_bufs(info, info->rbufs, info->rbuf_count);
3369 free_bufs(info, info->tbufs, info->tbuf_count);
3370 free_desc(info);
3371 }
3372 free_tmp_rbuf(info);
3373}
3374
3375static int claim_resources(struct slgt_info *info)
3376{
3377 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3378 DBGERR(("%s reg addr conflict, addr=%08X\n",
3379 info->device_name, info->phys_reg_addr));
3380 info->init_error = DiagStatus_AddressConflict;
3381 goto errout;
3382 }
3383 else
3384 info->reg_addr_requested = true;
3385
3386 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3387 if (!info->reg_addr) {
3388 DBGERR(("%s can't map device registers, addr=%08X\n",
3389 info->device_name, info->phys_reg_addr));
3390 info->init_error = DiagStatus_CantAssignPciResources;
3391 goto errout;
3392 }
3393 return 0;
3394
3395errout:
3396 release_resources(info);
3397 return -ENODEV;
3398}
3399
3400static void release_resources(struct slgt_info *info)
3401{
3402 if (info->irq_requested) {
3403 free_irq(info->irq_level, info);
3404 info->irq_requested = false;
3405 }
3406
3407 if (info->reg_addr_requested) {
3408 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3409 info->reg_addr_requested = false;
3410 }
3411
3412 if (info->reg_addr) {
3413 iounmap(info->reg_addr);
3414 info->reg_addr = NULL;
3415 }
3416}
3417
3418/* Add the specified device instance data structure to the
3419 * global linked list of devices and increment the device count.
3420 */
3421static void add_device(struct slgt_info *info)
3422{
3423 char *devstr;
3424
3425 info->next_device = NULL;
3426 info->line = slgt_device_count;
3427 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3428
3429 if (info->line < MAX_DEVICES) {
3430 if (maxframe[info->line])
3431 info->max_frame_size = maxframe[info->line];
3432 }
3433
3434 slgt_device_count++;
3435
3436 if (!slgt_device_list)
3437 slgt_device_list = info;
3438 else {
3439 struct slgt_info *current_dev = slgt_device_list;
3440 while(current_dev->next_device)
3441 current_dev = current_dev->next_device;
3442 current_dev->next_device = info;
3443 }
3444
3445 if (info->max_frame_size < 4096)
3446 info->max_frame_size = 4096;
3447 else if (info->max_frame_size > 65535)
3448 info->max_frame_size = 65535;
3449
3450 switch(info->pdev->device) {
3451 case SYNCLINK_GT_DEVICE_ID:
3452 devstr = "GT";
3453 break;
3454 case SYNCLINK_GT2_DEVICE_ID:
3455 devstr = "GT2";
3456 break;
3457 case SYNCLINK_GT4_DEVICE_ID:
3458 devstr = "GT4";
3459 break;
3460 case SYNCLINK_AC_DEVICE_ID:
3461 devstr = "AC";
3462 info->params.mode = MGSL_MODE_ASYNC;
3463 break;
3464 default:
3465 devstr = "(unknown model)";
3466 }
3467 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3468 devstr, info->device_name, info->phys_reg_addr,
3469 info->irq_level, info->max_frame_size);
3470
3471#if SYNCLINK_GENERIC_HDLC
3472 hdlcdev_init(info);
3473#endif
3474}
3475
3476static const struct tty_port_operations slgt_port_ops = {
3477 .carrier_raised = carrier_raised,
3478 .dtr_rts = dtr_rts,
3479};
3480
3481/*
3482 * allocate device instance structure, return NULL on failure
3483 */
3484static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3485{
3486 struct slgt_info *info;
3487
3488 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3489
3490 if (!info) {
3491 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3492 driver_name, adapter_num, port_num));
3493 } else {
3494 tty_port_init(&info->port);
3495 info->port.ops = &slgt_port_ops;
3496 INIT_WORK(&info->task, bh_handler);
3497 info->max_frame_size = 4096;
3498 info->base_clock = 14745600;
3499 info->rbuf_fill_level = DMABUFSIZE;
3500 init_waitqueue_head(&info->status_event_wait_q);
3501 init_waitqueue_head(&info->event_wait_q);
3502 spin_lock_init(&info->netlock);
3503 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3504 info->idle_mode = HDLC_TXIDLE_FLAGS;
3505 info->adapter_num = adapter_num;
3506 info->port_num = port_num;
3507
3508 timer_setup(&info->tx_timer, tx_timeout, 0);
3509 timer_setup(&info->rx_timer, rx_timeout, 0);
3510
3511 /* Copy configuration info to device instance data */
3512 info->pdev = pdev;
3513 info->irq_level = pdev->irq;
3514 info->phys_reg_addr = pci_resource_start(pdev,0);
3515
3516 info->bus_type = MGSL_BUS_TYPE_PCI;
3517 info->irq_flags = IRQF_SHARED;
3518
3519 info->init_error = -1; /* assume error, set to 0 on successful init */
3520 }
3521
3522 return info;
3523}
3524
3525static void device_init(int adapter_num, struct pci_dev *pdev)
3526{
3527 struct slgt_info *port_array[SLGT_MAX_PORTS];
3528 int i;
3529 int port_count = 1;
3530
3531 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3532 port_count = 2;
3533 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3534 port_count = 4;
3535
3536 /* allocate device instances for all ports */
3537 for (i=0; i < port_count; ++i) {
3538 port_array[i] = alloc_dev(adapter_num, i, pdev);
3539 if (port_array[i] == NULL) {
3540 for (--i; i >= 0; --i) {
3541 tty_port_destroy(&port_array[i]->port);
3542 kfree(port_array[i]);
3543 }
3544 return;
3545 }
3546 }
3547
3548 /* give copy of port_array to all ports and add to device list */
3549 for (i=0; i < port_count; ++i) {
3550 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3551 add_device(port_array[i]);
3552 port_array[i]->port_count = port_count;
3553 spin_lock_init(&port_array[i]->lock);
3554 }
3555
3556 /* Allocate and claim adapter resources */
3557 if (!claim_resources(port_array[0])) {
3558
3559 alloc_dma_bufs(port_array[0]);
3560
3561 /* copy resource information from first port to others */
3562 for (i = 1; i < port_count; ++i) {
3563 port_array[i]->irq_level = port_array[0]->irq_level;
3564 port_array[i]->reg_addr = port_array[0]->reg_addr;
3565 alloc_dma_bufs(port_array[i]);
3566 }
3567
3568 if (request_irq(port_array[0]->irq_level,
3569 slgt_interrupt,
3570 port_array[0]->irq_flags,
3571 port_array[0]->device_name,
3572 port_array[0]) < 0) {
3573 DBGERR(("%s request_irq failed IRQ=%d\n",
3574 port_array[0]->device_name,
3575 port_array[0]->irq_level));
3576 } else {
3577 port_array[0]->irq_requested = true;
3578 adapter_test(port_array[0]);
3579 for (i=1 ; i < port_count ; i++) {
3580 port_array[i]->init_error = port_array[0]->init_error;
3581 port_array[i]->gpio_present = port_array[0]->gpio_present;
3582 }
3583 }
3584 }
3585
3586 for (i = 0; i < port_count; ++i) {
3587 struct slgt_info *info = port_array[i];
3588 tty_port_register_device(&info->port, serial_driver, info->line,
3589 &info->pdev->dev);
3590 }
3591}
3592
3593static int init_one(struct pci_dev *dev,
3594 const struct pci_device_id *ent)
3595{
3596 if (pci_enable_device(dev)) {
3597 printk("error enabling pci device %p\n", dev);
3598 return -EIO;
3599 }
3600 pci_set_master(dev);
3601 device_init(slgt_device_count, dev);
3602 return 0;
3603}
3604
3605static void remove_one(struct pci_dev *dev)
3606{
3607}
3608
3609static const struct tty_operations ops = {
3610 .open = open,
3611 .close = close,
3612 .write = write,
3613 .put_char = put_char,
3614 .flush_chars = flush_chars,
3615 .write_room = write_room,
3616 .chars_in_buffer = chars_in_buffer,
3617 .flush_buffer = flush_buffer,
3618 .ioctl = ioctl,
3619 .compat_ioctl = slgt_compat_ioctl,
3620 .throttle = throttle,
3621 .unthrottle = unthrottle,
3622 .send_xchar = send_xchar,
3623 .break_ctl = set_break,
3624 .wait_until_sent = wait_until_sent,
3625 .set_termios = set_termios,
3626 .stop = tx_hold,
3627 .start = tx_release,
3628 .hangup = hangup,
3629 .tiocmget = tiocmget,
3630 .tiocmset = tiocmset,
3631 .get_icount = get_icount,
3632 .proc_show = synclink_gt_proc_show,
3633};
3634
3635static void slgt_cleanup(void)
3636{
3637 struct slgt_info *info;
3638 struct slgt_info *tmp;
3639
3640 printk(KERN_INFO "unload %s\n", driver_name);
3641
3642 if (serial_driver) {
3643 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3644 tty_unregister_device(serial_driver, info->line);
3645 tty_unregister_driver(serial_driver);
3646 tty_driver_kref_put(serial_driver);
3647 }
3648
3649 /* reset devices */
3650 info = slgt_device_list;
3651 while(info) {
3652 reset_port(info);
3653 info = info->next_device;
3654 }
3655
3656 /* release devices */
3657 info = slgt_device_list;
3658 while(info) {
3659#if SYNCLINK_GENERIC_HDLC
3660 hdlcdev_exit(info);
3661#endif
3662 free_dma_bufs(info);
3663 free_tmp_rbuf(info);
3664 if (info->port_num == 0)
3665 release_resources(info);
3666 tmp = info;
3667 info = info->next_device;
3668 tty_port_destroy(&tmp->port);
3669 kfree(tmp);
3670 }
3671
3672 if (pci_registered)
3673 pci_unregister_driver(&pci_driver);
3674}
3675
3676/*
3677 * Driver initialization entry point.
3678 */
3679static int __init slgt_init(void)
3680{
3681 int rc;
3682
3683 printk(KERN_INFO "%s\n", driver_name);
3684
3685 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3686 TTY_DRIVER_DYNAMIC_DEV);
3687 if (IS_ERR(serial_driver)) {
3688 printk("%s can't allocate tty driver\n", driver_name);
3689 return PTR_ERR(serial_driver);
3690 }
3691
3692 /* Initialize the tty_driver structure */
3693
3694 serial_driver->driver_name = slgt_driver_name;
3695 serial_driver->name = tty_dev_prefix;
3696 serial_driver->major = ttymajor;
3697 serial_driver->minor_start = 64;
3698 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3699 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3700 serial_driver->init_termios = tty_std_termios;
3701 serial_driver->init_termios.c_cflag =
3702 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3703 serial_driver->init_termios.c_ispeed = 9600;
3704 serial_driver->init_termios.c_ospeed = 9600;
3705 tty_set_operations(serial_driver, &ops);
3706 if ((rc = tty_register_driver(serial_driver)) < 0) {
3707 DBGERR(("%s can't register serial driver\n", driver_name));
3708 tty_driver_kref_put(serial_driver);
3709 serial_driver = NULL;
3710 goto error;
3711 }
3712
3713 printk(KERN_INFO "%s, tty major#%d\n",
3714 driver_name, serial_driver->major);
3715
3716 slgt_device_count = 0;
3717 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3718 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3719 goto error;
3720 }
3721 pci_registered = true;
3722
3723 if (!slgt_device_list)
3724 printk("%s no devices found\n",driver_name);
3725
3726 return 0;
3727
3728error:
3729 slgt_cleanup();
3730 return rc;
3731}
3732
3733static void __exit slgt_exit(void)
3734{
3735 slgt_cleanup();
3736}
3737
3738module_init(slgt_init);
3739module_exit(slgt_exit);
3740
3741/*
3742 * register access routines
3743 */
3744
3745#define CALC_REGADDR() \
3746 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3747 if (addr >= 0x80) \
3748 reg_addr += (info->port_num) * 32; \
3749 else if (addr >= 0x40) \
3750 reg_addr += (info->port_num) * 16;
3751
3752static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3753{
3754 CALC_REGADDR();
3755 return readb((void __iomem *)reg_addr);
3756}
3757
3758static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3759{
3760 CALC_REGADDR();
3761 writeb(value, (void __iomem *)reg_addr);
3762}
3763
3764static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3765{
3766 CALC_REGADDR();
3767 return readw((void __iomem *)reg_addr);
3768}
3769
3770static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3771{
3772 CALC_REGADDR();
3773 writew(value, (void __iomem *)reg_addr);
3774}
3775
3776static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3777{
3778 CALC_REGADDR();
3779 return readl((void __iomem *)reg_addr);
3780}
3781
3782static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3783{
3784 CALC_REGADDR();
3785 writel(value, (void __iomem *)reg_addr);
3786}
3787
3788static void rdma_reset(struct slgt_info *info)
3789{
3790 unsigned int i;
3791
3792 /* set reset bit */
3793 wr_reg32(info, RDCSR, BIT1);
3794
3795 /* wait for enable bit cleared */
3796 for(i=0 ; i < 1000 ; i++)
3797 if (!(rd_reg32(info, RDCSR) & BIT0))
3798 break;
3799}
3800
3801static void tdma_reset(struct slgt_info *info)
3802{
3803 unsigned int i;
3804
3805 /* set reset bit */
3806 wr_reg32(info, TDCSR, BIT1);
3807
3808 /* wait for enable bit cleared */
3809 for(i=0 ; i < 1000 ; i++)
3810 if (!(rd_reg32(info, TDCSR) & BIT0))
3811 break;
3812}
3813
3814/*
3815 * enable internal loopback
3816 * TxCLK and RxCLK are generated from BRG
3817 * and TxD is looped back to RxD internally.
3818 */
3819static void enable_loopback(struct slgt_info *info)
3820{
3821 /* SCR (serial control) BIT2=loopback enable */
3822 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3823
3824 if (info->params.mode != MGSL_MODE_ASYNC) {
3825 /* CCR (clock control)
3826 * 07..05 tx clock source (010 = BRG)
3827 * 04..02 rx clock source (010 = BRG)
3828 * 01 auxclk enable (0 = disable)
3829 * 00 BRG enable (1 = enable)
3830 *
3831 * 0100 1001
3832 */
3833 wr_reg8(info, CCR, 0x49);
3834
3835 /* set speed if available, otherwise use default */
3836 if (info->params.clock_speed)
3837 set_rate(info, info->params.clock_speed);
3838 else
3839 set_rate(info, 3686400);
3840 }
3841}
3842
3843/*
3844 * set baud rate generator to specified rate
3845 */
3846static void set_rate(struct slgt_info *info, u32 rate)
3847{
3848 unsigned int div;
3849 unsigned int osc = info->base_clock;
3850
3851 /* div = osc/rate - 1
3852 *
3853 * Round div up if osc/rate is not integer to
3854 * force to next slowest rate.
3855 */
3856
3857 if (rate) {
3858 div = osc/rate;
3859 if (!(osc % rate) && div)
3860 div--;
3861 wr_reg16(info, BDR, (unsigned short)div);
3862 }
3863}
3864
3865static void rx_stop(struct slgt_info *info)
3866{
3867 unsigned short val;
3868
3869 /* disable and reset receiver */
3870 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3871 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3872 wr_reg16(info, RCR, val); /* clear reset bit */
3873
3874 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3875
3876 /* clear pending rx interrupts */
3877 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3878
3879 rdma_reset(info);
3880
3881 info->rx_enabled = false;
3882 info->rx_restart = false;
3883}
3884
3885static void rx_start(struct slgt_info *info)
3886{
3887 unsigned short val;
3888
3889 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3890
3891 /* clear pending rx overrun IRQ */
3892 wr_reg16(info, SSR, IRQ_RXOVER);
3893
3894 /* reset and disable receiver */
3895 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3896 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3897 wr_reg16(info, RCR, val); /* clear reset bit */
3898
3899 rdma_reset(info);
3900 reset_rbufs(info);
3901
3902 if (info->rx_pio) {
3903 /* rx request when rx FIFO not empty */
3904 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3905 slgt_irq_on(info, IRQ_RXDATA);
3906 if (info->params.mode == MGSL_MODE_ASYNC) {
3907 /* enable saving of rx status */
3908 wr_reg32(info, RDCSR, BIT6);
3909 }
3910 } else {
3911 /* rx request when rx FIFO half full */
3912 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3913 /* set 1st descriptor address */
3914 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3915
3916 if (info->params.mode != MGSL_MODE_ASYNC) {
3917 /* enable rx DMA and DMA interrupt */
3918 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3919 } else {
3920 /* enable saving of rx status, rx DMA and DMA interrupt */
3921 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3922 }
3923 }
3924
3925 slgt_irq_on(info, IRQ_RXOVER);
3926
3927 /* enable receiver */
3928 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3929
3930 info->rx_restart = false;
3931 info->rx_enabled = true;
3932}
3933
3934static void tx_start(struct slgt_info *info)
3935{
3936 if (!info->tx_enabled) {
3937 wr_reg16(info, TCR,
3938 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3939 info->tx_enabled = true;
3940 }
3941
3942 if (desc_count(info->tbufs[info->tbuf_start])) {
3943 info->drop_rts_on_tx_done = false;
3944
3945 if (info->params.mode != MGSL_MODE_ASYNC) {
3946 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3947 get_gtsignals(info);
3948 if (!(info->signals & SerialSignal_RTS)) {
3949 info->signals |= SerialSignal_RTS;
3950 set_gtsignals(info);
3951 info->drop_rts_on_tx_done = true;
3952 }
3953 }
3954
3955 slgt_irq_off(info, IRQ_TXDATA);
3956 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3957 /* clear tx idle and underrun status bits */
3958 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3959 } else {
3960 slgt_irq_off(info, IRQ_TXDATA);
3961 slgt_irq_on(info, IRQ_TXIDLE);
3962 /* clear tx idle status bit */
3963 wr_reg16(info, SSR, IRQ_TXIDLE);
3964 }
3965 /* set 1st descriptor address and start DMA */
3966 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3967 wr_reg32(info, TDCSR, BIT2 + BIT0);
3968 info->tx_active = true;
3969 }
3970}
3971
3972static void tx_stop(struct slgt_info *info)
3973{
3974 unsigned short val;
3975
3976 del_timer(&info->tx_timer);
3977
3978 tdma_reset(info);
3979
3980 /* reset and disable transmitter */
3981 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3982 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3983
3984 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3985
3986 /* clear tx idle and underrun status bit */
3987 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3988
3989 reset_tbufs(info);
3990
3991 info->tx_enabled = false;
3992 info->tx_active = false;
3993}
3994
3995static void reset_port(struct slgt_info *info)
3996{
3997 if (!info->reg_addr)
3998 return;
3999
4000 tx_stop(info);
4001 rx_stop(info);
4002
4003 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4004 set_gtsignals(info);
4005
4006 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4007}
4008
4009static void reset_adapter(struct slgt_info *info)
4010{
4011 int i;
4012 for (i=0; i < info->port_count; ++i) {
4013 if (info->port_array[i])
4014 reset_port(info->port_array[i]);
4015 }
4016}
4017
4018static void async_mode(struct slgt_info *info)
4019{
4020 unsigned short val;
4021
4022 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4023 tx_stop(info);
4024 rx_stop(info);
4025
4026 /* TCR (tx control)
4027 *
4028 * 15..13 mode, 010=async
4029 * 12..10 encoding, 000=NRZ
4030 * 09 parity enable
4031 * 08 1=odd parity, 0=even parity
4032 * 07 1=RTS driver control
4033 * 06 1=break enable
4034 * 05..04 character length
4035 * 00=5 bits
4036 * 01=6 bits
4037 * 10=7 bits
4038 * 11=8 bits
4039 * 03 0=1 stop bit, 1=2 stop bits
4040 * 02 reset
4041 * 01 enable
4042 * 00 auto-CTS enable
4043 */
4044 val = 0x4000;
4045
4046 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4047 val |= BIT7;
4048
4049 if (info->params.parity != ASYNC_PARITY_NONE) {
4050 val |= BIT9;
4051 if (info->params.parity == ASYNC_PARITY_ODD)
4052 val |= BIT8;
4053 }
4054
4055 switch (info->params.data_bits)
4056 {
4057 case 6: val |= BIT4; break;
4058 case 7: val |= BIT5; break;
4059 case 8: val |= BIT5 + BIT4; break;
4060 }
4061
4062 if (info->params.stop_bits != 1)
4063 val |= BIT3;
4064
4065 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4066 val |= BIT0;
4067
4068 wr_reg16(info, TCR, val);
4069
4070 /* RCR (rx control)
4071 *
4072 * 15..13 mode, 010=async
4073 * 12..10 encoding, 000=NRZ
4074 * 09 parity enable
4075 * 08 1=odd parity, 0=even parity
4076 * 07..06 reserved, must be 0
4077 * 05..04 character length
4078 * 00=5 bits
4079 * 01=6 bits
4080 * 10=7 bits
4081 * 11=8 bits
4082 * 03 reserved, must be zero
4083 * 02 reset
4084 * 01 enable
4085 * 00 auto-DCD enable
4086 */
4087 val = 0x4000;
4088
4089 if (info->params.parity != ASYNC_PARITY_NONE) {
4090 val |= BIT9;
4091 if (info->params.parity == ASYNC_PARITY_ODD)
4092 val |= BIT8;
4093 }
4094
4095 switch (info->params.data_bits)
4096 {
4097 case 6: val |= BIT4; break;
4098 case 7: val |= BIT5; break;
4099 case 8: val |= BIT5 + BIT4; break;
4100 }
4101
4102 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4103 val |= BIT0;
4104
4105 wr_reg16(info, RCR, val);
4106
4107 /* CCR (clock control)
4108 *
4109 * 07..05 011 = tx clock source is BRG/16
4110 * 04..02 010 = rx clock source is BRG
4111 * 01 0 = auxclk disabled
4112 * 00 1 = BRG enabled
4113 *
4114 * 0110 1001
4115 */
4116 wr_reg8(info, CCR, 0x69);
4117
4118 msc_set_vcr(info);
4119
4120 /* SCR (serial control)
4121 *
4122 * 15 1=tx req on FIFO half empty
4123 * 14 1=rx req on FIFO half full
4124 * 13 tx data IRQ enable
4125 * 12 tx idle IRQ enable
4126 * 11 rx break on IRQ enable
4127 * 10 rx data IRQ enable
4128 * 09 rx break off IRQ enable
4129 * 08 overrun IRQ enable
4130 * 07 DSR IRQ enable
4131 * 06 CTS IRQ enable
4132 * 05 DCD IRQ enable
4133 * 04 RI IRQ enable
4134 * 03 0=16x sampling, 1=8x sampling
4135 * 02 1=txd->rxd internal loopback enable
4136 * 01 reserved, must be zero
4137 * 00 1=master IRQ enable
4138 */
4139 val = BIT15 + BIT14 + BIT0;
4140 /* JCR[8] : 1 = x8 async mode feature available */
4141 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4142 ((info->base_clock < (info->params.data_rate * 16)) ||
4143 (info->base_clock % (info->params.data_rate * 16)))) {
4144 /* use 8x sampling */
4145 val |= BIT3;
4146 set_rate(info, info->params.data_rate * 8);
4147 } else {
4148 /* use 16x sampling */
4149 set_rate(info, info->params.data_rate * 16);
4150 }
4151 wr_reg16(info, SCR, val);
4152
4153 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4154
4155 if (info->params.loopback)
4156 enable_loopback(info);
4157}
4158
4159static void sync_mode(struct slgt_info *info)
4160{
4161 unsigned short val;
4162
4163 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4164 tx_stop(info);
4165 rx_stop(info);
4166
4167 /* TCR (tx control)
4168 *
4169 * 15..13 mode
4170 * 000=HDLC/SDLC
4171 * 001=raw bit synchronous
4172 * 010=asynchronous/isochronous
4173 * 011=monosync byte synchronous
4174 * 100=bisync byte synchronous
4175 * 101=xsync byte synchronous
4176 * 12..10 encoding
4177 * 09 CRC enable
4178 * 08 CRC32
4179 * 07 1=RTS driver control
4180 * 06 preamble enable
4181 * 05..04 preamble length
4182 * 03 share open/close flag
4183 * 02 reset
4184 * 01 enable
4185 * 00 auto-CTS enable
4186 */
4187 val = BIT2;
4188
4189 switch(info->params.mode) {
4190 case MGSL_MODE_XSYNC:
4191 val |= BIT15 + BIT13;
4192 break;
4193 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4194 case MGSL_MODE_BISYNC: val |= BIT15; break;
4195 case MGSL_MODE_RAW: val |= BIT13; break;
4196 }
4197 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4198 val |= BIT7;
4199
4200 switch(info->params.encoding)
4201 {
4202 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4203 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4204 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4205 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4206 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4207 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4208 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4209 }
4210
4211 switch (info->params.crc_type & HDLC_CRC_MASK)
4212 {
4213 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4214 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4215 }
4216
4217 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4218 val |= BIT6;
4219
4220 switch (info->params.preamble_length)
4221 {
4222 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4223 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4224 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4225 }
4226
4227 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4228 val |= BIT0;
4229
4230 wr_reg16(info, TCR, val);
4231
4232 /* TPR (transmit preamble) */
4233
4234 switch (info->params.preamble)
4235 {
4236 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4237 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4238 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4239 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4240 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4241 default: val = 0x7e; break;
4242 }
4243 wr_reg8(info, TPR, (unsigned char)val);
4244
4245 /* RCR (rx control)
4246 *
4247 * 15..13 mode
4248 * 000=HDLC/SDLC
4249 * 001=raw bit synchronous
4250 * 010=asynchronous/isochronous
4251 * 011=monosync byte synchronous
4252 * 100=bisync byte synchronous
4253 * 101=xsync byte synchronous
4254 * 12..10 encoding
4255 * 09 CRC enable
4256 * 08 CRC32
4257 * 07..03 reserved, must be 0
4258 * 02 reset
4259 * 01 enable
4260 * 00 auto-DCD enable
4261 */
4262 val = 0;
4263
4264 switch(info->params.mode) {
4265 case MGSL_MODE_XSYNC:
4266 val |= BIT15 + BIT13;
4267 break;
4268 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4269 case MGSL_MODE_BISYNC: val |= BIT15; break;
4270 case MGSL_MODE_RAW: val |= BIT13; break;
4271 }
4272
4273 switch(info->params.encoding)
4274 {
4275 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4276 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4277 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4278 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4279 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4280 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4281 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4282 }
4283
4284 switch (info->params.crc_type & HDLC_CRC_MASK)
4285 {
4286 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4287 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4288 }
4289
4290 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4291 val |= BIT0;
4292
4293 wr_reg16(info, RCR, val);
4294
4295 /* CCR (clock control)
4296 *
4297 * 07..05 tx clock source
4298 * 04..02 rx clock source
4299 * 01 auxclk enable
4300 * 00 BRG enable
4301 */
4302 val = 0;
4303
4304 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4305 {
4306 // when RxC source is DPLL, BRG generates 16X DPLL
4307 // reference clock, so take TxC from BRG/16 to get
4308 // transmit clock at actual data rate
4309 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4310 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4311 else
4312 val |= BIT6; /* 010, txclk = BRG */
4313 }
4314 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4315 val |= BIT7; /* 100, txclk = DPLL Input */
4316 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4317 val |= BIT5; /* 001, txclk = RXC Input */
4318
4319 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4320 val |= BIT3; /* 010, rxclk = BRG */
4321 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4322 val |= BIT4; /* 100, rxclk = DPLL */
4323 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4324 val |= BIT2; /* 001, rxclk = TXC Input */
4325
4326 if (info->params.clock_speed)
4327 val |= BIT1 + BIT0;
4328
4329 wr_reg8(info, CCR, (unsigned char)val);
4330
4331 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4332 {
4333 // program DPLL mode
4334 switch(info->params.encoding)
4335 {
4336 case HDLC_ENCODING_BIPHASE_MARK:
4337 case HDLC_ENCODING_BIPHASE_SPACE:
4338 val = BIT7; break;
4339 case HDLC_ENCODING_BIPHASE_LEVEL:
4340 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4341 val = BIT7 + BIT6; break;
4342 default: val = BIT6; // NRZ encodings
4343 }
4344 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4345
4346 // DPLL requires a 16X reference clock from BRG
4347 set_rate(info, info->params.clock_speed * 16);
4348 }
4349 else
4350 set_rate(info, info->params.clock_speed);
4351
4352 tx_set_idle(info);
4353
4354 msc_set_vcr(info);
4355
4356 /* SCR (serial control)
4357 *
4358 * 15 1=tx req on FIFO half empty
4359 * 14 1=rx req on FIFO half full
4360 * 13 tx data IRQ enable
4361 * 12 tx idle IRQ enable
4362 * 11 underrun IRQ enable
4363 * 10 rx data IRQ enable
4364 * 09 rx idle IRQ enable
4365 * 08 overrun IRQ enable
4366 * 07 DSR IRQ enable
4367 * 06 CTS IRQ enable
4368 * 05 DCD IRQ enable
4369 * 04 RI IRQ enable
4370 * 03 reserved, must be zero
4371 * 02 1=txd->rxd internal loopback enable
4372 * 01 reserved, must be zero
4373 * 00 1=master IRQ enable
4374 */
4375 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4376
4377 if (info->params.loopback)
4378 enable_loopback(info);
4379}
4380
4381/*
4382 * set transmit idle mode
4383 */
4384static void tx_set_idle(struct slgt_info *info)
4385{
4386 unsigned char val;
4387 unsigned short tcr;
4388
4389 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4390 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4391 */
4392 tcr = rd_reg16(info, TCR);
4393 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4394 /* disable preamble, set idle size to 16 bits */
4395 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4396 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4397 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4398 } else if (!(tcr & BIT6)) {
4399 /* preamble is disabled, set idle size to 8 bits */
4400 tcr &= ~(BIT5 + BIT4);
4401 }
4402 wr_reg16(info, TCR, tcr);
4403
4404 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4405 /* LSB of custom tx idle specified in tx idle register */
4406 val = (unsigned char)(info->idle_mode & 0xff);
4407 } else {
4408 /* standard 8 bit idle patterns */
4409 switch(info->idle_mode)
4410 {
4411 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4412 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4413 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4414 case HDLC_TXIDLE_ZEROS:
4415 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4416 default: val = 0xff;
4417 }
4418 }
4419
4420 wr_reg8(info, TIR, val);
4421}
4422
4423/*
4424 * get state of V24 status (input) signals
4425 */
4426static void get_gtsignals(struct slgt_info *info)
4427{
4428 unsigned short status = rd_reg16(info, SSR);
4429
4430 /* clear all serial signals except RTS and DTR */
4431 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4432
4433 if (status & BIT3)
4434 info->signals |= SerialSignal_DSR;
4435 if (status & BIT2)
4436 info->signals |= SerialSignal_CTS;
4437 if (status & BIT1)
4438 info->signals |= SerialSignal_DCD;
4439 if (status & BIT0)
4440 info->signals |= SerialSignal_RI;
4441}
4442
4443/*
4444 * set V.24 Control Register based on current configuration
4445 */
4446static void msc_set_vcr(struct slgt_info *info)
4447{
4448 unsigned char val = 0;
4449
4450 /* VCR (V.24 control)
4451 *
4452 * 07..04 serial IF select
4453 * 03 DTR
4454 * 02 RTS
4455 * 01 LL
4456 * 00 RL
4457 */
4458
4459 switch(info->if_mode & MGSL_INTERFACE_MASK)
4460 {
4461 case MGSL_INTERFACE_RS232:
4462 val |= BIT5; /* 0010 */
4463 break;
4464 case MGSL_INTERFACE_V35:
4465 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4466 break;
4467 case MGSL_INTERFACE_RS422:
4468 val |= BIT6; /* 0100 */
4469 break;
4470 }
4471
4472 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4473 val |= BIT4;
4474 if (info->signals & SerialSignal_DTR)
4475 val |= BIT3;
4476 if (info->signals & SerialSignal_RTS)
4477 val |= BIT2;
4478 if (info->if_mode & MGSL_INTERFACE_LL)
4479 val |= BIT1;
4480 if (info->if_mode & MGSL_INTERFACE_RL)
4481 val |= BIT0;
4482 wr_reg8(info, VCR, val);
4483}
4484
4485/*
4486 * set state of V24 control (output) signals
4487 */
4488static void set_gtsignals(struct slgt_info *info)
4489{
4490 unsigned char val = rd_reg8(info, VCR);
4491 if (info->signals & SerialSignal_DTR)
4492 val |= BIT3;
4493 else
4494 val &= ~BIT3;
4495 if (info->signals & SerialSignal_RTS)
4496 val |= BIT2;
4497 else
4498 val &= ~BIT2;
4499 wr_reg8(info, VCR, val);
4500}
4501
4502/*
4503 * free range of receive DMA buffers (i to last)
4504 */
4505static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4506{
4507 int done = 0;
4508
4509 while(!done) {
4510 /* reset current buffer for reuse */
4511 info->rbufs[i].status = 0;
4512 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4513 if (i == last)
4514 done = 1;
4515 if (++i == info->rbuf_count)
4516 i = 0;
4517 }
4518 info->rbuf_current = i;
4519}
4520
4521/*
4522 * mark all receive DMA buffers as free
4523 */
4524static void reset_rbufs(struct slgt_info *info)
4525{
4526 free_rbufs(info, 0, info->rbuf_count - 1);
4527 info->rbuf_fill_index = 0;
4528 info->rbuf_fill_count = 0;
4529}
4530
4531/*
4532 * pass receive HDLC frame to upper layer
4533 *
4534 * return true if frame available, otherwise false
4535 */
4536static bool rx_get_frame(struct slgt_info *info)
4537{
4538 unsigned int start, end;
4539 unsigned short status;
4540 unsigned int framesize = 0;
4541 unsigned long flags;
4542 struct tty_struct *tty = info->port.tty;
4543 unsigned char addr_field = 0xff;
4544 unsigned int crc_size = 0;
4545
4546 switch (info->params.crc_type & HDLC_CRC_MASK) {
4547 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4548 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4549 }
4550
4551check_again:
4552
4553 framesize = 0;
4554 addr_field = 0xff;
4555 start = end = info->rbuf_current;
4556
4557 for (;;) {
4558 if (!desc_complete(info->rbufs[end]))
4559 goto cleanup;
4560
4561 if (framesize == 0 && info->params.addr_filter != 0xff)
4562 addr_field = info->rbufs[end].buf[0];
4563
4564 framesize += desc_count(info->rbufs[end]);
4565
4566 if (desc_eof(info->rbufs[end]))
4567 break;
4568
4569 if (++end == info->rbuf_count)
4570 end = 0;
4571
4572 if (end == info->rbuf_current) {
4573 if (info->rx_enabled){
4574 spin_lock_irqsave(&info->lock,flags);
4575 rx_start(info);
4576 spin_unlock_irqrestore(&info->lock,flags);
4577 }
4578 goto cleanup;
4579 }
4580 }
4581
4582 /* status
4583 *
4584 * 15 buffer complete
4585 * 14..06 reserved
4586 * 05..04 residue
4587 * 02 eof (end of frame)
4588 * 01 CRC error
4589 * 00 abort
4590 */
4591 status = desc_status(info->rbufs[end]);
4592
4593 /* ignore CRC bit if not using CRC (bit is undefined) */
4594 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4595 status &= ~BIT1;
4596
4597 if (framesize == 0 ||
4598 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4599 free_rbufs(info, start, end);
4600 goto check_again;
4601 }
4602
4603 if (framesize < (2 + crc_size) || status & BIT0) {
4604 info->icount.rxshort++;
4605 framesize = 0;
4606 } else if (status & BIT1) {
4607 info->icount.rxcrc++;
4608 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4609 framesize = 0;
4610 }
4611
4612#if SYNCLINK_GENERIC_HDLC
4613 if (framesize == 0) {
4614 info->netdev->stats.rx_errors++;
4615 info->netdev->stats.rx_frame_errors++;
4616 }
4617#endif
4618
4619 DBGBH(("%s rx frame status=%04X size=%d\n",
4620 info->device_name, status, framesize));
4621 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4622
4623 if (framesize) {
4624 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4625 framesize -= crc_size;
4626 crc_size = 0;
4627 }
4628
4629 if (framesize > info->max_frame_size + crc_size)
4630 info->icount.rxlong++;
4631 else {
4632 /* copy dma buffer(s) to contiguous temp buffer */
4633 int copy_count = framesize;
4634 int i = start;
4635 unsigned char *p = info->tmp_rbuf;
4636 info->tmp_rbuf_count = framesize;
4637
4638 info->icount.rxok++;
4639
4640 while(copy_count) {
4641 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4642 memcpy(p, info->rbufs[i].buf, partial_count);
4643 p += partial_count;
4644 copy_count -= partial_count;
4645 if (++i == info->rbuf_count)
4646 i = 0;
4647 }
4648
4649 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4650 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4651 framesize++;
4652 }
4653
4654#if SYNCLINK_GENERIC_HDLC
4655 if (info->netcount)
4656 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4657 else
4658#endif
4659 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4660 }
4661 }
4662 free_rbufs(info, start, end);
4663 return true;
4664
4665cleanup:
4666 return false;
4667}
4668
4669/*
4670 * pass receive buffer (RAW synchronous mode) to tty layer
4671 * return true if buffer available, otherwise false
4672 */
4673static bool rx_get_buf(struct slgt_info *info)
4674{
4675 unsigned int i = info->rbuf_current;
4676 unsigned int count;
4677
4678 if (!desc_complete(info->rbufs[i]))
4679 return false;
4680 count = desc_count(info->rbufs[i]);
4681 switch(info->params.mode) {
4682 case MGSL_MODE_MONOSYNC:
4683 case MGSL_MODE_BISYNC:
4684 case MGSL_MODE_XSYNC:
4685 /* ignore residue in byte synchronous modes */
4686 if (desc_residue(info->rbufs[i]))
4687 count--;
4688 break;
4689 }
4690 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4691 DBGINFO(("rx_get_buf size=%d\n", count));
4692 if (count)
4693 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4694 info->flag_buf, count);
4695 free_rbufs(info, i, i);
4696 return true;
4697}
4698
4699static void reset_tbufs(struct slgt_info *info)
4700{
4701 unsigned int i;
4702 info->tbuf_current = 0;
4703 for (i=0 ; i < info->tbuf_count ; i++) {
4704 info->tbufs[i].status = 0;
4705 info->tbufs[i].count = 0;
4706 }
4707}
4708
4709/*
4710 * return number of free transmit DMA buffers
4711 */
4712static unsigned int free_tbuf_count(struct slgt_info *info)
4713{
4714 unsigned int count = 0;
4715 unsigned int i = info->tbuf_current;
4716
4717 do
4718 {
4719 if (desc_count(info->tbufs[i]))
4720 break; /* buffer in use */
4721 ++count;
4722 if (++i == info->tbuf_count)
4723 i=0;
4724 } while (i != info->tbuf_current);
4725
4726 /* if tx DMA active, last zero count buffer is in use */
4727 if (count && (rd_reg32(info, TDCSR) & BIT0))
4728 --count;
4729
4730 return count;
4731}
4732
4733/*
4734 * return number of bytes in unsent transmit DMA buffers
4735 * and the serial controller tx FIFO
4736 */
4737static unsigned int tbuf_bytes(struct slgt_info *info)
4738{
4739 unsigned int total_count = 0;
4740 unsigned int i = info->tbuf_current;
4741 unsigned int reg_value;
4742 unsigned int count;
4743 unsigned int active_buf_count = 0;
4744
4745 /*
4746 * Add descriptor counts for all tx DMA buffers.
4747 * If count is zero (cleared by DMA controller after read),
4748 * the buffer is complete or is actively being read from.
4749 *
4750 * Record buf_count of last buffer with zero count starting
4751 * from current ring position. buf_count is mirror
4752 * copy of count and is not cleared by serial controller.
4753 * If DMA controller is active, that buffer is actively
4754 * being read so add to total.
4755 */
4756 do {
4757 count = desc_count(info->tbufs[i]);
4758 if (count)
4759 total_count += count;
4760 else if (!total_count)
4761 active_buf_count = info->tbufs[i].buf_count;
4762 if (++i == info->tbuf_count)
4763 i = 0;
4764 } while (i != info->tbuf_current);
4765
4766 /* read tx DMA status register */
4767 reg_value = rd_reg32(info, TDCSR);
4768
4769 /* if tx DMA active, last zero count buffer is in use */
4770 if (reg_value & BIT0)
4771 total_count += active_buf_count;
4772
4773 /* add tx FIFO count = reg_value[15..8] */
4774 total_count += (reg_value >> 8) & 0xff;
4775
4776 /* if transmitter active add one byte for shift register */
4777 if (info->tx_active)
4778 total_count++;
4779
4780 return total_count;
4781}
4782
4783/*
4784 * load data into transmit DMA buffer ring and start transmitter if needed
4785 * return true if data accepted, otherwise false (buffers full)
4786 */
4787static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4788{
4789 unsigned short count;
4790 unsigned int i;
4791 struct slgt_desc *d;
4792
4793 /* check required buffer space */
4794 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4795 return false;
4796
4797 DBGDATA(info, buf, size, "tx");
4798
4799 /*
4800 * copy data to one or more DMA buffers in circular ring
4801 * tbuf_start = first buffer for this data
4802 * tbuf_current = next free buffer
4803 *
4804 * Copy all data before making data visible to DMA controller by
4805 * setting descriptor count of the first buffer.
4806 * This prevents an active DMA controller from reading the first DMA
4807 * buffers of a frame and stopping before the final buffers are filled.
4808 */
4809
4810 info->tbuf_start = i = info->tbuf_current;
4811
4812 while (size) {
4813 d = &info->tbufs[i];
4814
4815 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4816 memcpy(d->buf, buf, count);
4817
4818 size -= count;
4819 buf += count;
4820
4821 /*
4822 * set EOF bit for last buffer of HDLC frame or
4823 * for every buffer in raw mode
4824 */
4825 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4826 info->params.mode == MGSL_MODE_RAW)
4827 set_desc_eof(*d, 1);
4828 else
4829 set_desc_eof(*d, 0);
4830
4831 /* set descriptor count for all but first buffer */
4832 if (i != info->tbuf_start)
4833 set_desc_count(*d, count);
4834 d->buf_count = count;
4835
4836 if (++i == info->tbuf_count)
4837 i = 0;
4838 }
4839
4840 info->tbuf_current = i;
4841
4842 /* set first buffer count to make new data visible to DMA controller */
4843 d = &info->tbufs[info->tbuf_start];
4844 set_desc_count(*d, d->buf_count);
4845
4846 /* start transmitter if needed and update transmit timeout */
4847 if (!info->tx_active)
4848 tx_start(info);
4849 update_tx_timer(info);
4850
4851 return true;
4852}
4853
4854static int register_test(struct slgt_info *info)
4855{
4856 static unsigned short patterns[] =
4857 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4858 static unsigned int count = ARRAY_SIZE(patterns);
4859 unsigned int i;
4860 int rc = 0;
4861
4862 for (i=0 ; i < count ; i++) {
4863 wr_reg16(info, TIR, patterns[i]);
4864 wr_reg16(info, BDR, patterns[(i+1)%count]);
4865 if ((rd_reg16(info, TIR) != patterns[i]) ||
4866 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4867 rc = -ENODEV;
4868 break;
4869 }
4870 }
4871 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4872 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4873 return rc;
4874}
4875
4876static int irq_test(struct slgt_info *info)
4877{
4878 unsigned long timeout;
4879 unsigned long flags;
4880 struct tty_struct *oldtty = info->port.tty;
4881 u32 speed = info->params.data_rate;
4882
4883 info->params.data_rate = 921600;
4884 info->port.tty = NULL;
4885
4886 spin_lock_irqsave(&info->lock, flags);
4887 async_mode(info);
4888 slgt_irq_on(info, IRQ_TXIDLE);
4889
4890 /* enable transmitter */
4891 wr_reg16(info, TCR,
4892 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4893
4894 /* write one byte and wait for tx idle */
4895 wr_reg16(info, TDR, 0);
4896
4897 /* assume failure */
4898 info->init_error = DiagStatus_IrqFailure;
4899 info->irq_occurred = false;
4900
4901 spin_unlock_irqrestore(&info->lock, flags);
4902
4903 timeout=100;
4904 while(timeout-- && !info->irq_occurred)
4905 msleep_interruptible(10);
4906
4907 spin_lock_irqsave(&info->lock,flags);
4908 reset_port(info);
4909 spin_unlock_irqrestore(&info->lock,flags);
4910
4911 info->params.data_rate = speed;
4912 info->port.tty = oldtty;
4913
4914 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4915 return info->irq_occurred ? 0 : -ENODEV;
4916}
4917
4918static int loopback_test_rx(struct slgt_info *info)
4919{
4920 unsigned char *src, *dest;
4921 int count;
4922
4923 if (desc_complete(info->rbufs[0])) {
4924 count = desc_count(info->rbufs[0]);
4925 src = info->rbufs[0].buf;
4926 dest = info->tmp_rbuf;
4927
4928 for( ; count ; count-=2, src+=2) {
4929 /* src=data byte (src+1)=status byte */
4930 if (!(*(src+1) & (BIT9 + BIT8))) {
4931 *dest = *src;
4932 dest++;
4933 info->tmp_rbuf_count++;
4934 }
4935 }
4936 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4937 return 1;
4938 }
4939 return 0;
4940}
4941
4942static int loopback_test(struct slgt_info *info)
4943{
4944#define TESTFRAMESIZE 20
4945
4946 unsigned long timeout;
4947 u16 count;
4948 unsigned char buf[TESTFRAMESIZE];
4949 int rc = -ENODEV;
4950 unsigned long flags;
4951
4952 struct tty_struct *oldtty = info->port.tty;
4953 MGSL_PARAMS params;
4954
4955 memcpy(¶ms, &info->params, sizeof(params));
4956
4957 info->params.mode = MGSL_MODE_ASYNC;
4958 info->params.data_rate = 921600;
4959 info->params.loopback = 1;
4960 info->port.tty = NULL;
4961
4962 /* build and send transmit frame */
4963 for (count = 0; count < TESTFRAMESIZE; ++count)
4964 buf[count] = (unsigned char)count;
4965
4966 info->tmp_rbuf_count = 0;
4967 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4968
4969 /* program hardware for HDLC and enabled receiver */
4970 spin_lock_irqsave(&info->lock,flags);
4971 async_mode(info);
4972 rx_start(info);
4973 tx_load(info, buf, count);
4974 spin_unlock_irqrestore(&info->lock, flags);
4975
4976 /* wait for receive complete */
4977 for (timeout = 100; timeout; --timeout) {
4978 msleep_interruptible(10);
4979 if (loopback_test_rx(info)) {
4980 rc = 0;
4981 break;
4982 }
4983 }
4984
4985 /* verify received frame length and contents */
4986 if (!rc && (info->tmp_rbuf_count != count ||
4987 memcmp(buf, info->tmp_rbuf, count))) {
4988 rc = -ENODEV;
4989 }
4990
4991 spin_lock_irqsave(&info->lock,flags);
4992 reset_adapter(info);
4993 spin_unlock_irqrestore(&info->lock,flags);
4994
4995 memcpy(&info->params, ¶ms, sizeof(info->params));
4996 info->port.tty = oldtty;
4997
4998 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4999 return rc;
5000}
5001
5002static int adapter_test(struct slgt_info *info)
5003{
5004 DBGINFO(("testing %s\n", info->device_name));
5005 if (register_test(info) < 0) {
5006 printk("register test failure %s addr=%08X\n",
5007 info->device_name, info->phys_reg_addr);
5008 } else if (irq_test(info) < 0) {
5009 printk("IRQ test failure %s IRQ=%d\n",
5010 info->device_name, info->irq_level);
5011 } else if (loopback_test(info) < 0) {
5012 printk("loopback test failure %s\n", info->device_name);
5013 }
5014 return info->init_error;
5015}
5016
5017/*
5018 * transmit timeout handler
5019 */
5020static void tx_timeout(struct timer_list *t)
5021{
5022 struct slgt_info *info = from_timer(info, t, tx_timer);
5023 unsigned long flags;
5024
5025 DBGINFO(("%s tx_timeout\n", info->device_name));
5026 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5027 info->icount.txtimeout++;
5028 }
5029 spin_lock_irqsave(&info->lock,flags);
5030 tx_stop(info);
5031 spin_unlock_irqrestore(&info->lock,flags);
5032
5033#if SYNCLINK_GENERIC_HDLC
5034 if (info->netcount)
5035 hdlcdev_tx_done(info);
5036 else
5037#endif
5038 bh_transmit(info);
5039}
5040
5041/*
5042 * receive buffer polling timer
5043 */
5044static void rx_timeout(struct timer_list *t)
5045{
5046 struct slgt_info *info = from_timer(info, t, rx_timer);
5047 unsigned long flags;
5048
5049 DBGINFO(("%s rx_timeout\n", info->device_name));
5050 spin_lock_irqsave(&info->lock, flags);
5051 info->pending_bh |= BH_RECEIVE;
5052 spin_unlock_irqrestore(&info->lock, flags);
5053 bh_handler(&info->task);
5054}
5055