1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
   4 * Author: Jon Ringle <jringle@gridpoint.com>
   5 *
   6 *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
   7 */
   8
   9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11#include <linux/bitops.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/gpio/driver.h>
  16#include <linux/i2c.h>
  17#include <linux/mod_devicetable.h>
  18#include <linux/module.h>
  19#include <linux/property.h>
  20#include <linux/regmap.h>
  21#include <linux/serial_core.h>
  22#include <linux/serial.h>
  23#include <linux/tty.h>
  24#include <linux/tty_flip.h>
  25#include <linux/spi/spi.h>
  26#include <linux/uaccess.h>
  27#include <uapi/linux/sched/types.h>
  28
  29#define SC16IS7XX_NAME			"sc16is7xx"
  30#define SC16IS7XX_MAX_DEVS		8
  31
  32/* SC16IS7XX register definitions */
  33#define SC16IS7XX_RHR_REG		(0x00) /* RX FIFO */
  34#define SC16IS7XX_THR_REG		(0x00) /* TX FIFO */
  35#define SC16IS7XX_IER_REG		(0x01) /* Interrupt enable */
  36#define SC16IS7XX_IIR_REG		(0x02) /* Interrupt Identification */
  37#define SC16IS7XX_FCR_REG		(0x02) /* FIFO control */
  38#define SC16IS7XX_LCR_REG		(0x03) /* Line Control */
  39#define SC16IS7XX_MCR_REG		(0x04) /* Modem Control */
  40#define SC16IS7XX_LSR_REG		(0x05) /* Line Status */
  41#define SC16IS7XX_MSR_REG		(0x06) /* Modem Status */
  42#define SC16IS7XX_SPR_REG		(0x07) /* Scratch Pad */
  43#define SC16IS7XX_TXLVL_REG		(0x08) /* TX FIFO level */
  44#define SC16IS7XX_RXLVL_REG		(0x09) /* RX FIFO level */
  45#define SC16IS7XX_IODIR_REG		(0x0a) /* I/O Direction
  46						* - only on 75x/76x
  47						*/
  48#define SC16IS7XX_IOSTATE_REG		(0x0b) /* I/O State
  49						* - only on 75x/76x
  50						*/
  51#define SC16IS7XX_IOINTENA_REG		(0x0c) /* I/O Interrupt Enable
  52						* - only on 75x/76x
  53						*/
  54#define SC16IS7XX_IOCONTROL_REG		(0x0e) /* I/O Control
  55						* - only on 75x/76x
  56						*/
  57#define SC16IS7XX_EFCR_REG		(0x0f) /* Extra Features Control */
  58
  59/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
  60#define SC16IS7XX_TCR_REG		(0x06) /* Transmit control */
  61#define SC16IS7XX_TLR_REG		(0x07) /* Trigger level */
  62
  63/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
  64#define SC16IS7XX_DLL_REG		(0x00) /* Divisor Latch Low */
  65#define SC16IS7XX_DLH_REG		(0x01) /* Divisor Latch High */
  66
  67/* Enhanced Register set: Only if (LCR == 0xBF) */
  68#define SC16IS7XX_EFR_REG		(0x02) /* Enhanced Features */
  69#define SC16IS7XX_XON1_REG		(0x04) /* Xon1 word */
  70#define SC16IS7XX_XON2_REG		(0x05) /* Xon2 word */
  71#define SC16IS7XX_XOFF1_REG		(0x06) /* Xoff1 word */
  72#define SC16IS7XX_XOFF2_REG		(0x07) /* Xoff2 word */
  73
  74/* IER register bits */
  75#define SC16IS7XX_IER_RDI_BIT		(1 << 0) /* Enable RX data interrupt */
  76#define SC16IS7XX_IER_THRI_BIT		(1 << 1) /* Enable TX holding register
  77						  * interrupt */
  78#define SC16IS7XX_IER_RLSI_BIT		(1 << 2) /* Enable RX line status
  79						  * interrupt */
  80#define SC16IS7XX_IER_MSI_BIT		(1 << 3) /* Enable Modem status
  81						  * interrupt */
  82
  83/* IER register bits - write only if (EFR[4] == 1) */
  84#define SC16IS7XX_IER_SLEEP_BIT		(1 << 4) /* Enable Sleep mode */
  85#define SC16IS7XX_IER_XOFFI_BIT		(1 << 5) /* Enable Xoff interrupt */
  86#define SC16IS7XX_IER_RTSI_BIT		(1 << 6) /* Enable nRTS interrupt */
  87#define SC16IS7XX_IER_CTSI_BIT		(1 << 7) /* Enable nCTS interrupt */
  88
  89/* FCR register bits */
  90#define SC16IS7XX_FCR_FIFO_BIT		(1 << 0) /* Enable FIFO */
  91#define SC16IS7XX_FCR_RXRESET_BIT	(1 << 1) /* Reset RX FIFO */
  92#define SC16IS7XX_FCR_TXRESET_BIT	(1 << 2) /* Reset TX FIFO */
  93#define SC16IS7XX_FCR_RXLVLL_BIT	(1 << 6) /* RX Trigger level LSB */
  94#define SC16IS7XX_FCR_RXLVLH_BIT	(1 << 7) /* RX Trigger level MSB */
  95
  96/* FCR register bits - write only if (EFR[4] == 1) */
  97#define SC16IS7XX_FCR_TXLVLL_BIT	(1 << 4) /* TX Trigger level LSB */
  98#define SC16IS7XX_FCR_TXLVLH_BIT	(1 << 5) /* TX Trigger level MSB */
  99
 100/* IIR register bits */
 101#define SC16IS7XX_IIR_NO_INT_BIT	(1 << 0) /* No interrupts pending */
 102#define SC16IS7XX_IIR_ID_MASK		0x3e     /* Mask for the interrupt ID */
 103#define SC16IS7XX_IIR_THRI_SRC		0x02     /* TX holding register empty */
 104#define SC16IS7XX_IIR_RDI_SRC		0x04     /* RX data interrupt */
 105#define SC16IS7XX_IIR_RLSE_SRC		0x06     /* RX line status error */
 106#define SC16IS7XX_IIR_RTOI_SRC		0x0c     /* RX time-out interrupt */
 107#define SC16IS7XX_IIR_MSI_SRC		0x00     /* Modem status interrupt
 108						  * - only on 75x/76x
 109						  */
 110#define SC16IS7XX_IIR_INPIN_SRC		0x30     /* Input pin change of state
 111						  * - only on 75x/76x
 112						  */
 113#define SC16IS7XX_IIR_XOFFI_SRC		0x10     /* Received Xoff */
 114#define SC16IS7XX_IIR_CTSRTS_SRC	0x20     /* nCTS,nRTS change of state
 115						  * from active (LOW)
 116						  * to inactive (HIGH)
 117						  */
 118/* LCR register bits */
 119#define SC16IS7XX_LCR_LENGTH0_BIT	(1 << 0) /* Word length bit 0 */
 120#define SC16IS7XX_LCR_LENGTH1_BIT	(1 << 1) /* Word length bit 1
 121						  *
 122						  * Word length bits table:
 123						  * 00 -> 5 bit words
 124						  * 01 -> 6 bit words
 125						  * 10 -> 7 bit words
 126						  * 11 -> 8 bit words
 127						  */
 128#define SC16IS7XX_LCR_STOPLEN_BIT	(1 << 2) /* STOP length bit
 129						  *
 130						  * STOP length bit table:
 131						  * 0 -> 1 stop bit
 132						  * 1 -> 1-1.5 stop bits if
 133						  *      word length is 5,
 134						  *      2 stop bits otherwise
 135						  */
 136#define SC16IS7XX_LCR_PARITY_BIT	(1 << 3) /* Parity bit enable */
 137#define SC16IS7XX_LCR_EVENPARITY_BIT	(1 << 4) /* Even parity bit enable */
 138#define SC16IS7XX_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
 139#define SC16IS7XX_LCR_TXBREAK_BIT	(1 << 6) /* TX break enable */
 140#define SC16IS7XX_LCR_DLAB_BIT		(1 << 7) /* Divisor Latch enable */
 141#define SC16IS7XX_LCR_WORD_LEN_5	(0x00)
 142#define SC16IS7XX_LCR_WORD_LEN_6	(0x01)
 143#define SC16IS7XX_LCR_WORD_LEN_7	(0x02)
 144#define SC16IS7XX_LCR_WORD_LEN_8	(0x03)
 145#define SC16IS7XX_LCR_CONF_MODE_A	SC16IS7XX_LCR_DLAB_BIT /* Special
 146								* reg set */
 147#define SC16IS7XX_LCR_CONF_MODE_B	0xBF                   /* Enhanced
 148								* reg set */
 149
 150/* MCR register bits */
 151#define SC16IS7XX_MCR_DTR_BIT		(1 << 0) /* DTR complement
 152						  * - only on 75x/76x
 153						  */
 154#define SC16IS7XX_MCR_RTS_BIT		(1 << 1) /* RTS complement */
 155#define SC16IS7XX_MCR_TCRTLR_BIT	(1 << 2) /* TCR/TLR register enable */
 156#define SC16IS7XX_MCR_LOOP_BIT		(1 << 4) /* Enable loopback test mode */
 157#define SC16IS7XX_MCR_XONANY_BIT	(1 << 5) /* Enable Xon Any
 158						  * - write enabled
 159						  * if (EFR[4] == 1)
 160						  */
 161#define SC16IS7XX_MCR_IRDA_BIT		(1 << 6) /* Enable IrDA mode
 162						  * - write enabled
 163						  * if (EFR[4] == 1)
 164						  */
 165#define SC16IS7XX_MCR_CLKSEL_BIT	(1 << 7) /* Divide clock by 4
 166						  * - write enabled
 167						  * if (EFR[4] == 1)
 168						  */
 169
 170/* LSR register bits */
 171#define SC16IS7XX_LSR_DR_BIT		(1 << 0) /* Receiver data ready */
 172#define SC16IS7XX_LSR_OE_BIT		(1 << 1) /* Overrun Error */
 173#define SC16IS7XX_LSR_PE_BIT		(1 << 2) /* Parity Error */
 174#define SC16IS7XX_LSR_FE_BIT		(1 << 3) /* Frame Error */
 175#define SC16IS7XX_LSR_BI_BIT		(1 << 4) /* Break Interrupt */
 176#define SC16IS7XX_LSR_BRK_ERROR_MASK	0x1E     /* BI, FE, PE, OE bits */
 177#define SC16IS7XX_LSR_THRE_BIT		(1 << 5) /* TX holding register empty */
 178#define SC16IS7XX_LSR_TEMT_BIT		(1 << 6) /* Transmitter empty */
 179#define SC16IS7XX_LSR_FIFOE_BIT		(1 << 7) /* Fifo Error */
 180
 181/* MSR register bits */
 182#define SC16IS7XX_MSR_DCTS_BIT		(1 << 0) /* Delta CTS Clear To Send */
 183#define SC16IS7XX_MSR_DDSR_BIT		(1 << 1) /* Delta DSR Data Set Ready
 184						  * or (IO4)
 185						  * - only on 75x/76x
 186						  */
 187#define SC16IS7XX_MSR_DRI_BIT		(1 << 2) /* Delta RI Ring Indicator
 188						  * or (IO7)
 189						  * - only on 75x/76x
 190						  */
 191#define SC16IS7XX_MSR_DCD_BIT		(1 << 3) /* Delta CD Carrier Detect
 192						  * or (IO6)
 193						  * - only on 75x/76x
 194						  */
 195#define SC16IS7XX_MSR_CTS_BIT		(1 << 4) /* CTS */
 196#define SC16IS7XX_MSR_DSR_BIT		(1 << 5) /* DSR (IO4)
 197						  * - only on 75x/76x
 198						  */
 199#define SC16IS7XX_MSR_RI_BIT		(1 << 6) /* RI (IO7)
 200						  * - only on 75x/76x
 201						  */
 202#define SC16IS7XX_MSR_CD_BIT		(1 << 7) /* CD (IO6)
 203						  * - only on 75x/76x
 204						  */
 205#define SC16IS7XX_MSR_DELTA_MASK	0x0F     /* Any of the delta bits! */
 206
 207/*
 208 * TCR register bits
 209 * TCR trigger levels are available from 0 to 60 characters with a granularity
 210 * of four.
 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
 212 * no built-in hardware check to make sure this condition is met. Also, the TCR
 213 * must be programmed with this condition before auto RTS or software flow
 214 * control is enabled to avoid spurious operation of the device.
 215 */
 216#define SC16IS7XX_TCR_RX_HALT(words)	((((words) / 4) & 0x0f) << 0)
 217#define SC16IS7XX_TCR_RX_RESUME(words)	((((words) / 4) & 0x0f) << 4)
 218
 219/*
 220 * TLR register bits
 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
 223 * trigger levels. Trigger levels from 4 characters to 60 characters are
 224 * available with a granularity of four.
 225 *
 226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
 228 * the trigger level defined in FCR is discarded. This applies to both transmit
 229 * FIFO and receive FIFO trigger level setting.
 230 *
 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
 232 * default state, that is, '00'.
 233 */
 234#define SC16IS7XX_TLR_TX_TRIGGER(words)	((((words) / 4) & 0x0f) << 0)
 235#define SC16IS7XX_TLR_RX_TRIGGER(words)	((((words) / 4) & 0x0f) << 4)
 236
 237/* IOControl register bits (Only 750/760) */
 238#define SC16IS7XX_IOCONTROL_LATCH_BIT	(1 << 0) /* Enable input latching */
 239#define SC16IS7XX_IOCONTROL_MODEM_BIT	(1 << 1) /* Enable GPIO[7:4] as modem pins */
 240#define SC16IS7XX_IOCONTROL_SRESET_BIT	(1 << 3) /* Software Reset */
 241
 242/* EFCR register bits */
 243#define SC16IS7XX_EFCR_9BIT_MODE_BIT	(1 << 0) /* Enable 9-bit or Multidrop
 244						  * mode (RS485) */
 245#define SC16IS7XX_EFCR_RXDISABLE_BIT	(1 << 1) /* Disable receiver */
 246#define SC16IS7XX_EFCR_TXDISABLE_BIT	(1 << 2) /* Disable transmitter */
 247#define SC16IS7XX_EFCR_AUTO_RS485_BIT	(1 << 4) /* Auto RS485 RTS direction */
 248#define SC16IS7XX_EFCR_RTS_INVERT_BIT	(1 << 5) /* RTS output inversion */
 249#define SC16IS7XX_EFCR_IRDA_MODE_BIT	(1 << 7) /* IrDA mode
 250						  * 0 = rate upto 115.2 kbit/s
 251						  *   - Only 750/760
 252						  * 1 = rate upto 1.152 Mbit/s
 253						  *   - Only 760
 254						  */
 255
 256/* EFR register bits */
 257#define SC16IS7XX_EFR_AUTORTS_BIT	(1 << 6) /* Auto RTS flow ctrl enable */
 258#define SC16IS7XX_EFR_AUTOCTS_BIT	(1 << 7) /* Auto CTS flow ctrl enable */
 259#define SC16IS7XX_EFR_XOFF2_DETECT_BIT	(1 << 5) /* Enable Xoff2 detection */
 260#define SC16IS7XX_EFR_ENABLE_BIT	(1 << 4) /* Enable enhanced functions
 261						  * and writing to IER[7:4],
 262						  * FCR[5:4], MCR[7:5]
 263						  */
 264#define SC16IS7XX_EFR_SWFLOW3_BIT	(1 << 3) /* SWFLOW bit 3 */
 265#define SC16IS7XX_EFR_SWFLOW2_BIT	(1 << 2) /* SWFLOW bit 2
 266						  *
 267						  * SWFLOW bits 3 & 2 table:
 268						  * 00 -> no transmitter flow
 269						  *       control
 270						  * 01 -> transmitter generates
 271						  *       XON2 and XOFF2
 272						  * 10 -> transmitter generates
 273						  *       XON1 and XOFF1
 274						  * 11 -> transmitter generates
 275						  *       XON1, XON2, XOFF1 and
 276						  *       XOFF2
 277						  */
 278#define SC16IS7XX_EFR_SWFLOW1_BIT	(1 << 1) /* SWFLOW bit 2 */
 279#define SC16IS7XX_EFR_SWFLOW0_BIT	(1 << 0) /* SWFLOW bit 3
 280						  *
 281						  * SWFLOW bits 3 & 2 table:
 282						  * 00 -> no received flow
 283						  *       control
 284						  * 01 -> receiver compares
 285						  *       XON2 and XOFF2
 286						  * 10 -> receiver compares
 287						  *       XON1 and XOFF1
 288						  * 11 -> receiver compares
 289						  *       XON1, XON2, XOFF1 and
 290						  *       XOFF2
 291						  */
 
 
 
 
 
 
 
 
 292
 293/* Misc definitions */
 294#define SC16IS7XX_FIFO_SIZE		(64)
 295#define SC16IS7XX_REG_SHIFT		2
 296
 297struct sc16is7xx_devtype {
 298	char	name[10];
 299	int	nr_gpio;
 300	int	nr_uart;
 
 301};
 302
 303#define SC16IS7XX_RECONF_MD		(1 << 0)
 304#define SC16IS7XX_RECONF_IER		(1 << 1)
 305#define SC16IS7XX_RECONF_RS485		(1 << 2)
 306
 307struct sc16is7xx_one_config {
 308	unsigned int			flags;
 309	u8				ier_clear;
 
 310};
 311
 312struct sc16is7xx_one {
 313	struct uart_port		port;
 314	u8				line;
 315	struct kthread_work		tx_work;
 316	struct kthread_work		reg_work;
 
 317	struct sc16is7xx_one_config	config;
 
 
 318};
 319
 320struct sc16is7xx_port {
 321	const struct sc16is7xx_devtype	*devtype;
 322	struct regmap			*regmap;
 323	struct clk			*clk;
 324#ifdef CONFIG_GPIOLIB
 325	struct gpio_chip		gpio;
 326#endif
 327	unsigned char			buf[SC16IS7XX_FIFO_SIZE];
 328	struct kthread_worker		kworker;
 329	struct task_struct		*kworker_task;
 330	struct kthread_work		irq_work;
 331	struct mutex			efr_lock;
 332	struct sc16is7xx_one		p[0];
 333};
 334
 335static unsigned long sc16is7xx_lines;
 336
 337static struct uart_driver sc16is7xx_uart = {
 338	.owner		= THIS_MODULE,
 339	.dev_name	= "ttySC",
 340	.nr		= SC16IS7XX_MAX_DEVS,
 341};
 342
 
 
 
 343#define to_sc16is7xx_port(p,e)	((container_of((p), struct sc16is7xx_port, e)))
 344#define to_sc16is7xx_one(p,e)	((container_of((p), struct sc16is7xx_one, e)))
 345
 346static int sc16is7xx_line(struct uart_port *port)
 347{
 348	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 349
 350	return one->line;
 351}
 352
 353static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
 354{
 355	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 356	unsigned int val = 0;
 357	const u8 line = sc16is7xx_line(port);
 358
 359	regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
 360
 361	return val;
 362}
 363
 364static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
 365{
 366	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 367	const u8 line = sc16is7xx_line(port);
 368
 369	regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
 370}
 371
 372static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
 373{
 374	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 375	const u8 line = sc16is7xx_line(port);
 376	u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
 377
 378	regcache_cache_bypass(s->regmap, true);
 379	regmap_raw_read(s->regmap, addr, s->buf, rxlen);
 380	regcache_cache_bypass(s->regmap, false);
 381}
 382
 383static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
 384{
 385	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 386	const u8 line = sc16is7xx_line(port);
 387	u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
 388
 389	/*
 390	 * Don't send zero-length data, at least on SPI it confuses the chip
 391	 * delivering wrong TXLVL data.
 392	 */
 393	if (unlikely(!to_send))
 394		return;
 395
 396	regcache_cache_bypass(s->regmap, true);
 397	regmap_raw_write(s->regmap, addr, s->buf, to_send);
 398	regcache_cache_bypass(s->regmap, false);
 399}
 400
 401static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
 402				  u8 mask, u8 val)
 403{
 404	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 405	const u8 line = sc16is7xx_line(port);
 406
 407	regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
 408			   mask, val);
 409}
 410
 411static int sc16is7xx_alloc_line(void)
 412{
 413	int i;
 414
 415	BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
 416
 417	for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
 418		if (!test_and_set_bit(i, &sc16is7xx_lines))
 419			break;
 420
 421	return i;
 422}
 423
 424static void sc16is7xx_power(struct uart_port *port, int on)
 425{
 426	sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
 427			      SC16IS7XX_IER_SLEEP_BIT,
 428			      on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
 429}
 430
 431static const struct sc16is7xx_devtype sc16is74x_devtype = {
 432	.name		= "SC16IS74X",
 433	.nr_gpio	= 0,
 434	.nr_uart	= 1,
 
 435};
 436
 437static const struct sc16is7xx_devtype sc16is750_devtype = {
 438	.name		= "SC16IS750",
 439	.nr_gpio	= 8,
 440	.nr_uart	= 1,
 
 441};
 442
 443static const struct sc16is7xx_devtype sc16is752_devtype = {
 444	.name		= "SC16IS752",
 445	.nr_gpio	= 8,
 446	.nr_uart	= 2,
 
 447};
 448
 449static const struct sc16is7xx_devtype sc16is760_devtype = {
 450	.name		= "SC16IS760",
 451	.nr_gpio	= 8,
 452	.nr_uart	= 1,
 
 453};
 454
 455static const struct sc16is7xx_devtype sc16is762_devtype = {
 456	.name		= "SC16IS762",
 457	.nr_gpio	= 8,
 458	.nr_uart	= 2,
 
 459};
 460
 461static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
 462{
 463	switch (reg >> SC16IS7XX_REG_SHIFT) {
 464	case SC16IS7XX_RHR_REG:
 465	case SC16IS7XX_IIR_REG:
 466	case SC16IS7XX_LSR_REG:
 467	case SC16IS7XX_MSR_REG:
 468	case SC16IS7XX_TXLVL_REG:
 469	case SC16IS7XX_RXLVL_REG:
 470	case SC16IS7XX_IOSTATE_REG:
 471		return true;
 472	default:
 473		break;
 474	}
 475
 476	return false;
 477}
 478
 479static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
 480{
 481	switch (reg >> SC16IS7XX_REG_SHIFT) {
 482	case SC16IS7XX_RHR_REG:
 483		return true;
 484	default:
 485		break;
 486	}
 487
 488	return false;
 489}
 490
 491static int sc16is7xx_set_baud(struct uart_port *port, int baud)
 492{
 493	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 494	u8 lcr;
 495	u8 prescaler = 0;
 496	unsigned long clk = port->uartclk, div = clk / 16 / baud;
 497
 498	if (div > 0xffff) {
 499		prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
 500		div /= 4;
 501	}
 502
 503	/* In an amazing feat of design, the Enhanced Features Register shares
 504	 * the address of the Interrupt Identification Register, and is
 505	 * switched in by writing a magic value (0xbf) to the Line Control
 506	 * Register. Any interrupt firing during this time will see the EFR
 507	 * where it expects the IIR to be, leading to "Unexpected interrupt"
 508	 * messages.
 509	 *
 510	 * Prevent this possibility by claiming a mutex while accessing the
 511	 * EFR, and claiming the same mutex from within the interrupt handler.
 512	 * This is similar to disabling the interrupt, but that doesn't work
 513	 * because the bulk of the interrupt processing is run as a workqueue
 514	 * job in thread context.
 515	 */
 516	mutex_lock(&s->efr_lock);
 517
 518	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
 519
 520	/* Open the LCR divisors for configuration */
 521	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
 522			     SC16IS7XX_LCR_CONF_MODE_B);
 523
 524	/* Enable enhanced features */
 525	regcache_cache_bypass(s->regmap, true);
 526	sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
 527			     SC16IS7XX_EFR_ENABLE_BIT);
 
 
 528	regcache_cache_bypass(s->regmap, false);
 529
 530	/* Put LCR back to the normal mode */
 531	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
 532
 533	mutex_unlock(&s->efr_lock);
 534
 535	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
 536			      SC16IS7XX_MCR_CLKSEL_BIT,
 537			      prescaler);
 538
 539	/* Open the LCR divisors for configuration */
 540	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
 541			     SC16IS7XX_LCR_CONF_MODE_A);
 542
 543	/* Write the new divisor */
 544	regcache_cache_bypass(s->regmap, true);
 545	sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
 546	sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
 547	regcache_cache_bypass(s->regmap, false);
 548
 549	/* Put LCR back to the normal mode */
 550	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
 551
 552	return DIV_ROUND_CLOSEST(clk / 16, div);
 553}
 554
 555static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
 556				unsigned int iir)
 557{
 558	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 559	unsigned int lsr = 0, ch, flag, bytes_read, i;
 560	bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
 561
 562	if (unlikely(rxlen >= sizeof(s->buf))) {
 563		dev_warn_ratelimited(port->dev,
 564				     "ttySC%i: Possible RX FIFO overrun: %d\n",
 565				     port->line, rxlen);
 566		port->icount.buf_overrun++;
 567		/* Ensure sanity of RX level */
 568		rxlen = sizeof(s->buf);
 569	}
 570
 571	while (rxlen) {
 572		/* Only read lsr if there are possible errors in FIFO */
 573		if (read_lsr) {
 574			lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
 575			if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
 576				read_lsr = false; /* No errors left in FIFO */
 577		} else
 578			lsr = 0;
 579
 580		if (read_lsr) {
 581			s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
 582			bytes_read = 1;
 583		} else {
 584			sc16is7xx_fifo_read(port, rxlen);
 585			bytes_read = rxlen;
 586		}
 587
 588		lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
 589
 590		port->icount.rx++;
 591		flag = TTY_NORMAL;
 592
 593		if (unlikely(lsr)) {
 594			if (lsr & SC16IS7XX_LSR_BI_BIT) {
 595				port->icount.brk++;
 596				if (uart_handle_break(port))
 597					continue;
 598			} else if (lsr & SC16IS7XX_LSR_PE_BIT)
 599				port->icount.parity++;
 600			else if (lsr & SC16IS7XX_LSR_FE_BIT)
 601				port->icount.frame++;
 602			else if (lsr & SC16IS7XX_LSR_OE_BIT)
 603				port->icount.overrun++;
 604
 605			lsr &= port->read_status_mask;
 606			if (lsr & SC16IS7XX_LSR_BI_BIT)
 607				flag = TTY_BREAK;
 608			else if (lsr & SC16IS7XX_LSR_PE_BIT)
 609				flag = TTY_PARITY;
 610			else if (lsr & SC16IS7XX_LSR_FE_BIT)
 611				flag = TTY_FRAME;
 612			else if (lsr & SC16IS7XX_LSR_OE_BIT)
 613				flag = TTY_OVERRUN;
 614		}
 615
 616		for (i = 0; i < bytes_read; ++i) {
 617			ch = s->buf[i];
 618			if (uart_handle_sysrq_char(port, ch))
 619				continue;
 620
 621			if (lsr & port->ignore_status_mask)
 622				continue;
 623
 624			uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
 625					 flag);
 626		}
 627		rxlen -= bytes_read;
 628	}
 629
 630	tty_flip_buffer_push(&port->state->port);
 631}
 632
 633static void sc16is7xx_handle_tx(struct uart_port *port)
 634{
 635	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 636	struct circ_buf *xmit = &port->state->xmit;
 637	unsigned int txlen, to_send, i;
 
 638
 639	if (unlikely(port->x_char)) {
 640		sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
 641		port->icount.tx++;
 642		port->x_char = 0;
 643		return;
 644	}
 645
 646	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 
 
 
 647		return;
 
 648
 649	/* Get length of data pending in circular buffer */
 650	to_send = uart_circ_chars_pending(xmit);
 651	if (likely(to_send)) {
 652		/* Limit to size of TX FIFO */
 653		txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
 654		if (txlen > SC16IS7XX_FIFO_SIZE) {
 655			dev_err_ratelimited(port->dev,
 656				"chip reports %d free bytes in TX fifo, but it only has %d",
 657				txlen, SC16IS7XX_FIFO_SIZE);
 658			txlen = 0;
 659		}
 660		to_send = (to_send > txlen) ? txlen : to_send;
 661
 662		/* Add data to send */
 663		port->icount.tx += to_send;
 664
 665		/* Convert to linear buffer */
 666		for (i = 0; i < to_send; ++i) {
 667			s->buf[i] = xmit->buf[xmit->tail];
 668			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 669		}
 670
 671		sc16is7xx_fifo_write(port, to_send);
 672	}
 673
 
 674	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 675		uart_write_wakeup(port);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 676}
 677
 678static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
 679{
 680	struct uart_port *port = &s->p[portno].port;
 681
 682	do {
 683		unsigned int iir, rxlen;
 
 684
 685		iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
 686		if (iir & SC16IS7XX_IIR_NO_INT_BIT)
 687			return false;
 688
 689		iir &= SC16IS7XX_IIR_ID_MASK;
 690
 691		switch (iir) {
 692		case SC16IS7XX_IIR_RDI_SRC:
 693		case SC16IS7XX_IIR_RLSE_SRC:
 694		case SC16IS7XX_IIR_RTOI_SRC:
 695		case SC16IS7XX_IIR_XOFFI_SRC:
 696			rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
 697			if (rxlen)
 698				sc16is7xx_handle_rx(port, rxlen, iir);
 699			break;
 
 
 
 
 
 700		case SC16IS7XX_IIR_THRI_SRC:
 701			sc16is7xx_handle_tx(port);
 702			break;
 703		default:
 704			dev_err_ratelimited(port->dev,
 705					    "ttySC%i: Unexpected interrupt: %x",
 706					    port->line, iir);
 707			break;
 708		}
 709	} while (0);
 710	return true;
 711}
 712
 713static void sc16is7xx_ist(struct kthread_work *ws)
 714{
 715	struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
 716
 717	mutex_lock(&s->efr_lock);
 718
 719	while (1) {
 720		bool keep_polling = false;
 721		int i;
 722
 723		for (i = 0; i < s->devtype->nr_uart; ++i)
 724			keep_polling |= sc16is7xx_port_irq(s, i);
 725		if (!keep_polling)
 726			break;
 727	}
 728
 729	mutex_unlock(&s->efr_lock);
 730}
 731
 732static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
 733{
 734	struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
 735
 736	kthread_queue_work(&s->kworker, &s->irq_work);
 737
 738	return IRQ_HANDLED;
 739}
 740
 741static void sc16is7xx_tx_proc(struct kthread_work *ws)
 742{
 743	struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
 
 
 744
 745	if ((port->rs485.flags & SER_RS485_ENABLED) &&
 746	    (port->rs485.delay_rts_before_send > 0))
 747		msleep(port->rs485.delay_rts_before_send);
 748
 
 749	sc16is7xx_handle_tx(port);
 
 
 
 
 
 750}
 751
 752static void sc16is7xx_reconf_rs485(struct uart_port *port)
 753{
 754	const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
 755			 SC16IS7XX_EFCR_RTS_INVERT_BIT;
 756	u32 efcr = 0;
 757	struct serial_rs485 *rs485 = &port->rs485;
 758	unsigned long irqflags;
 759
 760	spin_lock_irqsave(&port->lock, irqflags);
 761	if (rs485->flags & SER_RS485_ENABLED) {
 762		efcr |=	SC16IS7XX_EFCR_AUTO_RS485_BIT;
 763
 764		if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
 765			efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
 766	}
 767	spin_unlock_irqrestore(&port->lock, irqflags);
 768
 769	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
 770}
 771
 772static void sc16is7xx_reg_proc(struct kthread_work *ws)
 773{
 774	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
 775	struct sc16is7xx_one_config config;
 776	unsigned long irqflags;
 777
 778	spin_lock_irqsave(&one->port.lock, irqflags);
 779	config = one->config;
 780	memset(&one->config, 0, sizeof(one->config));
 781	spin_unlock_irqrestore(&one->port.lock, irqflags);
 782
 783	if (config.flags & SC16IS7XX_RECONF_MD) {
 
 
 
 
 
 
 
 
 
 
 
 784		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
 
 
 785				      SC16IS7XX_MCR_LOOP_BIT,
 786				      (one->port.mctrl & TIOCM_LOOP) ?
 787				      SC16IS7XX_MCR_LOOP_BIT : 0);
 788		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
 789				      SC16IS7XX_MCR_RTS_BIT,
 790				      (one->port.mctrl & TIOCM_RTS) ?
 791				      SC16IS7XX_MCR_RTS_BIT : 0);
 792		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
 793				      SC16IS7XX_MCR_DTR_BIT,
 794				      (one->port.mctrl & TIOCM_DTR) ?
 795				      SC16IS7XX_MCR_DTR_BIT : 0);
 796	}
 
 797	if (config.flags & SC16IS7XX_RECONF_IER)
 798		sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
 799				      config.ier_clear, 0);
 800
 801	if (config.flags & SC16IS7XX_RECONF_RS485)
 802		sc16is7xx_reconf_rs485(&one->port);
 803}
 804
 805static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
 806{
 807	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 808	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 809
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 810	one->config.flags |= SC16IS7XX_RECONF_IER;
 811	one->config.ier_clear |= bit;
 
 812	kthread_queue_work(&s->kworker, &one->reg_work);
 813}
 814
 815static void sc16is7xx_stop_tx(struct uart_port *port)
 816{
 817	sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
 818}
 819
 820static void sc16is7xx_stop_rx(struct uart_port *port)
 821{
 822	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
 823}
 824
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 825static void sc16is7xx_start_tx(struct uart_port *port)
 826{
 827	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 828	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 829
 830	kthread_queue_work(&s->kworker, &one->tx_work);
 831}
 832
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 833static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
 834{
 835	unsigned int lsr;
 836
 837	lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
 838
 839	return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
 840}
 841
 842static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
 843{
 844	/* DCD and DSR are not wired and CTS/RTS is handled automatically
 845	 * so just indicate DSR and CAR asserted
 846	 */
 847	return TIOCM_DSR | TIOCM_CAR;
 848}
 849
 850static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 851{
 852	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 853	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 854
 855	one->config.flags |= SC16IS7XX_RECONF_MD;
 856	kthread_queue_work(&s->kworker, &one->reg_work);
 857}
 858
 859static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
 860{
 861	sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
 862			      SC16IS7XX_LCR_TXBREAK_BIT,
 863			      break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
 864}
 865
 866static void sc16is7xx_set_termios(struct uart_port *port,
 867				  struct ktermios *termios,
 868				  struct ktermios *old)
 869{
 870	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 
 871	unsigned int lcr, flow = 0;
 872	int baud;
 
 
 
 873
 874	/* Mask termios capabilities we don't support */
 875	termios->c_cflag &= ~CMSPAR;
 876
 877	/* Word size */
 878	switch (termios->c_cflag & CSIZE) {
 879	case CS5:
 880		lcr = SC16IS7XX_LCR_WORD_LEN_5;
 881		break;
 882	case CS6:
 883		lcr = SC16IS7XX_LCR_WORD_LEN_6;
 884		break;
 885	case CS7:
 886		lcr = SC16IS7XX_LCR_WORD_LEN_7;
 887		break;
 888	case CS8:
 889		lcr = SC16IS7XX_LCR_WORD_LEN_8;
 890		break;
 891	default:
 892		lcr = SC16IS7XX_LCR_WORD_LEN_8;
 893		termios->c_cflag &= ~CSIZE;
 894		termios->c_cflag |= CS8;
 895		break;
 896	}
 897
 898	/* Parity */
 899	if (termios->c_cflag & PARENB) {
 900		lcr |= SC16IS7XX_LCR_PARITY_BIT;
 901		if (!(termios->c_cflag & PARODD))
 902			lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
 903	}
 904
 905	/* Stop bits */
 906	if (termios->c_cflag & CSTOPB)
 907		lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
 908
 909	/* Set read status mask */
 910	port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
 911	if (termios->c_iflag & INPCK)
 912		port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
 913					  SC16IS7XX_LSR_FE_BIT;
 914	if (termios->c_iflag & (BRKINT | PARMRK))
 915		port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
 916
 917	/* Set status ignore mask */
 918	port->ignore_status_mask = 0;
 919	if (termios->c_iflag & IGNBRK)
 920		port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
 921	if (!(termios->c_cflag & CREAD))
 922		port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
 923
 924	/* As above, claim the mutex while accessing the EFR. */
 925	mutex_lock(&s->efr_lock);
 926
 927	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
 928			     SC16IS7XX_LCR_CONF_MODE_B);
 929
 930	/* Configure flow control */
 931	regcache_cache_bypass(s->regmap, true);
 932	sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
 933	sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
 934	if (termios->c_cflag & CRTSCTS)
 
 
 935		flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
 936			SC16IS7XX_EFR_AUTORTS_BIT;
 
 
 937	if (termios->c_iflag & IXON)
 938		flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
 939	if (termios->c_iflag & IXOFF)
 940		flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
 941
 942	sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
 
 
 
 943	regcache_cache_bypass(s->regmap, false);
 944
 945	/* Update LCR register */
 946	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
 947
 948	mutex_unlock(&s->efr_lock);
 949
 950	/* Get baud rate generator configuration */
 951	baud = uart_get_baud_rate(port, termios, old,
 952				  port->uartclk / 16 / 4 / 0xffff,
 953				  port->uartclk / 16);
 954
 955	/* Setup baudrate generator */
 956	baud = sc16is7xx_set_baud(port, baud);
 957
 
 
 958	/* Update timeout according to new baud rate */
 959	uart_update_timeout(port, termios->c_cflag, baud);
 
 
 
 
 
 960}
 961
 962static int sc16is7xx_config_rs485(struct uart_port *port,
 963				  struct serial_rs485 *rs485)
 964{
 965	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 966	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 967
 968	if (rs485->flags & SER_RS485_ENABLED) {
 969		bool rts_during_rx, rts_during_tx;
 970
 971		rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
 972		rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
 973
 974		if (rts_during_rx == rts_during_tx)
 975			dev_err(port->dev,
 976				"unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
 977				rts_during_tx, rts_during_rx);
 978
 979		/*
 980		 * RTS signal is handled by HW, it's timing can't be influenced.
 981		 * However, it's sometimes useful to delay TX even without RTS
 982		 * control therefore we try to handle .delay_rts_before_send.
 983		 */
 984		if (rs485->delay_rts_after_send)
 985			return -EINVAL;
 986	}
 987
 988	port->rs485 = *rs485;
 989	one->config.flags |= SC16IS7XX_RECONF_RS485;
 990	kthread_queue_work(&s->kworker, &one->reg_work);
 991
 992	return 0;
 993}
 994
 995static int sc16is7xx_startup(struct uart_port *port)
 996{
 
 997	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 998	unsigned int val;
 
 999
1000	sc16is7xx_power(port, 1);
1001
1002	/* Reset FIFOs*/
1003	val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1004	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1005	udelay(5);
1006	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1007			     SC16IS7XX_FCR_FIFO_BIT);
1008
1009	/* Enable EFR */
1010	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1011			     SC16IS7XX_LCR_CONF_MODE_B);
1012
1013	regcache_cache_bypass(s->regmap, true);
1014
1015	/* Enable write access to enhanced features and internal clock div */
1016	sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1017			     SC16IS7XX_EFR_ENABLE_BIT);
 
1018
1019	/* Enable TCR/TLR */
1020	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1021			      SC16IS7XX_MCR_TCRTLR_BIT,
1022			      SC16IS7XX_MCR_TCRTLR_BIT);
1023
1024	/* Configure flow control levels */
1025	/* Flow control halt level 48, resume level 24 */
1026	sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1027			     SC16IS7XX_TCR_RX_RESUME(24) |
1028			     SC16IS7XX_TCR_RX_HALT(48));
1029
1030	regcache_cache_bypass(s->regmap, false);
1031
1032	/* Now, initialize the UART */
1033	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1034
 
 
 
 
 
 
 
1035	/* Enable the Rx and Tx FIFO */
1036	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1037			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1038			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1039			      0);
1040
1041	/* Enable RX, TX interrupts */
1042	val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
 
1043	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1044
 
 
 
 
 
1045	return 0;
1046}
1047
1048static void sc16is7xx_shutdown(struct uart_port *port)
1049{
1050	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 
 
 
1051
1052	/* Disable all interrupts */
1053	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1054	/* Disable TX/RX */
1055	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1056			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1057			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1058			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1059			      SC16IS7XX_EFCR_TXDISABLE_BIT);
1060
1061	sc16is7xx_power(port, 0);
1062
1063	kthread_flush_worker(&s->kworker);
1064}
1065
1066static const char *sc16is7xx_type(struct uart_port *port)
1067{
1068	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1069
1070	return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1071}
1072
1073static int sc16is7xx_request_port(struct uart_port *port)
1074{
1075	/* Do nothing */
1076	return 0;
1077}
1078
1079static void sc16is7xx_config_port(struct uart_port *port, int flags)
1080{
1081	if (flags & UART_CONFIG_TYPE)
1082		port->type = PORT_SC16IS7XX;
1083}
1084
1085static int sc16is7xx_verify_port(struct uart_port *port,
1086				 struct serial_struct *s)
1087{
1088	if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1089		return -EINVAL;
1090	if (s->irq != port->irq)
1091		return -EINVAL;
1092
1093	return 0;
1094}
1095
1096static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1097			 unsigned int oldstate)
1098{
1099	sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1100}
1101
1102static void sc16is7xx_null_void(struct uart_port *port)
1103{
1104	/* Do nothing */
1105}
1106
1107static const struct uart_ops sc16is7xx_ops = {
1108	.tx_empty	= sc16is7xx_tx_empty,
1109	.set_mctrl	= sc16is7xx_set_mctrl,
1110	.get_mctrl	= sc16is7xx_get_mctrl,
1111	.stop_tx	= sc16is7xx_stop_tx,
1112	.start_tx	= sc16is7xx_start_tx,
 
 
1113	.stop_rx	= sc16is7xx_stop_rx,
 
1114	.break_ctl	= sc16is7xx_break_ctl,
1115	.startup	= sc16is7xx_startup,
1116	.shutdown	= sc16is7xx_shutdown,
1117	.set_termios	= sc16is7xx_set_termios,
1118	.type		= sc16is7xx_type,
1119	.request_port	= sc16is7xx_request_port,
1120	.release_port	= sc16is7xx_null_void,
1121	.config_port	= sc16is7xx_config_port,
1122	.verify_port	= sc16is7xx_verify_port,
1123	.pm		= sc16is7xx_pm,
1124};
1125
1126#ifdef CONFIG_GPIOLIB
1127static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1128{
1129	unsigned int val;
1130	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1131	struct uart_port *port = &s->p[0].port;
1132
1133	val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1134
1135	return !!(val & BIT(offset));
1136}
1137
1138static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1139{
1140	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1141	struct uart_port *port = &s->p[0].port;
1142
1143	sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1144			      val ? BIT(offset) : 0);
1145}
1146
1147static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1148					  unsigned offset)
1149{
1150	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1151	struct uart_port *port = &s->p[0].port;
1152
1153	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1154
1155	return 0;
1156}
1157
1158static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1159					   unsigned offset, int val)
1160{
1161	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1162	struct uart_port *port = &s->p[0].port;
1163	u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1164
1165	if (val)
1166		state |= BIT(offset);
1167	else
1168		state &= ~BIT(offset);
1169	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1170	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1171			      BIT(offset));
1172
1173	return 0;
1174}
1175#endif
1176
 
 
 
 
 
 
1177static int sc16is7xx_probe(struct device *dev,
1178			   const struct sc16is7xx_devtype *devtype,
1179			   struct regmap *regmap, int irq, unsigned long flags)
1180{
1181	struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
1182	unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
 
1183	u32 uartclk = 0;
1184	int i, ret;
1185	struct sc16is7xx_port *s;
1186
1187	if (IS_ERR(regmap))
1188		return PTR_ERR(regmap);
1189
 
 
 
 
 
 
 
 
 
 
1190	/* Alloc port structure */
1191	s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1192	if (!s) {
1193		dev_err(dev, "Error allocating port structure\n");
1194		return -ENOMEM;
1195	}
1196
1197	/* Always ask for fixed clock rate from a property. */
1198	device_property_read_u32(dev, "clock-frequency", &uartclk);
1199
1200	s->clk = devm_clk_get(dev, NULL);
1201	if (IS_ERR(s->clk)) {
 
 
 
 
 
 
 
 
1202		if (uartclk)
1203			freq = uartclk;
1204		if (pfreq)
1205			freq = *pfreq;
1206		if (freq)
1207			dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1208		else
1209			return PTR_ERR(s->clk);
1210	} else {
1211		ret = clk_prepare_enable(s->clk);
1212		if (ret)
1213			return ret;
1214
1215		freq = clk_get_rate(s->clk);
1216	}
1217
1218	s->regmap = regmap;
1219	s->devtype = devtype;
1220	dev_set_drvdata(dev, s);
1221	mutex_init(&s->efr_lock);
1222
1223	kthread_init_worker(&s->kworker);
1224	kthread_init_work(&s->irq_work, sc16is7xx_ist);
1225	s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1226				      "sc16is7xx");
1227	if (IS_ERR(s->kworker_task)) {
1228		ret = PTR_ERR(s->kworker_task);
1229		goto out_clk;
1230	}
1231	sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1232
1233#ifdef CONFIG_GPIOLIB
1234	if (devtype->nr_gpio) {
1235		/* Setup GPIO cotroller */
1236		s->gpio.owner		 = THIS_MODULE;
1237		s->gpio.parent		 = dev;
1238		s->gpio.label		 = dev_name(dev);
1239		s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
1240		s->gpio.get		 = sc16is7xx_gpio_get;
1241		s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1242		s->gpio.set		 = sc16is7xx_gpio_set;
1243		s->gpio.base		 = -1;
1244		s->gpio.ngpio		 = devtype->nr_gpio;
1245		s->gpio.can_sleep	 = 1;
1246		ret = gpiochip_add_data(&s->gpio, s);
1247		if (ret)
1248			goto out_thread;
1249	}
1250#endif
1251
1252	/* reset device, purging any pending irq / data */
1253	regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1254			SC16IS7XX_IOCONTROL_SRESET_BIT);
1255
1256	for (i = 0; i < devtype->nr_uart; ++i) {
1257		s->p[i].line		= i;
1258		/* Initialize port data */
1259		s->p[i].port.dev	= dev;
1260		s->p[i].port.irq	= irq;
1261		s->p[i].port.type	= PORT_SC16IS7XX;
1262		s->p[i].port.fifosize	= SC16IS7XX_FIFO_SIZE;
1263		s->p[i].port.flags	= UPF_FIXED_TYPE | UPF_LOW_LATENCY;
 
1264		s->p[i].port.iotype	= UPIO_PORT;
1265		s->p[i].port.uartclk	= freq;
1266		s->p[i].port.rs485_config = sc16is7xx_config_rs485;
 
1267		s->p[i].port.ops	= &sc16is7xx_ops;
 
1268		s->p[i].port.line	= sc16is7xx_alloc_line();
 
1269		if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1270			ret = -ENOMEM;
1271			goto out_ports;
1272		}
1273
1274		/* Disable all interrupts */
1275		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1276		/* Disable TX/RX */
1277		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1278				     SC16IS7XX_EFCR_RXDISABLE_BIT |
1279				     SC16IS7XX_EFCR_TXDISABLE_BIT);
 
 
 
 
 
 
 
1280		/* Initialize kthread work structs */
1281		kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1282		kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
 
1283		/* Register port */
1284		uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1285
1286		/* Enable EFR */
1287		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1288				     SC16IS7XX_LCR_CONF_MODE_B);
1289
1290		regcache_cache_bypass(s->regmap, true);
1291
1292		/* Enable write access to enhanced features */
1293		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1294				     SC16IS7XX_EFR_ENABLE_BIT);
1295
1296		regcache_cache_bypass(s->regmap, false);
1297
1298		/* Restore access to general registers */
1299		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1300
1301		/* Go to suspend mode */
1302		sc16is7xx_power(&s->p[i].port, 0);
1303	}
1304
1305	/* Setup interrupt */
1306	ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1307			       flags, dev_name(dev), s);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1308	if (!ret)
1309		return 0;
1310
1311out_ports:
1312	for (i--; i >= 0; i--) {
1313		uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1314		clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1315	}
1316
1317#ifdef CONFIG_GPIOLIB
1318	if (devtype->nr_gpio)
1319		gpiochip_remove(&s->gpio);
1320
1321out_thread:
1322#endif
1323	kthread_stop(s->kworker_task);
1324
1325out_clk:
1326	if (!IS_ERR(s->clk))
1327		clk_disable_unprepare(s->clk);
1328
1329	return ret;
1330}
1331
1332static int sc16is7xx_remove(struct device *dev)
1333{
1334	struct sc16is7xx_port *s = dev_get_drvdata(dev);
1335	int i;
1336
1337#ifdef CONFIG_GPIOLIB
1338	if (s->devtype->nr_gpio)
1339		gpiochip_remove(&s->gpio);
1340#endif
1341
1342	for (i = 0; i < s->devtype->nr_uart; i++) {
 
1343		uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1344		clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1345		sc16is7xx_power(&s->p[i].port, 0);
1346	}
1347
1348	kthread_flush_worker(&s->kworker);
1349	kthread_stop(s->kworker_task);
1350
1351	if (!IS_ERR(s->clk))
1352		clk_disable_unprepare(s->clk);
1353
1354	return 0;
1355}
1356
1357static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1358	{ .compatible = "nxp,sc16is740",	.data = &sc16is74x_devtype, },
1359	{ .compatible = "nxp,sc16is741",	.data = &sc16is74x_devtype, },
1360	{ .compatible = "nxp,sc16is750",	.data = &sc16is750_devtype, },
1361	{ .compatible = "nxp,sc16is752",	.data = &sc16is752_devtype, },
1362	{ .compatible = "nxp,sc16is760",	.data = &sc16is760_devtype, },
1363	{ .compatible = "nxp,sc16is762",	.data = &sc16is762_devtype, },
1364	{ }
1365};
1366MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1367
1368static struct regmap_config regcfg = {
1369	.reg_bits = 7,
1370	.pad_bits = 1,
1371	.val_bits = 8,
1372	.cache_type = REGCACHE_RBTREE,
1373	.volatile_reg = sc16is7xx_regmap_volatile,
1374	.precious_reg = sc16is7xx_regmap_precious,
1375};
1376
1377#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1378static int sc16is7xx_spi_probe(struct spi_device *spi)
1379{
1380	const struct sc16is7xx_devtype *devtype;
1381	unsigned long flags = 0;
1382	struct regmap *regmap;
1383	int ret;
1384
1385	/* Setup SPI bus */
1386	spi->bits_per_word	= 8;
1387	/* only supports mode 0 on SC16IS762 */
1388	spi->mode		= spi->mode ? : SPI_MODE_0;
1389	spi->max_speed_hz	= spi->max_speed_hz ? : 15000000;
1390	ret = spi_setup(spi);
1391	if (ret)
1392		return ret;
1393
1394	if (spi->dev.of_node) {
1395		devtype = device_get_match_data(&spi->dev);
1396		if (!devtype)
1397			return -ENODEV;
1398	} else {
1399		const struct spi_device_id *id_entry = spi_get_device_id(spi);
1400
1401		devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1402		flags = IRQF_TRIGGER_FALLING;
1403	}
1404
1405	regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1406			      (devtype->nr_uart - 1);
1407	regmap = devm_regmap_init_spi(spi, &regcfg);
1408
1409	return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1410}
1411
1412static int sc16is7xx_spi_remove(struct spi_device *spi)
1413{
1414	return sc16is7xx_remove(&spi->dev);
1415}
1416
1417static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1418	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1419	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1420	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1421	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1422	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1423	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1424	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1425	{ }
1426};
1427
1428MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1429
1430static struct spi_driver sc16is7xx_spi_uart_driver = {
1431	.driver = {
1432		.name		= SC16IS7XX_NAME,
1433		.of_match_table	= sc16is7xx_dt_ids,
1434	},
1435	.probe		= sc16is7xx_spi_probe,
1436	.remove		= sc16is7xx_spi_remove,
1437	.id_table	= sc16is7xx_spi_id_table,
1438};
1439
1440MODULE_ALIAS("spi:sc16is7xx");
1441#endif
1442
1443#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1444static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1445			       const struct i2c_device_id *id)
1446{
1447	const struct sc16is7xx_devtype *devtype;
1448	unsigned long flags = 0;
1449	struct regmap *regmap;
1450
1451	if (i2c->dev.of_node) {
1452		devtype = device_get_match_data(&i2c->dev);
1453		if (!devtype)
1454			return -ENODEV;
1455	} else {
1456		devtype = (struct sc16is7xx_devtype *)id->driver_data;
1457		flags = IRQF_TRIGGER_FALLING;
1458	}
1459
1460	regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1461			      (devtype->nr_uart - 1);
1462	regmap = devm_regmap_init_i2c(i2c, &regcfg);
1463
1464	return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1465}
1466
1467static int sc16is7xx_i2c_remove(struct i2c_client *client)
1468{
1469	return sc16is7xx_remove(&client->dev);
1470}
1471
1472static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1473	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1474	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1475	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1476	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1477	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1478	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1479	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1480	{ }
1481};
1482MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1483
1484static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1485	.driver = {
1486		.name		= SC16IS7XX_NAME,
1487		.of_match_table	= sc16is7xx_dt_ids,
1488	},
1489	.probe		= sc16is7xx_i2c_probe,
1490	.remove		= sc16is7xx_i2c_remove,
1491	.id_table	= sc16is7xx_i2c_id_table,
1492};
1493
1494#endif
1495
1496static int __init sc16is7xx_init(void)
1497{
1498	int ret;
1499
1500	ret = uart_register_driver(&sc16is7xx_uart);
1501	if (ret) {
1502		pr_err("Registering UART driver failed\n");
1503		return ret;
1504	}
1505
1506#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1507	ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1508	if (ret < 0) {
1509		pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1510		goto err_i2c;
1511	}
1512#endif
1513
1514#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1515	ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1516	if (ret < 0) {
1517		pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1518		goto err_spi;
1519	}
1520#endif
1521	return ret;
1522
1523#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1524err_spi:
1525#endif
1526#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1527	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1528err_i2c:
1529#endif
1530	uart_unregister_driver(&sc16is7xx_uart);
1531	return ret;
1532}
1533module_init(sc16is7xx_init);
1534
1535static void __exit sc16is7xx_exit(void)
1536{
1537#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1538	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1539#endif
1540
1541#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1542	spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1543#endif
1544	uart_unregister_driver(&sc16is7xx_uart);
1545}
1546module_exit(sc16is7xx_exit);
1547
1548MODULE_LICENSE("GPL");
1549MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1550MODULE_DESCRIPTION("SC16IS7XX serial driver");