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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/of_gpio.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/console.h>
21#include <linux/clk.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/serial_core.h>
25#include <linux/delay.h>
26
27#include <asm/mach-pic32/pic32.h>
28#include "pic32_uart.h"
29
30/* UART name and device definitions */
31#define PIC32_DEV_NAME "pic32-uart"
32#define PIC32_MAX_UARTS 6
33#define PIC32_SDEV_NAME "ttyPIC"
34
35/* pic32_sport pointer for console use */
36static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
37
38static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
39{
40 /* wait for tx empty, otherwise chars will be lost or corrupted */
41 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
42 udelay(1);
43}
44
45static inline int pic32_enable_clock(struct pic32_sport *sport)
46{
47 int ret = clk_prepare_enable(sport->clk);
48
49 if (ret)
50 return ret;
51
52 sport->ref_clk++;
53 return 0;
54}
55
56static inline void pic32_disable_clock(struct pic32_sport *sport)
57{
58 sport->ref_clk--;
59 clk_disable_unprepare(sport->clk);
60}
61
62/* serial core request to check if uart tx buffer is empty */
63static unsigned int pic32_uart_tx_empty(struct uart_port *port)
64{
65 struct pic32_sport *sport = to_pic32_sport(port);
66 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
67
68 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
69}
70
71/* serial core request to set UART outputs */
72static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
73{
74 struct pic32_sport *sport = to_pic32_sport(port);
75
76 /* set loopback mode */
77 if (mctrl & TIOCM_LOOP)
78 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
79 PIC32_UART_MODE_LPBK);
80 else
81 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
82 PIC32_UART_MODE_LPBK);
83}
84
85/* get the state of CTS input pin for this port */
86static unsigned int get_cts_state(struct pic32_sport *sport)
87{
88 /* read and invert UxCTS */
89 if (gpio_is_valid(sport->cts_gpio))
90 return !gpio_get_value(sport->cts_gpio);
91
92 return 1;
93}
94
95/* serial core request to return the state of misc UART input pins */
96static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
97{
98 struct pic32_sport *sport = to_pic32_sport(port);
99 unsigned int mctrl = 0;
100
101 if (!sport->hw_flow_ctrl)
102 mctrl |= TIOCM_CTS;
103 else if (get_cts_state(sport))
104 mctrl |= TIOCM_CTS;
105
106 /* DSR and CD are not supported in PIC32, so return 1
107 * RI is not supported in PIC32, so return 0
108 */
109 mctrl |= TIOCM_CD;
110 mctrl |= TIOCM_DSR;
111
112 return mctrl;
113}
114
115/* stop tx and start tx are not called in pairs, therefore a flag indicates
116 * the status of irq to control the irq-depth.
117 */
118static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
119{
120 if (en && !tx_irq_enabled(sport)) {
121 enable_irq(sport->irq_tx);
122 tx_irq_enabled(sport) = 1;
123 } else if (!en && tx_irq_enabled(sport)) {
124 /* use disable_irq_nosync() and not disable_irq() to avoid self
125 * imposed deadlock by not waiting for irq handler to end,
126 * since this callback is called from interrupt context.
127 */
128 disable_irq_nosync(sport->irq_tx);
129 tx_irq_enabled(sport) = 0;
130 }
131}
132
133/* serial core request to disable tx ASAP (used for flow control) */
134static void pic32_uart_stop_tx(struct uart_port *port)
135{
136 struct pic32_sport *sport = to_pic32_sport(port);
137
138 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
139 return;
140
141 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
142 return;
143
144 /* wait for tx empty */
145 pic32_wait_deplete_txbuf(sport);
146
147 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
148 PIC32_UART_STA_UTXEN);
149 pic32_uart_irqtxen(sport, 0);
150}
151
152/* serial core request to (re)enable tx */
153static void pic32_uart_start_tx(struct uart_port *port)
154{
155 struct pic32_sport *sport = to_pic32_sport(port);
156
157 pic32_uart_irqtxen(sport, 1);
158 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
159 PIC32_UART_STA_UTXEN);
160}
161
162/* serial core request to stop rx, called before port shutdown */
163static void pic32_uart_stop_rx(struct uart_port *port)
164{
165 struct pic32_sport *sport = to_pic32_sport(port);
166
167 /* disable rx interrupts */
168 disable_irq(sport->irq_rx);
169
170 /* receiver Enable bit OFF */
171 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
172 PIC32_UART_STA_URXEN);
173}
174
175/* serial core request to start/stop emitting break char */
176static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
177{
178 struct pic32_sport *sport = to_pic32_sport(port);
179 unsigned long flags;
180
181 spin_lock_irqsave(&port->lock, flags);
182
183 if (ctl)
184 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
185 PIC32_UART_STA_UTXBRK);
186 else
187 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
188 PIC32_UART_STA_UTXBRK);
189
190 spin_unlock_irqrestore(&port->lock, flags);
191}
192
193/* get port type in string format */
194static const char *pic32_uart_type(struct uart_port *port)
195{
196 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
197}
198
199/* read all chars in rx fifo and send them to core */
200static void pic32_uart_do_rx(struct uart_port *port)
201{
202 struct pic32_sport *sport = to_pic32_sport(port);
203 struct tty_port *tty;
204 unsigned int max_count;
205
206 /* limit number of char read in interrupt, should not be
207 * higher than fifo size anyway since we're much faster than
208 * serial port
209 */
210 max_count = PIC32_UART_RX_FIFO_DEPTH;
211
212 spin_lock(&port->lock);
213
214 tty = &port->state->port;
215
216 do {
217 u32 sta_reg, c;
218 char flag;
219
220 /* get overrun/fifo empty information from status register */
221 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
222 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
223
224 /* fifo reset is required to clear interrupt */
225 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
226 PIC32_UART_STA_OERR);
227
228 port->icount.overrun++;
229 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
230 }
231
232 /* Can at least one more character can be read? */
233 if (!(sta_reg & PIC32_UART_STA_URXDA))
234 break;
235
236 /* read the character and increment the rx counter */
237 c = pic32_uart_readl(sport, PIC32_UART_RX);
238
239 port->icount.rx++;
240 flag = TTY_NORMAL;
241 c &= 0xff;
242
243 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
244 (sta_reg & PIC32_UART_STA_FERR))) {
245
246 /* do stats first */
247 if (sta_reg & PIC32_UART_STA_PERR)
248 port->icount.parity++;
249 if (sta_reg & PIC32_UART_STA_FERR)
250 port->icount.frame++;
251
252 /* update flag wrt read_status_mask */
253 sta_reg &= port->read_status_mask;
254
255 if (sta_reg & PIC32_UART_STA_FERR)
256 flag = TTY_FRAME;
257 if (sta_reg & PIC32_UART_STA_PERR)
258 flag = TTY_PARITY;
259 }
260
261 if (uart_handle_sysrq_char(port, c))
262 continue;
263
264 if ((sta_reg & port->ignore_status_mask) == 0)
265 tty_insert_flip_char(tty, c, flag);
266
267 } while (--max_count);
268
269 spin_unlock(&port->lock);
270
271 tty_flip_buffer_push(tty);
272}
273
274/* fill tx fifo with chars to send, stop when fifo is about to be full
275 * or when all chars have been sent.
276 */
277static void pic32_uart_do_tx(struct uart_port *port)
278{
279 struct pic32_sport *sport = to_pic32_sport(port);
280 struct circ_buf *xmit = &port->state->xmit;
281 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
282
283 if (port->x_char) {
284 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
285 port->icount.tx++;
286 port->x_char = 0;
287 return;
288 }
289
290 if (uart_tx_stopped(port)) {
291 pic32_uart_stop_tx(port);
292 return;
293 }
294
295 if (uart_circ_empty(xmit))
296 goto txq_empty;
297
298 /* keep stuffing chars into uart tx buffer
299 * 1) until uart fifo is full
300 * or
301 * 2) until the circ buffer is empty
302 * (all chars have been sent)
303 * or
304 * 3) until the max count is reached
305 * (prevents lingering here for too long in certain cases)
306 */
307 while (!(PIC32_UART_STA_UTXBF &
308 pic32_uart_readl(sport, PIC32_UART_STA))) {
309 unsigned int c = xmit->buf[xmit->tail];
310
311 pic32_uart_writel(sport, PIC32_UART_TX, c);
312
313 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
314 port->icount.tx++;
315 if (uart_circ_empty(xmit))
316 break;
317 if (--max_count == 0)
318 break;
319 }
320
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
322 uart_write_wakeup(port);
323
324 if (uart_circ_empty(xmit))
325 goto txq_empty;
326
327 return;
328
329txq_empty:
330 pic32_uart_irqtxen(sport, 0);
331}
332
333/* RX interrupt handler */
334static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
335{
336 struct uart_port *port = dev_id;
337
338 pic32_uart_do_rx(port);
339
340 return IRQ_HANDLED;
341}
342
343/* TX interrupt handler */
344static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
345{
346 struct uart_port *port = dev_id;
347 unsigned long flags;
348
349 spin_lock_irqsave(&port->lock, flags);
350 pic32_uart_do_tx(port);
351 spin_unlock_irqrestore(&port->lock, flags);
352
353 return IRQ_HANDLED;
354}
355
356/* FAULT interrupt handler */
357static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
358{
359 /* do nothing: pic32_uart_do_rx() handles faults. */
360 return IRQ_HANDLED;
361}
362
363/* enable rx & tx operation on uart */
364static void pic32_uart_en_and_unmask(struct uart_port *port)
365{
366 struct pic32_sport *sport = to_pic32_sport(port);
367
368 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
369 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
370 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
371 PIC32_UART_MODE_ON);
372}
373
374/* disable rx & tx operation on uart */
375static void pic32_uart_dsbl_and_mask(struct uart_port *port)
376{
377 struct pic32_sport *sport = to_pic32_sport(port);
378
379 /* wait for tx empty, otherwise chars will be lost or corrupted */
380 pic32_wait_deplete_txbuf(sport);
381
382 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
383 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
384 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
385 PIC32_UART_MODE_ON);
386}
387
388/* serial core request to initialize uart and start rx operation */
389static int pic32_uart_startup(struct uart_port *port)
390{
391 struct pic32_sport *sport = to_pic32_sport(port);
392 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
393 unsigned long flags;
394 int ret;
395
396 local_irq_save(flags);
397
398 ret = pic32_enable_clock(sport);
399 if (ret) {
400 local_irq_restore(flags);
401 goto out_done;
402 }
403
404 /* clear status and mode registers */
405 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
406 pic32_uart_writel(sport, PIC32_UART_STA, 0);
407
408 /* disable uart and mask all interrupts */
409 pic32_uart_dsbl_and_mask(port);
410
411 /* set default baud */
412 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
413
414 local_irq_restore(flags);
415
416 /* Each UART of a PIC32 has three interrupts therefore,
417 * we setup driver to register the 3 irqs for the device.
418 *
419 * For each irq request_irq() is called with interrupt disabled.
420 * And the irq is enabled as soon as we are ready to handle them.
421 */
422 tx_irq_enabled(sport) = 0;
423
424 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
425 pic32_uart_type(port),
426 sport->idx);
427 if (!sport->irq_fault_name) {
428 dev_err(port->dev, "%s: kasprintf err!", __func__);
429 ret = -ENOMEM;
430 goto out_done;
431 }
432 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
433 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
434 sport->irqflags_fault, sport->irq_fault_name, port);
435 if (ret) {
436 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
437 __func__, sport->irq_fault, ret,
438 pic32_uart_type(port));
439 goto out_f;
440 }
441
442 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
443 pic32_uart_type(port),
444 sport->idx);
445 if (!sport->irq_rx_name) {
446 dev_err(port->dev, "%s: kasprintf err!", __func__);
447 ret = -ENOMEM;
448 goto out_f;
449 }
450 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
451 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
452 sport->irqflags_rx, sport->irq_rx_name, port);
453 if (ret) {
454 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
455 __func__, sport->irq_rx, ret,
456 pic32_uart_type(port));
457 goto out_r;
458 }
459
460 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
461 pic32_uart_type(port),
462 sport->idx);
463 if (!sport->irq_tx_name) {
464 dev_err(port->dev, "%s: kasprintf err!", __func__);
465 ret = -ENOMEM;
466 goto out_r;
467 }
468 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
469 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
470 sport->irqflags_tx, sport->irq_tx_name, port);
471 if (ret) {
472 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
473 __func__, sport->irq_tx, ret,
474 pic32_uart_type(port));
475 goto out_t;
476 }
477
478 local_irq_save(flags);
479
480 /* set rx interrupt on first receive */
481 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
482 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
483
484 /* set interrupt on empty */
485 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
486 PIC32_UART_STA_UTXISEL1);
487
488 /* enable all interrupts and eanable uart */
489 pic32_uart_en_and_unmask(port);
490
491 enable_irq(sport->irq_rx);
492
493 return 0;
494
495out_t:
496 kfree(sport->irq_tx_name);
497 free_irq(sport->irq_tx, port);
498out_r:
499 kfree(sport->irq_rx_name);
500 free_irq(sport->irq_rx, port);
501out_f:
502 kfree(sport->irq_fault_name);
503 free_irq(sport->irq_fault, port);
504out_done:
505 return ret;
506}
507
508/* serial core request to flush & disable uart */
509static void pic32_uart_shutdown(struct uart_port *port)
510{
511 struct pic32_sport *sport = to_pic32_sport(port);
512 unsigned long flags;
513
514 /* disable uart */
515 spin_lock_irqsave(&port->lock, flags);
516 pic32_uart_dsbl_and_mask(port);
517 spin_unlock_irqrestore(&port->lock, flags);
518 pic32_disable_clock(sport);
519
520 /* free all 3 interrupts for this UART */
521 free_irq(sport->irq_fault, port);
522 free_irq(sport->irq_tx, port);
523 free_irq(sport->irq_rx, port);
524}
525
526/* serial core request to change current uart setting */
527static void pic32_uart_set_termios(struct uart_port *port,
528 struct ktermios *new,
529 struct ktermios *old)
530{
531 struct pic32_sport *sport = to_pic32_sport(port);
532 unsigned int baud;
533 unsigned int quot;
534 unsigned long flags;
535
536 spin_lock_irqsave(&port->lock, flags);
537
538 /* disable uart and mask all interrupts while changing speed */
539 pic32_uart_dsbl_and_mask(port);
540
541 /* stop bit options */
542 if (new->c_cflag & CSTOPB)
543 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
544 PIC32_UART_MODE_STSEL);
545 else
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
547 PIC32_UART_MODE_STSEL);
548
549 /* parity options */
550 if (new->c_cflag & PARENB) {
551 if (new->c_cflag & PARODD) {
552 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
553 PIC32_UART_MODE_PDSEL1);
554 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
555 PIC32_UART_MODE_PDSEL0);
556 } else {
557 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
558 PIC32_UART_MODE_PDSEL0);
559 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
560 PIC32_UART_MODE_PDSEL1);
561 }
562 } else {
563 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
564 PIC32_UART_MODE_PDSEL1 |
565 PIC32_UART_MODE_PDSEL0);
566 }
567 /* if hw flow ctrl, then the pins must be specified in device tree */
568 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
569 /* enable hardware flow control */
570 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
571 PIC32_UART_MODE_UEN1);
572 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
573 PIC32_UART_MODE_UEN0);
574 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
575 PIC32_UART_MODE_RTSMD);
576 } else {
577 /* disable hardware flow control */
578 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
579 PIC32_UART_MODE_UEN1);
580 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
581 PIC32_UART_MODE_UEN0);
582 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
583 PIC32_UART_MODE_RTSMD);
584 }
585
586 /* Always 8-bit */
587 new->c_cflag |= CS8;
588
589 /* Mark/Space parity is not supported */
590 new->c_cflag &= ~CMSPAR;
591
592 /* update baud */
593 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
594 quot = uart_get_divisor(port, baud) - 1;
595 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
596 uart_update_timeout(port, new->c_cflag, baud);
597
598 if (tty_termios_baud_rate(new))
599 tty_termios_encode_baud_rate(new, baud, baud);
600
601 /* enable uart */
602 pic32_uart_en_and_unmask(port);
603
604 spin_unlock_irqrestore(&port->lock, flags);
605}
606
607/* serial core request to claim uart iomem */
608static int pic32_uart_request_port(struct uart_port *port)
609{
610 struct platform_device *pdev = to_platform_device(port->dev);
611 struct resource *res_mem;
612
613 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 if (unlikely(!res_mem))
615 return -EINVAL;
616
617 if (!request_mem_region(port->mapbase, resource_size(res_mem),
618 "pic32_uart_mem"))
619 return -EBUSY;
620
621 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
622 resource_size(res_mem));
623 if (!port->membase) {
624 dev_err(port->dev, "Unable to map registers\n");
625 release_mem_region(port->mapbase, resource_size(res_mem));
626 return -ENOMEM;
627 }
628
629 return 0;
630}
631
632/* serial core request to release uart iomem */
633static void pic32_uart_release_port(struct uart_port *port)
634{
635 struct platform_device *pdev = to_platform_device(port->dev);
636 struct resource *res_mem;
637 unsigned int res_size;
638
639 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 if (unlikely(!res_mem))
641 return;
642 res_size = resource_size(res_mem);
643
644 release_mem_region(port->mapbase, res_size);
645}
646
647/* serial core request to do any port required auto-configuration */
648static void pic32_uart_config_port(struct uart_port *port, int flags)
649{
650 if (flags & UART_CONFIG_TYPE) {
651 if (pic32_uart_request_port(port))
652 return;
653 port->type = PORT_PIC32;
654 }
655}
656
657/* serial core request to check that port information in serinfo are suitable */
658static int pic32_uart_verify_port(struct uart_port *port,
659 struct serial_struct *serinfo)
660{
661 if (port->type != PORT_PIC32)
662 return -EINVAL;
663 if (port->irq != serinfo->irq)
664 return -EINVAL;
665 if (port->iotype != serinfo->io_type)
666 return -EINVAL;
667 if (port->mapbase != (unsigned long)serinfo->iomem_base)
668 return -EINVAL;
669
670 return 0;
671}
672
673/* serial core callbacks */
674static const struct uart_ops pic32_uart_ops = {
675 .tx_empty = pic32_uart_tx_empty,
676 .get_mctrl = pic32_uart_get_mctrl,
677 .set_mctrl = pic32_uart_set_mctrl,
678 .start_tx = pic32_uart_start_tx,
679 .stop_tx = pic32_uart_stop_tx,
680 .stop_rx = pic32_uart_stop_rx,
681 .break_ctl = pic32_uart_break_ctl,
682 .startup = pic32_uart_startup,
683 .shutdown = pic32_uart_shutdown,
684 .set_termios = pic32_uart_set_termios,
685 .type = pic32_uart_type,
686 .release_port = pic32_uart_release_port,
687 .request_port = pic32_uart_request_port,
688 .config_port = pic32_uart_config_port,
689 .verify_port = pic32_uart_verify_port,
690};
691
692#ifdef CONFIG_SERIAL_PIC32_CONSOLE
693/* output given char */
694static void pic32_console_putchar(struct uart_port *port, int ch)
695{
696 struct pic32_sport *sport = to_pic32_sport(port);
697
698 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
699 return;
700
701 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
702 return;
703
704 /* wait for tx empty */
705 pic32_wait_deplete_txbuf(sport);
706
707 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
708}
709
710/* console core request to output given string */
711static void pic32_console_write(struct console *co, const char *s,
712 unsigned int count)
713{
714 struct pic32_sport *sport = pic32_sports[co->index];
715 struct uart_port *port = pic32_get_port(sport);
716
717 /* call uart helper to deal with \r\n */
718 uart_console_write(port, s, count, pic32_console_putchar);
719}
720
721/* console core request to setup given console, find matching uart
722 * port and setup it.
723 */
724static int pic32_console_setup(struct console *co, char *options)
725{
726 struct pic32_sport *sport;
727 struct uart_port *port = NULL;
728 int baud = 115200;
729 int bits = 8;
730 int parity = 'n';
731 int flow = 'n';
732 int ret = 0;
733
734 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
735 return -ENODEV;
736
737 sport = pic32_sports[co->index];
738 if (!sport)
739 return -ENODEV;
740 port = pic32_get_port(sport);
741
742 ret = pic32_enable_clock(sport);
743 if (ret)
744 return ret;
745
746 if (options)
747 uart_parse_options(options, &baud, &parity, &bits, &flow);
748
749 return uart_set_options(port, co, baud, parity, bits, flow);
750}
751
752static struct uart_driver pic32_uart_driver;
753static struct console pic32_console = {
754 .name = PIC32_SDEV_NAME,
755 .write = pic32_console_write,
756 .device = uart_console_device,
757 .setup = pic32_console_setup,
758 .flags = CON_PRINTBUFFER,
759 .index = -1,
760 .data = &pic32_uart_driver,
761};
762#define PIC32_SCONSOLE (&pic32_console)
763
764static int __init pic32_console_init(void)
765{
766 register_console(&pic32_console);
767 return 0;
768}
769console_initcall(pic32_console_init);
770
771static inline bool is_pic32_console_port(struct uart_port *port)
772{
773 return port->cons && port->cons->index == port->line;
774}
775
776/*
777 * Late console initialization.
778 */
779static int __init pic32_late_console_init(void)
780{
781 if (!(pic32_console.flags & CON_ENABLED))
782 register_console(&pic32_console);
783
784 return 0;
785}
786
787core_initcall(pic32_late_console_init);
788
789#else
790#define PIC32_SCONSOLE NULL
791#endif
792
793static struct uart_driver pic32_uart_driver = {
794 .owner = THIS_MODULE,
795 .driver_name = PIC32_DEV_NAME,
796 .dev_name = PIC32_SDEV_NAME,
797 .nr = PIC32_MAX_UARTS,
798 .cons = PIC32_SCONSOLE,
799};
800
801static int pic32_uart_probe(struct platform_device *pdev)
802{
803 struct device_node *np = pdev->dev.of_node;
804 struct pic32_sport *sport;
805 int uart_idx = 0;
806 struct resource *res_mem;
807 struct uart_port *port;
808 int ret;
809
810 uart_idx = of_alias_get_id(np, "serial");
811 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
812 return -EINVAL;
813
814 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 if (!res_mem)
816 return -EINVAL;
817
818 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
819 if (!sport)
820 return -ENOMEM;
821
822 sport->idx = uart_idx;
823 sport->irq_fault = irq_of_parse_and_map(np, 0);
824 sport->irqflags_fault = IRQF_NO_THREAD;
825 sport->irq_rx = irq_of_parse_and_map(np, 1);
826 sport->irqflags_rx = IRQF_NO_THREAD;
827 sport->irq_tx = irq_of_parse_and_map(np, 2);
828 sport->irqflags_tx = IRQF_NO_THREAD;
829 sport->clk = devm_clk_get(&pdev->dev, NULL);
830 sport->cts_gpio = -EINVAL;
831 sport->dev = &pdev->dev;
832
833 /* Hardware flow control: gpios
834 * !Note: Basically, CTS is needed for reading the status.
835 */
836 sport->hw_flow_ctrl = false;
837 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
838 if (gpio_is_valid(sport->cts_gpio)) {
839 sport->hw_flow_ctrl = true;
840
841 ret = devm_gpio_request(sport->dev,
842 sport->cts_gpio, "CTS");
843 if (ret) {
844 dev_err(&pdev->dev,
845 "error requesting CTS GPIO\n");
846 goto err;
847 }
848
849 ret = gpio_direction_input(sport->cts_gpio);
850 if (ret) {
851 dev_err(&pdev->dev, "error setting CTS GPIO\n");
852 goto err;
853 }
854 }
855
856 pic32_sports[uart_idx] = sport;
857 port = &sport->port;
858 memset(port, 0, sizeof(*port));
859 port->iotype = UPIO_MEM;
860 port->mapbase = res_mem->start;
861 port->ops = &pic32_uart_ops;
862 port->flags = UPF_BOOT_AUTOCONF;
863 port->dev = &pdev->dev;
864 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
865 port->uartclk = clk_get_rate(sport->clk);
866 port->line = uart_idx;
867
868 ret = uart_add_one_port(&pic32_uart_driver, port);
869 if (ret) {
870 port->membase = NULL;
871 dev_err(port->dev, "%s: uart add port error!\n", __func__);
872 goto err;
873 }
874
875#ifdef CONFIG_SERIAL_PIC32_CONSOLE
876 if (is_pic32_console_port(port) &&
877 (pic32_console.flags & CON_ENABLED)) {
878 /* The peripheral clock has been enabled by console_setup,
879 * so disable it till the port is used.
880 */
881 pic32_disable_clock(sport);
882 }
883#endif
884
885 platform_set_drvdata(pdev, port);
886
887 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
888 __func__, uart_idx);
889
890 return 0;
891err:
892 /* automatic unroll of sport and gpios */
893 return ret;
894}
895
896static int pic32_uart_remove(struct platform_device *pdev)
897{
898 struct uart_port *port = platform_get_drvdata(pdev);
899 struct pic32_sport *sport = to_pic32_sport(port);
900
901 uart_remove_one_port(&pic32_uart_driver, port);
902 pic32_disable_clock(sport);
903 platform_set_drvdata(pdev, NULL);
904 pic32_sports[sport->idx] = NULL;
905
906 /* automatic unroll of sport and gpios */
907 return 0;
908}
909
910static const struct of_device_id pic32_serial_dt_ids[] = {
911 { .compatible = "microchip,pic32mzda-uart" },
912 { /* sentinel */ }
913};
914MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
915
916static struct platform_driver pic32_uart_platform_driver = {
917 .probe = pic32_uart_probe,
918 .remove = pic32_uart_remove,
919 .driver = {
920 .name = PIC32_DEV_NAME,
921 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
922 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
923 },
924};
925
926static int __init pic32_uart_init(void)
927{
928 int ret;
929
930 ret = uart_register_driver(&pic32_uart_driver);
931 if (ret) {
932 pr_err("failed to register %s:%d\n",
933 pic32_uart_driver.driver_name, ret);
934 return ret;
935 }
936
937 ret = platform_driver_register(&pic32_uart_platform_driver);
938 if (ret) {
939 pr_err("fail to register pic32 uart\n");
940 uart_unregister_driver(&pic32_uart_driver);
941 }
942
943 return ret;
944}
945arch_initcall(pic32_uart_init);
946
947static void __exit pic32_uart_exit(void)
948{
949#ifdef CONFIG_SERIAL_PIC32_CONSOLE
950 unregister_console(&pic32_console);
951#endif
952 platform_driver_unregister(&pic32_uart_platform_driver);
953 uart_unregister_driver(&pic32_uart_driver);
954}
955module_exit(pic32_uart_exit);
956
957MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
958MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
959MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/of_gpio.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/console.h>
21#include <linux/clk.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/serial_core.h>
25#include <linux/delay.h>
26
27#include <asm/mach-pic32/pic32.h>
28
29/* UART name and device definitions */
30#define PIC32_DEV_NAME "pic32-uart"
31#define PIC32_MAX_UARTS 6
32#define PIC32_SDEV_NAME "ttyPIC"
33
34#define PIC32_UART_DFLT_BRATE 9600
35#define PIC32_UART_TX_FIFO_DEPTH 8
36#define PIC32_UART_RX_FIFO_DEPTH 8
37
38#define PIC32_UART_MODE 0x00
39#define PIC32_UART_STA 0x10
40#define PIC32_UART_TX 0x20
41#define PIC32_UART_RX 0x30
42#define PIC32_UART_BRG 0x40
43
44/* struct pic32_sport - pic32 serial port descriptor
45 * @port: uart port descriptor
46 * @idx: port index
47 * @irq_fault: virtual fault interrupt number
48 * @irq_fault_name: irq fault name
49 * @irq_rx: virtual rx interrupt number
50 * @irq_rx_name: irq rx name
51 * @irq_tx: virtual tx interrupt number
52 * @irq_tx_name: irq tx name
53 * @cts_gpiod: clear to send GPIO
54 * @dev: device descriptor
55 **/
56struct pic32_sport {
57 struct uart_port port;
58 int idx;
59
60 int irq_fault;
61 const char *irq_fault_name;
62 int irq_rx;
63 const char *irq_rx_name;
64 int irq_tx;
65 const char *irq_tx_name;
66 bool enable_tx_irq;
67
68 struct gpio_desc *cts_gpiod;
69
70 struct clk *clk;
71
72 struct device *dev;
73};
74
75static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
76{
77 return container_of(port, struct pic32_sport, port);
78}
79
80static inline void pic32_uart_writel(struct pic32_sport *sport,
81 u32 reg, u32 val)
82{
83 __raw_writel(val, sport->port.membase + reg);
84}
85
86static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
87{
88 return __raw_readl(sport->port.membase + reg);
89}
90
91/* pic32 uart mode register bits */
92#define PIC32_UART_MODE_ON BIT(15)
93#define PIC32_UART_MODE_FRZ BIT(14)
94#define PIC32_UART_MODE_SIDL BIT(13)
95#define PIC32_UART_MODE_IREN BIT(12)
96#define PIC32_UART_MODE_RTSMD BIT(11)
97#define PIC32_UART_MODE_RESV1 BIT(10)
98#define PIC32_UART_MODE_UEN1 BIT(9)
99#define PIC32_UART_MODE_UEN0 BIT(8)
100#define PIC32_UART_MODE_WAKE BIT(7)
101#define PIC32_UART_MODE_LPBK BIT(6)
102#define PIC32_UART_MODE_ABAUD BIT(5)
103#define PIC32_UART_MODE_RXINV BIT(4)
104#define PIC32_UART_MODE_BRGH BIT(3)
105#define PIC32_UART_MODE_PDSEL1 BIT(2)
106#define PIC32_UART_MODE_PDSEL0 BIT(1)
107#define PIC32_UART_MODE_STSEL BIT(0)
108
109/* pic32 uart status register bits */
110#define PIC32_UART_STA_UTXISEL1 BIT(15)
111#define PIC32_UART_STA_UTXISEL0 BIT(14)
112#define PIC32_UART_STA_UTXINV BIT(13)
113#define PIC32_UART_STA_URXEN BIT(12)
114#define PIC32_UART_STA_UTXBRK BIT(11)
115#define PIC32_UART_STA_UTXEN BIT(10)
116#define PIC32_UART_STA_UTXBF BIT(9)
117#define PIC32_UART_STA_TRMT BIT(8)
118#define PIC32_UART_STA_URXISEL1 BIT(7)
119#define PIC32_UART_STA_URXISEL0 BIT(6)
120#define PIC32_UART_STA_ADDEN BIT(5)
121#define PIC32_UART_STA_RIDLE BIT(4)
122#define PIC32_UART_STA_PERR BIT(3)
123#define PIC32_UART_STA_FERR BIT(2)
124#define PIC32_UART_STA_OERR BIT(1)
125#define PIC32_UART_STA_URXDA BIT(0)
126
127/* pic32_sport pointer for console use */
128static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
129
130static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
131{
132 /* wait for tx empty, otherwise chars will be lost or corrupted */
133 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
134 udelay(1);
135}
136
137/* serial core request to check if uart tx buffer is empty */
138static unsigned int pic32_uart_tx_empty(struct uart_port *port)
139{
140 struct pic32_sport *sport = to_pic32_sport(port);
141 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
142
143 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
144}
145
146/* serial core request to set UART outputs */
147static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148{
149 struct pic32_sport *sport = to_pic32_sport(port);
150
151 /* set loopback mode */
152 if (mctrl & TIOCM_LOOP)
153 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
154 PIC32_UART_MODE_LPBK);
155 else
156 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
157 PIC32_UART_MODE_LPBK);
158}
159
160/* serial core request to return the state of misc UART input pins */
161static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
162{
163 struct pic32_sport *sport = to_pic32_sport(port);
164 unsigned int mctrl = 0;
165
166 /* get the state of CTS input pin for this port */
167 if (!sport->cts_gpiod)
168 mctrl |= TIOCM_CTS;
169 else if (gpiod_get_value(sport->cts_gpiod))
170 mctrl |= TIOCM_CTS;
171
172 /* DSR and CD are not supported in PIC32, so return 1
173 * RI is not supported in PIC32, so return 0
174 */
175 mctrl |= TIOCM_CD;
176 mctrl |= TIOCM_DSR;
177
178 return mctrl;
179}
180
181/* stop tx and start tx are not called in pairs, therefore a flag indicates
182 * the status of irq to control the irq-depth.
183 */
184static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
185{
186 if (en && !sport->enable_tx_irq) {
187 enable_irq(sport->irq_tx);
188 sport->enable_tx_irq = true;
189 } else if (!en && sport->enable_tx_irq) {
190 /* use disable_irq_nosync() and not disable_irq() to avoid self
191 * imposed deadlock by not waiting for irq handler to end,
192 * since this callback is called from interrupt context.
193 */
194 disable_irq_nosync(sport->irq_tx);
195 sport->enable_tx_irq = false;
196 }
197}
198
199/* serial core request to disable tx ASAP (used for flow control) */
200static void pic32_uart_stop_tx(struct uart_port *port)
201{
202 struct pic32_sport *sport = to_pic32_sport(port);
203
204 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
205 return;
206
207 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
208 return;
209
210 /* wait for tx empty */
211 pic32_wait_deplete_txbuf(sport);
212
213 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
214 PIC32_UART_STA_UTXEN);
215 pic32_uart_irqtxen(sport, 0);
216}
217
218/* serial core request to (re)enable tx */
219static void pic32_uart_start_tx(struct uart_port *port)
220{
221 struct pic32_sport *sport = to_pic32_sport(port);
222
223 pic32_uart_irqtxen(sport, 1);
224 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
225 PIC32_UART_STA_UTXEN);
226}
227
228/* serial core request to stop rx, called before port shutdown */
229static void pic32_uart_stop_rx(struct uart_port *port)
230{
231 struct pic32_sport *sport = to_pic32_sport(port);
232
233 /* disable rx interrupts */
234 disable_irq(sport->irq_rx);
235
236 /* receiver Enable bit OFF */
237 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
238 PIC32_UART_STA_URXEN);
239}
240
241/* serial core request to start/stop emitting break char */
242static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
243{
244 struct pic32_sport *sport = to_pic32_sport(port);
245 unsigned long flags;
246
247 spin_lock_irqsave(&port->lock, flags);
248
249 if (ctl)
250 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
251 PIC32_UART_STA_UTXBRK);
252 else
253 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
254 PIC32_UART_STA_UTXBRK);
255
256 spin_unlock_irqrestore(&port->lock, flags);
257}
258
259/* get port type in string format */
260static const char *pic32_uart_type(struct uart_port *port)
261{
262 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
263}
264
265/* read all chars in rx fifo and send them to core */
266static void pic32_uart_do_rx(struct uart_port *port)
267{
268 struct pic32_sport *sport = to_pic32_sport(port);
269 struct tty_port *tty;
270 unsigned int max_count;
271
272 /* limit number of char read in interrupt, should not be
273 * higher than fifo size anyway since we're much faster than
274 * serial port
275 */
276 max_count = PIC32_UART_RX_FIFO_DEPTH;
277
278 spin_lock(&port->lock);
279
280 tty = &port->state->port;
281
282 do {
283 u32 sta_reg, c;
284 char flag;
285
286 /* get overrun/fifo empty information from status register */
287 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
288 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
289
290 /* fifo reset is required to clear interrupt */
291 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
292 PIC32_UART_STA_OERR);
293
294 port->icount.overrun++;
295 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
296 }
297
298 /* Can at least one more character can be read? */
299 if (!(sta_reg & PIC32_UART_STA_URXDA))
300 break;
301
302 /* read the character and increment the rx counter */
303 c = pic32_uart_readl(sport, PIC32_UART_RX);
304
305 port->icount.rx++;
306 flag = TTY_NORMAL;
307 c &= 0xff;
308
309 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
310 (sta_reg & PIC32_UART_STA_FERR))) {
311
312 /* do stats first */
313 if (sta_reg & PIC32_UART_STA_PERR)
314 port->icount.parity++;
315 if (sta_reg & PIC32_UART_STA_FERR)
316 port->icount.frame++;
317
318 /* update flag wrt read_status_mask */
319 sta_reg &= port->read_status_mask;
320
321 if (sta_reg & PIC32_UART_STA_FERR)
322 flag = TTY_FRAME;
323 if (sta_reg & PIC32_UART_STA_PERR)
324 flag = TTY_PARITY;
325 }
326
327 if (uart_handle_sysrq_char(port, c))
328 continue;
329
330 if ((sta_reg & port->ignore_status_mask) == 0)
331 tty_insert_flip_char(tty, c, flag);
332
333 } while (--max_count);
334
335 spin_unlock(&port->lock);
336
337 tty_flip_buffer_push(tty);
338}
339
340/* fill tx fifo with chars to send, stop when fifo is about to be full
341 * or when all chars have been sent.
342 */
343static void pic32_uart_do_tx(struct uart_port *port)
344{
345 struct pic32_sport *sport = to_pic32_sport(port);
346 struct circ_buf *xmit = &port->state->xmit;
347 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
348
349 if (port->x_char) {
350 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
351 port->icount.tx++;
352 port->x_char = 0;
353 return;
354 }
355
356 if (uart_tx_stopped(port)) {
357 pic32_uart_stop_tx(port);
358 return;
359 }
360
361 if (uart_circ_empty(xmit))
362 goto txq_empty;
363
364 /* keep stuffing chars into uart tx buffer
365 * 1) until uart fifo is full
366 * or
367 * 2) until the circ buffer is empty
368 * (all chars have been sent)
369 * or
370 * 3) until the max count is reached
371 * (prevents lingering here for too long in certain cases)
372 */
373 while (!(PIC32_UART_STA_UTXBF &
374 pic32_uart_readl(sport, PIC32_UART_STA))) {
375 unsigned int c = xmit->buf[xmit->tail];
376
377 pic32_uart_writel(sport, PIC32_UART_TX, c);
378
379 uart_xmit_advance(port, 1);
380 if (uart_circ_empty(xmit))
381 break;
382 if (--max_count == 0)
383 break;
384 }
385
386 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
387 uart_write_wakeup(port);
388
389 if (uart_circ_empty(xmit))
390 goto txq_empty;
391
392 return;
393
394txq_empty:
395 pic32_uart_irqtxen(sport, 0);
396}
397
398/* RX interrupt handler */
399static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
400{
401 struct uart_port *port = dev_id;
402
403 pic32_uart_do_rx(port);
404
405 return IRQ_HANDLED;
406}
407
408/* TX interrupt handler */
409static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
410{
411 struct uart_port *port = dev_id;
412 unsigned long flags;
413
414 spin_lock_irqsave(&port->lock, flags);
415 pic32_uart_do_tx(port);
416 spin_unlock_irqrestore(&port->lock, flags);
417
418 return IRQ_HANDLED;
419}
420
421/* FAULT interrupt handler */
422static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
423{
424 /* do nothing: pic32_uart_do_rx() handles faults. */
425 return IRQ_HANDLED;
426}
427
428/* enable rx & tx operation on uart */
429static void pic32_uart_en_and_unmask(struct uart_port *port)
430{
431 struct pic32_sport *sport = to_pic32_sport(port);
432
433 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
434 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
435 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
436 PIC32_UART_MODE_ON);
437}
438
439/* disable rx & tx operation on uart */
440static void pic32_uart_dsbl_and_mask(struct uart_port *port)
441{
442 struct pic32_sport *sport = to_pic32_sport(port);
443
444 /* wait for tx empty, otherwise chars will be lost or corrupted */
445 pic32_wait_deplete_txbuf(sport);
446
447 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
448 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
449 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
450 PIC32_UART_MODE_ON);
451}
452
453/* serial core request to initialize uart and start rx operation */
454static int pic32_uart_startup(struct uart_port *port)
455{
456 struct pic32_sport *sport = to_pic32_sport(port);
457 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
458 unsigned long flags;
459 int ret;
460
461 local_irq_save(flags);
462
463 ret = clk_prepare_enable(sport->clk);
464 if (ret) {
465 local_irq_restore(flags);
466 goto out_done;
467 }
468
469 /* clear status and mode registers */
470 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
471 pic32_uart_writel(sport, PIC32_UART_STA, 0);
472
473 /* disable uart and mask all interrupts */
474 pic32_uart_dsbl_and_mask(port);
475
476 /* set default baud */
477 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
478
479 local_irq_restore(flags);
480
481 /* Each UART of a PIC32 has three interrupts therefore,
482 * we setup driver to register the 3 irqs for the device.
483 *
484 * For each irq request_irq() is called with interrupt disabled.
485 * And the irq is enabled as soon as we are ready to handle them.
486 */
487 sport->enable_tx_irq = false;
488
489 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
490 pic32_uart_type(port),
491 sport->idx);
492 if (!sport->irq_fault_name) {
493 dev_err(port->dev, "%s: kasprintf err!", __func__);
494 ret = -ENOMEM;
495 goto out_disable_clk;
496 }
497 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
498 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
499 IRQF_NO_THREAD, sport->irq_fault_name, port);
500 if (ret) {
501 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
502 __func__, sport->irq_fault, ret,
503 pic32_uart_type(port));
504 goto out_f;
505 }
506
507 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
508 pic32_uart_type(port),
509 sport->idx);
510 if (!sport->irq_rx_name) {
511 dev_err(port->dev, "%s: kasprintf err!", __func__);
512 ret = -ENOMEM;
513 goto out_f;
514 }
515 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
516 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
517 IRQF_NO_THREAD, sport->irq_rx_name, port);
518 if (ret) {
519 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
520 __func__, sport->irq_rx, ret,
521 pic32_uart_type(port));
522 goto out_r;
523 }
524
525 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
526 pic32_uart_type(port),
527 sport->idx);
528 if (!sport->irq_tx_name) {
529 dev_err(port->dev, "%s: kasprintf err!", __func__);
530 ret = -ENOMEM;
531 goto out_r;
532 }
533 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
534 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
535 IRQF_NO_THREAD, sport->irq_tx_name, port);
536 if (ret) {
537 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
538 __func__, sport->irq_tx, ret,
539 pic32_uart_type(port));
540 goto out_t;
541 }
542
543 local_irq_save(flags);
544
545 /* set rx interrupt on first receive */
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
547 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
548
549 /* set interrupt on empty */
550 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
551 PIC32_UART_STA_UTXISEL1);
552
553 /* enable all interrupts and eanable uart */
554 pic32_uart_en_and_unmask(port);
555
556 local_irq_restore(flags);
557
558 enable_irq(sport->irq_rx);
559
560 return 0;
561
562out_t:
563 free_irq(sport->irq_tx, port);
564 kfree(sport->irq_tx_name);
565out_r:
566 free_irq(sport->irq_rx, port);
567 kfree(sport->irq_rx_name);
568out_f:
569 free_irq(sport->irq_fault, port);
570 kfree(sport->irq_fault_name);
571out_disable_clk:
572 clk_disable_unprepare(sport->clk);
573out_done:
574 return ret;
575}
576
577/* serial core request to flush & disable uart */
578static void pic32_uart_shutdown(struct uart_port *port)
579{
580 struct pic32_sport *sport = to_pic32_sport(port);
581 unsigned long flags;
582
583 /* disable uart */
584 spin_lock_irqsave(&port->lock, flags);
585 pic32_uart_dsbl_and_mask(port);
586 spin_unlock_irqrestore(&port->lock, flags);
587 clk_disable_unprepare(sport->clk);
588
589 /* free all 3 interrupts for this UART */
590 free_irq(sport->irq_fault, port);
591 kfree(sport->irq_fault_name);
592 free_irq(sport->irq_tx, port);
593 kfree(sport->irq_tx_name);
594 free_irq(sport->irq_rx, port);
595 kfree(sport->irq_rx_name);
596}
597
598/* serial core request to change current uart setting */
599static void pic32_uart_set_termios(struct uart_port *port,
600 struct ktermios *new,
601 const struct ktermios *old)
602{
603 struct pic32_sport *sport = to_pic32_sport(port);
604 unsigned int baud;
605 unsigned int quot;
606 unsigned long flags;
607
608 spin_lock_irqsave(&port->lock, flags);
609
610 /* disable uart and mask all interrupts while changing speed */
611 pic32_uart_dsbl_and_mask(port);
612
613 /* stop bit options */
614 if (new->c_cflag & CSTOPB)
615 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
616 PIC32_UART_MODE_STSEL);
617 else
618 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
619 PIC32_UART_MODE_STSEL);
620
621 /* parity options */
622 if (new->c_cflag & PARENB) {
623 if (new->c_cflag & PARODD) {
624 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
625 PIC32_UART_MODE_PDSEL1);
626 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
627 PIC32_UART_MODE_PDSEL0);
628 } else {
629 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
630 PIC32_UART_MODE_PDSEL0);
631 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
632 PIC32_UART_MODE_PDSEL1);
633 }
634 } else {
635 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
636 PIC32_UART_MODE_PDSEL1 |
637 PIC32_UART_MODE_PDSEL0);
638 }
639 /* if hw flow ctrl, then the pins must be specified in device tree */
640 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
641 /* enable hardware flow control */
642 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
643 PIC32_UART_MODE_UEN1);
644 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
645 PIC32_UART_MODE_UEN0);
646 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
647 PIC32_UART_MODE_RTSMD);
648 } else {
649 /* disable hardware flow control */
650 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
651 PIC32_UART_MODE_UEN1);
652 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
653 PIC32_UART_MODE_UEN0);
654 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
655 PIC32_UART_MODE_RTSMD);
656 }
657
658 /* Always 8-bit */
659 new->c_cflag |= CS8;
660
661 /* Mark/Space parity is not supported */
662 new->c_cflag &= ~CMSPAR;
663
664 /* update baud */
665 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
666 quot = uart_get_divisor(port, baud) - 1;
667 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
668 uart_update_timeout(port, new->c_cflag, baud);
669
670 if (tty_termios_baud_rate(new))
671 tty_termios_encode_baud_rate(new, baud, baud);
672
673 /* enable uart */
674 pic32_uart_en_and_unmask(port);
675
676 spin_unlock_irqrestore(&port->lock, flags);
677}
678
679/* serial core request to claim uart iomem */
680static int pic32_uart_request_port(struct uart_port *port)
681{
682 struct platform_device *pdev = to_platform_device(port->dev);
683 struct resource *res_mem;
684
685 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 if (unlikely(!res_mem))
687 return -EINVAL;
688
689 if (!request_mem_region(port->mapbase, resource_size(res_mem),
690 "pic32_uart_mem"))
691 return -EBUSY;
692
693 port->membase = devm_ioremap(port->dev, port->mapbase,
694 resource_size(res_mem));
695 if (!port->membase) {
696 dev_err(port->dev, "Unable to map registers\n");
697 release_mem_region(port->mapbase, resource_size(res_mem));
698 return -ENOMEM;
699 }
700
701 return 0;
702}
703
704/* serial core request to release uart iomem */
705static void pic32_uart_release_port(struct uart_port *port)
706{
707 struct platform_device *pdev = to_platform_device(port->dev);
708 struct resource *res_mem;
709 unsigned int res_size;
710
711 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 if (unlikely(!res_mem))
713 return;
714 res_size = resource_size(res_mem);
715
716 release_mem_region(port->mapbase, res_size);
717}
718
719/* serial core request to do any port required auto-configuration */
720static void pic32_uart_config_port(struct uart_port *port, int flags)
721{
722 if (flags & UART_CONFIG_TYPE) {
723 if (pic32_uart_request_port(port))
724 return;
725 port->type = PORT_PIC32;
726 }
727}
728
729/* serial core request to check that port information in serinfo are suitable */
730static int pic32_uart_verify_port(struct uart_port *port,
731 struct serial_struct *serinfo)
732{
733 if (port->type != PORT_PIC32)
734 return -EINVAL;
735 if (port->irq != serinfo->irq)
736 return -EINVAL;
737 if (port->iotype != serinfo->io_type)
738 return -EINVAL;
739 if (port->mapbase != (unsigned long)serinfo->iomem_base)
740 return -EINVAL;
741
742 return 0;
743}
744
745/* serial core callbacks */
746static const struct uart_ops pic32_uart_ops = {
747 .tx_empty = pic32_uart_tx_empty,
748 .get_mctrl = pic32_uart_get_mctrl,
749 .set_mctrl = pic32_uart_set_mctrl,
750 .start_tx = pic32_uart_start_tx,
751 .stop_tx = pic32_uart_stop_tx,
752 .stop_rx = pic32_uart_stop_rx,
753 .break_ctl = pic32_uart_break_ctl,
754 .startup = pic32_uart_startup,
755 .shutdown = pic32_uart_shutdown,
756 .set_termios = pic32_uart_set_termios,
757 .type = pic32_uart_type,
758 .release_port = pic32_uart_release_port,
759 .request_port = pic32_uart_request_port,
760 .config_port = pic32_uart_config_port,
761 .verify_port = pic32_uart_verify_port,
762};
763
764#ifdef CONFIG_SERIAL_PIC32_CONSOLE
765/* output given char */
766static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
767{
768 struct pic32_sport *sport = to_pic32_sport(port);
769
770 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
771 return;
772
773 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
774 return;
775
776 /* wait for tx empty */
777 pic32_wait_deplete_txbuf(sport);
778
779 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
780}
781
782/* console core request to output given string */
783static void pic32_console_write(struct console *co, const char *s,
784 unsigned int count)
785{
786 struct pic32_sport *sport = pic32_sports[co->index];
787
788 /* call uart helper to deal with \r\n */
789 uart_console_write(&sport->port, s, count, pic32_console_putchar);
790}
791
792/* console core request to setup given console, find matching uart
793 * port and setup it.
794 */
795static int pic32_console_setup(struct console *co, char *options)
796{
797 struct pic32_sport *sport;
798 int baud = 115200;
799 int bits = 8;
800 int parity = 'n';
801 int flow = 'n';
802 int ret = 0;
803
804 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
805 return -ENODEV;
806
807 sport = pic32_sports[co->index];
808 if (!sport)
809 return -ENODEV;
810
811 ret = clk_prepare_enable(sport->clk);
812 if (ret)
813 return ret;
814
815 if (options)
816 uart_parse_options(options, &baud, &parity, &bits, &flow);
817
818 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
819}
820
821static struct uart_driver pic32_uart_driver;
822static struct console pic32_console = {
823 .name = PIC32_SDEV_NAME,
824 .write = pic32_console_write,
825 .device = uart_console_device,
826 .setup = pic32_console_setup,
827 .flags = CON_PRINTBUFFER,
828 .index = -1,
829 .data = &pic32_uart_driver,
830};
831#define PIC32_SCONSOLE (&pic32_console)
832
833static int __init pic32_console_init(void)
834{
835 register_console(&pic32_console);
836 return 0;
837}
838console_initcall(pic32_console_init);
839
840/*
841 * Late console initialization.
842 */
843static int __init pic32_late_console_init(void)
844{
845 if (!console_is_registered(&pic32_console))
846 register_console(&pic32_console);
847
848 return 0;
849}
850
851core_initcall(pic32_late_console_init);
852
853#else
854#define PIC32_SCONSOLE NULL
855#endif
856
857static struct uart_driver pic32_uart_driver = {
858 .owner = THIS_MODULE,
859 .driver_name = PIC32_DEV_NAME,
860 .dev_name = PIC32_SDEV_NAME,
861 .nr = PIC32_MAX_UARTS,
862 .cons = PIC32_SCONSOLE,
863};
864
865static int pic32_uart_probe(struct platform_device *pdev)
866{
867 struct device *dev = &pdev->dev;
868 struct device_node *np = dev->of_node;
869 struct pic32_sport *sport;
870 int uart_idx = 0;
871 struct resource *res_mem;
872 struct uart_port *port;
873 int ret;
874
875 uart_idx = of_alias_get_id(np, "serial");
876 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
877 return -EINVAL;
878
879 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880 if (!res_mem)
881 return -EINVAL;
882
883 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
884 if (!sport)
885 return -ENOMEM;
886
887 sport->idx = uart_idx;
888 sport->irq_fault = irq_of_parse_and_map(np, 0);
889 sport->irq_rx = irq_of_parse_and_map(np, 1);
890 sport->irq_tx = irq_of_parse_and_map(np, 2);
891 sport->clk = devm_clk_get(&pdev->dev, NULL);
892 sport->dev = &pdev->dev;
893
894 /* Hardware flow control: gpios
895 * !Note: Basically, CTS is needed for reading the status.
896 */
897 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
898 if (IS_ERR(sport->cts_gpiod))
899 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
900 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
901
902 pic32_sports[uart_idx] = sport;
903 port = &sport->port;
904 port->iotype = UPIO_MEM;
905 port->mapbase = res_mem->start;
906 port->ops = &pic32_uart_ops;
907 port->flags = UPF_BOOT_AUTOCONF;
908 port->dev = &pdev->dev;
909 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
910 port->uartclk = clk_get_rate(sport->clk);
911 port->line = uart_idx;
912
913 ret = uart_add_one_port(&pic32_uart_driver, port);
914 if (ret) {
915 port->membase = NULL;
916 dev_err(port->dev, "%s: uart add port error!\n", __func__);
917 goto err;
918 }
919
920#ifdef CONFIG_SERIAL_PIC32_CONSOLE
921 if (uart_console_registered(port)) {
922 /* The peripheral clock has been enabled by console_setup,
923 * so disable it till the port is used.
924 */
925 clk_disable_unprepare(sport->clk);
926 }
927#endif
928
929 platform_set_drvdata(pdev, port);
930
931 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
932 __func__, uart_idx);
933
934 return 0;
935err:
936 /* automatic unroll of sport and gpios */
937 return ret;
938}
939
940static int pic32_uart_remove(struct platform_device *pdev)
941{
942 struct uart_port *port = platform_get_drvdata(pdev);
943 struct pic32_sport *sport = to_pic32_sport(port);
944
945 uart_remove_one_port(&pic32_uart_driver, port);
946 clk_disable_unprepare(sport->clk);
947 platform_set_drvdata(pdev, NULL);
948 pic32_sports[sport->idx] = NULL;
949
950 /* automatic unroll of sport and gpios */
951 return 0;
952}
953
954static const struct of_device_id pic32_serial_dt_ids[] = {
955 { .compatible = "microchip,pic32mzda-uart" },
956 { /* sentinel */ }
957};
958MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
959
960static struct platform_driver pic32_uart_platform_driver = {
961 .probe = pic32_uart_probe,
962 .remove = pic32_uart_remove,
963 .driver = {
964 .name = PIC32_DEV_NAME,
965 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
966 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
967 },
968};
969
970static int __init pic32_uart_init(void)
971{
972 int ret;
973
974 ret = uart_register_driver(&pic32_uart_driver);
975 if (ret) {
976 pr_err("failed to register %s:%d\n",
977 pic32_uart_driver.driver_name, ret);
978 return ret;
979 }
980
981 ret = platform_driver_register(&pic32_uart_platform_driver);
982 if (ret) {
983 pr_err("fail to register pic32 uart\n");
984 uart_unregister_driver(&pic32_uart_driver);
985 }
986
987 return ret;
988}
989arch_initcall(pic32_uart_init);
990
991static void __exit pic32_uart_exit(void)
992{
993#ifdef CONFIG_SERIAL_PIC32_CONSOLE
994 unregister_console(&pic32_console);
995#endif
996 platform_driver_unregister(&pic32_uart_platform_driver);
997 uart_unregister_driver(&pic32_uart_driver);
998}
999module_exit(pic32_uart_exit);
1000
1001MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1002MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1003MODULE_LICENSE("GPL v2");