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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_device.h>
11#include <linux/of_pci.h>
12#include <linux/pci_hotplug.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/cpumask.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/hypervisor.h>
19#include <linux/irqdomain.h>
20#include <linux/pm_runtime.h>
21#include "pci.h"
22
23#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
24#define CARDBUS_RESERVE_BUSNR 3
25
26static struct resource busn_resource = {
27 .name = "PCI busn",
28 .start = 0,
29 .end = 255,
30 .flags = IORESOURCE_BUS,
31};
32
33/* Ugh. Need to stop exporting this to modules. */
34LIST_HEAD(pci_root_buses);
35EXPORT_SYMBOL(pci_root_buses);
36
37static LIST_HEAD(pci_domain_busn_res_list);
38
39struct pci_domain_busn_res {
40 struct list_head list;
41 struct resource res;
42 int domain_nr;
43};
44
45static struct resource *get_pci_domain_busn_res(int domain_nr)
46{
47 struct pci_domain_busn_res *r;
48
49 list_for_each_entry(r, &pci_domain_busn_res_list, list)
50 if (r->domain_nr == domain_nr)
51 return &r->res;
52
53 r = kzalloc(sizeof(*r), GFP_KERNEL);
54 if (!r)
55 return NULL;
56
57 r->domain_nr = domain_nr;
58 r->res.start = 0;
59 r->res.end = 0xff;
60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61
62 list_add_tail(&r->list, &pci_domain_busn_res_list);
63
64 return &r->res;
65}
66
67/*
68 * Some device drivers need know if PCI is initiated.
69 * Basically, we think PCI is not initiated when there
70 * is no device to be found on the pci_bus_type.
71 */
72int no_pci_devices(void)
73{
74 struct device *dev;
75 int no_devices;
76
77 dev = bus_find_next_device(&pci_bus_type, NULL);
78 no_devices = (dev == NULL);
79 put_device(dev);
80 return no_devices;
81}
82EXPORT_SYMBOL(no_pci_devices);
83
84/*
85 * PCI Bus Class
86 */
87static void release_pcibus_dev(struct device *dev)
88{
89 struct pci_bus *pci_bus = to_pci_bus(dev);
90
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
94 kfree(pci_bus);
95}
96
97static struct class pcibus_class = {
98 .name = "pci_bus",
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
101};
102
103static int __init pcibus_class_init(void)
104{
105 return class_register(&pcibus_class);
106}
107postcore_initcall(pcibus_class_init);
108
109static u64 pci_size(u64 base, u64 maxbase, u64 mask)
110{
111 u64 size = mask & maxbase; /* Find the significant bits */
112 if (!size)
113 return 0;
114
115 /*
116 * Get the lowest of them to find the decode size, and from that
117 * the extent.
118 */
119 size = size & ~(size-1);
120
121 /*
122 * base == maxbase can be valid only if the BAR has already been
123 * programmed with all 1s.
124 */
125 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
126 return 0;
127
128 return size;
129}
130
131static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132{
133 u32 mem_type;
134 unsigned long flags;
135
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
140 }
141
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
146
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
156 break;
157 default:
158 /* mem unknown type treated as 32-bit BAR */
159 break;
160 }
161 return flags;
162}
163
164#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
166/**
167 * pci_read_base - Read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
172 *
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 */
175int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
177{
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
180 u16 orig_cmd;
181 struct pci_bus_region region, inverted_region;
182
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
192 }
193
194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201 /*
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 * 1 must be clear.
206 */
207 if (sz == 0xffffffff)
208 sz = 0;
209
210 /*
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
213 */
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 } else {
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 }
229 } else {
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
235 }
236
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
246 }
247
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
250
251 if (!sz64)
252 goto fail;
253
254 sz64 = pci_size(l64, sz64, mask64);
255 if (!sz64) {
256 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
258 goto fail;
259 }
260
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
267 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
269 goto out;
270 }
271
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
275 res->start = 0;
276 res->end = sz64 - 1;
277 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
279 goto out;
280 }
281 }
282
283 region.start = l64;
284 region.end = l64 + sz64 - 1;
285
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288
289 /*
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
294 *
295 * resource_to_bus(bus_to_resource(A)) == A
296 *
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
299 */
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
302 res->start = 0;
303 res->end = region.end - region.start;
304 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
306 }
307
308 goto out;
309
310
311fail:
312 res->flags = 0;
313out:
314 if (res->flags)
315 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
316
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318}
319
320static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321{
322 unsigned int pos, reg;
323
324 if (dev->non_compliant_bars)
325 return;
326
327 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
328 if (dev->is_virtfn)
329 return;
330
331 for (pos = 0; pos < howmany; pos++) {
332 struct resource *res = &dev->resource[pos];
333 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
334 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
335 }
336
337 if (rom) {
338 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
339 dev->rom_base_reg = rom;
340 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
341 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
342 __pci_read_base(dev, pci_bar_mem32, res, rom);
343 }
344}
345
346static void pci_read_bridge_windows(struct pci_dev *bridge)
347{
348 u16 io;
349 u32 pmem, tmp;
350
351 pci_read_config_word(bridge, PCI_IO_BASE, &io);
352 if (!io) {
353 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
354 pci_read_config_word(bridge, PCI_IO_BASE, &io);
355 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
356 }
357 if (io)
358 bridge->io_window = 1;
359
360 /*
361 * DECchip 21050 pass 2 errata: the bridge may miss an address
362 * disconnect boundary by one PCI data phase. Workaround: do not
363 * use prefetching on this device.
364 */
365 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
366 return;
367
368 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
369 if (!pmem) {
370 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
371 0xffe0fff0);
372 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
373 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
374 }
375 if (!pmem)
376 return;
377
378 bridge->pref_window = 1;
379
380 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
381
382 /*
383 * Bridge claims to have a 64-bit prefetchable memory
384 * window; verify that the upper bits are actually
385 * writable.
386 */
387 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
388 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
389 0xffffffff);
390 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
391 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
392 if (tmp)
393 bridge->pref_64_window = 1;
394 }
395}
396
397static void pci_read_bridge_io(struct pci_bus *child)
398{
399 struct pci_dev *dev = child->self;
400 u8 io_base_lo, io_limit_lo;
401 unsigned long io_mask, io_granularity, base, limit;
402 struct pci_bus_region region;
403 struct resource *res;
404
405 io_mask = PCI_IO_RANGE_MASK;
406 io_granularity = 0x1000;
407 if (dev->io_window_1k) {
408 /* Support 1K I/O space granularity */
409 io_mask = PCI_IO_1K_RANGE_MASK;
410 io_granularity = 0x400;
411 }
412
413 res = child->resource[0];
414 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
415 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
416 base = (io_base_lo & io_mask) << 8;
417 limit = (io_limit_lo & io_mask) << 8;
418
419 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
420 u16 io_base_hi, io_limit_hi;
421
422 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
423 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
424 base |= ((unsigned long) io_base_hi << 16);
425 limit |= ((unsigned long) io_limit_hi << 16);
426 }
427
428 if (base <= limit) {
429 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
430 region.start = base;
431 region.end = limit + io_granularity - 1;
432 pcibios_bus_to_resource(dev->bus, res, ®ion);
433 pci_info(dev, " bridge window %pR\n", res);
434 }
435}
436
437static void pci_read_bridge_mmio(struct pci_bus *child)
438{
439 struct pci_dev *dev = child->self;
440 u16 mem_base_lo, mem_limit_lo;
441 unsigned long base, limit;
442 struct pci_bus_region region;
443 struct resource *res;
444
445 res = child->resource[1];
446 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
447 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
448 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
449 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 if (base <= limit) {
451 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
452 region.start = base;
453 region.end = limit + 0xfffff;
454 pcibios_bus_to_resource(dev->bus, res, ®ion);
455 pci_info(dev, " bridge window %pR\n", res);
456 }
457}
458
459static void pci_read_bridge_mmio_pref(struct pci_bus *child)
460{
461 struct pci_dev *dev = child->self;
462 u16 mem_base_lo, mem_limit_lo;
463 u64 base64, limit64;
464 pci_bus_addr_t base, limit;
465 struct pci_bus_region region;
466 struct resource *res;
467
468 res = child->resource[2];
469 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
470 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
471 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
472 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
473
474 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
475 u32 mem_base_hi, mem_limit_hi;
476
477 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
478 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
479
480 /*
481 * Some bridges set the base > limit by default, and some
482 * (broken) BIOSes do not initialize them. If we find
483 * this, just assume they are not being used.
484 */
485 if (mem_base_hi <= mem_limit_hi) {
486 base64 |= (u64) mem_base_hi << 32;
487 limit64 |= (u64) mem_limit_hi << 32;
488 }
489 }
490
491 base = (pci_bus_addr_t) base64;
492 limit = (pci_bus_addr_t) limit64;
493
494 if (base != base64) {
495 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
496 (unsigned long long) base64);
497 return;
498 }
499
500 if (base <= limit) {
501 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
502 IORESOURCE_MEM | IORESOURCE_PREFETCH;
503 if (res->flags & PCI_PREF_RANGE_TYPE_64)
504 res->flags |= IORESOURCE_MEM_64;
505 region.start = base;
506 region.end = limit + 0xfffff;
507 pcibios_bus_to_resource(dev->bus, res, ®ion);
508 pci_info(dev, " bridge window %pR\n", res);
509 }
510}
511
512void pci_read_bridge_bases(struct pci_bus *child)
513{
514 struct pci_dev *dev = child->self;
515 struct resource *res;
516 int i;
517
518 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
519 return;
520
521 pci_info(dev, "PCI bridge to %pR%s\n",
522 &child->busn_res,
523 dev->transparent ? " (subtractive decode)" : "");
524
525 pci_bus_remove_resources(child);
526 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
527 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
528
529 pci_read_bridge_io(child);
530 pci_read_bridge_mmio(child);
531 pci_read_bridge_mmio_pref(child);
532
533 if (dev->transparent) {
534 pci_bus_for_each_resource(child->parent, res, i) {
535 if (res && res->flags) {
536 pci_bus_add_resource(child, res,
537 PCI_SUBTRACTIVE_DECODE);
538 pci_info(dev, " bridge window %pR (subtractive decode)\n",
539 res);
540 }
541 }
542 }
543}
544
545static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
546{
547 struct pci_bus *b;
548
549 b = kzalloc(sizeof(*b), GFP_KERNEL);
550 if (!b)
551 return NULL;
552
553 INIT_LIST_HEAD(&b->node);
554 INIT_LIST_HEAD(&b->children);
555 INIT_LIST_HEAD(&b->devices);
556 INIT_LIST_HEAD(&b->slots);
557 INIT_LIST_HEAD(&b->resources);
558 b->max_bus_speed = PCI_SPEED_UNKNOWN;
559 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
560#ifdef CONFIG_PCI_DOMAINS_GENERIC
561 if (parent)
562 b->domain_nr = parent->domain_nr;
563#endif
564 return b;
565}
566
567static void devm_pci_release_host_bridge_dev(struct device *dev)
568{
569 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
570
571 if (bridge->release_fn)
572 bridge->release_fn(bridge);
573
574 pci_free_resource_list(&bridge->windows);
575}
576
577static void pci_release_host_bridge_dev(struct device *dev)
578{
579 devm_pci_release_host_bridge_dev(dev);
580 kfree(to_pci_host_bridge(dev));
581}
582
583static void pci_init_host_bridge(struct pci_host_bridge *bridge)
584{
585 INIT_LIST_HEAD(&bridge->windows);
586 INIT_LIST_HEAD(&bridge->dma_ranges);
587
588 /*
589 * We assume we can manage these PCIe features. Some systems may
590 * reserve these for use by the platform itself, e.g., an ACPI BIOS
591 * may implement its own AER handling and use _OSC to prevent the
592 * OS from interfering.
593 */
594 bridge->native_aer = 1;
595 bridge->native_pcie_hotplug = 1;
596 bridge->native_shpc_hotplug = 1;
597 bridge->native_pme = 1;
598 bridge->native_ltr = 1;
599}
600
601struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
602{
603 struct pci_host_bridge *bridge;
604
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
606 if (!bridge)
607 return NULL;
608
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
611
612 return bridge;
613}
614EXPORT_SYMBOL(pci_alloc_host_bridge);
615
616struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
617 size_t priv)
618{
619 struct pci_host_bridge *bridge;
620
621 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
622 if (!bridge)
623 return NULL;
624
625 pci_init_host_bridge(bridge);
626 bridge->dev.release = devm_pci_release_host_bridge_dev;
627
628 return bridge;
629}
630EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
631
632void pci_free_host_bridge(struct pci_host_bridge *bridge)
633{
634 pci_free_resource_list(&bridge->windows);
635 pci_free_resource_list(&bridge->dma_ranges);
636
637 kfree(bridge);
638}
639EXPORT_SYMBOL(pci_free_host_bridge);
640
641static const unsigned char pcix_bus_speed[] = {
642 PCI_SPEED_UNKNOWN, /* 0 */
643 PCI_SPEED_66MHz_PCIX, /* 1 */
644 PCI_SPEED_100MHz_PCIX, /* 2 */
645 PCI_SPEED_133MHz_PCIX, /* 3 */
646 PCI_SPEED_UNKNOWN, /* 4 */
647 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
648 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
649 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
650 PCI_SPEED_UNKNOWN, /* 8 */
651 PCI_SPEED_66MHz_PCIX_266, /* 9 */
652 PCI_SPEED_100MHz_PCIX_266, /* A */
653 PCI_SPEED_133MHz_PCIX_266, /* B */
654 PCI_SPEED_UNKNOWN, /* C */
655 PCI_SPEED_66MHz_PCIX_533, /* D */
656 PCI_SPEED_100MHz_PCIX_533, /* E */
657 PCI_SPEED_133MHz_PCIX_533 /* F */
658};
659
660const unsigned char pcie_link_speed[] = {
661 PCI_SPEED_UNKNOWN, /* 0 */
662 PCIE_SPEED_2_5GT, /* 1 */
663 PCIE_SPEED_5_0GT, /* 2 */
664 PCIE_SPEED_8_0GT, /* 3 */
665 PCIE_SPEED_16_0GT, /* 4 */
666 PCIE_SPEED_32_0GT, /* 5 */
667 PCI_SPEED_UNKNOWN, /* 6 */
668 PCI_SPEED_UNKNOWN, /* 7 */
669 PCI_SPEED_UNKNOWN, /* 8 */
670 PCI_SPEED_UNKNOWN, /* 9 */
671 PCI_SPEED_UNKNOWN, /* A */
672 PCI_SPEED_UNKNOWN, /* B */
673 PCI_SPEED_UNKNOWN, /* C */
674 PCI_SPEED_UNKNOWN, /* D */
675 PCI_SPEED_UNKNOWN, /* E */
676 PCI_SPEED_UNKNOWN /* F */
677};
678
679void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
680{
681 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
682}
683EXPORT_SYMBOL_GPL(pcie_update_link_speed);
684
685static unsigned char agp_speeds[] = {
686 AGP_UNKNOWN,
687 AGP_1X,
688 AGP_2X,
689 AGP_4X,
690 AGP_8X
691};
692
693static enum pci_bus_speed agp_speed(int agp3, int agpstat)
694{
695 int index = 0;
696
697 if (agpstat & 4)
698 index = 3;
699 else if (agpstat & 2)
700 index = 2;
701 else if (agpstat & 1)
702 index = 1;
703 else
704 goto out;
705
706 if (agp3) {
707 index += 2;
708 if (index == 5)
709 index = 0;
710 }
711
712 out:
713 return agp_speeds[index];
714}
715
716static void pci_set_bus_speed(struct pci_bus *bus)
717{
718 struct pci_dev *bridge = bus->self;
719 int pos;
720
721 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
722 if (!pos)
723 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
724 if (pos) {
725 u32 agpstat, agpcmd;
726
727 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
728 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
729
730 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
731 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
732 }
733
734 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
735 if (pos) {
736 u16 status;
737 enum pci_bus_speed max;
738
739 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
740 &status);
741
742 if (status & PCI_X_SSTATUS_533MHZ) {
743 max = PCI_SPEED_133MHz_PCIX_533;
744 } else if (status & PCI_X_SSTATUS_266MHZ) {
745 max = PCI_SPEED_133MHz_PCIX_266;
746 } else if (status & PCI_X_SSTATUS_133MHZ) {
747 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
748 max = PCI_SPEED_133MHz_PCIX_ECC;
749 else
750 max = PCI_SPEED_133MHz_PCIX;
751 } else {
752 max = PCI_SPEED_66MHz_PCIX;
753 }
754
755 bus->max_bus_speed = max;
756 bus->cur_bus_speed = pcix_bus_speed[
757 (status & PCI_X_SSTATUS_FREQ) >> 6];
758
759 return;
760 }
761
762 if (pci_is_pcie(bridge)) {
763 u32 linkcap;
764 u16 linksta;
765
766 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
767 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
768 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
769
770 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
771 pcie_update_link_speed(bus, linksta);
772 }
773}
774
775static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
776{
777 struct irq_domain *d;
778
779 /*
780 * Any firmware interface that can resolve the msi_domain
781 * should be called from here.
782 */
783 d = pci_host_bridge_of_msi_domain(bus);
784 if (!d)
785 d = pci_host_bridge_acpi_msi_domain(bus);
786
787#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
788 /*
789 * If no IRQ domain was found via the OF tree, try looking it up
790 * directly through the fwnode_handle.
791 */
792 if (!d) {
793 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
794
795 if (fwnode)
796 d = irq_find_matching_fwnode(fwnode,
797 DOMAIN_BUS_PCI_MSI);
798 }
799#endif
800
801 return d;
802}
803
804static void pci_set_bus_msi_domain(struct pci_bus *bus)
805{
806 struct irq_domain *d;
807 struct pci_bus *b;
808
809 /*
810 * The bus can be a root bus, a subordinate bus, or a virtual bus
811 * created by an SR-IOV device. Walk up to the first bridge device
812 * found or derive the domain from the host bridge.
813 */
814 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
815 if (b->self)
816 d = dev_get_msi_domain(&b->self->dev);
817 }
818
819 if (!d)
820 d = pci_host_bridge_msi_domain(b);
821
822 dev_set_msi_domain(&bus->dev, d);
823}
824
825static int pci_register_host_bridge(struct pci_host_bridge *bridge)
826{
827 struct device *parent = bridge->dev.parent;
828 struct resource_entry *window, *n;
829 struct pci_bus *bus, *b;
830 resource_size_t offset;
831 LIST_HEAD(resources);
832 struct resource *res;
833 char addr[64], *fmt;
834 const char *name;
835 int err;
836
837 bus = pci_alloc_bus(NULL);
838 if (!bus)
839 return -ENOMEM;
840
841 bridge->bus = bus;
842
843 /* Temporarily move resources off the list */
844 list_splice_init(&bridge->windows, &resources);
845 bus->sysdata = bridge->sysdata;
846 bus->msi = bridge->msi;
847 bus->ops = bridge->ops;
848 bus->number = bus->busn_res.start = bridge->busnr;
849#ifdef CONFIG_PCI_DOMAINS_GENERIC
850 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
851#endif
852
853 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
854 if (b) {
855 /* Ignore it if we already got here via a different bridge */
856 dev_dbg(&b->dev, "bus already known\n");
857 err = -EEXIST;
858 goto free;
859 }
860
861 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
862 bridge->busnr);
863
864 err = pcibios_root_bridge_prepare(bridge);
865 if (err)
866 goto free;
867
868 err = device_register(&bridge->dev);
869 if (err)
870 put_device(&bridge->dev);
871
872 bus->bridge = get_device(&bridge->dev);
873 device_enable_async_suspend(bus->bridge);
874 pci_set_bus_of_node(bus);
875 pci_set_bus_msi_domain(bus);
876
877 if (!parent)
878 set_dev_node(bus->bridge, pcibus_to_node(bus));
879
880 bus->dev.class = &pcibus_class;
881 bus->dev.parent = bus->bridge;
882
883 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
884 name = dev_name(&bus->dev);
885
886 err = device_register(&bus->dev);
887 if (err)
888 goto unregister;
889
890 pcibios_add_bus(bus);
891
892 /* Create legacy_io and legacy_mem files for this bus */
893 pci_create_legacy_files(bus);
894
895 if (parent)
896 dev_info(parent, "PCI host bridge to bus %s\n", name);
897 else
898 pr_info("PCI host bridge to bus %s\n", name);
899
900 /* Add initial resources to the bus */
901 resource_list_for_each_entry_safe(window, n, &resources) {
902 list_move_tail(&window->node, &bridge->windows);
903 offset = window->offset;
904 res = window->res;
905
906 if (res->flags & IORESOURCE_BUS)
907 pci_bus_insert_busn_res(bus, bus->number, res->end);
908 else
909 pci_bus_add_resource(bus, res, 0);
910
911 if (offset) {
912 if (resource_type(res) == IORESOURCE_IO)
913 fmt = " (bus address [%#06llx-%#06llx])";
914 else
915 fmt = " (bus address [%#010llx-%#010llx])";
916
917 snprintf(addr, sizeof(addr), fmt,
918 (unsigned long long)(res->start - offset),
919 (unsigned long long)(res->end - offset));
920 } else
921 addr[0] = '\0';
922
923 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
924 }
925
926 down_write(&pci_bus_sem);
927 list_add_tail(&bus->node, &pci_root_buses);
928 up_write(&pci_bus_sem);
929
930 return 0;
931
932unregister:
933 put_device(&bridge->dev);
934 device_unregister(&bridge->dev);
935
936free:
937 kfree(bus);
938 return err;
939}
940
941static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
942{
943 int pos;
944 u32 status;
945
946 /*
947 * If extended config space isn't accessible on a bridge's primary
948 * bus, we certainly can't access it on the secondary bus.
949 */
950 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
951 return false;
952
953 /*
954 * PCIe Root Ports and switch ports are PCIe on both sides, so if
955 * extended config space is accessible on the primary, it's also
956 * accessible on the secondary.
957 */
958 if (pci_is_pcie(bridge) &&
959 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
960 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
961 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
962 return true;
963
964 /*
965 * For the other bridge types:
966 * - PCI-to-PCI bridges
967 * - PCIe-to-PCI/PCI-X forward bridges
968 * - PCI/PCI-X-to-PCIe reverse bridges
969 * extended config space on the secondary side is only accessible
970 * if the bridge supports PCI-X Mode 2.
971 */
972 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
973 if (!pos)
974 return false;
975
976 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
977 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
978}
979
980static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
981 struct pci_dev *bridge, int busnr)
982{
983 struct pci_bus *child;
984 int i;
985 int ret;
986
987 /* Allocate a new bus and inherit stuff from the parent */
988 child = pci_alloc_bus(parent);
989 if (!child)
990 return NULL;
991
992 child->parent = parent;
993 child->ops = parent->ops;
994 child->msi = parent->msi;
995 child->sysdata = parent->sysdata;
996 child->bus_flags = parent->bus_flags;
997
998 /*
999 * Initialize some portions of the bus device, but don't register
1000 * it now as the parent is not properly set up yet.
1001 */
1002 child->dev.class = &pcibus_class;
1003 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1004
1005 /* Set up the primary, secondary and subordinate bus numbers */
1006 child->number = child->busn_res.start = busnr;
1007 child->primary = parent->busn_res.start;
1008 child->busn_res.end = 0xff;
1009
1010 if (!bridge) {
1011 child->dev.parent = parent->bridge;
1012 goto add_dev;
1013 }
1014
1015 child->self = bridge;
1016 child->bridge = get_device(&bridge->dev);
1017 child->dev.parent = child->bridge;
1018 pci_set_bus_of_node(child);
1019 pci_set_bus_speed(child);
1020
1021 /*
1022 * Check whether extended config space is accessible on the child
1023 * bus. Note that we currently assume it is always accessible on
1024 * the root bus.
1025 */
1026 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1027 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1028 pci_info(child, "extended config space not accessible\n");
1029 }
1030
1031 /* Set up default resource pointers and names */
1032 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1033 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1034 child->resource[i]->name = child->name;
1035 }
1036 bridge->subordinate = child;
1037
1038add_dev:
1039 pci_set_bus_msi_domain(child);
1040 ret = device_register(&child->dev);
1041 WARN_ON(ret < 0);
1042
1043 pcibios_add_bus(child);
1044
1045 if (child->ops->add_bus) {
1046 ret = child->ops->add_bus(child);
1047 if (WARN_ON(ret < 0))
1048 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1049 }
1050
1051 /* Create legacy_io and legacy_mem files for this bus */
1052 pci_create_legacy_files(child);
1053
1054 return child;
1055}
1056
1057struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1058 int busnr)
1059{
1060 struct pci_bus *child;
1061
1062 child = pci_alloc_child_bus(parent, dev, busnr);
1063 if (child) {
1064 down_write(&pci_bus_sem);
1065 list_add_tail(&child->node, &parent->children);
1066 up_write(&pci_bus_sem);
1067 }
1068 return child;
1069}
1070EXPORT_SYMBOL(pci_add_new_bus);
1071
1072static void pci_enable_crs(struct pci_dev *pdev)
1073{
1074 u16 root_cap = 0;
1075
1076 /* Enable CRS Software Visibility if supported */
1077 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1078 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1079 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1080 PCI_EXP_RTCTL_CRSSVE);
1081}
1082
1083static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1084 unsigned int available_buses);
1085/**
1086 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1087 * numbers from EA capability.
1088 * @dev: Bridge
1089 * @sec: updated with secondary bus number from EA
1090 * @sub: updated with subordinate bus number from EA
1091 *
1092 * If @dev is a bridge with EA capability, update @sec and @sub with
1093 * fixed bus numbers from the capability and return true. Otherwise,
1094 * return false.
1095 */
1096static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1097{
1098 int ea, offset;
1099 u32 dw;
1100
1101 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1102 return false;
1103
1104 /* find PCI EA capability in list */
1105 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1106 if (!ea)
1107 return false;
1108
1109 offset = ea + PCI_EA_FIRST_ENT;
1110 pci_read_config_dword(dev, offset, &dw);
1111 *sec = dw & PCI_EA_SEC_BUS_MASK;
1112 *sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1113 return true;
1114}
1115
1116/*
1117 * pci_scan_bridge_extend() - Scan buses behind a bridge
1118 * @bus: Parent bus the bridge is on
1119 * @dev: Bridge itself
1120 * @max: Starting subordinate number of buses behind this bridge
1121 * @available_buses: Total number of buses available for this bridge and
1122 * the devices below. After the minimal bus space has
1123 * been allocated the remaining buses will be
1124 * distributed equally between hotplug-capable bridges.
1125 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1126 * that need to be reconfigured.
1127 *
1128 * If it's a bridge, configure it and scan the bus behind it.
1129 * For CardBus bridges, we don't scan behind as the devices will
1130 * be handled by the bridge driver itself.
1131 *
1132 * We need to process bridges in two passes -- first we scan those
1133 * already configured by the BIOS and after we are done with all of
1134 * them, we proceed to assigning numbers to the remaining buses in
1135 * order to avoid overlaps between old and new bus numbers.
1136 *
1137 * Return: New subordinate number covering all buses behind this bridge.
1138 */
1139static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1140 int max, unsigned int available_buses,
1141 int pass)
1142{
1143 struct pci_bus *child;
1144 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1145 u32 buses, i, j = 0;
1146 u16 bctl;
1147 u8 primary, secondary, subordinate;
1148 int broken = 0;
1149 bool fixed_buses;
1150 u8 fixed_sec, fixed_sub;
1151 int next_busnr;
1152
1153 /*
1154 * Make sure the bridge is powered on to be able to access config
1155 * space of devices below it.
1156 */
1157 pm_runtime_get_sync(&dev->dev);
1158
1159 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1160 primary = buses & 0xFF;
1161 secondary = (buses >> 8) & 0xFF;
1162 subordinate = (buses >> 16) & 0xFF;
1163
1164 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1165 secondary, subordinate, pass);
1166
1167 if (!primary && (primary != bus->number) && secondary && subordinate) {
1168 pci_warn(dev, "Primary bus is hard wired to 0\n");
1169 primary = bus->number;
1170 }
1171
1172 /* Check if setup is sensible at all */
1173 if (!pass &&
1174 (primary != bus->number || secondary <= bus->number ||
1175 secondary > subordinate)) {
1176 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1177 secondary, subordinate);
1178 broken = 1;
1179 }
1180
1181 /*
1182 * Disable Master-Abort Mode during probing to avoid reporting of
1183 * bus errors in some architectures.
1184 */
1185 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1186 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1187 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1188
1189 pci_enable_crs(dev);
1190
1191 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1192 !is_cardbus && !broken) {
1193 unsigned int cmax;
1194
1195 /*
1196 * Bus already configured by firmware, process it in the
1197 * first pass and just note the configuration.
1198 */
1199 if (pass)
1200 goto out;
1201
1202 /*
1203 * The bus might already exist for two reasons: Either we
1204 * are rescanning the bus or the bus is reachable through
1205 * more than one bridge. The second case can happen with
1206 * the i450NX chipset.
1207 */
1208 child = pci_find_bus(pci_domain_nr(bus), secondary);
1209 if (!child) {
1210 child = pci_add_new_bus(bus, dev, secondary);
1211 if (!child)
1212 goto out;
1213 child->primary = primary;
1214 pci_bus_insert_busn_res(child, secondary, subordinate);
1215 child->bridge_ctl = bctl;
1216 }
1217
1218 cmax = pci_scan_child_bus(child);
1219 if (cmax > subordinate)
1220 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1221 subordinate, cmax);
1222
1223 /* Subordinate should equal child->busn_res.end */
1224 if (subordinate > max)
1225 max = subordinate;
1226 } else {
1227
1228 /*
1229 * We need to assign a number to this bus which we always
1230 * do in the second pass.
1231 */
1232 if (!pass) {
1233 if (pcibios_assign_all_busses() || broken || is_cardbus)
1234
1235 /*
1236 * Temporarily disable forwarding of the
1237 * configuration cycles on all bridges in
1238 * this bus segment to avoid possible
1239 * conflicts in the second pass between two
1240 * bridges programmed with overlapping bus
1241 * ranges.
1242 */
1243 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1244 buses & ~0xffffff);
1245 goto out;
1246 }
1247
1248 /* Clear errors */
1249 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1250
1251 /* Read bus numbers from EA Capability (if present) */
1252 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1253 if (fixed_buses)
1254 next_busnr = fixed_sec;
1255 else
1256 next_busnr = max + 1;
1257
1258 /*
1259 * Prevent assigning a bus number that already exists.
1260 * This can happen when a bridge is hot-plugged, so in this
1261 * case we only re-scan this bus.
1262 */
1263 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1264 if (!child) {
1265 child = pci_add_new_bus(bus, dev, next_busnr);
1266 if (!child)
1267 goto out;
1268 pci_bus_insert_busn_res(child, next_busnr,
1269 bus->busn_res.end);
1270 }
1271 max++;
1272 if (available_buses)
1273 available_buses--;
1274
1275 buses = (buses & 0xff000000)
1276 | ((unsigned int)(child->primary) << 0)
1277 | ((unsigned int)(child->busn_res.start) << 8)
1278 | ((unsigned int)(child->busn_res.end) << 16);
1279
1280 /*
1281 * yenta.c forces a secondary latency timer of 176.
1282 * Copy that behaviour here.
1283 */
1284 if (is_cardbus) {
1285 buses &= ~0xff000000;
1286 buses |= CARDBUS_LATENCY_TIMER << 24;
1287 }
1288
1289 /* We need to blast all three values with a single write */
1290 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1291
1292 if (!is_cardbus) {
1293 child->bridge_ctl = bctl;
1294 max = pci_scan_child_bus_extend(child, available_buses);
1295 } else {
1296
1297 /*
1298 * For CardBus bridges, we leave 4 bus numbers as
1299 * cards with a PCI-to-PCI bridge can be inserted
1300 * later.
1301 */
1302 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1303 struct pci_bus *parent = bus;
1304 if (pci_find_bus(pci_domain_nr(bus),
1305 max+i+1))
1306 break;
1307 while (parent->parent) {
1308 if ((!pcibios_assign_all_busses()) &&
1309 (parent->busn_res.end > max) &&
1310 (parent->busn_res.end <= max+i)) {
1311 j = 1;
1312 }
1313 parent = parent->parent;
1314 }
1315 if (j) {
1316
1317 /*
1318 * Often, there are two CardBus
1319 * bridges -- try to leave one
1320 * valid bus number for each one.
1321 */
1322 i /= 2;
1323 break;
1324 }
1325 }
1326 max += i;
1327 }
1328
1329 /*
1330 * Set subordinate bus number to its real value.
1331 * If fixed subordinate bus number exists from EA
1332 * capability then use it.
1333 */
1334 if (fixed_buses)
1335 max = fixed_sub;
1336 pci_bus_update_busn_res_end(child, max);
1337 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1338 }
1339
1340 sprintf(child->name,
1341 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1342 pci_domain_nr(bus), child->number);
1343
1344 /* Check that all devices are accessible */
1345 while (bus->parent) {
1346 if ((child->busn_res.end > bus->busn_res.end) ||
1347 (child->number > bus->busn_res.end) ||
1348 (child->number < bus->number) ||
1349 (child->busn_res.end < bus->number)) {
1350 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1351 &child->busn_res);
1352 break;
1353 }
1354 bus = bus->parent;
1355 }
1356
1357out:
1358 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1359
1360 pm_runtime_put(&dev->dev);
1361
1362 return max;
1363}
1364
1365/*
1366 * pci_scan_bridge() - Scan buses behind a bridge
1367 * @bus: Parent bus the bridge is on
1368 * @dev: Bridge itself
1369 * @max: Starting subordinate number of buses behind this bridge
1370 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1371 * that need to be reconfigured.
1372 *
1373 * If it's a bridge, configure it and scan the bus behind it.
1374 * For CardBus bridges, we don't scan behind as the devices will
1375 * be handled by the bridge driver itself.
1376 *
1377 * We need to process bridges in two passes -- first we scan those
1378 * already configured by the BIOS and after we are done with all of
1379 * them, we proceed to assigning numbers to the remaining buses in
1380 * order to avoid overlaps between old and new bus numbers.
1381 *
1382 * Return: New subordinate number covering all buses behind this bridge.
1383 */
1384int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1385{
1386 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1387}
1388EXPORT_SYMBOL(pci_scan_bridge);
1389
1390/*
1391 * Read interrupt line and base address registers.
1392 * The architecture-dependent code can tweak these, of course.
1393 */
1394static void pci_read_irq(struct pci_dev *dev)
1395{
1396 unsigned char irq;
1397
1398 /* VFs are not allowed to use INTx, so skip the config reads */
1399 if (dev->is_virtfn) {
1400 dev->pin = 0;
1401 dev->irq = 0;
1402 return;
1403 }
1404
1405 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1406 dev->pin = irq;
1407 if (irq)
1408 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1409 dev->irq = irq;
1410}
1411
1412void set_pcie_port_type(struct pci_dev *pdev)
1413{
1414 int pos;
1415 u16 reg16;
1416 int type;
1417 struct pci_dev *parent;
1418
1419 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1420 if (!pos)
1421 return;
1422
1423 pdev->pcie_cap = pos;
1424 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1425 pdev->pcie_flags_reg = reg16;
1426 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1427 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1428
1429 parent = pci_upstream_bridge(pdev);
1430 if (!parent)
1431 return;
1432
1433 /*
1434 * Some systems do not identify their upstream/downstream ports
1435 * correctly so detect impossible configurations here and correct
1436 * the port type accordingly.
1437 */
1438 type = pci_pcie_type(pdev);
1439 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1440 /*
1441 * If pdev claims to be downstream port but the parent
1442 * device is also downstream port assume pdev is actually
1443 * upstream port.
1444 */
1445 if (pcie_downstream_port(parent)) {
1446 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1447 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1448 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1449 }
1450 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1451 /*
1452 * If pdev claims to be upstream port but the parent
1453 * device is also upstream port assume pdev is actually
1454 * downstream port.
1455 */
1456 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1457 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1458 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1459 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1460 }
1461 }
1462}
1463
1464void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1465{
1466 u32 reg32;
1467
1468 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1469 if (reg32 & PCI_EXP_SLTCAP_HPC)
1470 pdev->is_hotplug_bridge = 1;
1471}
1472
1473static void set_pcie_thunderbolt(struct pci_dev *dev)
1474{
1475 int vsec = 0;
1476 u32 header;
1477
1478 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1479 PCI_EXT_CAP_ID_VNDR))) {
1480 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1481
1482 /* Is the device part of a Thunderbolt controller? */
1483 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1484 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1485 dev->is_thunderbolt = 1;
1486 return;
1487 }
1488 }
1489}
1490
1491static void set_pcie_untrusted(struct pci_dev *dev)
1492{
1493 struct pci_dev *parent;
1494
1495 /*
1496 * If the upstream bridge is untrusted we treat this device
1497 * untrusted as well.
1498 */
1499 parent = pci_upstream_bridge(dev);
1500 if (parent && parent->untrusted)
1501 dev->untrusted = true;
1502}
1503
1504/**
1505 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1506 * @dev: PCI device
1507 *
1508 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1509 * when forwarding a type1 configuration request the bridge must check that
1510 * the extended register address field is zero. The bridge is not permitted
1511 * to forward the transactions and must handle it as an Unsupported Request.
1512 * Some bridges do not follow this rule and simply drop the extended register
1513 * bits, resulting in the standard config space being aliased, every 256
1514 * bytes across the entire configuration space. Test for this condition by
1515 * comparing the first dword of each potential alias to the vendor/device ID.
1516 * Known offenders:
1517 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1518 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1519 */
1520static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1521{
1522#ifdef CONFIG_PCI_QUIRKS
1523 int pos;
1524 u32 header, tmp;
1525
1526 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1527
1528 for (pos = PCI_CFG_SPACE_SIZE;
1529 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1530 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1531 || header != tmp)
1532 return false;
1533 }
1534
1535 return true;
1536#else
1537 return false;
1538#endif
1539}
1540
1541/**
1542 * pci_cfg_space_size - Get the configuration space size of the PCI device
1543 * @dev: PCI device
1544 *
1545 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1546 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1547 * access it. Maybe we don't have a way to generate extended config space
1548 * accesses, or the device is behind a reverse Express bridge. So we try
1549 * reading the dword at 0x100 which must either be 0 or a valid extended
1550 * capability header.
1551 */
1552static int pci_cfg_space_size_ext(struct pci_dev *dev)
1553{
1554 u32 status;
1555 int pos = PCI_CFG_SPACE_SIZE;
1556
1557 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1558 return PCI_CFG_SPACE_SIZE;
1559 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1560 return PCI_CFG_SPACE_SIZE;
1561
1562 return PCI_CFG_SPACE_EXP_SIZE;
1563}
1564
1565int pci_cfg_space_size(struct pci_dev *dev)
1566{
1567 int pos;
1568 u32 status;
1569 u16 class;
1570
1571#ifdef CONFIG_PCI_IOV
1572 /*
1573 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1574 * implement a PCIe capability and therefore must implement extended
1575 * config space. We can skip the NO_EXTCFG test below and the
1576 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1577 * the fact that the SR-IOV capability on the PF resides in extended
1578 * config space and must be accessible and non-aliased to have enabled
1579 * support for this VF. This is a micro performance optimization for
1580 * systems supporting many VFs.
1581 */
1582 if (dev->is_virtfn)
1583 return PCI_CFG_SPACE_EXP_SIZE;
1584#endif
1585
1586 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1587 return PCI_CFG_SPACE_SIZE;
1588
1589 class = dev->class >> 8;
1590 if (class == PCI_CLASS_BRIDGE_HOST)
1591 return pci_cfg_space_size_ext(dev);
1592
1593 if (pci_is_pcie(dev))
1594 return pci_cfg_space_size_ext(dev);
1595
1596 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1597 if (!pos)
1598 return PCI_CFG_SPACE_SIZE;
1599
1600 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1601 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1602 return pci_cfg_space_size_ext(dev);
1603
1604 return PCI_CFG_SPACE_SIZE;
1605}
1606
1607static u32 pci_class(struct pci_dev *dev)
1608{
1609 u32 class;
1610
1611#ifdef CONFIG_PCI_IOV
1612 if (dev->is_virtfn)
1613 return dev->physfn->sriov->class;
1614#endif
1615 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1616 return class;
1617}
1618
1619static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1620{
1621#ifdef CONFIG_PCI_IOV
1622 if (dev->is_virtfn) {
1623 *vendor = dev->physfn->sriov->subsystem_vendor;
1624 *device = dev->physfn->sriov->subsystem_device;
1625 return;
1626 }
1627#endif
1628 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1629 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1630}
1631
1632static u8 pci_hdr_type(struct pci_dev *dev)
1633{
1634 u8 hdr_type;
1635
1636#ifdef CONFIG_PCI_IOV
1637 if (dev->is_virtfn)
1638 return dev->physfn->sriov->hdr_type;
1639#endif
1640 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1641 return hdr_type;
1642}
1643
1644#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1645
1646static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1647{
1648 /*
1649 * Disable the MSI hardware to avoid screaming interrupts
1650 * during boot. This is the power on reset default so
1651 * usually this should be a noop.
1652 */
1653 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1654 if (dev->msi_cap)
1655 pci_msi_set_enable(dev, 0);
1656
1657 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1658 if (dev->msix_cap)
1659 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1660}
1661
1662/**
1663 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1664 * @dev: PCI device
1665 *
1666 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1667 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1668 */
1669static int pci_intx_mask_broken(struct pci_dev *dev)
1670{
1671 u16 orig, toggle, new;
1672
1673 pci_read_config_word(dev, PCI_COMMAND, &orig);
1674 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1675 pci_write_config_word(dev, PCI_COMMAND, toggle);
1676 pci_read_config_word(dev, PCI_COMMAND, &new);
1677
1678 pci_write_config_word(dev, PCI_COMMAND, orig);
1679
1680 /*
1681 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1682 * r2.3, so strictly speaking, a device is not *broken* if it's not
1683 * writable. But we'll live with the misnomer for now.
1684 */
1685 if (new != toggle)
1686 return 1;
1687 return 0;
1688}
1689
1690static void early_dump_pci_device(struct pci_dev *pdev)
1691{
1692 u32 value[256 / 4];
1693 int i;
1694
1695 pci_info(pdev, "config space:\n");
1696
1697 for (i = 0; i < 256; i += 4)
1698 pci_read_config_dword(pdev, i, &value[i / 4]);
1699
1700 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1701 value, 256, false);
1702}
1703
1704/**
1705 * pci_setup_device - Fill in class and map information of a device
1706 * @dev: the device structure to fill
1707 *
1708 * Initialize the device structure with information about the device's
1709 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1710 * Called at initialisation of the PCI subsystem and by CardBus services.
1711 * Returns 0 on success and negative if unknown type of device (not normal,
1712 * bridge or CardBus).
1713 */
1714int pci_setup_device(struct pci_dev *dev)
1715{
1716 u32 class;
1717 u16 cmd;
1718 u8 hdr_type;
1719 int pos = 0;
1720 struct pci_bus_region region;
1721 struct resource *res;
1722
1723 hdr_type = pci_hdr_type(dev);
1724
1725 dev->sysdata = dev->bus->sysdata;
1726 dev->dev.parent = dev->bus->bridge;
1727 dev->dev.bus = &pci_bus_type;
1728 dev->hdr_type = hdr_type & 0x7f;
1729 dev->multifunction = !!(hdr_type & 0x80);
1730 dev->error_state = pci_channel_io_normal;
1731 set_pcie_port_type(dev);
1732
1733 pci_dev_assign_slot(dev);
1734
1735 /*
1736 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1737 * set this higher, assuming the system even supports it.
1738 */
1739 dev->dma_mask = 0xffffffff;
1740
1741 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1742 dev->bus->number, PCI_SLOT(dev->devfn),
1743 PCI_FUNC(dev->devfn));
1744
1745 class = pci_class(dev);
1746
1747 dev->revision = class & 0xff;
1748 dev->class = class >> 8; /* upper 3 bytes */
1749
1750 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1751 dev->vendor, dev->device, dev->hdr_type, dev->class);
1752
1753 if (pci_early_dump)
1754 early_dump_pci_device(dev);
1755
1756 /* Need to have dev->class ready */
1757 dev->cfg_size = pci_cfg_space_size(dev);
1758
1759 /* Need to have dev->cfg_size ready */
1760 set_pcie_thunderbolt(dev);
1761
1762 set_pcie_untrusted(dev);
1763
1764 /* "Unknown power state" */
1765 dev->current_state = PCI_UNKNOWN;
1766
1767 /* Early fixups, before probing the BARs */
1768 pci_fixup_device(pci_fixup_early, dev);
1769
1770 /* Device class may be changed after fixup */
1771 class = dev->class >> 8;
1772
1773 if (dev->non_compliant_bars) {
1774 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1775 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1776 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1777 cmd &= ~PCI_COMMAND_IO;
1778 cmd &= ~PCI_COMMAND_MEMORY;
1779 pci_write_config_word(dev, PCI_COMMAND, cmd);
1780 }
1781 }
1782
1783 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1784
1785 switch (dev->hdr_type) { /* header type */
1786 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1787 if (class == PCI_CLASS_BRIDGE_PCI)
1788 goto bad;
1789 pci_read_irq(dev);
1790 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1791
1792 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1793
1794 /*
1795 * Do the ugly legacy mode stuff here rather than broken chip
1796 * quirk code. Legacy mode ATA controllers have fixed
1797 * addresses. These are not always echoed in BAR0-3, and
1798 * BAR0-3 in a few cases contain junk!
1799 */
1800 if (class == PCI_CLASS_STORAGE_IDE) {
1801 u8 progif;
1802 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1803 if ((progif & 1) == 0) {
1804 region.start = 0x1F0;
1805 region.end = 0x1F7;
1806 res = &dev->resource[0];
1807 res->flags = LEGACY_IO_RESOURCE;
1808 pcibios_bus_to_resource(dev->bus, res, ®ion);
1809 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1810 res);
1811 region.start = 0x3F6;
1812 region.end = 0x3F6;
1813 res = &dev->resource[1];
1814 res->flags = LEGACY_IO_RESOURCE;
1815 pcibios_bus_to_resource(dev->bus, res, ®ion);
1816 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1817 res);
1818 }
1819 if ((progif & 4) == 0) {
1820 region.start = 0x170;
1821 region.end = 0x177;
1822 res = &dev->resource[2];
1823 res->flags = LEGACY_IO_RESOURCE;
1824 pcibios_bus_to_resource(dev->bus, res, ®ion);
1825 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1826 res);
1827 region.start = 0x376;
1828 region.end = 0x376;
1829 res = &dev->resource[3];
1830 res->flags = LEGACY_IO_RESOURCE;
1831 pcibios_bus_to_resource(dev->bus, res, ®ion);
1832 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1833 res);
1834 }
1835 }
1836 break;
1837
1838 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1839 /*
1840 * The PCI-to-PCI bridge spec requires that subtractive
1841 * decoding (i.e. transparent) bridge must have programming
1842 * interface code of 0x01.
1843 */
1844 pci_read_irq(dev);
1845 dev->transparent = ((dev->class & 0xff) == 1);
1846 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1847 pci_read_bridge_windows(dev);
1848 set_pcie_hotplug_bridge(dev);
1849 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1850 if (pos) {
1851 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1852 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1853 }
1854 break;
1855
1856 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1857 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1858 goto bad;
1859 pci_read_irq(dev);
1860 pci_read_bases(dev, 1, 0);
1861 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1862 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1863 break;
1864
1865 default: /* unknown header */
1866 pci_err(dev, "unknown header type %02x, ignoring device\n",
1867 dev->hdr_type);
1868 return -EIO;
1869
1870 bad:
1871 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1872 dev->class, dev->hdr_type);
1873 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1874 }
1875
1876 /* We found a fine healthy device, go go go... */
1877 return 0;
1878}
1879
1880static void pci_configure_mps(struct pci_dev *dev)
1881{
1882 struct pci_dev *bridge = pci_upstream_bridge(dev);
1883 int mps, mpss, p_mps, rc;
1884
1885 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1886 return;
1887
1888 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1889 if (dev->is_virtfn)
1890 return;
1891
1892 mps = pcie_get_mps(dev);
1893 p_mps = pcie_get_mps(bridge);
1894
1895 if (mps == p_mps)
1896 return;
1897
1898 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1899 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1900 mps, pci_name(bridge), p_mps);
1901 return;
1902 }
1903
1904 /*
1905 * Fancier MPS configuration is done later by
1906 * pcie_bus_configure_settings()
1907 */
1908 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1909 return;
1910
1911 mpss = 128 << dev->pcie_mpss;
1912 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1913 pcie_set_mps(bridge, mpss);
1914 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1915 mpss, p_mps, 128 << bridge->pcie_mpss);
1916 p_mps = pcie_get_mps(bridge);
1917 }
1918
1919 rc = pcie_set_mps(dev, p_mps);
1920 if (rc) {
1921 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1922 p_mps);
1923 return;
1924 }
1925
1926 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1927 p_mps, mps, mpss);
1928}
1929
1930int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1931{
1932 struct pci_host_bridge *host;
1933 u32 cap;
1934 u16 ctl;
1935 int ret;
1936
1937 if (!pci_is_pcie(dev))
1938 return 0;
1939
1940 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1941 if (ret)
1942 return 0;
1943
1944 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1945 return 0;
1946
1947 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1948 if (ret)
1949 return 0;
1950
1951 host = pci_find_host_bridge(dev->bus);
1952 if (!host)
1953 return 0;
1954
1955 /*
1956 * If some device in the hierarchy doesn't handle Extended Tags
1957 * correctly, make sure they're disabled.
1958 */
1959 if (host->no_ext_tags) {
1960 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1961 pci_info(dev, "disabling Extended Tags\n");
1962 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1963 PCI_EXP_DEVCTL_EXT_TAG);
1964 }
1965 return 0;
1966 }
1967
1968 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1969 pci_info(dev, "enabling Extended Tags\n");
1970 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1971 PCI_EXP_DEVCTL_EXT_TAG);
1972 }
1973 return 0;
1974}
1975
1976/**
1977 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1978 * @dev: PCI device to query
1979 *
1980 * Returns true if the device has enabled relaxed ordering attribute.
1981 */
1982bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1983{
1984 u16 v;
1985
1986 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1987
1988 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1989}
1990EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1991
1992static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1993{
1994 struct pci_dev *root;
1995
1996 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1997 if (dev->is_virtfn)
1998 return;
1999
2000 if (!pcie_relaxed_ordering_enabled(dev))
2001 return;
2002
2003 /*
2004 * For now, we only deal with Relaxed Ordering issues with Root
2005 * Ports. Peer-to-Peer DMA is another can of worms.
2006 */
2007 root = pci_find_pcie_root_port(dev);
2008 if (!root)
2009 return;
2010
2011 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2012 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2013 PCI_EXP_DEVCTL_RELAX_EN);
2014 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2015 }
2016}
2017
2018static void pci_configure_ltr(struct pci_dev *dev)
2019{
2020#ifdef CONFIG_PCIEASPM
2021 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2022 struct pci_dev *bridge;
2023 u32 cap, ctl;
2024
2025 if (!pci_is_pcie(dev))
2026 return;
2027
2028 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2029 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2030 return;
2031
2032 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2033 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2034 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2035 dev->ltr_path = 1;
2036 return;
2037 }
2038
2039 bridge = pci_upstream_bridge(dev);
2040 if (bridge && bridge->ltr_path)
2041 dev->ltr_path = 1;
2042
2043 return;
2044 }
2045
2046 if (!host->native_ltr)
2047 return;
2048
2049 /*
2050 * Software must not enable LTR in an Endpoint unless the Root
2051 * Complex and all intermediate Switches indicate support for LTR.
2052 * PCIe r4.0, sec 6.18.
2053 */
2054 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2055 ((bridge = pci_upstream_bridge(dev)) &&
2056 bridge->ltr_path)) {
2057 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2058 PCI_EXP_DEVCTL2_LTR_EN);
2059 dev->ltr_path = 1;
2060 }
2061#endif
2062}
2063
2064static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2065{
2066#ifdef CONFIG_PCI_PASID
2067 struct pci_dev *bridge;
2068 int pcie_type;
2069 u32 cap;
2070
2071 if (!pci_is_pcie(dev))
2072 return;
2073
2074 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2075 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2076 return;
2077
2078 pcie_type = pci_pcie_type(dev);
2079 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2080 pcie_type == PCI_EXP_TYPE_RC_END)
2081 dev->eetlp_prefix_path = 1;
2082 else {
2083 bridge = pci_upstream_bridge(dev);
2084 if (bridge && bridge->eetlp_prefix_path)
2085 dev->eetlp_prefix_path = 1;
2086 }
2087#endif
2088}
2089
2090static void pci_configure_serr(struct pci_dev *dev)
2091{
2092 u16 control;
2093
2094 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2095
2096 /*
2097 * A bridge will not forward ERR_ messages coming from an
2098 * endpoint unless SERR# forwarding is enabled.
2099 */
2100 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2101 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2102 control |= PCI_BRIDGE_CTL_SERR;
2103 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2104 }
2105 }
2106}
2107
2108static void pci_configure_device(struct pci_dev *dev)
2109{
2110 pci_configure_mps(dev);
2111 pci_configure_extended_tags(dev, NULL);
2112 pci_configure_relaxed_ordering(dev);
2113 pci_configure_ltr(dev);
2114 pci_configure_eetlp_prefix(dev);
2115 pci_configure_serr(dev);
2116
2117 pci_acpi_program_hp_params(dev);
2118}
2119
2120static void pci_release_capabilities(struct pci_dev *dev)
2121{
2122 pci_aer_exit(dev);
2123 pci_vpd_release(dev);
2124 pci_iov_release(dev);
2125 pci_free_cap_save_buffers(dev);
2126}
2127
2128/**
2129 * pci_release_dev - Free a PCI device structure when all users of it are
2130 * finished
2131 * @dev: device that's been disconnected
2132 *
2133 * Will be called only by the device core when all users of this PCI device are
2134 * done.
2135 */
2136static void pci_release_dev(struct device *dev)
2137{
2138 struct pci_dev *pci_dev;
2139
2140 pci_dev = to_pci_dev(dev);
2141 pci_release_capabilities(pci_dev);
2142 pci_release_of_node(pci_dev);
2143 pcibios_release_device(pci_dev);
2144 pci_bus_put(pci_dev->bus);
2145 kfree(pci_dev->driver_override);
2146 bitmap_free(pci_dev->dma_alias_mask);
2147 kfree(pci_dev);
2148}
2149
2150struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2151{
2152 struct pci_dev *dev;
2153
2154 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2155 if (!dev)
2156 return NULL;
2157
2158 INIT_LIST_HEAD(&dev->bus_list);
2159 dev->dev.type = &pci_dev_type;
2160 dev->bus = pci_bus_get(bus);
2161
2162 return dev;
2163}
2164EXPORT_SYMBOL(pci_alloc_dev);
2165
2166static bool pci_bus_crs_vendor_id(u32 l)
2167{
2168 return (l & 0xffff) == 0x0001;
2169}
2170
2171static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2172 int timeout)
2173{
2174 int delay = 1;
2175
2176 if (!pci_bus_crs_vendor_id(*l))
2177 return true; /* not a CRS completion */
2178
2179 if (!timeout)
2180 return false; /* CRS, but caller doesn't want to wait */
2181
2182 /*
2183 * We got the reserved Vendor ID that indicates a completion with
2184 * Configuration Request Retry Status (CRS). Retry until we get a
2185 * valid Vendor ID or we time out.
2186 */
2187 while (pci_bus_crs_vendor_id(*l)) {
2188 if (delay > timeout) {
2189 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2190 pci_domain_nr(bus), bus->number,
2191 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2192
2193 return false;
2194 }
2195 if (delay >= 1000)
2196 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2197 pci_domain_nr(bus), bus->number,
2198 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2199
2200 msleep(delay);
2201 delay *= 2;
2202
2203 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2204 return false;
2205 }
2206
2207 if (delay >= 1000)
2208 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2209 pci_domain_nr(bus), bus->number,
2210 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2211
2212 return true;
2213}
2214
2215bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2216 int timeout)
2217{
2218 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2219 return false;
2220
2221 /* Some broken boards return 0 or ~0 if a slot is empty: */
2222 if (*l == 0xffffffff || *l == 0x00000000 ||
2223 *l == 0x0000ffff || *l == 0xffff0000)
2224 return false;
2225
2226 if (pci_bus_crs_vendor_id(*l))
2227 return pci_bus_wait_crs(bus, devfn, l, timeout);
2228
2229 return true;
2230}
2231
2232bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2233 int timeout)
2234{
2235#ifdef CONFIG_PCI_QUIRKS
2236 struct pci_dev *bridge = bus->self;
2237
2238 /*
2239 * Certain IDT switches have an issue where they improperly trigger
2240 * ACS Source Validation errors on completions for config reads.
2241 */
2242 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2243 bridge->device == 0x80b5)
2244 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2245#endif
2246
2247 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2248}
2249EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2250
2251/*
2252 * Read the config data for a PCI device, sanity-check it,
2253 * and fill in the dev structure.
2254 */
2255static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2256{
2257 struct pci_dev *dev;
2258 u32 l;
2259
2260 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2261 return NULL;
2262
2263 dev = pci_alloc_dev(bus);
2264 if (!dev)
2265 return NULL;
2266
2267 dev->devfn = devfn;
2268 dev->vendor = l & 0xffff;
2269 dev->device = (l >> 16) & 0xffff;
2270
2271 pci_set_of_node(dev);
2272
2273 if (pci_setup_device(dev)) {
2274 pci_bus_put(dev->bus);
2275 kfree(dev);
2276 return NULL;
2277 }
2278
2279 return dev;
2280}
2281
2282void pcie_report_downtraining(struct pci_dev *dev)
2283{
2284 if (!pci_is_pcie(dev))
2285 return;
2286
2287 /* Look from the device up to avoid downstream ports with no devices */
2288 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2289 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2290 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2291 return;
2292
2293 /* Multi-function PCIe devices share the same link/status */
2294 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2295 return;
2296
2297 /* Print link status only if the device is constrained by the fabric */
2298 __pcie_print_link_status(dev, false);
2299}
2300
2301static void pci_init_capabilities(struct pci_dev *dev)
2302{
2303 /* Enhanced Allocation */
2304 pci_ea_init(dev);
2305
2306 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2307 pci_msi_setup_pci_dev(dev);
2308
2309 /* Buffers for saving PCIe and PCI-X capabilities */
2310 pci_allocate_cap_save_buffers(dev);
2311
2312 /* Power Management */
2313 pci_pm_init(dev);
2314
2315 /* Vital Product Data */
2316 pci_vpd_init(dev);
2317
2318 /* Alternative Routing-ID Forwarding */
2319 pci_configure_ari(dev);
2320
2321 /* Single Root I/O Virtualization */
2322 pci_iov_init(dev);
2323
2324 /* Address Translation Services */
2325 pci_ats_init(dev);
2326
2327 /* Enable ACS P2P upstream forwarding */
2328 pci_enable_acs(dev);
2329
2330 /* Precision Time Measurement */
2331 pci_ptm_init(dev);
2332
2333 /* Advanced Error Reporting */
2334 pci_aer_init(dev);
2335
2336 pcie_report_downtraining(dev);
2337
2338 if (pci_probe_reset_function(dev) == 0)
2339 dev->reset_fn = 1;
2340}
2341
2342/*
2343 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2344 * devices. Firmware interfaces that can select the MSI domain on a
2345 * per-device basis should be called from here.
2346 */
2347static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2348{
2349 struct irq_domain *d;
2350
2351 /*
2352 * If a domain has been set through the pcibios_add_device()
2353 * callback, then this is the one (platform code knows best).
2354 */
2355 d = dev_get_msi_domain(&dev->dev);
2356 if (d)
2357 return d;
2358
2359 /*
2360 * Let's see if we have a firmware interface able to provide
2361 * the domain.
2362 */
2363 d = pci_msi_get_device_domain(dev);
2364 if (d)
2365 return d;
2366
2367 return NULL;
2368}
2369
2370static void pci_set_msi_domain(struct pci_dev *dev)
2371{
2372 struct irq_domain *d;
2373
2374 /*
2375 * If the platform or firmware interfaces cannot supply a
2376 * device-specific MSI domain, then inherit the default domain
2377 * from the host bridge itself.
2378 */
2379 d = pci_dev_msi_domain(dev);
2380 if (!d)
2381 d = dev_get_msi_domain(&dev->bus->dev);
2382
2383 dev_set_msi_domain(&dev->dev, d);
2384}
2385
2386void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2387{
2388 int ret;
2389
2390 pci_configure_device(dev);
2391
2392 device_initialize(&dev->dev);
2393 dev->dev.release = pci_release_dev;
2394
2395 set_dev_node(&dev->dev, pcibus_to_node(bus));
2396 dev->dev.dma_mask = &dev->dma_mask;
2397 dev->dev.dma_parms = &dev->dma_parms;
2398 dev->dev.coherent_dma_mask = 0xffffffffull;
2399
2400 dma_set_max_seg_size(&dev->dev, 65536);
2401 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2402
2403 /* Fix up broken headers */
2404 pci_fixup_device(pci_fixup_header, dev);
2405
2406 /* Moved out from quirk header fixup code */
2407 pci_reassigndev_resource_alignment(dev);
2408
2409 /* Clear the state_saved flag */
2410 dev->state_saved = false;
2411
2412 /* Initialize various capabilities */
2413 pci_init_capabilities(dev);
2414
2415 /*
2416 * Add the device to our list of discovered devices
2417 * and the bus list for fixup functions, etc.
2418 */
2419 down_write(&pci_bus_sem);
2420 list_add_tail(&dev->bus_list, &bus->devices);
2421 up_write(&pci_bus_sem);
2422
2423 ret = pcibios_add_device(dev);
2424 WARN_ON(ret < 0);
2425
2426 /* Set up MSI IRQ domain */
2427 pci_set_msi_domain(dev);
2428
2429 /* Notifier could use PCI capabilities */
2430 dev->match_driver = false;
2431 ret = device_add(&dev->dev);
2432 WARN_ON(ret < 0);
2433}
2434
2435struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2436{
2437 struct pci_dev *dev;
2438
2439 dev = pci_get_slot(bus, devfn);
2440 if (dev) {
2441 pci_dev_put(dev);
2442 return dev;
2443 }
2444
2445 dev = pci_scan_device(bus, devfn);
2446 if (!dev)
2447 return NULL;
2448
2449 pci_device_add(dev, bus);
2450
2451 return dev;
2452}
2453EXPORT_SYMBOL(pci_scan_single_device);
2454
2455static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2456{
2457 int pos;
2458 u16 cap = 0;
2459 unsigned next_fn;
2460
2461 if (pci_ari_enabled(bus)) {
2462 if (!dev)
2463 return 0;
2464 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2465 if (!pos)
2466 return 0;
2467
2468 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2469 next_fn = PCI_ARI_CAP_NFN(cap);
2470 if (next_fn <= fn)
2471 return 0; /* protect against malformed list */
2472
2473 return next_fn;
2474 }
2475
2476 /* dev may be NULL for non-contiguous multifunction devices */
2477 if (!dev || dev->multifunction)
2478 return (fn + 1) % 8;
2479
2480 return 0;
2481}
2482
2483static int only_one_child(struct pci_bus *bus)
2484{
2485 struct pci_dev *bridge = bus->self;
2486
2487 /*
2488 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2489 * we scan for all possible devices, not just Device 0.
2490 */
2491 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2492 return 0;
2493
2494 /*
2495 * A PCIe Downstream Port normally leads to a Link with only Device
2496 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2497 * only for Device 0 in that situation.
2498 */
2499 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2500 return 1;
2501
2502 return 0;
2503}
2504
2505/**
2506 * pci_scan_slot - Scan a PCI slot on a bus for devices
2507 * @bus: PCI bus to scan
2508 * @devfn: slot number to scan (must have zero function)
2509 *
2510 * Scan a PCI slot on the specified PCI bus for devices, adding
2511 * discovered devices to the @bus->devices list. New devices
2512 * will not have is_added set.
2513 *
2514 * Returns the number of new devices found.
2515 */
2516int pci_scan_slot(struct pci_bus *bus, int devfn)
2517{
2518 unsigned fn, nr = 0;
2519 struct pci_dev *dev;
2520
2521 if (only_one_child(bus) && (devfn > 0))
2522 return 0; /* Already scanned the entire slot */
2523
2524 dev = pci_scan_single_device(bus, devfn);
2525 if (!dev)
2526 return 0;
2527 if (!pci_dev_is_added(dev))
2528 nr++;
2529
2530 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2531 dev = pci_scan_single_device(bus, devfn + fn);
2532 if (dev) {
2533 if (!pci_dev_is_added(dev))
2534 nr++;
2535 dev->multifunction = 1;
2536 }
2537 }
2538
2539 /* Only one slot has PCIe device */
2540 if (bus->self && nr)
2541 pcie_aspm_init_link_state(bus->self);
2542
2543 return nr;
2544}
2545EXPORT_SYMBOL(pci_scan_slot);
2546
2547static int pcie_find_smpss(struct pci_dev *dev, void *data)
2548{
2549 u8 *smpss = data;
2550
2551 if (!pci_is_pcie(dev))
2552 return 0;
2553
2554 /*
2555 * We don't have a way to change MPS settings on devices that have
2556 * drivers attached. A hot-added device might support only the minimum
2557 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2558 * where devices may be hot-added, we limit the fabric MPS to 128 so
2559 * hot-added devices will work correctly.
2560 *
2561 * However, if we hot-add a device to a slot directly below a Root
2562 * Port, it's impossible for there to be other existing devices below
2563 * the port. We don't limit the MPS in this case because we can
2564 * reconfigure MPS on both the Root Port and the hot-added device,
2565 * and there are no other devices involved.
2566 *
2567 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2568 */
2569 if (dev->is_hotplug_bridge &&
2570 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2571 *smpss = 0;
2572
2573 if (*smpss > dev->pcie_mpss)
2574 *smpss = dev->pcie_mpss;
2575
2576 return 0;
2577}
2578
2579static void pcie_write_mps(struct pci_dev *dev, int mps)
2580{
2581 int rc;
2582
2583 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2584 mps = 128 << dev->pcie_mpss;
2585
2586 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2587 dev->bus->self)
2588
2589 /*
2590 * For "Performance", the assumption is made that
2591 * downstream communication will never be larger than
2592 * the MRRS. So, the MPS only needs to be configured
2593 * for the upstream communication. This being the case,
2594 * walk from the top down and set the MPS of the child
2595 * to that of the parent bus.
2596 *
2597 * Configure the device MPS with the smaller of the
2598 * device MPSS or the bridge MPS (which is assumed to be
2599 * properly configured at this point to the largest
2600 * allowable MPS based on its parent bus).
2601 */
2602 mps = min(mps, pcie_get_mps(dev->bus->self));
2603 }
2604
2605 rc = pcie_set_mps(dev, mps);
2606 if (rc)
2607 pci_err(dev, "Failed attempting to set the MPS\n");
2608}
2609
2610static void pcie_write_mrrs(struct pci_dev *dev)
2611{
2612 int rc, mrrs;
2613
2614 /*
2615 * In the "safe" case, do not configure the MRRS. There appear to be
2616 * issues with setting MRRS to 0 on a number of devices.
2617 */
2618 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2619 return;
2620
2621 /*
2622 * For max performance, the MRRS must be set to the largest supported
2623 * value. However, it cannot be configured larger than the MPS the
2624 * device or the bus can support. This should already be properly
2625 * configured by a prior call to pcie_write_mps().
2626 */
2627 mrrs = pcie_get_mps(dev);
2628
2629 /*
2630 * MRRS is a R/W register. Invalid values can be written, but a
2631 * subsequent read will verify if the value is acceptable or not.
2632 * If the MRRS value provided is not acceptable (e.g., too large),
2633 * shrink the value until it is acceptable to the HW.
2634 */
2635 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2636 rc = pcie_set_readrq(dev, mrrs);
2637 if (!rc)
2638 break;
2639
2640 pci_warn(dev, "Failed attempting to set the MRRS\n");
2641 mrrs /= 2;
2642 }
2643
2644 if (mrrs < 128)
2645 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2646}
2647
2648static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2649{
2650 int mps, orig_mps;
2651
2652 if (!pci_is_pcie(dev))
2653 return 0;
2654
2655 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2656 pcie_bus_config == PCIE_BUS_DEFAULT)
2657 return 0;
2658
2659 mps = 128 << *(u8 *)data;
2660 orig_mps = pcie_get_mps(dev);
2661
2662 pcie_write_mps(dev, mps);
2663 pcie_write_mrrs(dev);
2664
2665 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2666 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2667 orig_mps, pcie_get_readrq(dev));
2668
2669 return 0;
2670}
2671
2672/*
2673 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2674 * parents then children fashion. If this changes, then this code will not
2675 * work as designed.
2676 */
2677void pcie_bus_configure_settings(struct pci_bus *bus)
2678{
2679 u8 smpss = 0;
2680
2681 if (!bus->self)
2682 return;
2683
2684 if (!pci_is_pcie(bus->self))
2685 return;
2686
2687 /*
2688 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2689 * to be aware of the MPS of the destination. To work around this,
2690 * simply force the MPS of the entire system to the smallest possible.
2691 */
2692 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2693 smpss = 0;
2694
2695 if (pcie_bus_config == PCIE_BUS_SAFE) {
2696 smpss = bus->self->pcie_mpss;
2697
2698 pcie_find_smpss(bus->self, &smpss);
2699 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2700 }
2701
2702 pcie_bus_configure_set(bus->self, &smpss);
2703 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2704}
2705EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2706
2707/*
2708 * Called after each bus is probed, but before its children are examined. This
2709 * is marked as __weak because multiple architectures define it.
2710 */
2711void __weak pcibios_fixup_bus(struct pci_bus *bus)
2712{
2713 /* nothing to do, expected to be removed in the future */
2714}
2715
2716/**
2717 * pci_scan_child_bus_extend() - Scan devices below a bus
2718 * @bus: Bus to scan for devices
2719 * @available_buses: Total number of buses available (%0 does not try to
2720 * extend beyond the minimal)
2721 *
2722 * Scans devices below @bus including subordinate buses. Returns new
2723 * subordinate number including all the found devices. Passing
2724 * @available_buses causes the remaining bus space to be distributed
2725 * equally between hotplug-capable bridges to allow future extension of the
2726 * hierarchy.
2727 */
2728static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2729 unsigned int available_buses)
2730{
2731 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2732 unsigned int start = bus->busn_res.start;
2733 unsigned int devfn, fn, cmax, max = start;
2734 struct pci_dev *dev;
2735 int nr_devs;
2736
2737 dev_dbg(&bus->dev, "scanning bus\n");
2738
2739 /* Go find them, Rover! */
2740 for (devfn = 0; devfn < 256; devfn += 8) {
2741 nr_devs = pci_scan_slot(bus, devfn);
2742
2743 /*
2744 * The Jailhouse hypervisor may pass individual functions of a
2745 * multi-function device to a guest without passing function 0.
2746 * Look for them as well.
2747 */
2748 if (jailhouse_paravirt() && nr_devs == 0) {
2749 for (fn = 1; fn < 8; fn++) {
2750 dev = pci_scan_single_device(bus, devfn + fn);
2751 if (dev)
2752 dev->multifunction = 1;
2753 }
2754 }
2755 }
2756
2757 /* Reserve buses for SR-IOV capability */
2758 used_buses = pci_iov_bus_range(bus);
2759 max += used_buses;
2760
2761 /*
2762 * After performing arch-dependent fixup of the bus, look behind
2763 * all PCI-to-PCI bridges on this bus.
2764 */
2765 if (!bus->is_added) {
2766 dev_dbg(&bus->dev, "fixups for bus\n");
2767 pcibios_fixup_bus(bus);
2768 bus->is_added = 1;
2769 }
2770
2771 /*
2772 * Calculate how many hotplug bridges and normal bridges there
2773 * are on this bus. We will distribute the additional available
2774 * buses between hotplug bridges.
2775 */
2776 for_each_pci_bridge(dev, bus) {
2777 if (dev->is_hotplug_bridge)
2778 hotplug_bridges++;
2779 else
2780 normal_bridges++;
2781 }
2782
2783 /*
2784 * Scan bridges that are already configured. We don't touch them
2785 * unless they are misconfigured (which will be done in the second
2786 * scan below).
2787 */
2788 for_each_pci_bridge(dev, bus) {
2789 cmax = max;
2790 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2791
2792 /*
2793 * Reserve one bus for each bridge now to avoid extending
2794 * hotplug bridges too much during the second scan below.
2795 */
2796 used_buses++;
2797 if (cmax - max > 1)
2798 used_buses += cmax - max - 1;
2799 }
2800
2801 /* Scan bridges that need to be reconfigured */
2802 for_each_pci_bridge(dev, bus) {
2803 unsigned int buses = 0;
2804
2805 if (!hotplug_bridges && normal_bridges == 1) {
2806
2807 /*
2808 * There is only one bridge on the bus (upstream
2809 * port) so it gets all available buses which it
2810 * can then distribute to the possible hotplug
2811 * bridges below.
2812 */
2813 buses = available_buses;
2814 } else if (dev->is_hotplug_bridge) {
2815
2816 /*
2817 * Distribute the extra buses between hotplug
2818 * bridges if any.
2819 */
2820 buses = available_buses / hotplug_bridges;
2821 buses = min(buses, available_buses - used_buses + 1);
2822 }
2823
2824 cmax = max;
2825 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2826 /* One bus is already accounted so don't add it again */
2827 if (max - cmax > 1)
2828 used_buses += max - cmax - 1;
2829 }
2830
2831 /*
2832 * Make sure a hotplug bridge has at least the minimum requested
2833 * number of buses but allow it to grow up to the maximum available
2834 * bus number of there is room.
2835 */
2836 if (bus->self && bus->self->is_hotplug_bridge) {
2837 used_buses = max_t(unsigned int, available_buses,
2838 pci_hotplug_bus_size - 1);
2839 if (max - start < used_buses) {
2840 max = start + used_buses;
2841
2842 /* Do not allocate more buses than we have room left */
2843 if (max > bus->busn_res.end)
2844 max = bus->busn_res.end;
2845
2846 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2847 &bus->busn_res, max - start);
2848 }
2849 }
2850
2851 /*
2852 * We've scanned the bus and so we know all about what's on
2853 * the other side of any bridges that may be on this bus plus
2854 * any devices.
2855 *
2856 * Return how far we've got finding sub-buses.
2857 */
2858 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2859 return max;
2860}
2861
2862/**
2863 * pci_scan_child_bus() - Scan devices below a bus
2864 * @bus: Bus to scan for devices
2865 *
2866 * Scans devices below @bus including subordinate buses. Returns new
2867 * subordinate number including all the found devices.
2868 */
2869unsigned int pci_scan_child_bus(struct pci_bus *bus)
2870{
2871 return pci_scan_child_bus_extend(bus, 0);
2872}
2873EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2874
2875/**
2876 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2877 * @bridge: Host bridge to set up
2878 *
2879 * Default empty implementation. Replace with an architecture-specific setup
2880 * routine, if necessary.
2881 */
2882int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2883{
2884 return 0;
2885}
2886
2887void __weak pcibios_add_bus(struct pci_bus *bus)
2888{
2889}
2890
2891void __weak pcibios_remove_bus(struct pci_bus *bus)
2892{
2893}
2894
2895struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2896 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2897{
2898 int error;
2899 struct pci_host_bridge *bridge;
2900
2901 bridge = pci_alloc_host_bridge(0);
2902 if (!bridge)
2903 return NULL;
2904
2905 bridge->dev.parent = parent;
2906
2907 list_splice_init(resources, &bridge->windows);
2908 bridge->sysdata = sysdata;
2909 bridge->busnr = bus;
2910 bridge->ops = ops;
2911
2912 error = pci_register_host_bridge(bridge);
2913 if (error < 0)
2914 goto err_out;
2915
2916 return bridge->bus;
2917
2918err_out:
2919 kfree(bridge);
2920 return NULL;
2921}
2922EXPORT_SYMBOL_GPL(pci_create_root_bus);
2923
2924int pci_host_probe(struct pci_host_bridge *bridge)
2925{
2926 struct pci_bus *bus, *child;
2927 int ret;
2928
2929 ret = pci_scan_root_bus_bridge(bridge);
2930 if (ret < 0) {
2931 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2932 return ret;
2933 }
2934
2935 bus = bridge->bus;
2936
2937 /*
2938 * We insert PCI resources into the iomem_resource and
2939 * ioport_resource trees in either pci_bus_claim_resources()
2940 * or pci_bus_assign_resources().
2941 */
2942 if (pci_has_flag(PCI_PROBE_ONLY)) {
2943 pci_bus_claim_resources(bus);
2944 } else {
2945 pci_bus_size_bridges(bus);
2946 pci_bus_assign_resources(bus);
2947
2948 list_for_each_entry(child, &bus->children, node)
2949 pcie_bus_configure_settings(child);
2950 }
2951
2952 pci_bus_add_devices(bus);
2953 return 0;
2954}
2955EXPORT_SYMBOL_GPL(pci_host_probe);
2956
2957int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2958{
2959 struct resource *res = &b->busn_res;
2960 struct resource *parent_res, *conflict;
2961
2962 res->start = bus;
2963 res->end = bus_max;
2964 res->flags = IORESOURCE_BUS;
2965
2966 if (!pci_is_root_bus(b))
2967 parent_res = &b->parent->busn_res;
2968 else {
2969 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2970 res->flags |= IORESOURCE_PCI_FIXED;
2971 }
2972
2973 conflict = request_resource_conflict(parent_res, res);
2974
2975 if (conflict)
2976 dev_info(&b->dev,
2977 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2978 res, pci_is_root_bus(b) ? "domain " : "",
2979 parent_res, conflict->name, conflict);
2980
2981 return conflict == NULL;
2982}
2983
2984int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2985{
2986 struct resource *res = &b->busn_res;
2987 struct resource old_res = *res;
2988 resource_size_t size;
2989 int ret;
2990
2991 if (res->start > bus_max)
2992 return -EINVAL;
2993
2994 size = bus_max - res->start + 1;
2995 ret = adjust_resource(res, res->start, size);
2996 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
2997 &old_res, ret ? "can not be" : "is", bus_max);
2998
2999 if (!ret && !res->parent)
3000 pci_bus_insert_busn_res(b, res->start, res->end);
3001
3002 return ret;
3003}
3004
3005void pci_bus_release_busn_res(struct pci_bus *b)
3006{
3007 struct resource *res = &b->busn_res;
3008 int ret;
3009
3010 if (!res->flags || !res->parent)
3011 return;
3012
3013 ret = release_resource(res);
3014 dev_info(&b->dev, "busn_res: %pR %s released\n",
3015 res, ret ? "can not be" : "is");
3016}
3017
3018int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3019{
3020 struct resource_entry *window;
3021 bool found = false;
3022 struct pci_bus *b;
3023 int max, bus, ret;
3024
3025 if (!bridge)
3026 return -EINVAL;
3027
3028 resource_list_for_each_entry(window, &bridge->windows)
3029 if (window->res->flags & IORESOURCE_BUS) {
3030 found = true;
3031 break;
3032 }
3033
3034 ret = pci_register_host_bridge(bridge);
3035 if (ret < 0)
3036 return ret;
3037
3038 b = bridge->bus;
3039 bus = bridge->busnr;
3040
3041 if (!found) {
3042 dev_info(&b->dev,
3043 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3044 bus);
3045 pci_bus_insert_busn_res(b, bus, 255);
3046 }
3047
3048 max = pci_scan_child_bus(b);
3049
3050 if (!found)
3051 pci_bus_update_busn_res_end(b, max);
3052
3053 return 0;
3054}
3055EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3056
3057struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3058 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3059{
3060 struct resource_entry *window;
3061 bool found = false;
3062 struct pci_bus *b;
3063 int max;
3064
3065 resource_list_for_each_entry(window, resources)
3066 if (window->res->flags & IORESOURCE_BUS) {
3067 found = true;
3068 break;
3069 }
3070
3071 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3072 if (!b)
3073 return NULL;
3074
3075 if (!found) {
3076 dev_info(&b->dev,
3077 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3078 bus);
3079 pci_bus_insert_busn_res(b, bus, 255);
3080 }
3081
3082 max = pci_scan_child_bus(b);
3083
3084 if (!found)
3085 pci_bus_update_busn_res_end(b, max);
3086
3087 return b;
3088}
3089EXPORT_SYMBOL(pci_scan_root_bus);
3090
3091struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3092 void *sysdata)
3093{
3094 LIST_HEAD(resources);
3095 struct pci_bus *b;
3096
3097 pci_add_resource(&resources, &ioport_resource);
3098 pci_add_resource(&resources, &iomem_resource);
3099 pci_add_resource(&resources, &busn_resource);
3100 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3101 if (b) {
3102 pci_scan_child_bus(b);
3103 } else {
3104 pci_free_resource_list(&resources);
3105 }
3106 return b;
3107}
3108EXPORT_SYMBOL(pci_scan_bus);
3109
3110/**
3111 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3112 * @bridge: PCI bridge for the bus to scan
3113 *
3114 * Scan a PCI bus and child buses for new devices, add them,
3115 * and enable them, resizing bridge mmio/io resource if necessary
3116 * and possible. The caller must ensure the child devices are already
3117 * removed for resizing to occur.
3118 *
3119 * Returns the max number of subordinate bus discovered.
3120 */
3121unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3122{
3123 unsigned int max;
3124 struct pci_bus *bus = bridge->subordinate;
3125
3126 max = pci_scan_child_bus(bus);
3127
3128 pci_assign_unassigned_bridge_resources(bridge);
3129
3130 pci_bus_add_devices(bus);
3131
3132 return max;
3133}
3134
3135/**
3136 * pci_rescan_bus - Scan a PCI bus for devices
3137 * @bus: PCI bus to scan
3138 *
3139 * Scan a PCI bus and child buses for new devices, add them,
3140 * and enable them.
3141 *
3142 * Returns the max number of subordinate bus discovered.
3143 */
3144unsigned int pci_rescan_bus(struct pci_bus *bus)
3145{
3146 unsigned int max;
3147
3148 max = pci_scan_child_bus(bus);
3149 pci_assign_unassigned_bus_resources(bus);
3150 pci_bus_add_devices(bus);
3151
3152 return max;
3153}
3154EXPORT_SYMBOL_GPL(pci_rescan_bus);
3155
3156/*
3157 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3158 * routines should always be executed under this mutex.
3159 */
3160static DEFINE_MUTEX(pci_rescan_remove_lock);
3161
3162void pci_lock_rescan_remove(void)
3163{
3164 mutex_lock(&pci_rescan_remove_lock);
3165}
3166EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3167
3168void pci_unlock_rescan_remove(void)
3169{
3170 mutex_unlock(&pci_rescan_remove_lock);
3171}
3172EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3173
3174static int __init pci_sort_bf_cmp(const struct device *d_a,
3175 const struct device *d_b)
3176{
3177 const struct pci_dev *a = to_pci_dev(d_a);
3178 const struct pci_dev *b = to_pci_dev(d_b);
3179
3180 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3181 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3182
3183 if (a->bus->number < b->bus->number) return -1;
3184 else if (a->bus->number > b->bus->number) return 1;
3185
3186 if (a->devfn < b->devfn) return -1;
3187 else if (a->devfn > b->devfn) return 1;
3188
3189 return 0;
3190}
3191
3192void __init pci_sort_breadthfirst(void)
3193{
3194 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3195}
3196
3197int pci_hp_add_bridge(struct pci_dev *dev)
3198{
3199 struct pci_bus *parent = dev->bus;
3200 int busnr, start = parent->busn_res.start;
3201 unsigned int available_buses = 0;
3202 int end = parent->busn_res.end;
3203
3204 for (busnr = start; busnr <= end; busnr++) {
3205 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3206 break;
3207 }
3208 if (busnr-- > end) {
3209 pci_err(dev, "No bus number available for hot-added bridge\n");
3210 return -1;
3211 }
3212
3213 /* Scan bridges that are already configured */
3214 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3215
3216 /*
3217 * Distribute the available bus numbers between hotplug-capable
3218 * bridges to make extending the chain later possible.
3219 */
3220 available_buses = end - busnr;
3221
3222 /* Scan bridges that need to be reconfigured */
3223 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3224
3225 if (!dev->subordinate)
3226 return -1;
3227
3228 return 0;
3229}
3230EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_device.h>
12#include <linux/of_pci.h>
13#include <linux/pci_hotplug.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include <linux/bitfield.h>
23#include "pci.h"
24
25#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26#define CARDBUS_RESERVE_BUSNR 3
27
28static struct resource busn_resource = {
29 .name = "PCI busn",
30 .start = 0,
31 .end = 255,
32 .flags = IORESOURCE_BUS,
33};
34
35/* Ugh. Need to stop exporting this to modules. */
36LIST_HEAD(pci_root_buses);
37EXPORT_SYMBOL(pci_root_buses);
38
39static LIST_HEAD(pci_domain_busn_res_list);
40
41struct pci_domain_busn_res {
42 struct list_head list;
43 struct resource res;
44 int domain_nr;
45};
46
47static struct resource *get_pci_domain_busn_res(int domain_nr)
48{
49 struct pci_domain_busn_res *r;
50
51 list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 if (r->domain_nr == domain_nr)
53 return &r->res;
54
55 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 if (!r)
57 return NULL;
58
59 r->domain_nr = domain_nr;
60 r->res.start = 0;
61 r->res.end = 0xff;
62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63
64 list_add_tail(&r->list, &pci_domain_busn_res_list);
65
66 return &r->res;
67}
68
69/*
70 * Some device drivers need know if PCI is initiated.
71 * Basically, we think PCI is not initiated when there
72 * is no device to be found on the pci_bus_type.
73 */
74int no_pci_devices(void)
75{
76 struct device *dev;
77 int no_devices;
78
79 dev = bus_find_next_device(&pci_bus_type, NULL);
80 no_devices = (dev == NULL);
81 put_device(dev);
82 return no_devices;
83}
84EXPORT_SYMBOL(no_pci_devices);
85
86/*
87 * PCI Bus Class
88 */
89static void release_pcibus_dev(struct device *dev)
90{
91 struct pci_bus *pci_bus = to_pci_bus(dev);
92
93 put_device(pci_bus->bridge);
94 pci_bus_remove_resources(pci_bus);
95 pci_release_bus_of_node(pci_bus);
96 kfree(pci_bus);
97}
98
99static struct class pcibus_class = {
100 .name = "pci_bus",
101 .dev_release = &release_pcibus_dev,
102 .dev_groups = pcibus_groups,
103};
104
105static int __init pcibus_class_init(void)
106{
107 return class_register(&pcibus_class);
108}
109postcore_initcall(pcibus_class_init);
110
111static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112{
113 u64 size = mask & maxbase; /* Find the significant bits */
114 if (!size)
115 return 0;
116
117 /*
118 * Get the lowest of them to find the decode size, and from that
119 * the extent.
120 */
121 size = size & ~(size-1);
122
123 /*
124 * base == maxbase can be valid only if the BAR has already been
125 * programmed with all 1s.
126 */
127 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
128 return 0;
129
130 return size;
131}
132
133static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134{
135 u32 mem_type;
136 unsigned long flags;
137
138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 flags |= IORESOURCE_IO;
141 return flags;
142 }
143
144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 flags |= IORESOURCE_MEM;
146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 flags |= IORESOURCE_PREFETCH;
148
149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 switch (mem_type) {
151 case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 /* 1M mem BAR treated as 32-bit BAR */
155 break;
156 case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 flags |= IORESOURCE_MEM_64;
158 break;
159 default:
160 /* mem unknown type treated as 32-bit BAR */
161 break;
162 }
163 return flags;
164}
165
166#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167
168/**
169 * __pci_read_base - Read a PCI BAR
170 * @dev: the PCI device
171 * @type: type of the BAR
172 * @res: resource buffer to be filled in
173 * @pos: BAR position in the config space
174 *
175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 */
177int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 struct resource *res, unsigned int pos)
179{
180 u32 l = 0, sz = 0, mask;
181 u64 l64, sz64, mask64;
182 u16 orig_cmd;
183 struct pci_bus_region region, inverted_region;
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (PCI_POSSIBLE_ERROR(sz))
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (PCI_POSSIBLE_ERROR(l))
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 if (l & PCI_ROM_ADDRESS_ENABLE)
233 res->flags |= IORESOURCE_ROM_ENABLE;
234 l64 = l & PCI_ROM_ADDRESS_MASK;
235 sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 mask64 = PCI_ROM_ADDRESS_MASK;
237 }
238
239 if (res->flags & IORESOURCE_MEM_64) {
240 pci_read_config_dword(dev, pos + 4, &l);
241 pci_write_config_dword(dev, pos + 4, ~0);
242 pci_read_config_dword(dev, pos + 4, &sz);
243 pci_write_config_dword(dev, pos + 4, l);
244
245 l64 |= ((u64)l << 32);
246 sz64 |= ((u64)sz << 32);
247 mask64 |= ((u64)~0 << 32);
248 }
249
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252
253 if (!sz64)
254 goto fail;
255
256 sz64 = pci_size(l64, sz64, mask64);
257 if (!sz64) {
258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 pos);
260 goto fail;
261 }
262
263 if (res->flags & IORESOURCE_MEM_64) {
264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 && sz64 > 0x100000000ULL) {
266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 res->start = 0;
268 res->end = 0;
269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 pos, (unsigned long long)sz64);
271 goto out;
272 }
273
274 if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 /* Above 32-bit boundary; try to reallocate */
276 res->flags |= IORESOURCE_UNSET;
277 res->start = 0;
278 res->end = sz64 - 1;
279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 pos, (unsigned long long)l64);
281 goto out;
282 }
283 }
284
285 region.start = l64;
286 region.end = l64 + sz64 - 1;
287
288 pcibios_bus_to_resource(dev->bus, res, ®ion);
289 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290
291 /*
292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 * the corresponding resource address (the physical address used by
294 * the CPU. Converting that resource address back to a bus address
295 * should yield the original BAR value:
296 *
297 * resource_to_bus(bus_to_resource(A)) == A
298 *
299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 * be claimed by the device.
301 */
302 if (inverted_region.start != region.start) {
303 res->flags |= IORESOURCE_UNSET;
304 res->start = 0;
305 res->end = region.end - region.start;
306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 pos, (unsigned long long)region.start);
308 }
309
310 goto out;
311
312
313fail:
314 res->flags = 0;
315out:
316 if (res->flags)
317 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318
319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320}
321
322static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323{
324 unsigned int pos, reg;
325
326 if (dev->non_compliant_bars)
327 return;
328
329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
330 if (dev->is_virtfn)
331 return;
332
333 for (pos = 0; pos < howmany; pos++) {
334 struct resource *res = &dev->resource[pos];
335 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
337 }
338
339 if (rom) {
340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 dev->rom_base_reg = rom;
342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 __pci_read_base(dev, pci_bar_mem32, res, rom);
345 }
346}
347
348static void pci_read_bridge_windows(struct pci_dev *bridge)
349{
350 u16 io;
351 u32 pmem, tmp;
352
353 pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 if (!io) {
355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 }
359 if (io)
360 bridge->io_window = 1;
361
362 /*
363 * DECchip 21050 pass 2 errata: the bridge may miss an address
364 * disconnect boundary by one PCI data phase. Workaround: do not
365 * use prefetching on this device.
366 */
367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 return;
369
370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 if (!pmem) {
372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 0xffe0fff0);
374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 }
377 if (!pmem)
378 return;
379
380 bridge->pref_window = 1;
381
382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383
384 /*
385 * Bridge claims to have a 64-bit prefetchable memory
386 * window; verify that the upper bits are actually
387 * writable.
388 */
389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 0xffffffff);
392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 if (tmp)
395 bridge->pref_64_window = 1;
396 }
397}
398
399static void pci_read_bridge_io(struct pci_bus *child)
400{
401 struct pci_dev *dev = child->self;
402 u8 io_base_lo, io_limit_lo;
403 unsigned long io_mask, io_granularity, base, limit;
404 struct pci_bus_region region;
405 struct resource *res;
406
407 io_mask = PCI_IO_RANGE_MASK;
408 io_granularity = 0x1000;
409 if (dev->io_window_1k) {
410 /* Support 1K I/O space granularity */
411 io_mask = PCI_IO_1K_RANGE_MASK;
412 io_granularity = 0x400;
413 }
414
415 res = child->resource[0];
416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 base = (io_base_lo & io_mask) << 8;
419 limit = (io_limit_lo & io_mask) << 8;
420
421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 u16 io_base_hi, io_limit_hi;
423
424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 base |= ((unsigned long) io_base_hi << 16);
427 limit |= ((unsigned long) io_limit_hi << 16);
428 }
429
430 if (base <= limit) {
431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 region.start = base;
433 region.end = limit + io_granularity - 1;
434 pcibios_bus_to_resource(dev->bus, res, ®ion);
435 pci_info(dev, " bridge window %pR\n", res);
436 }
437}
438
439static void pci_read_bridge_mmio(struct pci_bus *child)
440{
441 struct pci_dev *dev = child->self;
442 u16 mem_base_lo, mem_limit_lo;
443 unsigned long base, limit;
444 struct pci_bus_region region;
445 struct resource *res;
446
447 res = child->resource[1];
448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 if (base <= limit) {
453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 region.start = base;
455 region.end = limit + 0xfffff;
456 pcibios_bus_to_resource(dev->bus, res, ®ion);
457 pci_info(dev, " bridge window %pR\n", res);
458 }
459}
460
461static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462{
463 struct pci_dev *dev = child->self;
464 u16 mem_base_lo, mem_limit_lo;
465 u64 base64, limit64;
466 pci_bus_addr_t base, limit;
467 struct pci_bus_region region;
468 struct resource *res;
469
470 res = child->resource[2];
471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475
476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 u32 mem_base_hi, mem_limit_hi;
478
479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481
482 /*
483 * Some bridges set the base > limit by default, and some
484 * (broken) BIOSes do not initialize them. If we find
485 * this, just assume they are not being used.
486 */
487 if (mem_base_hi <= mem_limit_hi) {
488 base64 |= (u64) mem_base_hi << 32;
489 limit64 |= (u64) mem_limit_hi << 32;
490 }
491 }
492
493 base = (pci_bus_addr_t) base64;
494 limit = (pci_bus_addr_t) limit64;
495
496 if (base != base64) {
497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 (unsigned long long) base64);
499 return;
500 }
501
502 if (base <= limit) {
503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 res->flags |= IORESOURCE_MEM_64;
507 region.start = base;
508 region.end = limit + 0xfffff;
509 pcibios_bus_to_resource(dev->bus, res, ®ion);
510 pci_info(dev, " bridge window %pR\n", res);
511 }
512}
513
514void pci_read_bridge_bases(struct pci_bus *child)
515{
516 struct pci_dev *dev = child->self;
517 struct resource *res;
518 int i;
519
520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
521 return;
522
523 pci_info(dev, "PCI bridge to %pR%s\n",
524 &child->busn_res,
525 dev->transparent ? " (subtractive decode)" : "");
526
527 pci_bus_remove_resources(child);
528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530
531 pci_read_bridge_io(child);
532 pci_read_bridge_mmio(child);
533 pci_read_bridge_mmio_pref(child);
534
535 if (dev->transparent) {
536 pci_bus_for_each_resource(child->parent, res, i) {
537 if (res && res->flags) {
538 pci_bus_add_resource(child, res,
539 PCI_SUBTRACTIVE_DECODE);
540 pci_info(dev, " bridge window %pR (subtractive decode)\n",
541 res);
542 }
543 }
544 }
545}
546
547static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548{
549 struct pci_bus *b;
550
551 b = kzalloc(sizeof(*b), GFP_KERNEL);
552 if (!b)
553 return NULL;
554
555 INIT_LIST_HEAD(&b->node);
556 INIT_LIST_HEAD(&b->children);
557 INIT_LIST_HEAD(&b->devices);
558 INIT_LIST_HEAD(&b->slots);
559 INIT_LIST_HEAD(&b->resources);
560 b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562#ifdef CONFIG_PCI_DOMAINS_GENERIC
563 if (parent)
564 b->domain_nr = parent->domain_nr;
565#endif
566 return b;
567}
568
569static void pci_release_host_bridge_dev(struct device *dev)
570{
571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572
573 if (bridge->release_fn)
574 bridge->release_fn(bridge);
575
576 pci_free_resource_list(&bridge->windows);
577 pci_free_resource_list(&bridge->dma_ranges);
578 kfree(bridge);
579}
580
581static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582{
583 INIT_LIST_HEAD(&bridge->windows);
584 INIT_LIST_HEAD(&bridge->dma_ranges);
585
586 /*
587 * We assume we can manage these PCIe features. Some systems may
588 * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 * may implement its own AER handling and use _OSC to prevent the
590 * OS from interfering.
591 */
592 bridge->native_aer = 1;
593 bridge->native_pcie_hotplug = 1;
594 bridge->native_shpc_hotplug = 1;
595 bridge->native_pme = 1;
596 bridge->native_ltr = 1;
597 bridge->native_dpc = 1;
598 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
599
600 device_initialize(&bridge->dev);
601}
602
603struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
604{
605 struct pci_host_bridge *bridge;
606
607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
608 if (!bridge)
609 return NULL;
610
611 pci_init_host_bridge(bridge);
612 bridge->dev.release = pci_release_host_bridge_dev;
613
614 return bridge;
615}
616EXPORT_SYMBOL(pci_alloc_host_bridge);
617
618static void devm_pci_alloc_host_bridge_release(void *data)
619{
620 pci_free_host_bridge(data);
621}
622
623struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
624 size_t priv)
625{
626 int ret;
627 struct pci_host_bridge *bridge;
628
629 bridge = pci_alloc_host_bridge(priv);
630 if (!bridge)
631 return NULL;
632
633 bridge->dev.parent = dev;
634
635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
636 bridge);
637 if (ret)
638 return NULL;
639
640 ret = devm_of_pci_bridge_init(dev, bridge);
641 if (ret)
642 return NULL;
643
644 return bridge;
645}
646EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
647
648void pci_free_host_bridge(struct pci_host_bridge *bridge)
649{
650 put_device(&bridge->dev);
651}
652EXPORT_SYMBOL(pci_free_host_bridge);
653
654/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
655static const unsigned char pcix_bus_speed[] = {
656 PCI_SPEED_UNKNOWN, /* 0 */
657 PCI_SPEED_66MHz_PCIX, /* 1 */
658 PCI_SPEED_100MHz_PCIX, /* 2 */
659 PCI_SPEED_133MHz_PCIX, /* 3 */
660 PCI_SPEED_UNKNOWN, /* 4 */
661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
664 PCI_SPEED_UNKNOWN, /* 8 */
665 PCI_SPEED_66MHz_PCIX_266, /* 9 */
666 PCI_SPEED_100MHz_PCIX_266, /* A */
667 PCI_SPEED_133MHz_PCIX_266, /* B */
668 PCI_SPEED_UNKNOWN, /* C */
669 PCI_SPEED_66MHz_PCIX_533, /* D */
670 PCI_SPEED_100MHz_PCIX_533, /* E */
671 PCI_SPEED_133MHz_PCIX_533 /* F */
672};
673
674/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
675const unsigned char pcie_link_speed[] = {
676 PCI_SPEED_UNKNOWN, /* 0 */
677 PCIE_SPEED_2_5GT, /* 1 */
678 PCIE_SPEED_5_0GT, /* 2 */
679 PCIE_SPEED_8_0GT, /* 3 */
680 PCIE_SPEED_16_0GT, /* 4 */
681 PCIE_SPEED_32_0GT, /* 5 */
682 PCIE_SPEED_64_0GT, /* 6 */
683 PCI_SPEED_UNKNOWN, /* 7 */
684 PCI_SPEED_UNKNOWN, /* 8 */
685 PCI_SPEED_UNKNOWN, /* 9 */
686 PCI_SPEED_UNKNOWN, /* A */
687 PCI_SPEED_UNKNOWN, /* B */
688 PCI_SPEED_UNKNOWN, /* C */
689 PCI_SPEED_UNKNOWN, /* D */
690 PCI_SPEED_UNKNOWN, /* E */
691 PCI_SPEED_UNKNOWN /* F */
692};
693EXPORT_SYMBOL_GPL(pcie_link_speed);
694
695const char *pci_speed_string(enum pci_bus_speed speed)
696{
697 /* Indexed by the pci_bus_speed enum */
698 static const char *speed_strings[] = {
699 "33 MHz PCI", /* 0x00 */
700 "66 MHz PCI", /* 0x01 */
701 "66 MHz PCI-X", /* 0x02 */
702 "100 MHz PCI-X", /* 0x03 */
703 "133 MHz PCI-X", /* 0x04 */
704 NULL, /* 0x05 */
705 NULL, /* 0x06 */
706 NULL, /* 0x07 */
707 NULL, /* 0x08 */
708 "66 MHz PCI-X 266", /* 0x09 */
709 "100 MHz PCI-X 266", /* 0x0a */
710 "133 MHz PCI-X 266", /* 0x0b */
711 "Unknown AGP", /* 0x0c */
712 "1x AGP", /* 0x0d */
713 "2x AGP", /* 0x0e */
714 "4x AGP", /* 0x0f */
715 "8x AGP", /* 0x10 */
716 "66 MHz PCI-X 533", /* 0x11 */
717 "100 MHz PCI-X 533", /* 0x12 */
718 "133 MHz PCI-X 533", /* 0x13 */
719 "2.5 GT/s PCIe", /* 0x14 */
720 "5.0 GT/s PCIe", /* 0x15 */
721 "8.0 GT/s PCIe", /* 0x16 */
722 "16.0 GT/s PCIe", /* 0x17 */
723 "32.0 GT/s PCIe", /* 0x18 */
724 "64.0 GT/s PCIe", /* 0x19 */
725 };
726
727 if (speed < ARRAY_SIZE(speed_strings))
728 return speed_strings[speed];
729 return "Unknown";
730}
731EXPORT_SYMBOL_GPL(pci_speed_string);
732
733void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
734{
735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
736}
737EXPORT_SYMBOL_GPL(pcie_update_link_speed);
738
739static unsigned char agp_speeds[] = {
740 AGP_UNKNOWN,
741 AGP_1X,
742 AGP_2X,
743 AGP_4X,
744 AGP_8X
745};
746
747static enum pci_bus_speed agp_speed(int agp3, int agpstat)
748{
749 int index = 0;
750
751 if (agpstat & 4)
752 index = 3;
753 else if (agpstat & 2)
754 index = 2;
755 else if (agpstat & 1)
756 index = 1;
757 else
758 goto out;
759
760 if (agp3) {
761 index += 2;
762 if (index == 5)
763 index = 0;
764 }
765
766 out:
767 return agp_speeds[index];
768}
769
770static void pci_set_bus_speed(struct pci_bus *bus)
771{
772 struct pci_dev *bridge = bus->self;
773 int pos;
774
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
776 if (!pos)
777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
778 if (pos) {
779 u32 agpstat, agpcmd;
780
781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
783
784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
786 }
787
788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
789 if (pos) {
790 u16 status;
791 enum pci_bus_speed max;
792
793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
794 &status);
795
796 if (status & PCI_X_SSTATUS_533MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_533;
798 } else if (status & PCI_X_SSTATUS_266MHZ) {
799 max = PCI_SPEED_133MHz_PCIX_266;
800 } else if (status & PCI_X_SSTATUS_133MHZ) {
801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
802 max = PCI_SPEED_133MHz_PCIX_ECC;
803 else
804 max = PCI_SPEED_133MHz_PCIX;
805 } else {
806 max = PCI_SPEED_66MHz_PCIX;
807 }
808
809 bus->max_bus_speed = max;
810 bus->cur_bus_speed = pcix_bus_speed[
811 (status & PCI_X_SSTATUS_FREQ) >> 6];
812
813 return;
814 }
815
816 if (pci_is_pcie(bridge)) {
817 u32 linkcap;
818 u16 linksta;
819
820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
822 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
823
824 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
825 pcie_update_link_speed(bus, linksta);
826 }
827}
828
829static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830{
831 struct irq_domain *d;
832
833 /* If the host bridge driver sets a MSI domain of the bridge, use it */
834 d = dev_get_msi_domain(bus->bridge);
835
836 /*
837 * Any firmware interface that can resolve the msi_domain
838 * should be called from here.
839 */
840 if (!d)
841 d = pci_host_bridge_of_msi_domain(bus);
842 if (!d)
843 d = pci_host_bridge_acpi_msi_domain(bus);
844
845 /*
846 * If no IRQ domain was found via the OF tree, try looking it up
847 * directly through the fwnode_handle.
848 */
849 if (!d) {
850 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
851
852 if (fwnode)
853 d = irq_find_matching_fwnode(fwnode,
854 DOMAIN_BUS_PCI_MSI);
855 }
856
857 return d;
858}
859
860static void pci_set_bus_msi_domain(struct pci_bus *bus)
861{
862 struct irq_domain *d;
863 struct pci_bus *b;
864
865 /*
866 * The bus can be a root bus, a subordinate bus, or a virtual bus
867 * created by an SR-IOV device. Walk up to the first bridge device
868 * found or derive the domain from the host bridge.
869 */
870 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
871 if (b->self)
872 d = dev_get_msi_domain(&b->self->dev);
873 }
874
875 if (!d)
876 d = pci_host_bridge_msi_domain(b);
877
878 dev_set_msi_domain(&bus->dev, d);
879}
880
881static int pci_register_host_bridge(struct pci_host_bridge *bridge)
882{
883 struct device *parent = bridge->dev.parent;
884 struct resource_entry *window, *next, *n;
885 struct pci_bus *bus, *b;
886 resource_size_t offset, next_offset;
887 LIST_HEAD(resources);
888 struct resource *res, *next_res;
889 char addr[64], *fmt;
890 const char *name;
891 int err;
892
893 bus = pci_alloc_bus(NULL);
894 if (!bus)
895 return -ENOMEM;
896
897 bridge->bus = bus;
898
899 bus->sysdata = bridge->sysdata;
900 bus->ops = bridge->ops;
901 bus->number = bus->busn_res.start = bridge->busnr;
902#ifdef CONFIG_PCI_DOMAINS_GENERIC
903 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
904 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 else
906 bus->domain_nr = bridge->domain_nr;
907 if (bus->domain_nr < 0) {
908 err = bus->domain_nr;
909 goto free;
910 }
911#endif
912
913 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
914 if (b) {
915 /* Ignore it if we already got here via a different bridge */
916 dev_dbg(&b->dev, "bus already known\n");
917 err = -EEXIST;
918 goto free;
919 }
920
921 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
922 bridge->busnr);
923
924 err = pcibios_root_bridge_prepare(bridge);
925 if (err)
926 goto free;
927
928 /* Temporarily move resources off the list */
929 list_splice_init(&bridge->windows, &resources);
930 err = device_add(&bridge->dev);
931 if (err) {
932 put_device(&bridge->dev);
933 goto free;
934 }
935 bus->bridge = get_device(&bridge->dev);
936 device_enable_async_suspend(bus->bridge);
937 pci_set_bus_of_node(bus);
938 pci_set_bus_msi_domain(bus);
939 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
940 !pci_host_of_has_msi_map(parent))
941 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
942
943 if (!parent)
944 set_dev_node(bus->bridge, pcibus_to_node(bus));
945
946 bus->dev.class = &pcibus_class;
947 bus->dev.parent = bus->bridge;
948
949 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
950 name = dev_name(&bus->dev);
951
952 err = device_register(&bus->dev);
953 if (err)
954 goto unregister;
955
956 pcibios_add_bus(bus);
957
958 if (bus->ops->add_bus) {
959 err = bus->ops->add_bus(bus);
960 if (WARN_ON(err < 0))
961 dev_err(&bus->dev, "failed to add bus: %d\n", err);
962 }
963
964 /* Create legacy_io and legacy_mem files for this bus */
965 pci_create_legacy_files(bus);
966
967 if (parent)
968 dev_info(parent, "PCI host bridge to bus %s\n", name);
969 else
970 pr_info("PCI host bridge to bus %s\n", name);
971
972 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
973 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
974
975 /* Coalesce contiguous windows */
976 resource_list_for_each_entry_safe(window, n, &resources) {
977 if (list_is_last(&window->node, &resources))
978 break;
979
980 next = list_next_entry(window, node);
981 offset = window->offset;
982 res = window->res;
983 next_offset = next->offset;
984 next_res = next->res;
985
986 if (res->flags != next_res->flags || offset != next_offset)
987 continue;
988
989 if (res->end + 1 == next_res->start) {
990 next_res->start = res->start;
991 res->flags = res->start = res->end = 0;
992 }
993 }
994
995 /* Add initial resources to the bus */
996 resource_list_for_each_entry_safe(window, n, &resources) {
997 offset = window->offset;
998 res = window->res;
999 if (!res->end)
1000 continue;
1001
1002 list_move_tail(&window->node, &bridge->windows);
1003
1004 if (res->flags & IORESOURCE_BUS)
1005 pci_bus_insert_busn_res(bus, bus->number, res->end);
1006 else
1007 pci_bus_add_resource(bus, res, 0);
1008
1009 if (offset) {
1010 if (resource_type(res) == IORESOURCE_IO)
1011 fmt = " (bus address [%#06llx-%#06llx])";
1012 else
1013 fmt = " (bus address [%#010llx-%#010llx])";
1014
1015 snprintf(addr, sizeof(addr), fmt,
1016 (unsigned long long)(res->start - offset),
1017 (unsigned long long)(res->end - offset));
1018 } else
1019 addr[0] = '\0';
1020
1021 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1022 }
1023
1024 down_write(&pci_bus_sem);
1025 list_add_tail(&bus->node, &pci_root_buses);
1026 up_write(&pci_bus_sem);
1027
1028 return 0;
1029
1030unregister:
1031 put_device(&bridge->dev);
1032 device_del(&bridge->dev);
1033
1034free:
1035#ifdef CONFIG_PCI_DOMAINS_GENERIC
1036 pci_bus_release_domain_nr(bus, parent);
1037#endif
1038 kfree(bus);
1039 return err;
1040}
1041
1042static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1043{
1044 int pos;
1045 u32 status;
1046
1047 /*
1048 * If extended config space isn't accessible on a bridge's primary
1049 * bus, we certainly can't access it on the secondary bus.
1050 */
1051 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1052 return false;
1053
1054 /*
1055 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1056 * extended config space is accessible on the primary, it's also
1057 * accessible on the secondary.
1058 */
1059 if (pci_is_pcie(bridge) &&
1060 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1061 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1062 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1063 return true;
1064
1065 /*
1066 * For the other bridge types:
1067 * - PCI-to-PCI bridges
1068 * - PCIe-to-PCI/PCI-X forward bridges
1069 * - PCI/PCI-X-to-PCIe reverse bridges
1070 * extended config space on the secondary side is only accessible
1071 * if the bridge supports PCI-X Mode 2.
1072 */
1073 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1074 if (!pos)
1075 return false;
1076
1077 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1078 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1079}
1080
1081static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1082 struct pci_dev *bridge, int busnr)
1083{
1084 struct pci_bus *child;
1085 struct pci_host_bridge *host;
1086 int i;
1087 int ret;
1088
1089 /* Allocate a new bus and inherit stuff from the parent */
1090 child = pci_alloc_bus(parent);
1091 if (!child)
1092 return NULL;
1093
1094 child->parent = parent;
1095 child->sysdata = parent->sysdata;
1096 child->bus_flags = parent->bus_flags;
1097
1098 host = pci_find_host_bridge(parent);
1099 if (host->child_ops)
1100 child->ops = host->child_ops;
1101 else
1102 child->ops = parent->ops;
1103
1104 /*
1105 * Initialize some portions of the bus device, but don't register
1106 * it now as the parent is not properly set up yet.
1107 */
1108 child->dev.class = &pcibus_class;
1109 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1110
1111 /* Set up the primary, secondary and subordinate bus numbers */
1112 child->number = child->busn_res.start = busnr;
1113 child->primary = parent->busn_res.start;
1114 child->busn_res.end = 0xff;
1115
1116 if (!bridge) {
1117 child->dev.parent = parent->bridge;
1118 goto add_dev;
1119 }
1120
1121 child->self = bridge;
1122 child->bridge = get_device(&bridge->dev);
1123 child->dev.parent = child->bridge;
1124 pci_set_bus_of_node(child);
1125 pci_set_bus_speed(child);
1126
1127 /*
1128 * Check whether extended config space is accessible on the child
1129 * bus. Note that we currently assume it is always accessible on
1130 * the root bus.
1131 */
1132 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1133 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1134 pci_info(child, "extended config space not accessible\n");
1135 }
1136
1137 /* Set up default resource pointers and names */
1138 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1139 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1140 child->resource[i]->name = child->name;
1141 }
1142 bridge->subordinate = child;
1143
1144add_dev:
1145 pci_set_bus_msi_domain(child);
1146 ret = device_register(&child->dev);
1147 WARN_ON(ret < 0);
1148
1149 pcibios_add_bus(child);
1150
1151 if (child->ops->add_bus) {
1152 ret = child->ops->add_bus(child);
1153 if (WARN_ON(ret < 0))
1154 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1155 }
1156
1157 /* Create legacy_io and legacy_mem files for this bus */
1158 pci_create_legacy_files(child);
1159
1160 return child;
1161}
1162
1163struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1164 int busnr)
1165{
1166 struct pci_bus *child;
1167
1168 child = pci_alloc_child_bus(parent, dev, busnr);
1169 if (child) {
1170 down_write(&pci_bus_sem);
1171 list_add_tail(&child->node, &parent->children);
1172 up_write(&pci_bus_sem);
1173 }
1174 return child;
1175}
1176EXPORT_SYMBOL(pci_add_new_bus);
1177
1178static void pci_enable_crs(struct pci_dev *pdev)
1179{
1180 u16 root_cap = 0;
1181
1182 /* Enable CRS Software Visibility if supported */
1183 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1184 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1185 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1186 PCI_EXP_RTCTL_CRSSVE);
1187}
1188
1189static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1190 unsigned int available_buses);
1191/**
1192 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1193 * numbers from EA capability.
1194 * @dev: Bridge
1195 * @sec: updated with secondary bus number from EA
1196 * @sub: updated with subordinate bus number from EA
1197 *
1198 * If @dev is a bridge with EA capability that specifies valid secondary
1199 * and subordinate bus numbers, return true with the bus numbers in @sec
1200 * and @sub. Otherwise return false.
1201 */
1202static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1203{
1204 int ea, offset;
1205 u32 dw;
1206 u8 ea_sec, ea_sub;
1207
1208 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1209 return false;
1210
1211 /* find PCI EA capability in list */
1212 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1213 if (!ea)
1214 return false;
1215
1216 offset = ea + PCI_EA_FIRST_ENT;
1217 pci_read_config_dword(dev, offset, &dw);
1218 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1219 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1220 if (ea_sec == 0 || ea_sub < ea_sec)
1221 return false;
1222
1223 *sec = ea_sec;
1224 *sub = ea_sub;
1225 return true;
1226}
1227
1228/*
1229 * pci_scan_bridge_extend() - Scan buses behind a bridge
1230 * @bus: Parent bus the bridge is on
1231 * @dev: Bridge itself
1232 * @max: Starting subordinate number of buses behind this bridge
1233 * @available_buses: Total number of buses available for this bridge and
1234 * the devices below. After the minimal bus space has
1235 * been allocated the remaining buses will be
1236 * distributed equally between hotplug-capable bridges.
1237 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1238 * that need to be reconfigured.
1239 *
1240 * If it's a bridge, configure it and scan the bus behind it.
1241 * For CardBus bridges, we don't scan behind as the devices will
1242 * be handled by the bridge driver itself.
1243 *
1244 * We need to process bridges in two passes -- first we scan those
1245 * already configured by the BIOS and after we are done with all of
1246 * them, we proceed to assigning numbers to the remaining buses in
1247 * order to avoid overlaps between old and new bus numbers.
1248 *
1249 * Return: New subordinate number covering all buses behind this bridge.
1250 */
1251static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1252 int max, unsigned int available_buses,
1253 int pass)
1254{
1255 struct pci_bus *child;
1256 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1257 u32 buses, i, j = 0;
1258 u16 bctl;
1259 u8 primary, secondary, subordinate;
1260 int broken = 0;
1261 bool fixed_buses;
1262 u8 fixed_sec, fixed_sub;
1263 int next_busnr;
1264
1265 /*
1266 * Make sure the bridge is powered on to be able to access config
1267 * space of devices below it.
1268 */
1269 pm_runtime_get_sync(&dev->dev);
1270
1271 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1272 primary = buses & 0xFF;
1273 secondary = (buses >> 8) & 0xFF;
1274 subordinate = (buses >> 16) & 0xFF;
1275
1276 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1277 secondary, subordinate, pass);
1278
1279 if (!primary && (primary != bus->number) && secondary && subordinate) {
1280 pci_warn(dev, "Primary bus is hard wired to 0\n");
1281 primary = bus->number;
1282 }
1283
1284 /* Check if setup is sensible at all */
1285 if (!pass &&
1286 (primary != bus->number || secondary <= bus->number ||
1287 secondary > subordinate)) {
1288 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1289 secondary, subordinate);
1290 broken = 1;
1291 }
1292
1293 /*
1294 * Disable Master-Abort Mode during probing to avoid reporting of
1295 * bus errors in some architectures.
1296 */
1297 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1298 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1299 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1300
1301 pci_enable_crs(dev);
1302
1303 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1304 !is_cardbus && !broken) {
1305 unsigned int cmax, buses;
1306
1307 /*
1308 * Bus already configured by firmware, process it in the
1309 * first pass and just note the configuration.
1310 */
1311 if (pass)
1312 goto out;
1313
1314 /*
1315 * The bus might already exist for two reasons: Either we
1316 * are rescanning the bus or the bus is reachable through
1317 * more than one bridge. The second case can happen with
1318 * the i450NX chipset.
1319 */
1320 child = pci_find_bus(pci_domain_nr(bus), secondary);
1321 if (!child) {
1322 child = pci_add_new_bus(bus, dev, secondary);
1323 if (!child)
1324 goto out;
1325 child->primary = primary;
1326 pci_bus_insert_busn_res(child, secondary, subordinate);
1327 child->bridge_ctl = bctl;
1328 }
1329
1330 buses = subordinate - secondary;
1331 cmax = pci_scan_child_bus_extend(child, buses);
1332 if (cmax > subordinate)
1333 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1334 subordinate, cmax);
1335
1336 /* Subordinate should equal child->busn_res.end */
1337 if (subordinate > max)
1338 max = subordinate;
1339 } else {
1340
1341 /*
1342 * We need to assign a number to this bus which we always
1343 * do in the second pass.
1344 */
1345 if (!pass) {
1346 if (pcibios_assign_all_busses() || broken || is_cardbus)
1347
1348 /*
1349 * Temporarily disable forwarding of the
1350 * configuration cycles on all bridges in
1351 * this bus segment to avoid possible
1352 * conflicts in the second pass between two
1353 * bridges programmed with overlapping bus
1354 * ranges.
1355 */
1356 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1357 buses & ~0xffffff);
1358 goto out;
1359 }
1360
1361 /* Clear errors */
1362 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1363
1364 /* Read bus numbers from EA Capability (if present) */
1365 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1366 if (fixed_buses)
1367 next_busnr = fixed_sec;
1368 else
1369 next_busnr = max + 1;
1370
1371 /*
1372 * Prevent assigning a bus number that already exists.
1373 * This can happen when a bridge is hot-plugged, so in this
1374 * case we only re-scan this bus.
1375 */
1376 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1377 if (!child) {
1378 child = pci_add_new_bus(bus, dev, next_busnr);
1379 if (!child)
1380 goto out;
1381 pci_bus_insert_busn_res(child, next_busnr,
1382 bus->busn_res.end);
1383 }
1384 max++;
1385 if (available_buses)
1386 available_buses--;
1387
1388 buses = (buses & 0xff000000)
1389 | ((unsigned int)(child->primary) << 0)
1390 | ((unsigned int)(child->busn_res.start) << 8)
1391 | ((unsigned int)(child->busn_res.end) << 16);
1392
1393 /*
1394 * yenta.c forces a secondary latency timer of 176.
1395 * Copy that behaviour here.
1396 */
1397 if (is_cardbus) {
1398 buses &= ~0xff000000;
1399 buses |= CARDBUS_LATENCY_TIMER << 24;
1400 }
1401
1402 /* We need to blast all three values with a single write */
1403 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1404
1405 if (!is_cardbus) {
1406 child->bridge_ctl = bctl;
1407 max = pci_scan_child_bus_extend(child, available_buses);
1408 } else {
1409
1410 /*
1411 * For CardBus bridges, we leave 4 bus numbers as
1412 * cards with a PCI-to-PCI bridge can be inserted
1413 * later.
1414 */
1415 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1416 struct pci_bus *parent = bus;
1417 if (pci_find_bus(pci_domain_nr(bus),
1418 max+i+1))
1419 break;
1420 while (parent->parent) {
1421 if ((!pcibios_assign_all_busses()) &&
1422 (parent->busn_res.end > max) &&
1423 (parent->busn_res.end <= max+i)) {
1424 j = 1;
1425 }
1426 parent = parent->parent;
1427 }
1428 if (j) {
1429
1430 /*
1431 * Often, there are two CardBus
1432 * bridges -- try to leave one
1433 * valid bus number for each one.
1434 */
1435 i /= 2;
1436 break;
1437 }
1438 }
1439 max += i;
1440 }
1441
1442 /*
1443 * Set subordinate bus number to its real value.
1444 * If fixed subordinate bus number exists from EA
1445 * capability then use it.
1446 */
1447 if (fixed_buses)
1448 max = fixed_sub;
1449 pci_bus_update_busn_res_end(child, max);
1450 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1451 }
1452
1453 sprintf(child->name,
1454 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1455 pci_domain_nr(bus), child->number);
1456
1457 /* Check that all devices are accessible */
1458 while (bus->parent) {
1459 if ((child->busn_res.end > bus->busn_res.end) ||
1460 (child->number > bus->busn_res.end) ||
1461 (child->number < bus->number) ||
1462 (child->busn_res.end < bus->number)) {
1463 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1464 &child->busn_res);
1465 break;
1466 }
1467 bus = bus->parent;
1468 }
1469
1470out:
1471 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1472
1473 pm_runtime_put(&dev->dev);
1474
1475 return max;
1476}
1477
1478/*
1479 * pci_scan_bridge() - Scan buses behind a bridge
1480 * @bus: Parent bus the bridge is on
1481 * @dev: Bridge itself
1482 * @max: Starting subordinate number of buses behind this bridge
1483 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1484 * that need to be reconfigured.
1485 *
1486 * If it's a bridge, configure it and scan the bus behind it.
1487 * For CardBus bridges, we don't scan behind as the devices will
1488 * be handled by the bridge driver itself.
1489 *
1490 * We need to process bridges in two passes -- first we scan those
1491 * already configured by the BIOS and after we are done with all of
1492 * them, we proceed to assigning numbers to the remaining buses in
1493 * order to avoid overlaps between old and new bus numbers.
1494 *
1495 * Return: New subordinate number covering all buses behind this bridge.
1496 */
1497int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1498{
1499 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1500}
1501EXPORT_SYMBOL(pci_scan_bridge);
1502
1503/*
1504 * Read interrupt line and base address registers.
1505 * The architecture-dependent code can tweak these, of course.
1506 */
1507static void pci_read_irq(struct pci_dev *dev)
1508{
1509 unsigned char irq;
1510
1511 /* VFs are not allowed to use INTx, so skip the config reads */
1512 if (dev->is_virtfn) {
1513 dev->pin = 0;
1514 dev->irq = 0;
1515 return;
1516 }
1517
1518 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1519 dev->pin = irq;
1520 if (irq)
1521 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1522 dev->irq = irq;
1523}
1524
1525void set_pcie_port_type(struct pci_dev *pdev)
1526{
1527 int pos;
1528 u16 reg16;
1529 int type;
1530 struct pci_dev *parent;
1531
1532 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1533 if (!pos)
1534 return;
1535
1536 pdev->pcie_cap = pos;
1537 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1538 pdev->pcie_flags_reg = reg16;
1539 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1540 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1541
1542 parent = pci_upstream_bridge(pdev);
1543 if (!parent)
1544 return;
1545
1546 /*
1547 * Some systems do not identify their upstream/downstream ports
1548 * correctly so detect impossible configurations here and correct
1549 * the port type accordingly.
1550 */
1551 type = pci_pcie_type(pdev);
1552 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1553 /*
1554 * If pdev claims to be downstream port but the parent
1555 * device is also downstream port assume pdev is actually
1556 * upstream port.
1557 */
1558 if (pcie_downstream_port(parent)) {
1559 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1560 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1561 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1562 }
1563 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1564 /*
1565 * If pdev claims to be upstream port but the parent
1566 * device is also upstream port assume pdev is actually
1567 * downstream port.
1568 */
1569 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1570 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1571 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1572 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1573 }
1574 }
1575}
1576
1577void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1578{
1579 u32 reg32;
1580
1581 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1582 if (reg32 & PCI_EXP_SLTCAP_HPC)
1583 pdev->is_hotplug_bridge = 1;
1584}
1585
1586static void set_pcie_thunderbolt(struct pci_dev *dev)
1587{
1588 u16 vsec;
1589
1590 /* Is the device part of a Thunderbolt controller? */
1591 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1592 if (vsec)
1593 dev->is_thunderbolt = 1;
1594}
1595
1596static void set_pcie_untrusted(struct pci_dev *dev)
1597{
1598 struct pci_dev *parent;
1599
1600 /*
1601 * If the upstream bridge is untrusted we treat this device
1602 * untrusted as well.
1603 */
1604 parent = pci_upstream_bridge(dev);
1605 if (parent && (parent->untrusted || parent->external_facing))
1606 dev->untrusted = true;
1607}
1608
1609static void pci_set_removable(struct pci_dev *dev)
1610{
1611 struct pci_dev *parent = pci_upstream_bridge(dev);
1612
1613 /*
1614 * We (only) consider everything downstream from an external_facing
1615 * device to be removable by the user. We're mainly concerned with
1616 * consumer platforms with user accessible thunderbolt ports that are
1617 * vulnerable to DMA attacks, and we expect those ports to be marked by
1618 * the firmware as external_facing. Devices in traditional hotplug
1619 * slots can technically be removed, but the expectation is that unless
1620 * the port is marked with external_facing, such devices are less
1621 * accessible to user / may not be removed by end user, and thus not
1622 * exposed as "removable" to userspace.
1623 */
1624 if (parent &&
1625 (parent->external_facing || dev_is_removable(&parent->dev)))
1626 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1627}
1628
1629/**
1630 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1631 * @dev: PCI device
1632 *
1633 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1634 * when forwarding a type1 configuration request the bridge must check that
1635 * the extended register address field is zero. The bridge is not permitted
1636 * to forward the transactions and must handle it as an Unsupported Request.
1637 * Some bridges do not follow this rule and simply drop the extended register
1638 * bits, resulting in the standard config space being aliased, every 256
1639 * bytes across the entire configuration space. Test for this condition by
1640 * comparing the first dword of each potential alias to the vendor/device ID.
1641 * Known offenders:
1642 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1643 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1644 */
1645static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1646{
1647#ifdef CONFIG_PCI_QUIRKS
1648 int pos;
1649 u32 header, tmp;
1650
1651 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1652
1653 for (pos = PCI_CFG_SPACE_SIZE;
1654 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1655 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1656 || header != tmp)
1657 return false;
1658 }
1659
1660 return true;
1661#else
1662 return false;
1663#endif
1664}
1665
1666/**
1667 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1668 * @dev: PCI device
1669 *
1670 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1671 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1672 * access it. Maybe we don't have a way to generate extended config space
1673 * accesses, or the device is behind a reverse Express bridge. So we try
1674 * reading the dword at 0x100 which must either be 0 or a valid extended
1675 * capability header.
1676 */
1677static int pci_cfg_space_size_ext(struct pci_dev *dev)
1678{
1679 u32 status;
1680 int pos = PCI_CFG_SPACE_SIZE;
1681
1682 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1683 return PCI_CFG_SPACE_SIZE;
1684 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1685 return PCI_CFG_SPACE_SIZE;
1686
1687 return PCI_CFG_SPACE_EXP_SIZE;
1688}
1689
1690int pci_cfg_space_size(struct pci_dev *dev)
1691{
1692 int pos;
1693 u32 status;
1694 u16 class;
1695
1696#ifdef CONFIG_PCI_IOV
1697 /*
1698 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1699 * implement a PCIe capability and therefore must implement extended
1700 * config space. We can skip the NO_EXTCFG test below and the
1701 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1702 * the fact that the SR-IOV capability on the PF resides in extended
1703 * config space and must be accessible and non-aliased to have enabled
1704 * support for this VF. This is a micro performance optimization for
1705 * systems supporting many VFs.
1706 */
1707 if (dev->is_virtfn)
1708 return PCI_CFG_SPACE_EXP_SIZE;
1709#endif
1710
1711 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1712 return PCI_CFG_SPACE_SIZE;
1713
1714 class = dev->class >> 8;
1715 if (class == PCI_CLASS_BRIDGE_HOST)
1716 return pci_cfg_space_size_ext(dev);
1717
1718 if (pci_is_pcie(dev))
1719 return pci_cfg_space_size_ext(dev);
1720
1721 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1722 if (!pos)
1723 return PCI_CFG_SPACE_SIZE;
1724
1725 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1726 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1727 return pci_cfg_space_size_ext(dev);
1728
1729 return PCI_CFG_SPACE_SIZE;
1730}
1731
1732static u32 pci_class(struct pci_dev *dev)
1733{
1734 u32 class;
1735
1736#ifdef CONFIG_PCI_IOV
1737 if (dev->is_virtfn)
1738 return dev->physfn->sriov->class;
1739#endif
1740 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1741 return class;
1742}
1743
1744static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1745{
1746#ifdef CONFIG_PCI_IOV
1747 if (dev->is_virtfn) {
1748 *vendor = dev->physfn->sriov->subsystem_vendor;
1749 *device = dev->physfn->sriov->subsystem_device;
1750 return;
1751 }
1752#endif
1753 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1754 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1755}
1756
1757static u8 pci_hdr_type(struct pci_dev *dev)
1758{
1759 u8 hdr_type;
1760
1761#ifdef CONFIG_PCI_IOV
1762 if (dev->is_virtfn)
1763 return dev->physfn->sriov->hdr_type;
1764#endif
1765 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1766 return hdr_type;
1767}
1768
1769#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1770
1771/**
1772 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1773 * @dev: PCI device
1774 *
1775 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1776 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1777 */
1778static int pci_intx_mask_broken(struct pci_dev *dev)
1779{
1780 u16 orig, toggle, new;
1781
1782 pci_read_config_word(dev, PCI_COMMAND, &orig);
1783 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1784 pci_write_config_word(dev, PCI_COMMAND, toggle);
1785 pci_read_config_word(dev, PCI_COMMAND, &new);
1786
1787 pci_write_config_word(dev, PCI_COMMAND, orig);
1788
1789 /*
1790 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1791 * r2.3, so strictly speaking, a device is not *broken* if it's not
1792 * writable. But we'll live with the misnomer for now.
1793 */
1794 if (new != toggle)
1795 return 1;
1796 return 0;
1797}
1798
1799static void early_dump_pci_device(struct pci_dev *pdev)
1800{
1801 u32 value[256 / 4];
1802 int i;
1803
1804 pci_info(pdev, "config space:\n");
1805
1806 for (i = 0; i < 256; i += 4)
1807 pci_read_config_dword(pdev, i, &value[i / 4]);
1808
1809 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1810 value, 256, false);
1811}
1812
1813/**
1814 * pci_setup_device - Fill in class and map information of a device
1815 * @dev: the device structure to fill
1816 *
1817 * Initialize the device structure with information about the device's
1818 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1819 * Called at initialisation of the PCI subsystem and by CardBus services.
1820 * Returns 0 on success and negative if unknown type of device (not normal,
1821 * bridge or CardBus).
1822 */
1823int pci_setup_device(struct pci_dev *dev)
1824{
1825 u32 class;
1826 u16 cmd;
1827 u8 hdr_type;
1828 int pos = 0;
1829 struct pci_bus_region region;
1830 struct resource *res;
1831
1832 hdr_type = pci_hdr_type(dev);
1833
1834 dev->sysdata = dev->bus->sysdata;
1835 dev->dev.parent = dev->bus->bridge;
1836 dev->dev.bus = &pci_bus_type;
1837 dev->hdr_type = hdr_type & 0x7f;
1838 dev->multifunction = !!(hdr_type & 0x80);
1839 dev->error_state = pci_channel_io_normal;
1840 set_pcie_port_type(dev);
1841
1842 pci_set_of_node(dev);
1843 pci_set_acpi_fwnode(dev);
1844
1845 pci_dev_assign_slot(dev);
1846
1847 /*
1848 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1849 * set this higher, assuming the system even supports it.
1850 */
1851 dev->dma_mask = 0xffffffff;
1852
1853 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1854 dev->bus->number, PCI_SLOT(dev->devfn),
1855 PCI_FUNC(dev->devfn));
1856
1857 class = pci_class(dev);
1858
1859 dev->revision = class & 0xff;
1860 dev->class = class >> 8; /* upper 3 bytes */
1861
1862 if (pci_early_dump)
1863 early_dump_pci_device(dev);
1864
1865 /* Need to have dev->class ready */
1866 dev->cfg_size = pci_cfg_space_size(dev);
1867
1868 /* Need to have dev->cfg_size ready */
1869 set_pcie_thunderbolt(dev);
1870
1871 set_pcie_untrusted(dev);
1872
1873 /* "Unknown power state" */
1874 dev->current_state = PCI_UNKNOWN;
1875
1876 /* Early fixups, before probing the BARs */
1877 pci_fixup_device(pci_fixup_early, dev);
1878
1879 pci_set_removable(dev);
1880
1881 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1882 dev->vendor, dev->device, dev->hdr_type, dev->class);
1883
1884 /* Device class may be changed after fixup */
1885 class = dev->class >> 8;
1886
1887 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1888 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1889 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1890 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1891 cmd &= ~PCI_COMMAND_IO;
1892 cmd &= ~PCI_COMMAND_MEMORY;
1893 pci_write_config_word(dev, PCI_COMMAND, cmd);
1894 }
1895 }
1896
1897 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1898
1899 switch (dev->hdr_type) { /* header type */
1900 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1901 if (class == PCI_CLASS_BRIDGE_PCI)
1902 goto bad;
1903 pci_read_irq(dev);
1904 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1905
1906 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1907
1908 /*
1909 * Do the ugly legacy mode stuff here rather than broken chip
1910 * quirk code. Legacy mode ATA controllers have fixed
1911 * addresses. These are not always echoed in BAR0-3, and
1912 * BAR0-3 in a few cases contain junk!
1913 */
1914 if (class == PCI_CLASS_STORAGE_IDE) {
1915 u8 progif;
1916 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1917 if ((progif & 1) == 0) {
1918 region.start = 0x1F0;
1919 region.end = 0x1F7;
1920 res = &dev->resource[0];
1921 res->flags = LEGACY_IO_RESOURCE;
1922 pcibios_bus_to_resource(dev->bus, res, ®ion);
1923 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1924 res);
1925 region.start = 0x3F6;
1926 region.end = 0x3F6;
1927 res = &dev->resource[1];
1928 res->flags = LEGACY_IO_RESOURCE;
1929 pcibios_bus_to_resource(dev->bus, res, ®ion);
1930 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1931 res);
1932 }
1933 if ((progif & 4) == 0) {
1934 region.start = 0x170;
1935 region.end = 0x177;
1936 res = &dev->resource[2];
1937 res->flags = LEGACY_IO_RESOURCE;
1938 pcibios_bus_to_resource(dev->bus, res, ®ion);
1939 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1940 res);
1941 region.start = 0x376;
1942 region.end = 0x376;
1943 res = &dev->resource[3];
1944 res->flags = LEGACY_IO_RESOURCE;
1945 pcibios_bus_to_resource(dev->bus, res, ®ion);
1946 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1947 res);
1948 }
1949 }
1950 break;
1951
1952 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1953 /*
1954 * The PCI-to-PCI bridge spec requires that subtractive
1955 * decoding (i.e. transparent) bridge must have programming
1956 * interface code of 0x01.
1957 */
1958 pci_read_irq(dev);
1959 dev->transparent = ((dev->class & 0xff) == 1);
1960 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1961 pci_read_bridge_windows(dev);
1962 set_pcie_hotplug_bridge(dev);
1963 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1964 if (pos) {
1965 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1966 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1967 }
1968 break;
1969
1970 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1971 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1972 goto bad;
1973 pci_read_irq(dev);
1974 pci_read_bases(dev, 1, 0);
1975 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1976 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1977 break;
1978
1979 default: /* unknown header */
1980 pci_err(dev, "unknown header type %02x, ignoring device\n",
1981 dev->hdr_type);
1982 pci_release_of_node(dev);
1983 return -EIO;
1984
1985 bad:
1986 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1987 dev->class, dev->hdr_type);
1988 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1989 }
1990
1991 /* We found a fine healthy device, go go go... */
1992 return 0;
1993}
1994
1995static void pci_configure_mps(struct pci_dev *dev)
1996{
1997 struct pci_dev *bridge = pci_upstream_bridge(dev);
1998 int mps, mpss, p_mps, rc;
1999
2000 if (!pci_is_pcie(dev))
2001 return;
2002
2003 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2004 if (dev->is_virtfn)
2005 return;
2006
2007 /*
2008 * For Root Complex Integrated Endpoints, program the maximum
2009 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2010 */
2011 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2012 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2013 mps = 128;
2014 else
2015 mps = 128 << dev->pcie_mpss;
2016 rc = pcie_set_mps(dev, mps);
2017 if (rc) {
2018 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2019 mps);
2020 }
2021 return;
2022 }
2023
2024 if (!bridge || !pci_is_pcie(bridge))
2025 return;
2026
2027 mps = pcie_get_mps(dev);
2028 p_mps = pcie_get_mps(bridge);
2029
2030 if (mps == p_mps)
2031 return;
2032
2033 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2034 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2035 mps, pci_name(bridge), p_mps);
2036 return;
2037 }
2038
2039 /*
2040 * Fancier MPS configuration is done later by
2041 * pcie_bus_configure_settings()
2042 */
2043 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2044 return;
2045
2046 mpss = 128 << dev->pcie_mpss;
2047 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2048 pcie_set_mps(bridge, mpss);
2049 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2050 mpss, p_mps, 128 << bridge->pcie_mpss);
2051 p_mps = pcie_get_mps(bridge);
2052 }
2053
2054 rc = pcie_set_mps(dev, p_mps);
2055 if (rc) {
2056 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2057 p_mps);
2058 return;
2059 }
2060
2061 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2062 p_mps, mps, mpss);
2063}
2064
2065int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2066{
2067 struct pci_host_bridge *host;
2068 u32 cap;
2069 u16 ctl;
2070 int ret;
2071
2072 if (!pci_is_pcie(dev))
2073 return 0;
2074
2075 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2076 if (ret)
2077 return 0;
2078
2079 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2080 return 0;
2081
2082 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2083 if (ret)
2084 return 0;
2085
2086 host = pci_find_host_bridge(dev->bus);
2087 if (!host)
2088 return 0;
2089
2090 /*
2091 * If some device in the hierarchy doesn't handle Extended Tags
2092 * correctly, make sure they're disabled.
2093 */
2094 if (host->no_ext_tags) {
2095 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2096 pci_info(dev, "disabling Extended Tags\n");
2097 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2098 PCI_EXP_DEVCTL_EXT_TAG);
2099 }
2100 return 0;
2101 }
2102
2103 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2104 pci_info(dev, "enabling Extended Tags\n");
2105 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2106 PCI_EXP_DEVCTL_EXT_TAG);
2107 }
2108 return 0;
2109}
2110
2111/**
2112 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2113 * @dev: PCI device to query
2114 *
2115 * Returns true if the device has enabled relaxed ordering attribute.
2116 */
2117bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2118{
2119 u16 v;
2120
2121 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2122
2123 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2124}
2125EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2126
2127static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2128{
2129 struct pci_dev *root;
2130
2131 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2132 if (dev->is_virtfn)
2133 return;
2134
2135 if (!pcie_relaxed_ordering_enabled(dev))
2136 return;
2137
2138 /*
2139 * For now, we only deal with Relaxed Ordering issues with Root
2140 * Ports. Peer-to-Peer DMA is another can of worms.
2141 */
2142 root = pcie_find_root_port(dev);
2143 if (!root)
2144 return;
2145
2146 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2147 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2148 PCI_EXP_DEVCTL_RELAX_EN);
2149 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2150 }
2151}
2152
2153static void pci_configure_ltr(struct pci_dev *dev)
2154{
2155#ifdef CONFIG_PCIEASPM
2156 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2157 struct pci_dev *bridge;
2158 u32 cap, ctl;
2159
2160 if (!pci_is_pcie(dev))
2161 return;
2162
2163 /* Read L1 PM substate capabilities */
2164 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2165
2166 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2167 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2168 return;
2169
2170 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2171 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2172 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2173 dev->ltr_path = 1;
2174 return;
2175 }
2176
2177 bridge = pci_upstream_bridge(dev);
2178 if (bridge && bridge->ltr_path)
2179 dev->ltr_path = 1;
2180
2181 return;
2182 }
2183
2184 if (!host->native_ltr)
2185 return;
2186
2187 /*
2188 * Software must not enable LTR in an Endpoint unless the Root
2189 * Complex and all intermediate Switches indicate support for LTR.
2190 * PCIe r4.0, sec 6.18.
2191 */
2192 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2193 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2194 PCI_EXP_DEVCTL2_LTR_EN);
2195 dev->ltr_path = 1;
2196 return;
2197 }
2198
2199 /*
2200 * If we're configuring a hot-added device, LTR was likely
2201 * disabled in the upstream bridge, so re-enable it before enabling
2202 * it in the new device.
2203 */
2204 bridge = pci_upstream_bridge(dev);
2205 if (bridge && bridge->ltr_path) {
2206 pci_bridge_reconfigure_ltr(dev);
2207 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2208 PCI_EXP_DEVCTL2_LTR_EN);
2209 dev->ltr_path = 1;
2210 }
2211#endif
2212}
2213
2214static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2215{
2216#ifdef CONFIG_PCI_PASID
2217 struct pci_dev *bridge;
2218 int pcie_type;
2219 u32 cap;
2220
2221 if (!pci_is_pcie(dev))
2222 return;
2223
2224 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2225 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2226 return;
2227
2228 pcie_type = pci_pcie_type(dev);
2229 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2230 pcie_type == PCI_EXP_TYPE_RC_END)
2231 dev->eetlp_prefix_path = 1;
2232 else {
2233 bridge = pci_upstream_bridge(dev);
2234 if (bridge && bridge->eetlp_prefix_path)
2235 dev->eetlp_prefix_path = 1;
2236 }
2237#endif
2238}
2239
2240static void pci_configure_serr(struct pci_dev *dev)
2241{
2242 u16 control;
2243
2244 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2245
2246 /*
2247 * A bridge will not forward ERR_ messages coming from an
2248 * endpoint unless SERR# forwarding is enabled.
2249 */
2250 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2251 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2252 control |= PCI_BRIDGE_CTL_SERR;
2253 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2254 }
2255 }
2256}
2257
2258static void pci_configure_device(struct pci_dev *dev)
2259{
2260 pci_configure_mps(dev);
2261 pci_configure_extended_tags(dev, NULL);
2262 pci_configure_relaxed_ordering(dev);
2263 pci_configure_ltr(dev);
2264 pci_configure_eetlp_prefix(dev);
2265 pci_configure_serr(dev);
2266
2267 pci_acpi_program_hp_params(dev);
2268}
2269
2270static void pci_release_capabilities(struct pci_dev *dev)
2271{
2272 pci_aer_exit(dev);
2273 pci_rcec_exit(dev);
2274 pci_iov_release(dev);
2275 pci_free_cap_save_buffers(dev);
2276}
2277
2278/**
2279 * pci_release_dev - Free a PCI device structure when all users of it are
2280 * finished
2281 * @dev: device that's been disconnected
2282 *
2283 * Will be called only by the device core when all users of this PCI device are
2284 * done.
2285 */
2286static void pci_release_dev(struct device *dev)
2287{
2288 struct pci_dev *pci_dev;
2289
2290 pci_dev = to_pci_dev(dev);
2291 pci_release_capabilities(pci_dev);
2292 pci_release_of_node(pci_dev);
2293 pcibios_release_device(pci_dev);
2294 pci_bus_put(pci_dev->bus);
2295 kfree(pci_dev->driver_override);
2296 bitmap_free(pci_dev->dma_alias_mask);
2297 dev_dbg(dev, "device released\n");
2298 kfree(pci_dev);
2299}
2300
2301struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2302{
2303 struct pci_dev *dev;
2304
2305 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2306 if (!dev)
2307 return NULL;
2308
2309 INIT_LIST_HEAD(&dev->bus_list);
2310 dev->dev.type = &pci_dev_type;
2311 dev->bus = pci_bus_get(bus);
2312 dev->driver_exclusive_resource = (struct resource) {
2313 .name = "PCI Exclusive",
2314 .start = 0,
2315 .end = -1,
2316 };
2317
2318#ifdef CONFIG_PCI_MSI
2319 raw_spin_lock_init(&dev->msi_lock);
2320#endif
2321 return dev;
2322}
2323EXPORT_SYMBOL(pci_alloc_dev);
2324
2325static bool pci_bus_crs_vendor_id(u32 l)
2326{
2327 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2328}
2329
2330static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2331 int timeout)
2332{
2333 int delay = 1;
2334
2335 if (!pci_bus_crs_vendor_id(*l))
2336 return true; /* not a CRS completion */
2337
2338 if (!timeout)
2339 return false; /* CRS, but caller doesn't want to wait */
2340
2341 /*
2342 * We got the reserved Vendor ID that indicates a completion with
2343 * Configuration Request Retry Status (CRS). Retry until we get a
2344 * valid Vendor ID or we time out.
2345 */
2346 while (pci_bus_crs_vendor_id(*l)) {
2347 if (delay > timeout) {
2348 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2349 pci_domain_nr(bus), bus->number,
2350 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2351
2352 return false;
2353 }
2354 if (delay >= 1000)
2355 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2356 pci_domain_nr(bus), bus->number,
2357 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2358
2359 msleep(delay);
2360 delay *= 2;
2361
2362 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2363 return false;
2364 }
2365
2366 if (delay >= 1000)
2367 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2368 pci_domain_nr(bus), bus->number,
2369 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2370
2371 return true;
2372}
2373
2374bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2375 int timeout)
2376{
2377 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2378 return false;
2379
2380 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2381 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2382 *l == 0x0000ffff || *l == 0xffff0000)
2383 return false;
2384
2385 if (pci_bus_crs_vendor_id(*l))
2386 return pci_bus_wait_crs(bus, devfn, l, timeout);
2387
2388 return true;
2389}
2390
2391bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2392 int timeout)
2393{
2394#ifdef CONFIG_PCI_QUIRKS
2395 struct pci_dev *bridge = bus->self;
2396
2397 /*
2398 * Certain IDT switches have an issue where they improperly trigger
2399 * ACS Source Validation errors on completions for config reads.
2400 */
2401 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2402 bridge->device == 0x80b5)
2403 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2404#endif
2405
2406 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2407}
2408EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2409
2410/*
2411 * Read the config data for a PCI device, sanity-check it,
2412 * and fill in the dev structure.
2413 */
2414static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2415{
2416 struct pci_dev *dev;
2417 u32 l;
2418
2419 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2420 return NULL;
2421
2422 dev = pci_alloc_dev(bus);
2423 if (!dev)
2424 return NULL;
2425
2426 dev->devfn = devfn;
2427 dev->vendor = l & 0xffff;
2428 dev->device = (l >> 16) & 0xffff;
2429
2430 if (pci_setup_device(dev)) {
2431 pci_bus_put(dev->bus);
2432 kfree(dev);
2433 return NULL;
2434 }
2435
2436 return dev;
2437}
2438
2439void pcie_report_downtraining(struct pci_dev *dev)
2440{
2441 if (!pci_is_pcie(dev))
2442 return;
2443
2444 /* Look from the device up to avoid downstream ports with no devices */
2445 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2446 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2447 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2448 return;
2449
2450 /* Multi-function PCIe devices share the same link/status */
2451 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2452 return;
2453
2454 /* Print link status only if the device is constrained by the fabric */
2455 __pcie_print_link_status(dev, false);
2456}
2457
2458static void pci_init_capabilities(struct pci_dev *dev)
2459{
2460 pci_ea_init(dev); /* Enhanced Allocation */
2461 pci_msi_init(dev); /* Disable MSI */
2462 pci_msix_init(dev); /* Disable MSI-X */
2463
2464 /* Buffers for saving PCIe and PCI-X capabilities */
2465 pci_allocate_cap_save_buffers(dev);
2466
2467 pci_pm_init(dev); /* Power Management */
2468 pci_vpd_init(dev); /* Vital Product Data */
2469 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2470 pci_iov_init(dev); /* Single Root I/O Virtualization */
2471 pci_ats_init(dev); /* Address Translation Services */
2472 pci_pri_init(dev); /* Page Request Interface */
2473 pci_pasid_init(dev); /* Process Address Space ID */
2474 pci_acs_init(dev); /* Access Control Services */
2475 pci_ptm_init(dev); /* Precision Time Measurement */
2476 pci_aer_init(dev); /* Advanced Error Reporting */
2477 pci_dpc_init(dev); /* Downstream Port Containment */
2478 pci_rcec_init(dev); /* Root Complex Event Collector */
2479
2480 pcie_report_downtraining(dev);
2481 pci_init_reset_methods(dev);
2482}
2483
2484/*
2485 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2486 * devices. Firmware interfaces that can select the MSI domain on a
2487 * per-device basis should be called from here.
2488 */
2489static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2490{
2491 struct irq_domain *d;
2492
2493 /*
2494 * If a domain has been set through the pcibios_device_add()
2495 * callback, then this is the one (platform code knows best).
2496 */
2497 d = dev_get_msi_domain(&dev->dev);
2498 if (d)
2499 return d;
2500
2501 /*
2502 * Let's see if we have a firmware interface able to provide
2503 * the domain.
2504 */
2505 d = pci_msi_get_device_domain(dev);
2506 if (d)
2507 return d;
2508
2509 return NULL;
2510}
2511
2512static void pci_set_msi_domain(struct pci_dev *dev)
2513{
2514 struct irq_domain *d;
2515
2516 /*
2517 * If the platform or firmware interfaces cannot supply a
2518 * device-specific MSI domain, then inherit the default domain
2519 * from the host bridge itself.
2520 */
2521 d = pci_dev_msi_domain(dev);
2522 if (!d)
2523 d = dev_get_msi_domain(&dev->bus->dev);
2524
2525 dev_set_msi_domain(&dev->dev, d);
2526}
2527
2528void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2529{
2530 int ret;
2531
2532 pci_configure_device(dev);
2533
2534 device_initialize(&dev->dev);
2535 dev->dev.release = pci_release_dev;
2536
2537 set_dev_node(&dev->dev, pcibus_to_node(bus));
2538 dev->dev.dma_mask = &dev->dma_mask;
2539 dev->dev.dma_parms = &dev->dma_parms;
2540 dev->dev.coherent_dma_mask = 0xffffffffull;
2541
2542 dma_set_max_seg_size(&dev->dev, 65536);
2543 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2544
2545 /* Fix up broken headers */
2546 pci_fixup_device(pci_fixup_header, dev);
2547
2548 pci_reassigndev_resource_alignment(dev);
2549
2550 dev->state_saved = false;
2551
2552 pci_init_capabilities(dev);
2553
2554 /*
2555 * Add the device to our list of discovered devices
2556 * and the bus list for fixup functions, etc.
2557 */
2558 down_write(&pci_bus_sem);
2559 list_add_tail(&dev->bus_list, &bus->devices);
2560 up_write(&pci_bus_sem);
2561
2562 ret = pcibios_device_add(dev);
2563 WARN_ON(ret < 0);
2564
2565 /* Set up MSI IRQ domain */
2566 pci_set_msi_domain(dev);
2567
2568 /* Notifier could use PCI capabilities */
2569 dev->match_driver = false;
2570 ret = device_add(&dev->dev);
2571 WARN_ON(ret < 0);
2572}
2573
2574struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2575{
2576 struct pci_dev *dev;
2577
2578 dev = pci_get_slot(bus, devfn);
2579 if (dev) {
2580 pci_dev_put(dev);
2581 return dev;
2582 }
2583
2584 dev = pci_scan_device(bus, devfn);
2585 if (!dev)
2586 return NULL;
2587
2588 pci_device_add(dev, bus);
2589
2590 return dev;
2591}
2592EXPORT_SYMBOL(pci_scan_single_device);
2593
2594static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2595{
2596 int pos;
2597 u16 cap = 0;
2598 unsigned int next_fn;
2599
2600 if (!dev)
2601 return -ENODEV;
2602
2603 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2604 if (!pos)
2605 return -ENODEV;
2606
2607 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2608 next_fn = PCI_ARI_CAP_NFN(cap);
2609 if (next_fn <= fn)
2610 return -ENODEV; /* protect against malformed list */
2611
2612 return next_fn;
2613}
2614
2615static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2616{
2617 if (pci_ari_enabled(bus))
2618 return next_ari_fn(bus, dev, fn);
2619
2620 if (fn >= 7)
2621 return -ENODEV;
2622 /* only multifunction devices may have more functions */
2623 if (dev && !dev->multifunction)
2624 return -ENODEV;
2625
2626 return fn + 1;
2627}
2628
2629static int only_one_child(struct pci_bus *bus)
2630{
2631 struct pci_dev *bridge = bus->self;
2632
2633 /*
2634 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2635 * we scan for all possible devices, not just Device 0.
2636 */
2637 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2638 return 0;
2639
2640 /*
2641 * A PCIe Downstream Port normally leads to a Link with only Device
2642 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2643 * only for Device 0 in that situation.
2644 */
2645 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2646 return 1;
2647
2648 return 0;
2649}
2650
2651/**
2652 * pci_scan_slot - Scan a PCI slot on a bus for devices
2653 * @bus: PCI bus to scan
2654 * @devfn: slot number to scan (must have zero function)
2655 *
2656 * Scan a PCI slot on the specified PCI bus for devices, adding
2657 * discovered devices to the @bus->devices list. New devices
2658 * will not have is_added set.
2659 *
2660 * Returns the number of new devices found.
2661 */
2662int pci_scan_slot(struct pci_bus *bus, int devfn)
2663{
2664 struct pci_dev *dev;
2665 int fn = 0, nr = 0;
2666
2667 if (only_one_child(bus) && (devfn > 0))
2668 return 0; /* Already scanned the entire slot */
2669
2670 do {
2671 dev = pci_scan_single_device(bus, devfn + fn);
2672 if (dev) {
2673 if (!pci_dev_is_added(dev))
2674 nr++;
2675 if (fn > 0)
2676 dev->multifunction = 1;
2677 } else if (fn == 0) {
2678 /*
2679 * Function 0 is required unless we are running on
2680 * a hypervisor that passes through individual PCI
2681 * functions.
2682 */
2683 if (!hypervisor_isolated_pci_functions())
2684 break;
2685 }
2686 fn = next_fn(bus, dev, fn);
2687 } while (fn >= 0);
2688
2689 /* Only one slot has PCIe device */
2690 if (bus->self && nr)
2691 pcie_aspm_init_link_state(bus->self);
2692
2693 return nr;
2694}
2695EXPORT_SYMBOL(pci_scan_slot);
2696
2697static int pcie_find_smpss(struct pci_dev *dev, void *data)
2698{
2699 u8 *smpss = data;
2700
2701 if (!pci_is_pcie(dev))
2702 return 0;
2703
2704 /*
2705 * We don't have a way to change MPS settings on devices that have
2706 * drivers attached. A hot-added device might support only the minimum
2707 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2708 * where devices may be hot-added, we limit the fabric MPS to 128 so
2709 * hot-added devices will work correctly.
2710 *
2711 * However, if we hot-add a device to a slot directly below a Root
2712 * Port, it's impossible for there to be other existing devices below
2713 * the port. We don't limit the MPS in this case because we can
2714 * reconfigure MPS on both the Root Port and the hot-added device,
2715 * and there are no other devices involved.
2716 *
2717 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2718 */
2719 if (dev->is_hotplug_bridge &&
2720 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2721 *smpss = 0;
2722
2723 if (*smpss > dev->pcie_mpss)
2724 *smpss = dev->pcie_mpss;
2725
2726 return 0;
2727}
2728
2729static void pcie_write_mps(struct pci_dev *dev, int mps)
2730{
2731 int rc;
2732
2733 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2734 mps = 128 << dev->pcie_mpss;
2735
2736 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2737 dev->bus->self)
2738
2739 /*
2740 * For "Performance", the assumption is made that
2741 * downstream communication will never be larger than
2742 * the MRRS. So, the MPS only needs to be configured
2743 * for the upstream communication. This being the case,
2744 * walk from the top down and set the MPS of the child
2745 * to that of the parent bus.
2746 *
2747 * Configure the device MPS with the smaller of the
2748 * device MPSS or the bridge MPS (which is assumed to be
2749 * properly configured at this point to the largest
2750 * allowable MPS based on its parent bus).
2751 */
2752 mps = min(mps, pcie_get_mps(dev->bus->self));
2753 }
2754
2755 rc = pcie_set_mps(dev, mps);
2756 if (rc)
2757 pci_err(dev, "Failed attempting to set the MPS\n");
2758}
2759
2760static void pcie_write_mrrs(struct pci_dev *dev)
2761{
2762 int rc, mrrs;
2763
2764 /*
2765 * In the "safe" case, do not configure the MRRS. There appear to be
2766 * issues with setting MRRS to 0 on a number of devices.
2767 */
2768 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2769 return;
2770
2771 /*
2772 * For max performance, the MRRS must be set to the largest supported
2773 * value. However, it cannot be configured larger than the MPS the
2774 * device or the bus can support. This should already be properly
2775 * configured by a prior call to pcie_write_mps().
2776 */
2777 mrrs = pcie_get_mps(dev);
2778
2779 /*
2780 * MRRS is a R/W register. Invalid values can be written, but a
2781 * subsequent read will verify if the value is acceptable or not.
2782 * If the MRRS value provided is not acceptable (e.g., too large),
2783 * shrink the value until it is acceptable to the HW.
2784 */
2785 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2786 rc = pcie_set_readrq(dev, mrrs);
2787 if (!rc)
2788 break;
2789
2790 pci_warn(dev, "Failed attempting to set the MRRS\n");
2791 mrrs /= 2;
2792 }
2793
2794 if (mrrs < 128)
2795 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2796}
2797
2798static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2799{
2800 int mps, orig_mps;
2801
2802 if (!pci_is_pcie(dev))
2803 return 0;
2804
2805 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2806 pcie_bus_config == PCIE_BUS_DEFAULT)
2807 return 0;
2808
2809 mps = 128 << *(u8 *)data;
2810 orig_mps = pcie_get_mps(dev);
2811
2812 pcie_write_mps(dev, mps);
2813 pcie_write_mrrs(dev);
2814
2815 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2816 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2817 orig_mps, pcie_get_readrq(dev));
2818
2819 return 0;
2820}
2821
2822/*
2823 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2824 * parents then children fashion. If this changes, then this code will not
2825 * work as designed.
2826 */
2827void pcie_bus_configure_settings(struct pci_bus *bus)
2828{
2829 u8 smpss = 0;
2830
2831 if (!bus->self)
2832 return;
2833
2834 if (!pci_is_pcie(bus->self))
2835 return;
2836
2837 /*
2838 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2839 * to be aware of the MPS of the destination. To work around this,
2840 * simply force the MPS of the entire system to the smallest possible.
2841 */
2842 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2843 smpss = 0;
2844
2845 if (pcie_bus_config == PCIE_BUS_SAFE) {
2846 smpss = bus->self->pcie_mpss;
2847
2848 pcie_find_smpss(bus->self, &smpss);
2849 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2850 }
2851
2852 pcie_bus_configure_set(bus->self, &smpss);
2853 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2854}
2855EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2856
2857/*
2858 * Called after each bus is probed, but before its children are examined. This
2859 * is marked as __weak because multiple architectures define it.
2860 */
2861void __weak pcibios_fixup_bus(struct pci_bus *bus)
2862{
2863 /* nothing to do, expected to be removed in the future */
2864}
2865
2866/**
2867 * pci_scan_child_bus_extend() - Scan devices below a bus
2868 * @bus: Bus to scan for devices
2869 * @available_buses: Total number of buses available (%0 does not try to
2870 * extend beyond the minimal)
2871 *
2872 * Scans devices below @bus including subordinate buses. Returns new
2873 * subordinate number including all the found devices. Passing
2874 * @available_buses causes the remaining bus space to be distributed
2875 * equally between hotplug-capable bridges to allow future extension of the
2876 * hierarchy.
2877 */
2878static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2879 unsigned int available_buses)
2880{
2881 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2882 unsigned int start = bus->busn_res.start;
2883 unsigned int devfn, cmax, max = start;
2884 struct pci_dev *dev;
2885
2886 dev_dbg(&bus->dev, "scanning bus\n");
2887
2888 /* Go find them, Rover! */
2889 for (devfn = 0; devfn < 256; devfn += 8)
2890 pci_scan_slot(bus, devfn);
2891
2892 /* Reserve buses for SR-IOV capability */
2893 used_buses = pci_iov_bus_range(bus);
2894 max += used_buses;
2895
2896 /*
2897 * After performing arch-dependent fixup of the bus, look behind
2898 * all PCI-to-PCI bridges on this bus.
2899 */
2900 if (!bus->is_added) {
2901 dev_dbg(&bus->dev, "fixups for bus\n");
2902 pcibios_fixup_bus(bus);
2903 bus->is_added = 1;
2904 }
2905
2906 /*
2907 * Calculate how many hotplug bridges and normal bridges there
2908 * are on this bus. We will distribute the additional available
2909 * buses between hotplug bridges.
2910 */
2911 for_each_pci_bridge(dev, bus) {
2912 if (dev->is_hotplug_bridge)
2913 hotplug_bridges++;
2914 else
2915 normal_bridges++;
2916 }
2917
2918 /*
2919 * Scan bridges that are already configured. We don't touch them
2920 * unless they are misconfigured (which will be done in the second
2921 * scan below).
2922 */
2923 for_each_pci_bridge(dev, bus) {
2924 cmax = max;
2925 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2926
2927 /*
2928 * Reserve one bus for each bridge now to avoid extending
2929 * hotplug bridges too much during the second scan below.
2930 */
2931 used_buses++;
2932 if (max - cmax > 1)
2933 used_buses += max - cmax - 1;
2934 }
2935
2936 /* Scan bridges that need to be reconfigured */
2937 for_each_pci_bridge(dev, bus) {
2938 unsigned int buses = 0;
2939
2940 if (!hotplug_bridges && normal_bridges == 1) {
2941 /*
2942 * There is only one bridge on the bus (upstream
2943 * port) so it gets all available buses which it
2944 * can then distribute to the possible hotplug
2945 * bridges below.
2946 */
2947 buses = available_buses;
2948 } else if (dev->is_hotplug_bridge) {
2949 /*
2950 * Distribute the extra buses between hotplug
2951 * bridges if any.
2952 */
2953 buses = available_buses / hotplug_bridges;
2954 buses = min(buses, available_buses - used_buses + 1);
2955 }
2956
2957 cmax = max;
2958 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2959 /* One bus is already accounted so don't add it again */
2960 if (max - cmax > 1)
2961 used_buses += max - cmax - 1;
2962 }
2963
2964 /*
2965 * Make sure a hotplug bridge has at least the minimum requested
2966 * number of buses but allow it to grow up to the maximum available
2967 * bus number if there is room.
2968 */
2969 if (bus->self && bus->self->is_hotplug_bridge) {
2970 used_buses = max_t(unsigned int, available_buses,
2971 pci_hotplug_bus_size - 1);
2972 if (max - start < used_buses) {
2973 max = start + used_buses;
2974
2975 /* Do not allocate more buses than we have room left */
2976 if (max > bus->busn_res.end)
2977 max = bus->busn_res.end;
2978
2979 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2980 &bus->busn_res, max - start);
2981 }
2982 }
2983
2984 /*
2985 * We've scanned the bus and so we know all about what's on
2986 * the other side of any bridges that may be on this bus plus
2987 * any devices.
2988 *
2989 * Return how far we've got finding sub-buses.
2990 */
2991 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2992 return max;
2993}
2994
2995/**
2996 * pci_scan_child_bus() - Scan devices below a bus
2997 * @bus: Bus to scan for devices
2998 *
2999 * Scans devices below @bus including subordinate buses. Returns new
3000 * subordinate number including all the found devices.
3001 */
3002unsigned int pci_scan_child_bus(struct pci_bus *bus)
3003{
3004 return pci_scan_child_bus_extend(bus, 0);
3005}
3006EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3007
3008/**
3009 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3010 * @bridge: Host bridge to set up
3011 *
3012 * Default empty implementation. Replace with an architecture-specific setup
3013 * routine, if necessary.
3014 */
3015int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3016{
3017 return 0;
3018}
3019
3020void __weak pcibios_add_bus(struct pci_bus *bus)
3021{
3022}
3023
3024void __weak pcibios_remove_bus(struct pci_bus *bus)
3025{
3026}
3027
3028struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3029 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3030{
3031 int error;
3032 struct pci_host_bridge *bridge;
3033
3034 bridge = pci_alloc_host_bridge(0);
3035 if (!bridge)
3036 return NULL;
3037
3038 bridge->dev.parent = parent;
3039
3040 list_splice_init(resources, &bridge->windows);
3041 bridge->sysdata = sysdata;
3042 bridge->busnr = bus;
3043 bridge->ops = ops;
3044
3045 error = pci_register_host_bridge(bridge);
3046 if (error < 0)
3047 goto err_out;
3048
3049 return bridge->bus;
3050
3051err_out:
3052 put_device(&bridge->dev);
3053 return NULL;
3054}
3055EXPORT_SYMBOL_GPL(pci_create_root_bus);
3056
3057int pci_host_probe(struct pci_host_bridge *bridge)
3058{
3059 struct pci_bus *bus, *child;
3060 int ret;
3061
3062 ret = pci_scan_root_bus_bridge(bridge);
3063 if (ret < 0) {
3064 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3065 return ret;
3066 }
3067
3068 bus = bridge->bus;
3069
3070 /*
3071 * We insert PCI resources into the iomem_resource and
3072 * ioport_resource trees in either pci_bus_claim_resources()
3073 * or pci_bus_assign_resources().
3074 */
3075 if (pci_has_flag(PCI_PROBE_ONLY)) {
3076 pci_bus_claim_resources(bus);
3077 } else {
3078 pci_bus_size_bridges(bus);
3079 pci_bus_assign_resources(bus);
3080
3081 list_for_each_entry(child, &bus->children, node)
3082 pcie_bus_configure_settings(child);
3083 }
3084
3085 pci_bus_add_devices(bus);
3086 return 0;
3087}
3088EXPORT_SYMBOL_GPL(pci_host_probe);
3089
3090int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3091{
3092 struct resource *res = &b->busn_res;
3093 struct resource *parent_res, *conflict;
3094
3095 res->start = bus;
3096 res->end = bus_max;
3097 res->flags = IORESOURCE_BUS;
3098
3099 if (!pci_is_root_bus(b))
3100 parent_res = &b->parent->busn_res;
3101 else {
3102 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3103 res->flags |= IORESOURCE_PCI_FIXED;
3104 }
3105
3106 conflict = request_resource_conflict(parent_res, res);
3107
3108 if (conflict)
3109 dev_info(&b->dev,
3110 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3111 res, pci_is_root_bus(b) ? "domain " : "",
3112 parent_res, conflict->name, conflict);
3113
3114 return conflict == NULL;
3115}
3116
3117int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3118{
3119 struct resource *res = &b->busn_res;
3120 struct resource old_res = *res;
3121 resource_size_t size;
3122 int ret;
3123
3124 if (res->start > bus_max)
3125 return -EINVAL;
3126
3127 size = bus_max - res->start + 1;
3128 ret = adjust_resource(res, res->start, size);
3129 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3130 &old_res, ret ? "can not be" : "is", bus_max);
3131
3132 if (!ret && !res->parent)
3133 pci_bus_insert_busn_res(b, res->start, res->end);
3134
3135 return ret;
3136}
3137
3138void pci_bus_release_busn_res(struct pci_bus *b)
3139{
3140 struct resource *res = &b->busn_res;
3141 int ret;
3142
3143 if (!res->flags || !res->parent)
3144 return;
3145
3146 ret = release_resource(res);
3147 dev_info(&b->dev, "busn_res: %pR %s released\n",
3148 res, ret ? "can not be" : "is");
3149}
3150
3151int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3152{
3153 struct resource_entry *window;
3154 bool found = false;
3155 struct pci_bus *b;
3156 int max, bus, ret;
3157
3158 if (!bridge)
3159 return -EINVAL;
3160
3161 resource_list_for_each_entry(window, &bridge->windows)
3162 if (window->res->flags & IORESOURCE_BUS) {
3163 bridge->busnr = window->res->start;
3164 found = true;
3165 break;
3166 }
3167
3168 ret = pci_register_host_bridge(bridge);
3169 if (ret < 0)
3170 return ret;
3171
3172 b = bridge->bus;
3173 bus = bridge->busnr;
3174
3175 if (!found) {
3176 dev_info(&b->dev,
3177 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3178 bus);
3179 pci_bus_insert_busn_res(b, bus, 255);
3180 }
3181
3182 max = pci_scan_child_bus(b);
3183
3184 if (!found)
3185 pci_bus_update_busn_res_end(b, max);
3186
3187 return 0;
3188}
3189EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3190
3191struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3192 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3193{
3194 struct resource_entry *window;
3195 bool found = false;
3196 struct pci_bus *b;
3197 int max;
3198
3199 resource_list_for_each_entry(window, resources)
3200 if (window->res->flags & IORESOURCE_BUS) {
3201 found = true;
3202 break;
3203 }
3204
3205 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3206 if (!b)
3207 return NULL;
3208
3209 if (!found) {
3210 dev_info(&b->dev,
3211 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3212 bus);
3213 pci_bus_insert_busn_res(b, bus, 255);
3214 }
3215
3216 max = pci_scan_child_bus(b);
3217
3218 if (!found)
3219 pci_bus_update_busn_res_end(b, max);
3220
3221 return b;
3222}
3223EXPORT_SYMBOL(pci_scan_root_bus);
3224
3225struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3226 void *sysdata)
3227{
3228 LIST_HEAD(resources);
3229 struct pci_bus *b;
3230
3231 pci_add_resource(&resources, &ioport_resource);
3232 pci_add_resource(&resources, &iomem_resource);
3233 pci_add_resource(&resources, &busn_resource);
3234 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3235 if (b) {
3236 pci_scan_child_bus(b);
3237 } else {
3238 pci_free_resource_list(&resources);
3239 }
3240 return b;
3241}
3242EXPORT_SYMBOL(pci_scan_bus);
3243
3244/**
3245 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3246 * @bridge: PCI bridge for the bus to scan
3247 *
3248 * Scan a PCI bus and child buses for new devices, add them,
3249 * and enable them, resizing bridge mmio/io resource if necessary
3250 * and possible. The caller must ensure the child devices are already
3251 * removed for resizing to occur.
3252 *
3253 * Returns the max number of subordinate bus discovered.
3254 */
3255unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3256{
3257 unsigned int max;
3258 struct pci_bus *bus = bridge->subordinate;
3259
3260 max = pci_scan_child_bus(bus);
3261
3262 pci_assign_unassigned_bridge_resources(bridge);
3263
3264 pci_bus_add_devices(bus);
3265
3266 return max;
3267}
3268
3269/**
3270 * pci_rescan_bus - Scan a PCI bus for devices
3271 * @bus: PCI bus to scan
3272 *
3273 * Scan a PCI bus and child buses for new devices, add them,
3274 * and enable them.
3275 *
3276 * Returns the max number of subordinate bus discovered.
3277 */
3278unsigned int pci_rescan_bus(struct pci_bus *bus)
3279{
3280 unsigned int max;
3281
3282 max = pci_scan_child_bus(bus);
3283 pci_assign_unassigned_bus_resources(bus);
3284 pci_bus_add_devices(bus);
3285
3286 return max;
3287}
3288EXPORT_SYMBOL_GPL(pci_rescan_bus);
3289
3290/*
3291 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3292 * routines should always be executed under this mutex.
3293 */
3294static DEFINE_MUTEX(pci_rescan_remove_lock);
3295
3296void pci_lock_rescan_remove(void)
3297{
3298 mutex_lock(&pci_rescan_remove_lock);
3299}
3300EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3301
3302void pci_unlock_rescan_remove(void)
3303{
3304 mutex_unlock(&pci_rescan_remove_lock);
3305}
3306EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3307
3308static int __init pci_sort_bf_cmp(const struct device *d_a,
3309 const struct device *d_b)
3310{
3311 const struct pci_dev *a = to_pci_dev(d_a);
3312 const struct pci_dev *b = to_pci_dev(d_b);
3313
3314 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3315 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3316
3317 if (a->bus->number < b->bus->number) return -1;
3318 else if (a->bus->number > b->bus->number) return 1;
3319
3320 if (a->devfn < b->devfn) return -1;
3321 else if (a->devfn > b->devfn) return 1;
3322
3323 return 0;
3324}
3325
3326void __init pci_sort_breadthfirst(void)
3327{
3328 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3329}
3330
3331int pci_hp_add_bridge(struct pci_dev *dev)
3332{
3333 struct pci_bus *parent = dev->bus;
3334 int busnr, start = parent->busn_res.start;
3335 unsigned int available_buses = 0;
3336 int end = parent->busn_res.end;
3337
3338 for (busnr = start; busnr <= end; busnr++) {
3339 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3340 break;
3341 }
3342 if (busnr-- > end) {
3343 pci_err(dev, "No bus number available for hot-added bridge\n");
3344 return -1;
3345 }
3346
3347 /* Scan bridges that are already configured */
3348 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3349
3350 /*
3351 * Distribute the available bus numbers between hotplug-capable
3352 * bridges to make extending the chain later possible.
3353 */
3354 available_buses = end - busnr;
3355
3356 /* Scan bridges that need to be reconfigured */
3357 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3358
3359 if (!dev->subordinate)
3360 return -1;
3361
3362 return 0;
3363}
3364EXPORT_SYMBOL_GPL(pci_hp_add_bridge);