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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX drm driver - Television Encoder (TVEv2)
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/regulator/consumer.h>
16#include <linux/spinlock.h>
17#include <linux/videodev2.h>
18
19#include <video/imx-ipu-v3.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_fb_helper.h>
23#include <drm/drm_probe_helper.h>
24
25#include "imx-drm.h"
26
27#define TVE_COM_CONF_REG 0x00
28#define TVE_TVDAC0_CONT_REG 0x28
29#define TVE_TVDAC1_CONT_REG 0x2c
30#define TVE_TVDAC2_CONT_REG 0x30
31#define TVE_CD_CONT_REG 0x34
32#define TVE_INT_CONT_REG 0x64
33#define TVE_STAT_REG 0x68
34#define TVE_TST_MODE_REG 0x6c
35#define TVE_MV_CONT_REG 0xdc
36
37/* TVE_COM_CONF_REG */
38#define TVE_SYNC_CH_2_EN BIT(22)
39#define TVE_SYNC_CH_1_EN BIT(21)
40#define TVE_SYNC_CH_0_EN BIT(20)
41#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
42#define TVE_TV_OUT_DISABLE (0x0 << 12)
43#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
44#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
45#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
46#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
47#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
48#define TVE_TV_OUT_YPBPR (0x6 << 12)
49#define TVE_TV_OUT_RGB (0x7 << 12)
50#define TVE_TV_STAND_MASK (0xf << 8)
51#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
52#define TVE_P2I_CONV_EN BIT(7)
53#define TVE_INP_VIDEO_FORM BIT(6)
54#define TVE_INP_YCBCR_422 (0x0 << 6)
55#define TVE_INP_YCBCR_444 (0x1 << 6)
56#define TVE_DATA_SOURCE_MASK (0x3 << 4)
57#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
58#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
59#define TVE_DATA_SOURCE_EXT (0x2 << 4)
60#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
61#define TVE_IPU_CLK_EN_OFS 3
62#define TVE_IPU_CLK_EN BIT(3)
63#define TVE_DAC_SAMP_RATE_OFS 1
64#define TVE_DAC_SAMP_RATE_WIDTH 2
65#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
66#define TVE_DAC_FULL_RATE (0x0 << 1)
67#define TVE_DAC_DIV2_RATE (0x1 << 1)
68#define TVE_DAC_DIV4_RATE (0x2 << 1)
69#define TVE_EN BIT(0)
70
71/* TVE_TVDACx_CONT_REG */
72#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
73
74/* TVE_CD_CONT_REG */
75#define TVE_CD_CH_2_SM_EN BIT(22)
76#define TVE_CD_CH_1_SM_EN BIT(21)
77#define TVE_CD_CH_0_SM_EN BIT(20)
78#define TVE_CD_CH_2_LM_EN BIT(18)
79#define TVE_CD_CH_1_LM_EN BIT(17)
80#define TVE_CD_CH_0_LM_EN BIT(16)
81#define TVE_CD_CH_2_REF_LVL BIT(10)
82#define TVE_CD_CH_1_REF_LVL BIT(9)
83#define TVE_CD_CH_0_REF_LVL BIT(8)
84#define TVE_CD_EN BIT(0)
85
86/* TVE_INT_CONT_REG */
87#define TVE_FRAME_END_IEN BIT(13)
88#define TVE_CD_MON_END_IEN BIT(2)
89#define TVE_CD_SM_IEN BIT(1)
90#define TVE_CD_LM_IEN BIT(0)
91
92/* TVE_TST_MODE_REG */
93#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
94
95#define IMX_TVE_DAC_VOLTAGE 2750000
96
97enum {
98 TVE_MODE_TVOUT,
99 TVE_MODE_VGA,
100};
101
102struct imx_tve {
103 struct drm_connector connector;
104 struct drm_encoder encoder;
105 struct device *dev;
106 spinlock_t lock; /* register lock */
107 bool enabled;
108 int mode;
109 int di_hsync_pin;
110 int di_vsync_pin;
111
112 struct regmap *regmap;
113 struct regulator *dac_reg;
114 struct i2c_adapter *ddc;
115 struct clk *clk;
116 struct clk *di_sel_clk;
117 struct clk_hw clk_hw_di;
118 struct clk *di_clk;
119};
120
121static inline struct imx_tve *con_to_tve(struct drm_connector *c)
122{
123 return container_of(c, struct imx_tve, connector);
124}
125
126static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
127{
128 return container_of(e, struct imx_tve, encoder);
129}
130
131static void tve_lock(void *__tve)
132__acquires(&tve->lock)
133{
134 struct imx_tve *tve = __tve;
135
136 spin_lock(&tve->lock);
137}
138
139static void tve_unlock(void *__tve)
140__releases(&tve->lock)
141{
142 struct imx_tve *tve = __tve;
143
144 spin_unlock(&tve->lock);
145}
146
147static void tve_enable(struct imx_tve *tve)
148{
149 if (!tve->enabled) {
150 tve->enabled = true;
151 clk_prepare_enable(tve->clk);
152 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
153 TVE_EN, TVE_EN);
154 }
155
156 /* clear interrupt status register */
157 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
158
159 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
160 if (tve->mode == TVE_MODE_VGA)
161 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
162 else
163 regmap_write(tve->regmap, TVE_INT_CONT_REG,
164 TVE_CD_SM_IEN |
165 TVE_CD_LM_IEN |
166 TVE_CD_MON_END_IEN);
167}
168
169static void tve_disable(struct imx_tve *tve)
170{
171 if (tve->enabled) {
172 tve->enabled = false;
173 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
174 clk_disable_unprepare(tve->clk);
175 }
176}
177
178static int tve_setup_tvout(struct imx_tve *tve)
179{
180 return -ENOTSUPP;
181}
182
183static int tve_setup_vga(struct imx_tve *tve)
184{
185 unsigned int mask;
186 unsigned int val;
187 int ret;
188
189 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
190 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
191 TVE_TVDAC_GAIN_MASK, 0x0a);
192 if (ret)
193 return ret;
194
195 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
196 TVE_TVDAC_GAIN_MASK, 0x0a);
197 if (ret)
198 return ret;
199
200 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
201 TVE_TVDAC_GAIN_MASK, 0x0a);
202 if (ret)
203 return ret;
204
205 /* set configuration register */
206 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
207 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
208 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
209 val |= TVE_TV_STAND_HD_1080P30 | 0;
210 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
211 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
212 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
213 if (ret)
214 return ret;
215
216 /* set test mode (as documented) */
217 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
218 TVE_TVDAC_TEST_MODE_MASK, 1);
219}
220
221static int imx_tve_connector_get_modes(struct drm_connector *connector)
222{
223 struct imx_tve *tve = con_to_tve(connector);
224 struct edid *edid;
225 int ret = 0;
226
227 if (!tve->ddc)
228 return 0;
229
230 edid = drm_get_edid(connector, tve->ddc);
231 if (edid) {
232 drm_connector_update_edid_property(connector, edid);
233 ret = drm_add_edid_modes(connector, edid);
234 kfree(edid);
235 }
236
237 return ret;
238}
239
240static int imx_tve_connector_mode_valid(struct drm_connector *connector,
241 struct drm_display_mode *mode)
242{
243 struct imx_tve *tve = con_to_tve(connector);
244 unsigned long rate;
245
246 /* pixel clock with 2x oversampling */
247 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
248 if (rate == mode->clock)
249 return MODE_OK;
250
251 /* pixel clock without oversampling */
252 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
253 if (rate == mode->clock)
254 return MODE_OK;
255
256 dev_warn(tve->dev, "ignoring mode %dx%d\n",
257 mode->hdisplay, mode->vdisplay);
258
259 return MODE_BAD;
260}
261
262static struct drm_encoder *imx_tve_connector_best_encoder(
263 struct drm_connector *connector)
264{
265 struct imx_tve *tve = con_to_tve(connector);
266
267 return &tve->encoder;
268}
269
270static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
271 struct drm_display_mode *orig_mode,
272 struct drm_display_mode *mode)
273{
274 struct imx_tve *tve = enc_to_tve(encoder);
275 unsigned long rounded_rate;
276 unsigned long rate;
277 int div = 1;
278 int ret;
279
280 /*
281 * FIXME
282 * we should try 4k * mode->clock first,
283 * and enable 4x oversampling for lower resolutions
284 */
285 rate = 2000UL * mode->clock;
286 clk_set_rate(tve->clk, rate);
287 rounded_rate = clk_get_rate(tve->clk);
288 if (rounded_rate >= rate)
289 div = 2;
290 clk_set_rate(tve->di_clk, rounded_rate / div);
291
292 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
293 if (ret < 0) {
294 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
295 ret);
296 }
297
298 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
299 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
300
301 if (tve->mode == TVE_MODE_VGA)
302 ret = tve_setup_vga(tve);
303 else
304 ret = tve_setup_tvout(tve);
305 if (ret)
306 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
307}
308
309static void imx_tve_encoder_enable(struct drm_encoder *encoder)
310{
311 struct imx_tve *tve = enc_to_tve(encoder);
312
313 tve_enable(tve);
314}
315
316static void imx_tve_encoder_disable(struct drm_encoder *encoder)
317{
318 struct imx_tve *tve = enc_to_tve(encoder);
319
320 tve_disable(tve);
321}
322
323static int imx_tve_atomic_check(struct drm_encoder *encoder,
324 struct drm_crtc_state *crtc_state,
325 struct drm_connector_state *conn_state)
326{
327 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
328 struct imx_tve *tve = enc_to_tve(encoder);
329
330 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
331 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
332 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
333
334 return 0;
335}
336
337static const struct drm_connector_funcs imx_tve_connector_funcs = {
338 .fill_modes = drm_helper_probe_single_connector_modes,
339 .destroy = imx_drm_connector_destroy,
340 .reset = drm_atomic_helper_connector_reset,
341 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
342 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
343};
344
345static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
346 .get_modes = imx_tve_connector_get_modes,
347 .best_encoder = imx_tve_connector_best_encoder,
348 .mode_valid = imx_tve_connector_mode_valid,
349};
350
351static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
352 .destroy = imx_drm_encoder_destroy,
353};
354
355static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
356 .mode_set = imx_tve_encoder_mode_set,
357 .enable = imx_tve_encoder_enable,
358 .disable = imx_tve_encoder_disable,
359 .atomic_check = imx_tve_atomic_check,
360};
361
362static irqreturn_t imx_tve_irq_handler(int irq, void *data)
363{
364 struct imx_tve *tve = data;
365 unsigned int val;
366
367 regmap_read(tve->regmap, TVE_STAT_REG, &val);
368
369 /* clear interrupt status register */
370 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
371
372 return IRQ_HANDLED;
373}
374
375static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
376 unsigned long parent_rate)
377{
378 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
379 unsigned int val;
380 int ret;
381
382 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
383 if (ret < 0)
384 return 0;
385
386 switch (val & TVE_DAC_SAMP_RATE_MASK) {
387 case TVE_DAC_DIV4_RATE:
388 return parent_rate / 4;
389 case TVE_DAC_DIV2_RATE:
390 return parent_rate / 2;
391 case TVE_DAC_FULL_RATE:
392 default:
393 return parent_rate;
394 }
395
396 return 0;
397}
398
399static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
400 unsigned long *prate)
401{
402 unsigned long div;
403
404 div = *prate / rate;
405 if (div >= 4)
406 return *prate / 4;
407 else if (div >= 2)
408 return *prate / 2;
409 return *prate;
410}
411
412static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long parent_rate)
414{
415 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
416 unsigned long div;
417 u32 val;
418 int ret;
419
420 div = parent_rate / rate;
421 if (div >= 4)
422 val = TVE_DAC_DIV4_RATE;
423 else if (div >= 2)
424 val = TVE_DAC_DIV2_RATE;
425 else
426 val = TVE_DAC_FULL_RATE;
427
428 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
429 TVE_DAC_SAMP_RATE_MASK, val);
430
431 if (ret < 0) {
432 dev_err(tve->dev, "failed to set divider: %d\n", ret);
433 return ret;
434 }
435
436 return 0;
437}
438
439static const struct clk_ops clk_tve_di_ops = {
440 .round_rate = clk_tve_di_round_rate,
441 .set_rate = clk_tve_di_set_rate,
442 .recalc_rate = clk_tve_di_recalc_rate,
443};
444
445static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
446{
447 const char *tve_di_parent[1];
448 struct clk_init_data init = {
449 .name = "tve_di",
450 .ops = &clk_tve_di_ops,
451 .num_parents = 1,
452 .flags = 0,
453 };
454
455 tve_di_parent[0] = __clk_get_name(tve->clk);
456 init.parent_names = (const char **)&tve_di_parent;
457
458 tve->clk_hw_di.init = &init;
459 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
460 if (IS_ERR(tve->di_clk)) {
461 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
462 PTR_ERR(tve->di_clk));
463 return PTR_ERR(tve->di_clk);
464 }
465
466 return 0;
467}
468
469static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
470{
471 int encoder_type;
472 int ret;
473
474 encoder_type = tve->mode == TVE_MODE_VGA ?
475 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
476
477 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
478 if (ret)
479 return ret;
480
481 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
482 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
483 encoder_type, NULL);
484
485 drm_connector_helper_add(&tve->connector,
486 &imx_tve_connector_helper_funcs);
487 drm_connector_init_with_ddc(drm, &tve->connector,
488 &imx_tve_connector_funcs,
489 DRM_MODE_CONNECTOR_VGA,
490 tve->ddc);
491
492 drm_connector_attach_encoder(&tve->connector, &tve->encoder);
493
494 return 0;
495}
496
497static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
498{
499 return (reg % 4 == 0) && (reg <= 0xdc);
500}
501
502static struct regmap_config tve_regmap_config = {
503 .reg_bits = 32,
504 .val_bits = 32,
505 .reg_stride = 4,
506
507 .readable_reg = imx_tve_readable_reg,
508
509 .lock = tve_lock,
510 .unlock = tve_unlock,
511
512 .max_register = 0xdc,
513};
514
515static const char * const imx_tve_modes[] = {
516 [TVE_MODE_TVOUT] = "tvout",
517 [TVE_MODE_VGA] = "vga",
518};
519
520static const int of_get_tve_mode(struct device_node *np)
521{
522 const char *bm;
523 int ret, i;
524
525 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
526 if (ret < 0)
527 return ret;
528
529 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
530 if (!strcasecmp(bm, imx_tve_modes[i]))
531 return i;
532
533 return -EINVAL;
534}
535
536static int imx_tve_bind(struct device *dev, struct device *master, void *data)
537{
538 struct platform_device *pdev = to_platform_device(dev);
539 struct drm_device *drm = data;
540 struct device_node *np = dev->of_node;
541 struct device_node *ddc_node;
542 struct imx_tve *tve;
543 struct resource *res;
544 void __iomem *base;
545 unsigned int val;
546 int irq;
547 int ret;
548
549 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
550 if (!tve)
551 return -ENOMEM;
552
553 tve->dev = dev;
554 spin_lock_init(&tve->lock);
555
556 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
557 if (ddc_node) {
558 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
559 of_node_put(ddc_node);
560 }
561
562 tve->mode = of_get_tve_mode(np);
563 if (tve->mode != TVE_MODE_VGA) {
564 dev_err(dev, "only VGA mode supported, currently\n");
565 return -EINVAL;
566 }
567
568 if (tve->mode == TVE_MODE_VGA) {
569 ret = of_property_read_u32(np, "fsl,hsync-pin",
570 &tve->di_hsync_pin);
571
572 if (ret < 0) {
573 dev_err(dev, "failed to get hsync pin\n");
574 return ret;
575 }
576
577 ret = of_property_read_u32(np, "fsl,vsync-pin",
578 &tve->di_vsync_pin);
579
580 if (ret < 0) {
581 dev_err(dev, "failed to get vsync pin\n");
582 return ret;
583 }
584 }
585
586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
587 base = devm_ioremap_resource(dev, res);
588 if (IS_ERR(base))
589 return PTR_ERR(base);
590
591 tve_regmap_config.lock_arg = tve;
592 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
593 &tve_regmap_config);
594 if (IS_ERR(tve->regmap)) {
595 dev_err(dev, "failed to init regmap: %ld\n",
596 PTR_ERR(tve->regmap));
597 return PTR_ERR(tve->regmap);
598 }
599
600 irq = platform_get_irq(pdev, 0);
601 if (irq < 0) {
602 dev_err(dev, "failed to get irq\n");
603 return irq;
604 }
605
606 ret = devm_request_threaded_irq(dev, irq, NULL,
607 imx_tve_irq_handler, IRQF_ONESHOT,
608 "imx-tve", tve);
609 if (ret < 0) {
610 dev_err(dev, "failed to request irq: %d\n", ret);
611 return ret;
612 }
613
614 tve->dac_reg = devm_regulator_get(dev, "dac");
615 if (!IS_ERR(tve->dac_reg)) {
616 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
617 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
618 ret = regulator_enable(tve->dac_reg);
619 if (ret)
620 return ret;
621 }
622
623 tve->clk = devm_clk_get(dev, "tve");
624 if (IS_ERR(tve->clk)) {
625 dev_err(dev, "failed to get high speed tve clock: %ld\n",
626 PTR_ERR(tve->clk));
627 return PTR_ERR(tve->clk);
628 }
629
630 /* this is the IPU DI clock input selector, can be parented to tve_di */
631 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
632 if (IS_ERR(tve->di_sel_clk)) {
633 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
634 PTR_ERR(tve->di_sel_clk));
635 return PTR_ERR(tve->di_sel_clk);
636 }
637
638 ret = tve_clk_init(tve, base);
639 if (ret < 0)
640 return ret;
641
642 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
643 if (ret < 0) {
644 dev_err(dev, "failed to read configuration register: %d\n",
645 ret);
646 return ret;
647 }
648 if (val != 0x00100000) {
649 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
650 return -ENODEV;
651 }
652
653 /* disable cable detection for VGA mode */
654 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
655 if (ret)
656 return ret;
657
658 ret = imx_tve_register(drm, tve);
659 if (ret)
660 return ret;
661
662 dev_set_drvdata(dev, tve);
663
664 return 0;
665}
666
667static void imx_tve_unbind(struct device *dev, struct device *master,
668 void *data)
669{
670 struct imx_tve *tve = dev_get_drvdata(dev);
671
672 if (!IS_ERR(tve->dac_reg))
673 regulator_disable(tve->dac_reg);
674}
675
676static const struct component_ops imx_tve_ops = {
677 .bind = imx_tve_bind,
678 .unbind = imx_tve_unbind,
679};
680
681static int imx_tve_probe(struct platform_device *pdev)
682{
683 return component_add(&pdev->dev, &imx_tve_ops);
684}
685
686static int imx_tve_remove(struct platform_device *pdev)
687{
688 component_del(&pdev->dev, &imx_tve_ops);
689 return 0;
690}
691
692static const struct of_device_id imx_tve_dt_ids[] = {
693 { .compatible = "fsl,imx53-tve", },
694 { /* sentinel */ }
695};
696MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
697
698static struct platform_driver imx_tve_driver = {
699 .probe = imx_tve_probe,
700 .remove = imx_tve_remove,
701 .driver = {
702 .of_match_table = imx_tve_dt_ids,
703 .name = "imx-tve",
704 },
705};
706
707module_platform_driver(imx_tve_driver);
708
709MODULE_DESCRIPTION("i.MX Television Encoder driver");
710MODULE_AUTHOR("Philipp Zabel, Pengutronix");
711MODULE_LICENSE("GPL");
712MODULE_ALIAS("platform:imx-tve");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX drm driver - Television Encoder (TVEv2)
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/regulator/consumer.h>
16#include <linux/videodev2.h>
17
18#include <video/imx-ipu-v3.h>
19
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_edid.h>
22#include <drm/drm_managed.h>
23#include <drm/drm_probe_helper.h>
24#include <drm/drm_simple_kms_helper.h>
25
26#include "imx-drm.h"
27
28#define TVE_COM_CONF_REG 0x00
29#define TVE_TVDAC0_CONT_REG 0x28
30#define TVE_TVDAC1_CONT_REG 0x2c
31#define TVE_TVDAC2_CONT_REG 0x30
32#define TVE_CD_CONT_REG 0x34
33#define TVE_INT_CONT_REG 0x64
34#define TVE_STAT_REG 0x68
35#define TVE_TST_MODE_REG 0x6c
36#define TVE_MV_CONT_REG 0xdc
37
38/* TVE_COM_CONF_REG */
39#define TVE_SYNC_CH_2_EN BIT(22)
40#define TVE_SYNC_CH_1_EN BIT(21)
41#define TVE_SYNC_CH_0_EN BIT(20)
42#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
43#define TVE_TV_OUT_DISABLE (0x0 << 12)
44#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
45#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
46#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
47#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
48#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
49#define TVE_TV_OUT_YPBPR (0x6 << 12)
50#define TVE_TV_OUT_RGB (0x7 << 12)
51#define TVE_TV_STAND_MASK (0xf << 8)
52#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
53#define TVE_P2I_CONV_EN BIT(7)
54#define TVE_INP_VIDEO_FORM BIT(6)
55#define TVE_INP_YCBCR_422 (0x0 << 6)
56#define TVE_INP_YCBCR_444 (0x1 << 6)
57#define TVE_DATA_SOURCE_MASK (0x3 << 4)
58#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
59#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
60#define TVE_DATA_SOURCE_EXT (0x2 << 4)
61#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
62#define TVE_IPU_CLK_EN_OFS 3
63#define TVE_IPU_CLK_EN BIT(3)
64#define TVE_DAC_SAMP_RATE_OFS 1
65#define TVE_DAC_SAMP_RATE_WIDTH 2
66#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
67#define TVE_DAC_FULL_RATE (0x0 << 1)
68#define TVE_DAC_DIV2_RATE (0x1 << 1)
69#define TVE_DAC_DIV4_RATE (0x2 << 1)
70#define TVE_EN BIT(0)
71
72/* TVE_TVDACx_CONT_REG */
73#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
74
75/* TVE_CD_CONT_REG */
76#define TVE_CD_CH_2_SM_EN BIT(22)
77#define TVE_CD_CH_1_SM_EN BIT(21)
78#define TVE_CD_CH_0_SM_EN BIT(20)
79#define TVE_CD_CH_2_LM_EN BIT(18)
80#define TVE_CD_CH_1_LM_EN BIT(17)
81#define TVE_CD_CH_0_LM_EN BIT(16)
82#define TVE_CD_CH_2_REF_LVL BIT(10)
83#define TVE_CD_CH_1_REF_LVL BIT(9)
84#define TVE_CD_CH_0_REF_LVL BIT(8)
85#define TVE_CD_EN BIT(0)
86
87/* TVE_INT_CONT_REG */
88#define TVE_FRAME_END_IEN BIT(13)
89#define TVE_CD_MON_END_IEN BIT(2)
90#define TVE_CD_SM_IEN BIT(1)
91#define TVE_CD_LM_IEN BIT(0)
92
93/* TVE_TST_MODE_REG */
94#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
95
96#define IMX_TVE_DAC_VOLTAGE 2750000
97
98enum {
99 TVE_MODE_TVOUT,
100 TVE_MODE_VGA,
101};
102
103struct imx_tve_encoder {
104 struct drm_connector connector;
105 struct drm_encoder encoder;
106 struct imx_tve *tve;
107};
108
109struct imx_tve {
110 struct device *dev;
111 int mode;
112 int di_hsync_pin;
113 int di_vsync_pin;
114
115 struct regmap *regmap;
116 struct regulator *dac_reg;
117 struct i2c_adapter *ddc;
118 struct clk *clk;
119 struct clk *di_sel_clk;
120 struct clk_hw clk_hw_di;
121 struct clk *di_clk;
122};
123
124static inline struct imx_tve *con_to_tve(struct drm_connector *c)
125{
126 return container_of(c, struct imx_tve_encoder, connector)->tve;
127}
128
129static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
130{
131 return container_of(e, struct imx_tve_encoder, encoder)->tve;
132}
133
134static void tve_enable(struct imx_tve *tve)
135{
136 clk_prepare_enable(tve->clk);
137 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
138
139 /* clear interrupt status register */
140 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
141
142 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
143 if (tve->mode == TVE_MODE_VGA)
144 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
145 else
146 regmap_write(tve->regmap, TVE_INT_CONT_REG,
147 TVE_CD_SM_IEN |
148 TVE_CD_LM_IEN |
149 TVE_CD_MON_END_IEN);
150}
151
152static void tve_disable(struct imx_tve *tve)
153{
154 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
155 clk_disable_unprepare(tve->clk);
156}
157
158static int tve_setup_tvout(struct imx_tve *tve)
159{
160 return -ENOTSUPP;
161}
162
163static int tve_setup_vga(struct imx_tve *tve)
164{
165 unsigned int mask;
166 unsigned int val;
167 int ret;
168
169 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
170 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
171 TVE_TVDAC_GAIN_MASK, 0x0a);
172 if (ret)
173 return ret;
174
175 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
176 TVE_TVDAC_GAIN_MASK, 0x0a);
177 if (ret)
178 return ret;
179
180 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
181 TVE_TVDAC_GAIN_MASK, 0x0a);
182 if (ret)
183 return ret;
184
185 /* set configuration register */
186 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
187 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
188 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
189 val |= TVE_TV_STAND_HD_1080P30 | 0;
190 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
191 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
192 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
193 if (ret)
194 return ret;
195
196 /* set test mode (as documented) */
197 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
198 TVE_TVDAC_TEST_MODE_MASK, 1);
199}
200
201static int imx_tve_connector_get_modes(struct drm_connector *connector)
202{
203 struct imx_tve *tve = con_to_tve(connector);
204 struct edid *edid;
205 int ret = 0;
206
207 if (!tve->ddc)
208 return 0;
209
210 edid = drm_get_edid(connector, tve->ddc);
211 if (edid) {
212 drm_connector_update_edid_property(connector, edid);
213 ret = drm_add_edid_modes(connector, edid);
214 kfree(edid);
215 }
216
217 return ret;
218}
219
220static enum drm_mode_status
221imx_tve_connector_mode_valid(struct drm_connector *connector,
222 struct drm_display_mode *mode)
223{
224 struct imx_tve *tve = con_to_tve(connector);
225 unsigned long rate;
226
227 /* pixel clock with 2x oversampling */
228 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
229 if (rate == mode->clock)
230 return MODE_OK;
231
232 /* pixel clock without oversampling */
233 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
234 if (rate == mode->clock)
235 return MODE_OK;
236
237 dev_warn(tve->dev, "ignoring mode %dx%d\n",
238 mode->hdisplay, mode->vdisplay);
239
240 return MODE_BAD;
241}
242
243static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
244 struct drm_display_mode *orig_mode,
245 struct drm_display_mode *mode)
246{
247 struct imx_tve *tve = enc_to_tve(encoder);
248 unsigned long rounded_rate;
249 unsigned long rate;
250 int div = 1;
251 int ret;
252
253 /*
254 * FIXME
255 * we should try 4k * mode->clock first,
256 * and enable 4x oversampling for lower resolutions
257 */
258 rate = 2000UL * mode->clock;
259 clk_set_rate(tve->clk, rate);
260 rounded_rate = clk_get_rate(tve->clk);
261 if (rounded_rate >= rate)
262 div = 2;
263 clk_set_rate(tve->di_clk, rounded_rate / div);
264
265 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
266 if (ret < 0) {
267 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
268 ret);
269 }
270
271 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
272 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
273
274 if (tve->mode == TVE_MODE_VGA)
275 ret = tve_setup_vga(tve);
276 else
277 ret = tve_setup_tvout(tve);
278 if (ret)
279 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
280}
281
282static void imx_tve_encoder_enable(struct drm_encoder *encoder)
283{
284 struct imx_tve *tve = enc_to_tve(encoder);
285
286 tve_enable(tve);
287}
288
289static void imx_tve_encoder_disable(struct drm_encoder *encoder)
290{
291 struct imx_tve *tve = enc_to_tve(encoder);
292
293 tve_disable(tve);
294}
295
296static int imx_tve_atomic_check(struct drm_encoder *encoder,
297 struct drm_crtc_state *crtc_state,
298 struct drm_connector_state *conn_state)
299{
300 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
301 struct imx_tve *tve = enc_to_tve(encoder);
302
303 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
304 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
305 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
306
307 return 0;
308}
309
310static const struct drm_connector_funcs imx_tve_connector_funcs = {
311 .fill_modes = drm_helper_probe_single_connector_modes,
312 .destroy = imx_drm_connector_destroy,
313 .reset = drm_atomic_helper_connector_reset,
314 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
315 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
316};
317
318static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
319 .get_modes = imx_tve_connector_get_modes,
320 .mode_valid = imx_tve_connector_mode_valid,
321};
322
323static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
324 .mode_set = imx_tve_encoder_mode_set,
325 .enable = imx_tve_encoder_enable,
326 .disable = imx_tve_encoder_disable,
327 .atomic_check = imx_tve_atomic_check,
328};
329
330static irqreturn_t imx_tve_irq_handler(int irq, void *data)
331{
332 struct imx_tve *tve = data;
333 unsigned int val;
334
335 regmap_read(tve->regmap, TVE_STAT_REG, &val);
336
337 /* clear interrupt status register */
338 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
339
340 return IRQ_HANDLED;
341}
342
343static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
344 unsigned long parent_rate)
345{
346 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
347 unsigned int val;
348 int ret;
349
350 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
351 if (ret < 0)
352 return 0;
353
354 switch (val & TVE_DAC_SAMP_RATE_MASK) {
355 case TVE_DAC_DIV4_RATE:
356 return parent_rate / 4;
357 case TVE_DAC_DIV2_RATE:
358 return parent_rate / 2;
359 case TVE_DAC_FULL_RATE:
360 default:
361 return parent_rate;
362 }
363
364 return 0;
365}
366
367static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
368 unsigned long *prate)
369{
370 unsigned long div;
371
372 div = *prate / rate;
373 if (div >= 4)
374 return *prate / 4;
375 else if (div >= 2)
376 return *prate / 2;
377 return *prate;
378}
379
380static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
381 unsigned long parent_rate)
382{
383 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
384 unsigned long div;
385 u32 val;
386 int ret;
387
388 div = parent_rate / rate;
389 if (div >= 4)
390 val = TVE_DAC_DIV4_RATE;
391 else if (div >= 2)
392 val = TVE_DAC_DIV2_RATE;
393 else
394 val = TVE_DAC_FULL_RATE;
395
396 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
397 TVE_DAC_SAMP_RATE_MASK, val);
398
399 if (ret < 0) {
400 dev_err(tve->dev, "failed to set divider: %d\n", ret);
401 return ret;
402 }
403
404 return 0;
405}
406
407static const struct clk_ops clk_tve_di_ops = {
408 .round_rate = clk_tve_di_round_rate,
409 .set_rate = clk_tve_di_set_rate,
410 .recalc_rate = clk_tve_di_recalc_rate,
411};
412
413static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
414{
415 const char *tve_di_parent[1];
416 struct clk_init_data init = {
417 .name = "tve_di",
418 .ops = &clk_tve_di_ops,
419 .num_parents = 1,
420 .flags = 0,
421 };
422
423 tve_di_parent[0] = __clk_get_name(tve->clk);
424 init.parent_names = (const char **)&tve_di_parent;
425
426 tve->clk_hw_di.init = &init;
427 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
428 if (IS_ERR(tve->di_clk)) {
429 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
430 PTR_ERR(tve->di_clk));
431 return PTR_ERR(tve->di_clk);
432 }
433
434 return 0;
435}
436
437static void imx_tve_disable_regulator(void *data)
438{
439 struct imx_tve *tve = data;
440
441 regulator_disable(tve->dac_reg);
442}
443
444static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
445{
446 return (reg % 4 == 0) && (reg <= 0xdc);
447}
448
449static struct regmap_config tve_regmap_config = {
450 .reg_bits = 32,
451 .val_bits = 32,
452 .reg_stride = 4,
453
454 .readable_reg = imx_tve_readable_reg,
455
456 .fast_io = true,
457
458 .max_register = 0xdc,
459};
460
461static const char * const imx_tve_modes[] = {
462 [TVE_MODE_TVOUT] = "tvout",
463 [TVE_MODE_VGA] = "vga",
464};
465
466static int of_get_tve_mode(struct device_node *np)
467{
468 const char *bm;
469 int ret, i;
470
471 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
472 if (ret < 0)
473 return ret;
474
475 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
476 if (!strcasecmp(bm, imx_tve_modes[i]))
477 return i;
478
479 return -EINVAL;
480}
481
482static int imx_tve_bind(struct device *dev, struct device *master, void *data)
483{
484 struct drm_device *drm = data;
485 struct imx_tve *tve = dev_get_drvdata(dev);
486 struct imx_tve_encoder *tvee;
487 struct drm_encoder *encoder;
488 struct drm_connector *connector;
489 int encoder_type;
490 int ret;
491
492 encoder_type = tve->mode == TVE_MODE_VGA ?
493 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
494
495 tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
496 encoder_type);
497 if (IS_ERR(tvee))
498 return PTR_ERR(tvee);
499
500 tvee->tve = tve;
501 encoder = &tvee->encoder;
502 connector = &tvee->connector;
503
504 ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
505 if (ret)
506 return ret;
507
508 drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
509
510 drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
511 ret = drm_connector_init_with_ddc(drm, connector,
512 &imx_tve_connector_funcs,
513 DRM_MODE_CONNECTOR_VGA, tve->ddc);
514 if (ret)
515 return ret;
516
517 return drm_connector_attach_encoder(connector, encoder);
518}
519
520static const struct component_ops imx_tve_ops = {
521 .bind = imx_tve_bind,
522};
523
524static int imx_tve_probe(struct platform_device *pdev)
525{
526 struct device *dev = &pdev->dev;
527 struct device_node *np = dev->of_node;
528 struct device_node *ddc_node;
529 struct imx_tve *tve;
530 void __iomem *base;
531 unsigned int val;
532 int irq;
533 int ret;
534
535 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
536 if (!tve)
537 return -ENOMEM;
538
539 tve->dev = dev;
540
541 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
542 if (ddc_node) {
543 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
544 of_node_put(ddc_node);
545 }
546
547 tve->mode = of_get_tve_mode(np);
548 if (tve->mode != TVE_MODE_VGA) {
549 dev_err(dev, "only VGA mode supported, currently\n");
550 return -EINVAL;
551 }
552
553 if (tve->mode == TVE_MODE_VGA) {
554 ret = of_property_read_u32(np, "fsl,hsync-pin",
555 &tve->di_hsync_pin);
556
557 if (ret < 0) {
558 dev_err(dev, "failed to get hsync pin\n");
559 return ret;
560 }
561
562 ret = of_property_read_u32(np, "fsl,vsync-pin",
563 &tve->di_vsync_pin);
564
565 if (ret < 0) {
566 dev_err(dev, "failed to get vsync pin\n");
567 return ret;
568 }
569 }
570
571 base = devm_platform_ioremap_resource(pdev, 0);
572 if (IS_ERR(base))
573 return PTR_ERR(base);
574
575 tve_regmap_config.lock_arg = tve;
576 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
577 &tve_regmap_config);
578 if (IS_ERR(tve->regmap)) {
579 dev_err(dev, "failed to init regmap: %ld\n",
580 PTR_ERR(tve->regmap));
581 return PTR_ERR(tve->regmap);
582 }
583
584 irq = platform_get_irq(pdev, 0);
585 if (irq < 0)
586 return irq;
587
588 ret = devm_request_threaded_irq(dev, irq, NULL,
589 imx_tve_irq_handler, IRQF_ONESHOT,
590 "imx-tve", tve);
591 if (ret < 0) {
592 dev_err(dev, "failed to request irq: %d\n", ret);
593 return ret;
594 }
595
596 tve->dac_reg = devm_regulator_get(dev, "dac");
597 if (!IS_ERR(tve->dac_reg)) {
598 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
599 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
600 ret = regulator_enable(tve->dac_reg);
601 if (ret)
602 return ret;
603 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
604 if (ret)
605 return ret;
606 }
607
608 tve->clk = devm_clk_get(dev, "tve");
609 if (IS_ERR(tve->clk)) {
610 dev_err(dev, "failed to get high speed tve clock: %ld\n",
611 PTR_ERR(tve->clk));
612 return PTR_ERR(tve->clk);
613 }
614
615 /* this is the IPU DI clock input selector, can be parented to tve_di */
616 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
617 if (IS_ERR(tve->di_sel_clk)) {
618 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
619 PTR_ERR(tve->di_sel_clk));
620 return PTR_ERR(tve->di_sel_clk);
621 }
622
623 ret = tve_clk_init(tve, base);
624 if (ret < 0)
625 return ret;
626
627 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
628 if (ret < 0) {
629 dev_err(dev, "failed to read configuration register: %d\n",
630 ret);
631 return ret;
632 }
633 if (val != 0x00100000) {
634 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
635 return -ENODEV;
636 }
637
638 /* disable cable detection for VGA mode */
639 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
640 if (ret)
641 return ret;
642
643 platform_set_drvdata(pdev, tve);
644
645 return component_add(dev, &imx_tve_ops);
646}
647
648static int imx_tve_remove(struct platform_device *pdev)
649{
650 component_del(&pdev->dev, &imx_tve_ops);
651 return 0;
652}
653
654static const struct of_device_id imx_tve_dt_ids[] = {
655 { .compatible = "fsl,imx53-tve", },
656 { /* sentinel */ }
657};
658MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
659
660static struct platform_driver imx_tve_driver = {
661 .probe = imx_tve_probe,
662 .remove = imx_tve_remove,
663 .driver = {
664 .of_match_table = imx_tve_dt_ids,
665 .name = "imx-tve",
666 },
667};
668
669module_platform_driver(imx_tve_driver);
670
671MODULE_DESCRIPTION("i.MX Television Encoder driver");
672MODULE_AUTHOR("Philipp Zabel, Pengutronix");
673MODULE_LICENSE("GPL");
674MODULE_ALIAS("platform:imx-tve");