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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include "i915_drv.h"
36#include "gvt.h"
37
38static int get_edp_pipe(struct intel_vgpu *vgpu)
39{
40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41 int pipe = -1;
42
43 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44 case TRANS_DDI_EDP_INPUT_A_ON:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF:
46 pipe = PIPE_A;
47 break;
48 case TRANS_DDI_EDP_INPUT_B_ONOFF:
49 pipe = PIPE_B;
50 break;
51 case TRANS_DDI_EDP_INPUT_C_ONOFF:
52 pipe = PIPE_C;
53 break;
54 }
55 return pipe;
56}
57
58static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59{
60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
61
62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63 return 0;
64
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66 return 0;
67 return 1;
68}
69
70int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71{
72 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
73
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75 return -EINVAL;
76
77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
78 return 1;
79
80 if (edp_pipe_is_enabled(vgpu) &&
81 get_edp_pipe(vgpu) == pipe)
82 return 1;
83 return 0;
84}
85
86static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
87 {
88/* EDID with 1024x768 as its resolution */
89 /*Header*/
90 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
91 /* Vendor & Product Identification */
92 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
93 /* Version & Revision */
94 0x01, 0x04,
95 /* Basic Display Parameters & Features */
96 0xa5, 0x34, 0x20, 0x78, 0x23,
97 /* Color Characteristics */
98 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
99 /* Established Timings: maximum resolution is 1024x768 */
100 0x21, 0x08, 0x00,
101 /* Standard Timings. All invalid */
102 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
104 /* 18 Byte Data Blocks 1: invalid */
105 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
107 /* 18 Byte Data Blocks 2: invalid */
108 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
110 /* 18 Byte Data Blocks 3: invalid */
111 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
113 /* 18 Byte Data Blocks 4: invalid */
114 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
116 /* Extension Block Count */
117 0x00,
118 /* Checksum */
119 0xef,
120 },
121 {
122/* EDID with 1920x1200 as its resolution */
123 /*Header*/
124 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
125 /* Vendor & Product Identification */
126 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
127 /* Version & Revision */
128 0x01, 0x04,
129 /* Basic Display Parameters & Features */
130 0xa5, 0x34, 0x20, 0x78, 0x23,
131 /* Color Characteristics */
132 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
133 /* Established Timings: maximum resolution is 1024x768 */
134 0x21, 0x08, 0x00,
135 /*
136 * Standard Timings.
137 * below new resolutions can be supported:
138 * 1920x1080, 1280x720, 1280x960, 1280x1024,
139 * 1440x900, 1600x1200, 1680x1050
140 */
141 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
143 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
144 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
146 /* 18 Byte Data Blocks 2: invalid */
147 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
149 /* 18 Byte Data Blocks 3: invalid */
150 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
152 /* 18 Byte Data Blocks 4: invalid */
153 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
155 /* Extension Block Count */
156 0x00,
157 /* Checksum */
158 0x45,
159 },
160};
161
162#define DPCD_HEADER_SIZE 0xb
163
164/* let the virtual display supports DP1.2 */
165static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167};
168
169static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170{
171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172 int pipe;
173
174 if (IS_BROXTON(dev_priv)) {
175 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
176 BXT_DE_PORT_HP_DDIB |
177 BXT_DE_PORT_HP_DDIC);
178
179 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
181 BXT_DE_PORT_HP_DDIA;
182 }
183
184 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
185 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
186 BXT_DE_PORT_HP_DDIB;
187 }
188
189 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
190 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
191 BXT_DE_PORT_HP_DDIC;
192 }
193
194 return;
195 }
196
197 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
198 SDE_PORTC_HOTPLUG_CPT |
199 SDE_PORTD_HOTPLUG_CPT);
200
201 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
202 IS_COFFEELAKE(dev_priv)) {
203 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
204 SDE_PORTE_HOTPLUG_SPT);
205 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
206 SKL_FUSE_DOWNLOAD_STATUS |
207 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
208 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
209 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
210 vgpu_vreg_t(vgpu, LCPLL1_CTL) |=
211 LCPLL_PLL_ENABLE |
212 LCPLL_PLL_LOCK;
213 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
214
215 }
216
217 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
218 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
219 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
220 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
221 TRANS_DDI_PORT_MASK);
222 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
223 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
224 (PORT_B << TRANS_DDI_PORT_SHIFT) |
225 TRANS_DDI_FUNC_ENABLE);
226 if (IS_BROADWELL(dev_priv)) {
227 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
228 ~PORT_CLK_SEL_MASK;
229 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
230 PORT_CLK_SEL_LCPLL_810;
231 }
232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
233 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
234 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
235 }
236
237 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
238 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
239 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
240 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
241 TRANS_DDI_PORT_MASK);
242 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
243 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
244 (PORT_C << TRANS_DDI_PORT_SHIFT) |
245 TRANS_DDI_FUNC_ENABLE);
246 if (IS_BROADWELL(dev_priv)) {
247 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
248 ~PORT_CLK_SEL_MASK;
249 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
250 PORT_CLK_SEL_LCPLL_810;
251 }
252 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
253 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
254 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
255 }
256
257 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
258 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
259 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
260 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
261 TRANS_DDI_PORT_MASK);
262 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
263 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
264 (PORT_D << TRANS_DDI_PORT_SHIFT) |
265 TRANS_DDI_FUNC_ENABLE);
266 if (IS_BROADWELL(dev_priv)) {
267 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
268 ~PORT_CLK_SEL_MASK;
269 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
270 PORT_CLK_SEL_LCPLL_810;
271 }
272 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
273 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
274 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
275 }
276
277 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
278 IS_COFFEELAKE(dev_priv)) &&
279 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
280 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
281 }
282
283 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
284 if (IS_BROADWELL(dev_priv))
285 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
286 GEN8_PORT_DP_A_HOTPLUG;
287 else
288 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
289
290 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
291 }
292
293 /* Clear host CRT status, so guest couldn't detect this host CRT. */
294 if (IS_BROADWELL(dev_priv))
295 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
296
297 /* Disable Primary/Sprite/Cursor plane */
298 for_each_pipe(dev_priv, pipe) {
299 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
300 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
301 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
302 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
303 }
304
305 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
306}
307
308static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
309{
310 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
311
312 kfree(port->edid);
313 port->edid = NULL;
314
315 kfree(port->dpcd);
316 port->dpcd = NULL;
317}
318
319static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
320 int type, unsigned int resolution)
321{
322 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
323
324 if (WARN_ON(resolution >= GVT_EDID_NUM))
325 return -EINVAL;
326
327 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
328 if (!port->edid)
329 return -ENOMEM;
330
331 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
332 if (!port->dpcd) {
333 kfree(port->edid);
334 return -ENOMEM;
335 }
336
337 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
338 EDID_SIZE);
339 port->edid->data_valid = true;
340
341 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
342 port->dpcd->data_valid = true;
343 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
344 port->type = type;
345 port->id = resolution;
346
347 emulate_monitor_status_change(vgpu);
348
349 return 0;
350}
351
352/**
353 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
354 * be turned on/off when a virtual pipe is enabled/disabled.
355 * @gvt: a GVT device
356 *
357 * This function is used to turn on/off vblank timer according to currently
358 * enabled/disabled virtual pipes.
359 *
360 */
361void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
362{
363 struct intel_gvt_irq *irq = &gvt->irq;
364 struct intel_vgpu *vgpu;
365 int pipe, id;
366 int found = false;
367
368 mutex_lock(&gvt->lock);
369 for_each_active_vgpu(gvt, vgpu, id) {
370 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
371 if (pipe_is_enabled(vgpu, pipe)) {
372 found = true;
373 break;
374 }
375 }
376 if (found)
377 break;
378 }
379
380 /* all the pipes are disabled */
381 if (!found)
382 hrtimer_cancel(&irq->vblank_timer.timer);
383 else
384 hrtimer_start(&irq->vblank_timer.timer,
385 ktime_add_ns(ktime_get(), irq->vblank_timer.period),
386 HRTIMER_MODE_ABS);
387 mutex_unlock(&gvt->lock);
388}
389
390static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
391{
392 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
393 struct intel_vgpu_irq *irq = &vgpu->irq;
394 int vblank_event[] = {
395 [PIPE_A] = PIPE_A_VBLANK,
396 [PIPE_B] = PIPE_B_VBLANK,
397 [PIPE_C] = PIPE_C_VBLANK,
398 };
399 int event;
400
401 if (pipe < PIPE_A || pipe > PIPE_C)
402 return;
403
404 for_each_set_bit(event, irq->flip_done_event[pipe],
405 INTEL_GVT_EVENT_MAX) {
406 clear_bit(event, irq->flip_done_event[pipe]);
407 if (!pipe_is_enabled(vgpu, pipe))
408 continue;
409
410 intel_vgpu_trigger_virtual_event(vgpu, event);
411 }
412
413 if (pipe_is_enabled(vgpu, pipe)) {
414 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
415 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
416 }
417}
418
419static void emulate_vblank(struct intel_vgpu *vgpu)
420{
421 int pipe;
422
423 mutex_lock(&vgpu->vgpu_lock);
424 for_each_pipe(vgpu->gvt->dev_priv, pipe)
425 emulate_vblank_on_pipe(vgpu, pipe);
426 mutex_unlock(&vgpu->vgpu_lock);
427}
428
429/**
430 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
431 * @gvt: a GVT device
432 *
433 * This function is used to trigger vblank interrupts for vGPUs on GVT device
434 *
435 */
436void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
437{
438 struct intel_vgpu *vgpu;
439 int id;
440
441 mutex_lock(&gvt->lock);
442 for_each_active_vgpu(gvt, vgpu, id)
443 emulate_vblank(vgpu);
444 mutex_unlock(&gvt->lock);
445}
446
447/**
448 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
449 * @vgpu: a vGPU
450 * @connected: link state
451 *
452 * This function is used to trigger hotplug interrupt for vGPU
453 *
454 */
455void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
456{
457 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
458
459 /* TODO: add more platforms support */
460 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
461 if (connected) {
462 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
463 SFUSE_STRAP_DDID_DETECTED;
464 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
465 } else {
466 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
467 ~SFUSE_STRAP_DDID_DETECTED;
468 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
469 }
470 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
471 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
472 PORTD_HOTPLUG_STATUS_MASK;
473 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
474 }
475}
476
477/**
478 * intel_vgpu_clean_display - clean vGPU virtual display emulation
479 * @vgpu: a vGPU
480 *
481 * This function is used to clean vGPU virtual display emulation stuffs
482 *
483 */
484void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
485{
486 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
487
488 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
489 IS_COFFEELAKE(dev_priv))
490 clean_virtual_dp_monitor(vgpu, PORT_D);
491 else
492 clean_virtual_dp_monitor(vgpu, PORT_B);
493}
494
495/**
496 * intel_vgpu_init_display- initialize vGPU virtual display emulation
497 * @vgpu: a vGPU
498 * @resolution: resolution index for intel_vgpu_edid
499 *
500 * This function is used to initialize vGPU virtual display emulation stuffs
501 *
502 * Returns:
503 * Zero on success, negative error code if failed.
504 *
505 */
506int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
507{
508 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
509
510 intel_vgpu_init_i2c_edid(vgpu);
511
512 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
513 IS_COFFEELAKE(dev_priv))
514 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
515 resolution);
516 else
517 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
518 resolution);
519}
520
521/**
522 * intel_vgpu_reset_display- reset vGPU virtual display emulation
523 * @vgpu: a vGPU
524 *
525 * This function is used to reset vGPU virtual display emulation stuffs
526 *
527 */
528void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
529{
530 emulate_monitor_status_change(vgpu);
531}
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include "i915_drv.h"
36#include "i915_reg.h"
37#include "gvt.h"
38
39#include "display/intel_dpio_phy.h"
40
41static int get_edp_pipe(struct intel_vgpu *vgpu)
42{
43 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
44 int pipe = -1;
45
46 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
47 case TRANS_DDI_EDP_INPUT_A_ON:
48 case TRANS_DDI_EDP_INPUT_A_ONOFF:
49 pipe = PIPE_A;
50 break;
51 case TRANS_DDI_EDP_INPUT_B_ONOFF:
52 pipe = PIPE_B;
53 break;
54 case TRANS_DDI_EDP_INPUT_C_ONOFF:
55 pipe = PIPE_C;
56 break;
57 }
58 return pipe;
59}
60
61static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
62{
63 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
64
65 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
66 return 0;
67
68 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
69 return 0;
70 return 1;
71}
72
73int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
74{
75 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
76
77 if (drm_WARN_ON(&dev_priv->drm,
78 pipe < PIPE_A || pipe >= I915_MAX_PIPES))
79 return -EINVAL;
80
81 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
82 return 1;
83
84 if (edp_pipe_is_enabled(vgpu) &&
85 get_edp_pipe(vgpu) == pipe)
86 return 1;
87 return 0;
88}
89
90static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
91 {
92/* EDID with 1024x768 as its resolution */
93 /*Header*/
94 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
95 /* Vendor & Product Identification */
96 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
97 /* Version & Revision */
98 0x01, 0x04,
99 /* Basic Display Parameters & Features */
100 0xa5, 0x34, 0x20, 0x78, 0x23,
101 /* Color Characteristics */
102 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
103 /* Established Timings: maximum resolution is 1024x768 */
104 0x21, 0x08, 0x00,
105 /* Standard Timings. All invalid */
106 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
107 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
108 /* 18 Byte Data Blocks 1: invalid */
109 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
110 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
111 /* 18 Byte Data Blocks 2: invalid */
112 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
113 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
114 /* 18 Byte Data Blocks 3: invalid */
115 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
116 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
117 /* 18 Byte Data Blocks 4: invalid */
118 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
119 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
120 /* Extension Block Count */
121 0x00,
122 /* Checksum */
123 0xef,
124 },
125 {
126/* EDID with 1920x1200 as its resolution */
127 /*Header*/
128 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
129 /* Vendor & Product Identification */
130 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
131 /* Version & Revision */
132 0x01, 0x04,
133 /* Basic Display Parameters & Features */
134 0xa5, 0x34, 0x20, 0x78, 0x23,
135 /* Color Characteristics */
136 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
137 /* Established Timings: maximum resolution is 1024x768 */
138 0x21, 0x08, 0x00,
139 /*
140 * Standard Timings.
141 * below new resolutions can be supported:
142 * 1920x1080, 1280x720, 1280x960, 1280x1024,
143 * 1440x900, 1600x1200, 1680x1050
144 */
145 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
146 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
147 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
148 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
149 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
150 /* 18 Byte Data Blocks 2: invalid */
151 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
152 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
153 /* 18 Byte Data Blocks 3: invalid */
154 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
155 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
156 /* 18 Byte Data Blocks 4: invalid */
157 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
158 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
159 /* Extension Block Count */
160 0x00,
161 /* Checksum */
162 0x45,
163 },
164};
165
166#define DPCD_HEADER_SIZE 0xb
167
168/* let the virtual display supports DP1.2 */
169static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
170 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
171};
172
173static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
174{
175 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
176 int pipe;
177
178 if (IS_BROXTON(dev_priv)) {
179 enum transcoder trans;
180 enum port port;
181
182 /* Clear PIPE, DDI, PHY, HPD before setting new */
183 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
184 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
185 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
186 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
187
188 for_each_pipe(dev_priv, pipe) {
189 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
190 ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
191 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
192 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
193 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
194 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
195 }
196
197 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
198 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
199 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
200 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
201 }
202 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
203 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
204 TRANS_DDI_PORT_MASK);
205
206 for (port = PORT_A; port <= PORT_C; port++) {
207 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
208 ~BXT_PHY_LANE_ENABLED;
209 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
210 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
211 BXT_PHY_LANE_POWERDOWN_ACK);
212
213 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
214 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
215 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
216 PORT_PLL_ENABLE);
217
218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
219 ~(DDI_INIT_DISPLAY_DETECTED |
220 DDI_BUF_CTL_ENABLE);
221 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
222 }
223 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
224 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
225 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
226 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
228 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
229 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
230 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
231 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
232
233 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
234 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
235 ~PHY_POWER_GOOD;
236 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
237 ~PHY_POWER_GOOD;
238 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
239 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
240
241 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
242 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
243
244 /*
245 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
246 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
247 * TRANSCODER_A can be enabled. PORT_x depends on the input of
248 * setup_virtual_dp_monitor.
249 */
250 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
251 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
252
253 /*
254 * Golden M/N are calculated based on:
255 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
256 * DP link clk 1620 MHz and non-constant_n.
257 * TODO: calculate DP link symbol clk and stream clk m/n.
258 */
259 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
260 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
261 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
262 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
263 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
264
265 /* Enable per-DDI/PORT vreg */
266 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
267 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
268 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
269 PHY_POWER_GOOD;
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
271 BIT(30);
272 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
273 BXT_PHY_LANE_ENABLED;
274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
275 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
276 BXT_PHY_LANE_POWERDOWN_ACK);
277 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
278 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
279 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
280 PORT_PLL_ENABLE);
281 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
282 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
283 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
284 ~DDI_BUF_IS_IDLE;
285 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
286 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
287 TRANS_DDI_FUNC_ENABLE);
288 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
289 PORTA_HOTPLUG_ENABLE;
290 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
291 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
292 }
293
294 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
295 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
296 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
297 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
298 PHY_POWER_GOOD;
299 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
300 BIT(30);
301 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
302 BXT_PHY_LANE_ENABLED;
303 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
304 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
305 BXT_PHY_LANE_POWERDOWN_ACK);
306 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
307 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
308 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
309 PORT_PLL_ENABLE);
310 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
311 DDI_BUF_CTL_ENABLE;
312 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
313 ~DDI_BUF_IS_IDLE;
314 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
315 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
316 (PORT_B << TRANS_DDI_PORT_SHIFT) |
317 TRANS_DDI_FUNC_ENABLE);
318 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
319 PORTB_HOTPLUG_ENABLE;
320 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
321 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
322 }
323
324 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
325 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
326 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
327 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
328 PHY_POWER_GOOD;
329 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
330 BIT(30);
331 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
332 BXT_PHY_LANE_ENABLED;
333 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
334 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
335 BXT_PHY_LANE_POWERDOWN_ACK);
336 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
337 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
338 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
339 PORT_PLL_ENABLE);
340 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
341 DDI_BUF_CTL_ENABLE;
342 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
343 ~DDI_BUF_IS_IDLE;
344 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
345 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
346 (PORT_B << TRANS_DDI_PORT_SHIFT) |
347 TRANS_DDI_FUNC_ENABLE);
348 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
349 PORTC_HOTPLUG_ENABLE;
350 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
351 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
352 }
353
354 return;
355 }
356
357 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
358 SDE_PORTC_HOTPLUG_CPT |
359 SDE_PORTD_HOTPLUG_CPT);
360
361 if (IS_SKYLAKE(dev_priv) ||
362 IS_KABYLAKE(dev_priv) ||
363 IS_COFFEELAKE(dev_priv) ||
364 IS_COMETLAKE(dev_priv)) {
365 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
366 SDE_PORTE_HOTPLUG_SPT);
367 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
368 SKL_FUSE_DOWNLOAD_STATUS |
369 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
370 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
371 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
372 /*
373 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
374 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
375 * TRANSCODER_A can be enabled. PORT_x depends on the input of
376 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
377 * so we fixed to DPLL0 here.
378 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
379 */
380 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
381 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
382 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
383 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
384 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
385 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
386 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
387 /*
388 * Golden M/N are calculated based on:
389 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
390 * DP link clk 1620 MHz and non-constant_n.
391 * TODO: calculate DP link symbol clk and stream clk m/n.
392 */
393 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
394 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
395 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
396 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
397 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
398 }
399
400 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
401 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
402 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
403 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
404 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
405 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
406 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
407 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
408 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
409 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
410 TRANS_DDI_PORT_MASK);
411 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
412 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
413 (PORT_B << TRANS_DDI_PORT_SHIFT) |
414 TRANS_DDI_FUNC_ENABLE);
415 if (IS_BROADWELL(dev_priv)) {
416 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
417 ~PORT_CLK_SEL_MASK;
418 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
419 PORT_CLK_SEL_LCPLL_810;
420 }
421 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
422 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
423 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
424 }
425
426 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
427 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
428 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
429 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
430 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
431 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
432 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
433 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
434 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
435 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
436 TRANS_DDI_PORT_MASK);
437 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
438 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
439 (PORT_C << TRANS_DDI_PORT_SHIFT) |
440 TRANS_DDI_FUNC_ENABLE);
441 if (IS_BROADWELL(dev_priv)) {
442 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
443 ~PORT_CLK_SEL_MASK;
444 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
445 PORT_CLK_SEL_LCPLL_810;
446 }
447 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
448 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
449 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
450 }
451
452 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
453 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
454 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
455 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
456 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
457 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
458 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
459 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
460 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
461 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
462 TRANS_DDI_PORT_MASK);
463 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
464 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
465 (PORT_D << TRANS_DDI_PORT_SHIFT) |
466 TRANS_DDI_FUNC_ENABLE);
467 if (IS_BROADWELL(dev_priv)) {
468 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
469 ~PORT_CLK_SEL_MASK;
470 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
471 PORT_CLK_SEL_LCPLL_810;
472 }
473 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
474 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
475 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
476 }
477
478 if ((IS_SKYLAKE(dev_priv) ||
479 IS_KABYLAKE(dev_priv) ||
480 IS_COFFEELAKE(dev_priv) ||
481 IS_COMETLAKE(dev_priv)) &&
482 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
483 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
484 }
485
486 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
487 if (IS_BROADWELL(dev_priv))
488 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
489 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
490 else
491 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
492
493 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
494 }
495
496 /* Clear host CRT status, so guest couldn't detect this host CRT. */
497 if (IS_BROADWELL(dev_priv))
498 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
499
500 /* Disable Primary/Sprite/Cursor plane */
501 for_each_pipe(dev_priv, pipe) {
502 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
503 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
504 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
505 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
506 }
507
508 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
509}
510
511static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
512{
513 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
514
515 kfree(port->edid);
516 port->edid = NULL;
517
518 kfree(port->dpcd);
519 port->dpcd = NULL;
520}
521
522static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
523{
524 struct intel_vgpu_vblank_timer *vblank_timer;
525 struct intel_vgpu *vgpu;
526
527 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer);
528 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
529
530 /* Set vblank emulation request per-vGPU bit */
531 intel_gvt_request_service(vgpu->gvt,
532 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
533 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
534 return HRTIMER_RESTART;
535}
536
537static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
538 int type, unsigned int resolution)
539{
540 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
541 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
542 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
543
544 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
545 return -EINVAL;
546
547 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
548 if (!port->edid)
549 return -ENOMEM;
550
551 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
552 if (!port->dpcd) {
553 kfree(port->edid);
554 return -ENOMEM;
555 }
556
557 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
558 EDID_SIZE);
559 port->edid->data_valid = true;
560
561 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
562 port->dpcd->data_valid = true;
563 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
564 port->type = type;
565 port->id = resolution;
566 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;
567 vgpu->display.port_num = port_num;
568
569 /* Init hrtimer based on default refresh rate */
570 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
571 vblank_timer->timer.function = vblank_timer_fn;
572 vblank_timer->vrefresh_k = port->vrefresh_k;
573 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
574
575 emulate_monitor_status_change(vgpu);
576
577 return 0;
578}
579
580/**
581 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
582 * @vgpu: vGPU operated
583 * @turnon: Turn ON/OFF vblank_timer
584 *
585 * This function is used to turn on/off or update the per-vGPU vblank_timer
586 * when PIPECONF is enabled or disabled. vblank_timer period is also updated
587 * if guest changed the refresh rate.
588 *
589 */
590void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
591{
592 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
593 struct intel_vgpu_port *port =
594 intel_vgpu_port(vgpu, vgpu->display.port_num);
595
596 if (turnon) {
597 /*
598 * Skip the re-enable if already active and vrefresh unchanged.
599 * Otherwise, stop timer if already active and restart with new
600 * period.
601 */
602 if (vblank_timer->vrefresh_k != port->vrefresh_k ||
603 !hrtimer_active(&vblank_timer->timer)) {
604 /* Stop timer before start with new period if active */
605 if (hrtimer_active(&vblank_timer->timer))
606 hrtimer_cancel(&vblank_timer->timer);
607
608 /* Make sure new refresh rate updated to timer period */
609 vblank_timer->vrefresh_k = port->vrefresh_k;
610 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
611 hrtimer_start(&vblank_timer->timer,
612 ktime_add_ns(ktime_get(), vblank_timer->period),
613 HRTIMER_MODE_ABS);
614 }
615 } else {
616 /* Caller request to stop vblank */
617 hrtimer_cancel(&vblank_timer->timer);
618 }
619}
620
621static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
622{
623 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
624 struct intel_vgpu_irq *irq = &vgpu->irq;
625 int vblank_event[] = {
626 [PIPE_A] = PIPE_A_VBLANK,
627 [PIPE_B] = PIPE_B_VBLANK,
628 [PIPE_C] = PIPE_C_VBLANK,
629 };
630 int event;
631
632 if (pipe < PIPE_A || pipe > PIPE_C)
633 return;
634
635 for_each_set_bit(event, irq->flip_done_event[pipe],
636 INTEL_GVT_EVENT_MAX) {
637 clear_bit(event, irq->flip_done_event[pipe]);
638 if (!pipe_is_enabled(vgpu, pipe))
639 continue;
640
641 intel_vgpu_trigger_virtual_event(vgpu, event);
642 }
643
644 if (pipe_is_enabled(vgpu, pipe)) {
645 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
646 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
647 }
648}
649
650void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
651{
652 int pipe;
653
654 mutex_lock(&vgpu->vgpu_lock);
655 for_each_pipe(vgpu->gvt->gt->i915, pipe)
656 emulate_vblank_on_pipe(vgpu, pipe);
657 mutex_unlock(&vgpu->vgpu_lock);
658}
659
660/**
661 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
662 * @vgpu: a vGPU
663 * @connected: link state
664 *
665 * This function is used to trigger hotplug interrupt for vGPU
666 *
667 */
668void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
669{
670 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
671
672 /* TODO: add more platforms support */
673 if (IS_SKYLAKE(i915) ||
674 IS_KABYLAKE(i915) ||
675 IS_COFFEELAKE(i915) ||
676 IS_COMETLAKE(i915)) {
677 if (connected) {
678 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
679 SFUSE_STRAP_DDID_DETECTED;
680 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
681 } else {
682 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
683 ~SFUSE_STRAP_DDID_DETECTED;
684 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
685 }
686 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
687 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
688 PORTD_HOTPLUG_STATUS_MASK;
689 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
690 } else if (IS_BROXTON(i915)) {
691 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
692 if (connected) {
693 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
694 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
695 } else {
696 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
697 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
698 }
699 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
700 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
701 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
702 ~PORTA_HOTPLUG_STATUS_MASK;
703 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
704 PORTA_HOTPLUG_LONG_DETECT;
705 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
706 }
707 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
708 if (connected) {
709 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
710 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
711 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
712 SFUSE_STRAP_DDIB_DETECTED;
713 } else {
714 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
715 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
716 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
717 ~SFUSE_STRAP_DDIB_DETECTED;
718 }
719 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
720 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
721 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
722 ~PORTB_HOTPLUG_STATUS_MASK;
723 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
724 PORTB_HOTPLUG_LONG_DETECT;
725 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
726 }
727 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
728 if (connected) {
729 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
730 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
731 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
732 SFUSE_STRAP_DDIC_DETECTED;
733 } else {
734 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
735 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
736 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
737 ~SFUSE_STRAP_DDIC_DETECTED;
738 }
739 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
740 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
741 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
742 ~PORTC_HOTPLUG_STATUS_MASK;
743 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
744 PORTC_HOTPLUG_LONG_DETECT;
745 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
746 }
747 }
748}
749
750/**
751 * intel_vgpu_clean_display - clean vGPU virtual display emulation
752 * @vgpu: a vGPU
753 *
754 * This function is used to clean vGPU virtual display emulation stuffs
755 *
756 */
757void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
758{
759 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
760
761 if (IS_SKYLAKE(dev_priv) ||
762 IS_KABYLAKE(dev_priv) ||
763 IS_COFFEELAKE(dev_priv) ||
764 IS_COMETLAKE(dev_priv))
765 clean_virtual_dp_monitor(vgpu, PORT_D);
766 else
767 clean_virtual_dp_monitor(vgpu, PORT_B);
768
769 vgpu_update_vblank_emulation(vgpu, false);
770}
771
772/**
773 * intel_vgpu_init_display- initialize vGPU virtual display emulation
774 * @vgpu: a vGPU
775 * @resolution: resolution index for intel_vgpu_edid
776 *
777 * This function is used to initialize vGPU virtual display emulation stuffs
778 *
779 * Returns:
780 * Zero on success, negative error code if failed.
781 *
782 */
783int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
784{
785 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
786
787 intel_vgpu_init_i2c_edid(vgpu);
788
789 if (IS_SKYLAKE(dev_priv) ||
790 IS_KABYLAKE(dev_priv) ||
791 IS_COFFEELAKE(dev_priv) ||
792 IS_COMETLAKE(dev_priv))
793 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
794 resolution);
795 else
796 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
797 resolution);
798}
799
800/**
801 * intel_vgpu_reset_display- reset vGPU virtual display emulation
802 * @vgpu: a vGPU
803 *
804 * This function is used to reset vGPU virtual display emulation stuffs
805 *
806 */
807void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
808{
809 emulate_monitor_status_change(vgpu);
810}