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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25
26#include "amdgpu.h"
27#include "amdgpu_vcn.h"
28#include "soc15.h"
29#include "soc15d.h"
30#include "amdgpu_pm.h"
31#include "amdgpu_psp.h"
32
33#include "vcn/vcn_2_0_0_offset.h"
34#include "vcn/vcn_2_0_0_sh_mask.h"
35#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
36
37#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
38#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
39#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
40#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
41#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
42#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
43#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
44
45#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
46#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
47#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
48#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
49
50#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
51#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
52#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
53#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
54#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
55#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
56#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
57#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
58#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
59#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
60#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
61#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
62#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed
63#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
64#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
65#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
66#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
67
68#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
69
70#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
71#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
72#define mmUVD_REG_XX_MASK 0x026c
73#define mmUVD_REG_XX_MASK_BASE_IDX 1
74
75static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
76static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
77static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
78static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
79static int vcn_v2_0_set_powergating_state(void *handle,
80 enum amd_powergating_state state);
81static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
82 struct dpg_pause_state *new_state);
83
84/**
85 * vcn_v2_0_early_init - set function pointers
86 *
87 * @handle: amdgpu_device pointer
88 *
89 * Set ring and irq function pointers
90 */
91static int vcn_v2_0_early_init(void *handle)
92{
93 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
94
95 adev->vcn.num_vcn_inst = 1;
96 adev->vcn.num_enc_rings = 2;
97
98 vcn_v2_0_set_dec_ring_funcs(adev);
99 vcn_v2_0_set_enc_ring_funcs(adev);
100 vcn_v2_0_set_jpeg_ring_funcs(adev);
101 vcn_v2_0_set_irq_funcs(adev);
102
103 return 0;
104}
105
106/**
107 * vcn_v2_0_sw_init - sw init for VCN block
108 *
109 * @handle: amdgpu_device pointer
110 *
111 * Load firmware and sw initialization
112 */
113static int vcn_v2_0_sw_init(void *handle)
114{
115 struct amdgpu_ring *ring;
116 int i, r;
117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
118
119 /* VCN DEC TRAP */
120 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
121 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
122 &adev->vcn.inst->irq);
123 if (r)
124 return r;
125
126 /* VCN ENC TRAP */
127 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
128 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
129 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
130 &adev->vcn.inst->irq);
131 if (r)
132 return r;
133 }
134
135 /* VCN JPEG TRAP */
136 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
137 VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
138 if (r)
139 return r;
140
141 r = amdgpu_vcn_sw_init(adev);
142 if (r)
143 return r;
144
145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
146 const struct common_firmware_header *hdr;
147 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
148 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
149 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
150 adev->firmware.fw_size +=
151 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
152 DRM_INFO("PSP loading VCN firmware\n");
153 }
154
155 r = amdgpu_vcn_resume(adev);
156 if (r)
157 return r;
158
159 ring = &adev->vcn.inst->ring_dec;
160
161 ring->use_doorbell = true;
162 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
163
164 sprintf(ring->name, "vcn_dec");
165 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
166 if (r)
167 return r;
168
169 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
170 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
171 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
172 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
173 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
174 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
175
176 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
177 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
178 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
179 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
180 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
181 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
182 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
183 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
184 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
185 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
186
187 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
188 ring = &adev->vcn.inst->ring_enc[i];
189 ring->use_doorbell = true;
190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
191 sprintf(ring->name, "vcn_enc%d", i);
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
193 if (r)
194 return r;
195 }
196
197 ring = &adev->vcn.inst->ring_jpeg;
198 ring->use_doorbell = true;
199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
200 sprintf(ring->name, "vcn_jpeg");
201 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
202 if (r)
203 return r;
204
205 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
206
207 adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
208 adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
209
210 return 0;
211}
212
213/**
214 * vcn_v2_0_sw_fini - sw fini for VCN block
215 *
216 * @handle: amdgpu_device pointer
217 *
218 * VCN suspend and free up sw allocation
219 */
220static int vcn_v2_0_sw_fini(void *handle)
221{
222 int r;
223 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
224
225 r = amdgpu_vcn_suspend(adev);
226 if (r)
227 return r;
228
229 r = amdgpu_vcn_sw_fini(adev);
230
231 return r;
232}
233
234/**
235 * vcn_v2_0_hw_init - start and test VCN block
236 *
237 * @handle: amdgpu_device pointer
238 *
239 * Initialize the hardware, boot up the VCPU and do some testing
240 */
241static int vcn_v2_0_hw_init(void *handle)
242{
243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
244 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
245 int i, r;
246
247 adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
248 ring->doorbell_index, 0);
249
250 ring->sched.ready = true;
251 r = amdgpu_ring_test_ring(ring);
252 if (r) {
253 ring->sched.ready = false;
254 goto done;
255 }
256
257 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
258 ring = &adev->vcn.inst->ring_enc[i];
259 ring->sched.ready = true;
260 r = amdgpu_ring_test_ring(ring);
261 if (r) {
262 ring->sched.ready = false;
263 goto done;
264 }
265 }
266
267 ring = &adev->vcn.inst->ring_jpeg;
268 ring->sched.ready = true;
269 r = amdgpu_ring_test_ring(ring);
270 if (r) {
271 ring->sched.ready = false;
272 goto done;
273 }
274
275done:
276 if (!r)
277 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
278 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
279
280 return r;
281}
282
283/**
284 * vcn_v2_0_hw_fini - stop the hardware block
285 *
286 * @handle: amdgpu_device pointer
287 *
288 * Stop the VCN block, mark ring as not ready any more
289 */
290static int vcn_v2_0_hw_fini(void *handle)
291{
292 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
293 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
294 int i;
295
296 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
297 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
298 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
299 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
300
301 ring->sched.ready = false;
302
303 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
304 ring = &adev->vcn.inst->ring_enc[i];
305 ring->sched.ready = false;
306 }
307
308 ring = &adev->vcn.inst->ring_jpeg;
309 ring->sched.ready = false;
310
311 return 0;
312}
313
314/**
315 * vcn_v2_0_suspend - suspend VCN block
316 *
317 * @handle: amdgpu_device pointer
318 *
319 * HW fini and suspend VCN block
320 */
321static int vcn_v2_0_suspend(void *handle)
322{
323 int r;
324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
325
326 r = vcn_v2_0_hw_fini(adev);
327 if (r)
328 return r;
329
330 r = amdgpu_vcn_suspend(adev);
331
332 return r;
333}
334
335/**
336 * vcn_v2_0_resume - resume VCN block
337 *
338 * @handle: amdgpu_device pointer
339 *
340 * Resume firmware and hw init VCN block
341 */
342static int vcn_v2_0_resume(void *handle)
343{
344 int r;
345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
346
347 r = amdgpu_vcn_resume(adev);
348 if (r)
349 return r;
350
351 r = vcn_v2_0_hw_init(adev);
352
353 return r;
354}
355
356/**
357 * vcn_v2_0_mc_resume - memory controller programming
358 *
359 * @adev: amdgpu_device pointer
360 *
361 * Let the VCN memory controller know it's offsets
362 */
363static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
364{
365 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
366 uint32_t offset;
367
368 /* cache window 0: fw */
369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
370 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
371 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
372 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
373 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
374 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
375 offset = 0;
376 } else {
377 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
378 lower_32_bits(adev->vcn.inst->gpu_addr));
379 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
380 upper_32_bits(adev->vcn.inst->gpu_addr));
381 offset = size;
382 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
383 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
384 }
385
386 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
387
388 /* cache window 1: stack */
389 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
390 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
391 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
392 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
393 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
394 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
395
396 /* cache window 2: context */
397 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
398 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
399 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
400 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
401 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
402 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
403
404 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
405 WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
406}
407
408static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
409{
410 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
411 uint32_t offset;
412
413 /* cache window 0: fw */
414 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
415 if (!indirect) {
416 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
417 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
418 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
419 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
420 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
421 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
422 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
423 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
424 } else {
425 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
426 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
427 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
428 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
429 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
430 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
431 }
432 offset = 0;
433 } else {
434 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
435 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
436 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
437 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
438 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
439 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
440 offset = size;
441 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
442 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
443 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
444 }
445
446 if (!indirect)
447 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
448 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
449 else
450 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
451 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
452
453 /* cache window 1: stack */
454 if (!indirect) {
455 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
456 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
458 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
459 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
460 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
461 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
462 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
463 } else {
464 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
465 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
466 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
467 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
468 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
469 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
470 }
471 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
472 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
473
474 /* cache window 2: context */
475 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
476 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
477 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
478 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
479 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
480 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
481 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
482 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
483 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
484 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
485
486 /* non-cache window */
487 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
488 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
489 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
490 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
491 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
492 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
493 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
494 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
495
496 /* VCN global tiling registers */
497 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
498 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
499}
500
501/**
502 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
503 *
504 * @adev: amdgpu_device pointer
505 * @sw: enable SW clock gating
506 *
507 * Disable clock gating for VCN block
508 */
509static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
510{
511 uint32_t data;
512
513 /* UVD disable CGC */
514 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
515 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
516 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
517 else
518 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
519 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
520 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
521 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
522
523 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
524 data &= ~(UVD_CGC_GATE__SYS_MASK
525 | UVD_CGC_GATE__UDEC_MASK
526 | UVD_CGC_GATE__MPEG2_MASK
527 | UVD_CGC_GATE__REGS_MASK
528 | UVD_CGC_GATE__RBC_MASK
529 | UVD_CGC_GATE__LMI_MC_MASK
530 | UVD_CGC_GATE__LMI_UMC_MASK
531 | UVD_CGC_GATE__IDCT_MASK
532 | UVD_CGC_GATE__MPRD_MASK
533 | UVD_CGC_GATE__MPC_MASK
534 | UVD_CGC_GATE__LBSI_MASK
535 | UVD_CGC_GATE__LRBBM_MASK
536 | UVD_CGC_GATE__UDEC_RE_MASK
537 | UVD_CGC_GATE__UDEC_CM_MASK
538 | UVD_CGC_GATE__UDEC_IT_MASK
539 | UVD_CGC_GATE__UDEC_DB_MASK
540 | UVD_CGC_GATE__UDEC_MP_MASK
541 | UVD_CGC_GATE__WCB_MASK
542 | UVD_CGC_GATE__VCPU_MASK
543 | UVD_CGC_GATE__SCPU_MASK);
544 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
545
546 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
547 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
548 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
549 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
550 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
551 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
552 | UVD_CGC_CTRL__SYS_MODE_MASK
553 | UVD_CGC_CTRL__UDEC_MODE_MASK
554 | UVD_CGC_CTRL__MPEG2_MODE_MASK
555 | UVD_CGC_CTRL__REGS_MODE_MASK
556 | UVD_CGC_CTRL__RBC_MODE_MASK
557 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
558 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
559 | UVD_CGC_CTRL__IDCT_MODE_MASK
560 | UVD_CGC_CTRL__MPRD_MODE_MASK
561 | UVD_CGC_CTRL__MPC_MODE_MASK
562 | UVD_CGC_CTRL__LBSI_MODE_MASK
563 | UVD_CGC_CTRL__LRBBM_MODE_MASK
564 | UVD_CGC_CTRL__WCB_MODE_MASK
565 | UVD_CGC_CTRL__VCPU_MODE_MASK
566 | UVD_CGC_CTRL__SCPU_MODE_MASK);
567 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
568
569 /* turn on */
570 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
571 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
572 | UVD_SUVD_CGC_GATE__SIT_MASK
573 | UVD_SUVD_CGC_GATE__SMP_MASK
574 | UVD_SUVD_CGC_GATE__SCM_MASK
575 | UVD_SUVD_CGC_GATE__SDB_MASK
576 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
577 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
578 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
579 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
580 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
581 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
582 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
583 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
584 | UVD_SUVD_CGC_GATE__SCLR_MASK
585 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
586 | UVD_SUVD_CGC_GATE__ENT_MASK
587 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
588 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
589 | UVD_SUVD_CGC_GATE__SITE_MASK
590 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
591 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
592 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
593 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
594 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
595 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
596
597 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
598 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
599 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
600 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
601 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
602 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
603 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
604 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
605 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
606 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
607 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
608 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
609}
610
611static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
612 uint8_t sram_sel, uint8_t indirect)
613{
614 uint32_t reg_data = 0;
615
616 /* enable sw clock gating control */
617 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
618 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
619 else
620 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
621 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
622 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
623 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
624 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
625 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
626 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
627 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
628 UVD_CGC_CTRL__SYS_MODE_MASK |
629 UVD_CGC_CTRL__UDEC_MODE_MASK |
630 UVD_CGC_CTRL__MPEG2_MODE_MASK |
631 UVD_CGC_CTRL__REGS_MODE_MASK |
632 UVD_CGC_CTRL__RBC_MODE_MASK |
633 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
634 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
635 UVD_CGC_CTRL__IDCT_MODE_MASK |
636 UVD_CGC_CTRL__MPRD_MODE_MASK |
637 UVD_CGC_CTRL__MPC_MODE_MASK |
638 UVD_CGC_CTRL__LBSI_MODE_MASK |
639 UVD_CGC_CTRL__LRBBM_MODE_MASK |
640 UVD_CGC_CTRL__WCB_MODE_MASK |
641 UVD_CGC_CTRL__VCPU_MODE_MASK |
642 UVD_CGC_CTRL__SCPU_MODE_MASK);
643 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
644 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
645
646 /* turn off clock gating */
647 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
648 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
649
650 /* turn on SUVD clock gating */
651 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
652 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
653
654 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
655 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
656 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
657}
658
659/**
660 * jpeg_v2_0_start - start JPEG block
661 *
662 * @adev: amdgpu_device pointer
663 *
664 * Setup and start the JPEG block
665 */
666static int jpeg_v2_0_start(struct amdgpu_device *adev)
667{
668 struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
669 uint32_t tmp;
670 int r = 0;
671
672 /* disable power gating */
673 tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
674 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
675
676 SOC15_WAIT_ON_RREG(VCN, 0,
677 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
678 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
679
680 if (r) {
681 DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
682 return r;
683 }
684
685 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
686 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
687 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
688
689 /* JPEG disable CGC */
690 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
691 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
692 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
693 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
694 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
695
696 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
697 tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
698 | JPEG_CGC_GATE__JPEG2_DEC_MASK
699 | JPEG_CGC_GATE__JPEG_ENC_MASK
700 | JPEG_CGC_GATE__JMCIF_MASK
701 | JPEG_CGC_GATE__JRBBM_MASK);
702 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
703
704 /* enable JMI channel */
705 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
706 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
707
708 /* enable System Interrupt for JRBC */
709 WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
710 JPEG_SYS_INT_EN__DJRBC_MASK,
711 ~JPEG_SYS_INT_EN__DJRBC_MASK);
712
713 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
714 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
715 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
716 lower_32_bits(ring->gpu_addr));
717 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
718 upper_32_bits(ring->gpu_addr));
719 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
720 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
721 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
722 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
723 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
724
725 return 0;
726}
727
728/**
729 * jpeg_v2_0_stop - stop JPEG block
730 *
731 * @adev: amdgpu_device pointer
732 *
733 * stop the JPEG block
734 */
735static int jpeg_v2_0_stop(struct amdgpu_device *adev)
736{
737 uint32_t tmp;
738 int r = 0;
739
740 /* reset JMI */
741 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
742 UVD_JMI_CNTL__SOFT_RESET_MASK,
743 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
744
745 /* enable JPEG CGC */
746 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
747 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
748 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
749 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
750 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
751
752
753 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
754 tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
755 |JPEG_CGC_GATE__JPEG2_DEC_MASK
756 |JPEG_CGC_GATE__JPEG_ENC_MASK
757 |JPEG_CGC_GATE__JMCIF_MASK
758 |JPEG_CGC_GATE__JRBBM_MASK);
759 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
760
761 /* enable power gating */
762 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS));
763 tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
764 tmp |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
765 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
766
767 tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
768 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
769
770 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
771 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
772 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
773
774 if (r) {
775 DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
776 return r;
777 }
778
779 return r;
780}
781
782/**
783 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
784 *
785 * @adev: amdgpu_device pointer
786 * @sw: enable SW clock gating
787 *
788 * Enable clock gating for VCN block
789 */
790static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
791{
792 uint32_t data = 0;
793
794 /* enable UVD CGC */
795 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
796 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
797 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
798 else
799 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
800 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
801 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
802 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
803
804 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
805 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
806 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
807 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
808 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
809 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
810 | UVD_CGC_CTRL__SYS_MODE_MASK
811 | UVD_CGC_CTRL__UDEC_MODE_MASK
812 | UVD_CGC_CTRL__MPEG2_MODE_MASK
813 | UVD_CGC_CTRL__REGS_MODE_MASK
814 | UVD_CGC_CTRL__RBC_MODE_MASK
815 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
816 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
817 | UVD_CGC_CTRL__IDCT_MODE_MASK
818 | UVD_CGC_CTRL__MPRD_MODE_MASK
819 | UVD_CGC_CTRL__MPC_MODE_MASK
820 | UVD_CGC_CTRL__LBSI_MODE_MASK
821 | UVD_CGC_CTRL__LRBBM_MODE_MASK
822 | UVD_CGC_CTRL__WCB_MODE_MASK
823 | UVD_CGC_CTRL__VCPU_MODE_MASK
824 | UVD_CGC_CTRL__SCPU_MODE_MASK);
825 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
826
827 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
828 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
829 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
830 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
831 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
832 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
833 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
834 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
835 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
836 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
837 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
838 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
839}
840
841static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
842{
843 uint32_t data = 0;
844 int ret;
845
846 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
847 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
848 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
849 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
850 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
851 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
852 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
853 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
854 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
855 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
856 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
857
858 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
859 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
860 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
861 } else {
862 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
863 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
864 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
865 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
866 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
867 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
868 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
869 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
870 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
871 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
872 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
873 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
874 }
875
876 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
877 * UVDU_PWR_STATUS are 0 (power on) */
878
879 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
880 data &= ~0x103;
881 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
882 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
883 UVD_POWER_STATUS__UVD_PG_EN_MASK;
884
885 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
886}
887
888static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
889{
890 uint32_t data = 0;
891 int ret;
892
893 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
894 /* Before power off, this indicator has to be turned on */
895 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
896 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
897 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
898 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
899
900
901 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
902 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
903 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
904 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
905 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
906 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
907 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
908 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
909 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
910 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
911
912 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
913
914 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
915 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
916 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
917 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
918 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
919 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
920 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
921 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
922 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
923 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
924 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
925 }
926}
927
928static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
929{
930 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
931 uint32_t rb_bufsz, tmp;
932
933 vcn_v2_0_enable_static_power_gating(adev);
934
935 /* enable dynamic power gating mode */
936 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
937 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
938 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
939 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
940
941 if (indirect)
942 adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr;
943
944 /* enable clock gating */
945 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
946
947 /* enable VCPU clock */
948 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
949 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
950 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
951 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
952 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
953
954 /* disable master interupt */
955 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
956 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
957
958 /* setup mmUVD_LMI_CTRL */
959 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
960 UVD_LMI_CTRL__REQ_MODE_MASK |
961 UVD_LMI_CTRL__CRC_RESET_MASK |
962 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
963 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
964 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
965 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
966 0x00100000L);
967 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
968 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
969
970 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
971 UVD, 0, mmUVD_MPC_CNTL),
972 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
973
974 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
975 UVD, 0, mmUVD_MPC_SET_MUXA0),
976 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
977 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
978 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
979 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
980
981 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
982 UVD, 0, mmUVD_MPC_SET_MUXB0),
983 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
984 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
985 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
986 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
987
988 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
989 UVD, 0, mmUVD_MPC_SET_MUX),
990 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
991 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
992 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
993
994 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
995
996 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
997 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
998 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
999 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1000
1001 /* release VCPU reset to boot */
1002 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
1003 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
1004
1005 /* enable LMI MC and UMC channels */
1006 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
1007 UVD, 0, mmUVD_LMI_CTRL2),
1008 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
1009
1010 /* enable master interrupt */
1011 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
1012 UVD, 0, mmUVD_MASTINT_EN),
1013 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1014
1015 if (indirect)
1016 psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr,
1017 (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr -
1018 (uintptr_t)adev->vcn.dpg_sram_cpu_addr));
1019
1020 /* force RBC into idle state */
1021 rb_bufsz = order_base_2(ring->ring_size);
1022 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1023 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1024 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1025 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1026 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1027 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1028
1029 /* set the write pointer delay */
1030 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1031
1032 /* set the wb address */
1033 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1034 (upper_32_bits(ring->gpu_addr) >> 2));
1035
1036 /* programm the RB_BASE for ring buffer */
1037 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1038 lower_32_bits(ring->gpu_addr));
1039 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1040 upper_32_bits(ring->gpu_addr));
1041
1042 /* Initialize the ring buffer's read and write pointers */
1043 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1044
1045 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1046
1047 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1048 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1049 lower_32_bits(ring->wptr));
1050
1051 return 0;
1052}
1053
1054static int vcn_v2_0_start(struct amdgpu_device *adev)
1055{
1056 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1057 uint32_t rb_bufsz, tmp;
1058 uint32_t lmi_swap_cntl;
1059 int i, j, r;
1060
1061 if (adev->pm.dpm_enabled)
1062 amdgpu_dpm_enable_uvd(adev, true);
1063
1064 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1065 r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
1066 if (r)
1067 return r;
1068 goto jpeg;
1069 }
1070
1071 vcn_v2_0_disable_static_power_gating(adev);
1072
1073 /* set uvd status busy */
1074 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1075 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
1076
1077 /*SW clock gating */
1078 vcn_v2_0_disable_clock_gating(adev);
1079
1080 /* enable VCPU clock */
1081 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
1082 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1083
1084 /* disable master interrupt */
1085 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
1086 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1087
1088 /* setup mmUVD_LMI_CTRL */
1089 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
1090 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
1091 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1092 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1093 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1094 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1095
1096 /* setup mmUVD_MPC_CNTL */
1097 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
1098 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1099 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1100 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
1101
1102 /* setup UVD_MPC_SET_MUXA0 */
1103 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
1104 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1105 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1106 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1107 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1108
1109 /* setup UVD_MPC_SET_MUXB0 */
1110 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
1111 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1112 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1113 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1114 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1115
1116 /* setup mmUVD_MPC_SET_MUX */
1117 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
1118 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1119 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1120 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1121
1122 vcn_v2_0_mc_resume(adev);
1123
1124 /* release VCPU reset to boot */
1125 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1126 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1127
1128 /* enable LMI MC and UMC channels */
1129 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1130 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1131
1132 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1133 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1134 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1135 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1136
1137 /* disable byte swapping */
1138 lmi_swap_cntl = 0;
1139#ifdef __BIG_ENDIAN
1140 /* swap (8 in 32) RB and IB */
1141 lmi_swap_cntl = 0xa;
1142#endif
1143 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1144
1145 for (i = 0; i < 10; ++i) {
1146 uint32_t status;
1147
1148 for (j = 0; j < 100; ++j) {
1149 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1150 if (status & 2)
1151 break;
1152 mdelay(10);
1153 }
1154 r = 0;
1155 if (status & 2)
1156 break;
1157
1158 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1159 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1160 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1161 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1162 mdelay(10);
1163 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1164 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1165 mdelay(10);
1166 r = -1;
1167 }
1168
1169 if (r) {
1170 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1171 return r;
1172 }
1173
1174 /* enable master interrupt */
1175 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1176 UVD_MASTINT_EN__VCPU_EN_MASK,
1177 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1178
1179 /* clear the busy bit of VCN_STATUS */
1180 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1181 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1182
1183 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1184
1185 /* force RBC into idle state */
1186 rb_bufsz = order_base_2(ring->ring_size);
1187 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1188 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1189 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1190 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1191 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1192 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1193
1194 /* programm the RB_BASE for ring buffer */
1195 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1196 lower_32_bits(ring->gpu_addr));
1197 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1198 upper_32_bits(ring->gpu_addr));
1199
1200 /* Initialize the ring buffer's read and write pointers */
1201 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1202
1203 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1204 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1205 lower_32_bits(ring->wptr));
1206
1207 ring = &adev->vcn.inst->ring_enc[0];
1208 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1209 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1210 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1211 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1212 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1213
1214 ring = &adev->vcn.inst->ring_enc[1];
1215 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1216 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1217 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1218 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1219 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1220
1221jpeg:
1222 r = jpeg_v2_0_start(adev);
1223
1224 return r;
1225}
1226
1227static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1228{
1229 int ret_code = 0;
1230 uint32_t tmp;
1231
1232 /* Wait for power status to be 1 */
1233 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1234 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1235
1236 /* wait for read ptr to be equal to write ptr */
1237 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1238 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1239
1240 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1241 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1242
1243 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1245
1246 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1247 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1248
1249 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1250 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1251
1252 /* disable dynamic power gating mode */
1253 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1254 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1255
1256 return 0;
1257}
1258
1259static int vcn_v2_0_stop(struct amdgpu_device *adev)
1260{
1261 uint32_t tmp;
1262 int r;
1263
1264 r = jpeg_v2_0_stop(adev);
1265 if (r)
1266 return r;
1267
1268 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1269 r = vcn_v2_0_stop_dpg_mode(adev);
1270 if (r)
1271 return r;
1272 goto power_off;
1273 }
1274
1275 /* wait for uvd idle */
1276 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1277 if (r)
1278 return r;
1279
1280 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1281 UVD_LMI_STATUS__READ_CLEAN_MASK |
1282 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1283 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1284 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1285 if (r)
1286 return r;
1287
1288 /* stall UMC channel */
1289 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1290 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1291 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1292
1293 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1294 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1295 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1296 if (r)
1297 return r;
1298
1299 /* disable VCPU clock */
1300 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1301 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1302
1303 /* reset LMI UMC */
1304 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1305 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1306 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1307
1308 /* reset LMI */
1309 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1310 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1311 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1312
1313 /* reset VCPU */
1314 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1315 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1316 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1317
1318 /* clear status */
1319 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1320
1321 vcn_v2_0_enable_clock_gating(adev);
1322 vcn_v2_0_enable_static_power_gating(adev);
1323
1324power_off:
1325 if (adev->pm.dpm_enabled)
1326 amdgpu_dpm_enable_uvd(adev, false);
1327
1328 return 0;
1329}
1330
1331static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1332 struct dpg_pause_state *new_state)
1333{
1334 struct amdgpu_ring *ring;
1335 uint32_t reg_data = 0;
1336 int ret_code;
1337
1338 /* pause/unpause if state is changed */
1339 if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1340 DRM_DEBUG("dpg pause state changed %d -> %d",
1341 adev->vcn.pause_state.fw_based, new_state->fw_based);
1342 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1343 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1344
1345 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1346 ret_code = 0;
1347 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1348 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1349
1350 if (!ret_code) {
1351 /* pause DPG */
1352 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1353 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1354
1355 /* wait for ACK */
1356 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1357 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1358 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1359
1360 /* Restore */
1361 ring = &adev->vcn.inst->ring_enc[0];
1362 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1363 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1364 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1365 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1366 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1367
1368 ring = &adev->vcn.inst->ring_enc[1];
1369 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1370 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1371 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1372 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1373 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1374
1375 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1376 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1377
1378 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1379 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1380 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1381 }
1382 } else {
1383 /* unpause dpg, no need to wait */
1384 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1385 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1386 }
1387 adev->vcn.pause_state.fw_based = new_state->fw_based;
1388 }
1389
1390 return 0;
1391}
1392
1393static bool vcn_v2_0_is_idle(void *handle)
1394{
1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1396
1397 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1398}
1399
1400static int vcn_v2_0_wait_for_idle(void *handle)
1401{
1402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403 int ret = 0;
1404
1405 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1406 UVD_STATUS__IDLE, ret);
1407
1408 return ret;
1409}
1410
1411static int vcn_v2_0_set_clockgating_state(void *handle,
1412 enum amd_clockgating_state state)
1413{
1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1415 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1416
1417 if (enable) {
1418 /* wait for STATUS to clear */
1419 if (vcn_v2_0_is_idle(handle))
1420 return -EBUSY;
1421 vcn_v2_0_enable_clock_gating(adev);
1422 } else {
1423 /* disable HW gating and enable Sw gating */
1424 vcn_v2_0_disable_clock_gating(adev);
1425 }
1426 return 0;
1427}
1428
1429/**
1430 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1431 *
1432 * @ring: amdgpu_ring pointer
1433 *
1434 * Returns the current hardware read pointer
1435 */
1436static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1437{
1438 struct amdgpu_device *adev = ring->adev;
1439
1440 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1441}
1442
1443/**
1444 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1445 *
1446 * @ring: amdgpu_ring pointer
1447 *
1448 * Returns the current hardware write pointer
1449 */
1450static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1451{
1452 struct amdgpu_device *adev = ring->adev;
1453
1454 if (ring->use_doorbell)
1455 return adev->wb.wb[ring->wptr_offs];
1456 else
1457 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1458}
1459
1460/**
1461 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1462 *
1463 * @ring: amdgpu_ring pointer
1464 *
1465 * Commits the write pointer to the hardware
1466 */
1467static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1468{
1469 struct amdgpu_device *adev = ring->adev;
1470
1471 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1472 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1473 lower_32_bits(ring->wptr) | 0x80000000);
1474
1475 if (ring->use_doorbell) {
1476 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1477 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1478 } else {
1479 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1480 }
1481}
1482
1483/**
1484 * vcn_v2_0_dec_ring_insert_start - insert a start command
1485 *
1486 * @ring: amdgpu_ring pointer
1487 *
1488 * Write a start command to the ring.
1489 */
1490void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1491{
1492 struct amdgpu_device *adev = ring->adev;
1493
1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1495 amdgpu_ring_write(ring, 0);
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1497 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1498}
1499
1500/**
1501 * vcn_v2_0_dec_ring_insert_end - insert a end command
1502 *
1503 * @ring: amdgpu_ring pointer
1504 *
1505 * Write a end command to the ring.
1506 */
1507void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1508{
1509 struct amdgpu_device *adev = ring->adev;
1510
1511 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1512 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1513}
1514
1515/**
1516 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1517 *
1518 * @ring: amdgpu_ring pointer
1519 *
1520 * Write a nop command to the ring.
1521 */
1522void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1523{
1524 struct amdgpu_device *adev = ring->adev;
1525 int i;
1526
1527 WARN_ON(ring->wptr % 2 || count % 2);
1528
1529 for (i = 0; i < count / 2; i++) {
1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1531 amdgpu_ring_write(ring, 0);
1532 }
1533}
1534
1535/**
1536 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1537 *
1538 * @ring: amdgpu_ring pointer
1539 * @fence: fence to emit
1540 *
1541 * Write a fence and a trap command to the ring.
1542 */
1543void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1544 unsigned flags)
1545{
1546 struct amdgpu_device *adev = ring->adev;
1547
1548 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1549 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1550 amdgpu_ring_write(ring, seq);
1551
1552 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1553 amdgpu_ring_write(ring, addr & 0xffffffff);
1554
1555 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1556 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1557
1558 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1559 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1560
1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1562 amdgpu_ring_write(ring, 0);
1563
1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1565 amdgpu_ring_write(ring, 0);
1566
1567 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1568
1569 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1570}
1571
1572/**
1573 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1574 *
1575 * @ring: amdgpu_ring pointer
1576 * @ib: indirect buffer to execute
1577 *
1578 * Write ring commands to execute the indirect buffer
1579 */
1580void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1581 struct amdgpu_job *job,
1582 struct amdgpu_ib *ib,
1583 uint32_t flags)
1584{
1585 struct amdgpu_device *adev = ring->adev;
1586 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1587
1588 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1589 amdgpu_ring_write(ring, vmid);
1590
1591 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1592 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1593 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1594 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1595 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1596 amdgpu_ring_write(ring, ib->length_dw);
1597}
1598
1599void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1600 uint32_t val, uint32_t mask)
1601{
1602 struct amdgpu_device *adev = ring->adev;
1603
1604 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1605 amdgpu_ring_write(ring, reg << 2);
1606
1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1608 amdgpu_ring_write(ring, val);
1609
1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1611 amdgpu_ring_write(ring, mask);
1612
1613 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1614
1615 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1616}
1617
1618void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1619 unsigned vmid, uint64_t pd_addr)
1620{
1621 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1622 uint32_t data0, data1, mask;
1623
1624 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1625
1626 /* wait for register write */
1627 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1628 data1 = lower_32_bits(pd_addr);
1629 mask = 0xffffffff;
1630 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1631}
1632
1633void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1634 uint32_t reg, uint32_t val)
1635{
1636 struct amdgpu_device *adev = ring->adev;
1637
1638 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1639 amdgpu_ring_write(ring, reg << 2);
1640
1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1642 amdgpu_ring_write(ring, val);
1643
1644 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1645
1646 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1647}
1648
1649/**
1650 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1651 *
1652 * @ring: amdgpu_ring pointer
1653 *
1654 * Returns the current hardware enc read pointer
1655 */
1656static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1657{
1658 struct amdgpu_device *adev = ring->adev;
1659
1660 if (ring == &adev->vcn.inst->ring_enc[0])
1661 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1662 else
1663 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1664}
1665
1666 /**
1667 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1668 *
1669 * @ring: amdgpu_ring pointer
1670 *
1671 * Returns the current hardware enc write pointer
1672 */
1673static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1674{
1675 struct amdgpu_device *adev = ring->adev;
1676
1677 if (ring == &adev->vcn.inst->ring_enc[0]) {
1678 if (ring->use_doorbell)
1679 return adev->wb.wb[ring->wptr_offs];
1680 else
1681 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1682 } else {
1683 if (ring->use_doorbell)
1684 return adev->wb.wb[ring->wptr_offs];
1685 else
1686 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1687 }
1688}
1689
1690 /**
1691 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1692 *
1693 * @ring: amdgpu_ring pointer
1694 *
1695 * Commits the enc write pointer to the hardware
1696 */
1697static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1698{
1699 struct amdgpu_device *adev = ring->adev;
1700
1701 if (ring == &adev->vcn.inst->ring_enc[0]) {
1702 if (ring->use_doorbell) {
1703 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1704 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1705 } else {
1706 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1707 }
1708 } else {
1709 if (ring->use_doorbell) {
1710 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1711 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1712 } else {
1713 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1714 }
1715 }
1716}
1717
1718/**
1719 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1720 *
1721 * @ring: amdgpu_ring pointer
1722 * @fence: fence to emit
1723 *
1724 * Write enc a fence and a trap command to the ring.
1725 */
1726void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1727 u64 seq, unsigned flags)
1728{
1729 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1730
1731 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1732 amdgpu_ring_write(ring, addr);
1733 amdgpu_ring_write(ring, upper_32_bits(addr));
1734 amdgpu_ring_write(ring, seq);
1735 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1736}
1737
1738void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1739{
1740 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1741}
1742
1743/**
1744 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1745 *
1746 * @ring: amdgpu_ring pointer
1747 * @ib: indirect buffer to execute
1748 *
1749 * Write enc ring commands to execute the indirect buffer
1750 */
1751void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1752 struct amdgpu_job *job,
1753 struct amdgpu_ib *ib,
1754 uint32_t flags)
1755{
1756 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1757
1758 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1759 amdgpu_ring_write(ring, vmid);
1760 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1761 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1762 amdgpu_ring_write(ring, ib->length_dw);
1763}
1764
1765void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1766 uint32_t val, uint32_t mask)
1767{
1768 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1769 amdgpu_ring_write(ring, reg << 2);
1770 amdgpu_ring_write(ring, mask);
1771 amdgpu_ring_write(ring, val);
1772}
1773
1774void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1775 unsigned int vmid, uint64_t pd_addr)
1776{
1777 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1778
1779 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1780
1781 /* wait for reg writes */
1782 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1783 lower_32_bits(pd_addr), 0xffffffff);
1784}
1785
1786void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1787{
1788 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1789 amdgpu_ring_write(ring, reg << 2);
1790 amdgpu_ring_write(ring, val);
1791}
1792
1793/**
1794 * vcn_v2_0_jpeg_ring_get_rptr - get read pointer
1795 *
1796 * @ring: amdgpu_ring pointer
1797 *
1798 * Returns the current hardware read pointer
1799 */
1800static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1801{
1802 struct amdgpu_device *adev = ring->adev;
1803
1804 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1805}
1806
1807/**
1808 * vcn_v2_0_jpeg_ring_get_wptr - get write pointer
1809 *
1810 * @ring: amdgpu_ring pointer
1811 *
1812 * Returns the current hardware write pointer
1813 */
1814static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1815{
1816 struct amdgpu_device *adev = ring->adev;
1817
1818 if (ring->use_doorbell)
1819 return adev->wb.wb[ring->wptr_offs];
1820 else
1821 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1822}
1823
1824/**
1825 * vcn_v2_0_jpeg_ring_set_wptr - set write pointer
1826 *
1827 * @ring: amdgpu_ring pointer
1828 *
1829 * Commits the write pointer to the hardware
1830 */
1831static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1832{
1833 struct amdgpu_device *adev = ring->adev;
1834
1835 if (ring->use_doorbell) {
1836 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1837 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1838 } else {
1839 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1840 }
1841}
1842
1843/**
1844 * vcn_v2_0_jpeg_ring_insert_start - insert a start command
1845 *
1846 * @ring: amdgpu_ring pointer
1847 *
1848 * Write a start command to the ring.
1849 */
1850void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1851{
1852 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
1853 0, 0, PACKETJ_TYPE0));
1854 amdgpu_ring_write(ring, 0x68e04);
1855
1856 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
1857 0, 0, PACKETJ_TYPE0));
1858 amdgpu_ring_write(ring, 0x80010000);
1859}
1860
1861/**
1862 * vcn_v2_0_jpeg_ring_insert_end - insert a end command
1863 *
1864 * @ring: amdgpu_ring pointer
1865 *
1866 * Write a end command to the ring.
1867 */
1868void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1869{
1870 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
1871 0, 0, PACKETJ_TYPE0));
1872 amdgpu_ring_write(ring, 0x68e04);
1873
1874 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
1875 0, 0, PACKETJ_TYPE0));
1876 amdgpu_ring_write(ring, 0x00010000);
1877}
1878
1879/**
1880 * vcn_v2_0_jpeg_ring_emit_fence - emit an fence & trap command
1881 *
1882 * @ring: amdgpu_ring pointer
1883 * @fence: fence to emit
1884 *
1885 * Write a fence and a trap command to the ring.
1886 */
1887void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1888 unsigned flags)
1889{
1890 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1891
1892 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
1893 0, 0, PACKETJ_TYPE0));
1894 amdgpu_ring_write(ring, seq);
1895
1896 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
1897 0, 0, PACKETJ_TYPE0));
1898 amdgpu_ring_write(ring, seq);
1899
1900 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
1901 0, 0, PACKETJ_TYPE0));
1902 amdgpu_ring_write(ring, lower_32_bits(addr));
1903
1904 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
1905 0, 0, PACKETJ_TYPE0));
1906 amdgpu_ring_write(ring, upper_32_bits(addr));
1907
1908 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
1909 0, 0, PACKETJ_TYPE0));
1910 amdgpu_ring_write(ring, 0x8);
1911
1912 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
1913 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1914 amdgpu_ring_write(ring, 0);
1915
1916 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
1917 0, 0, PACKETJ_TYPE0));
1918 amdgpu_ring_write(ring, 0x3fbc);
1919
1920 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
1921 0, 0, PACKETJ_TYPE0));
1922 amdgpu_ring_write(ring, 0x1);
1923
1924 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1925 amdgpu_ring_write(ring, 0);
1926}
1927
1928/**
1929 * vcn_v2_0_jpeg_ring_emit_ib - execute indirect buffer
1930 *
1931 * @ring: amdgpu_ring pointer
1932 * @ib: indirect buffer to execute
1933 *
1934 * Write ring commands to execute the indirect buffer.
1935 */
1936void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1937 struct amdgpu_job *job,
1938 struct amdgpu_ib *ib,
1939 uint32_t flags)
1940{
1941 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1942
1943 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
1944 0, 0, PACKETJ_TYPE0));
1945 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1946
1947 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
1948 0, 0, PACKETJ_TYPE0));
1949 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1950
1951 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
1952 0, 0, PACKETJ_TYPE0));
1953 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1954
1955 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
1956 0, 0, PACKETJ_TYPE0));
1957 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1958
1959 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
1960 0, 0, PACKETJ_TYPE0));
1961 amdgpu_ring_write(ring, ib->length_dw);
1962
1963 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
1964 0, 0, PACKETJ_TYPE0));
1965 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1966
1967 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
1968 0, 0, PACKETJ_TYPE0));
1969 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1970
1971 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1972 amdgpu_ring_write(ring, 0);
1973
1974 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
1975 0, 0, PACKETJ_TYPE0));
1976 amdgpu_ring_write(ring, 0x01400200);
1977
1978 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
1979 0, 0, PACKETJ_TYPE0));
1980 amdgpu_ring_write(ring, 0x2);
1981
1982 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
1983 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1984 amdgpu_ring_write(ring, 0x2);
1985}
1986
1987void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1988 uint32_t val, uint32_t mask)
1989{
1990 uint32_t reg_offset = (reg << 2);
1991
1992 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
1993 0, 0, PACKETJ_TYPE0));
1994 amdgpu_ring_write(ring, 0x01400200);
1995
1996 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
1997 0, 0, PACKETJ_TYPE0));
1998 amdgpu_ring_write(ring, val);
1999
2000 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
2001 0, 0, PACKETJ_TYPE0));
2002 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
2003 amdgpu_ring_write(ring, 0);
2004 amdgpu_ring_write(ring,
2005 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
2006 } else {
2007 amdgpu_ring_write(ring, reg_offset);
2008 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
2009 0, 0, PACKETJ_TYPE3));
2010 }
2011 amdgpu_ring_write(ring, mask);
2012}
2013
2014void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
2015 unsigned vmid, uint64_t pd_addr)
2016{
2017 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
2018 uint32_t data0, data1, mask;
2019
2020 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2021
2022 /* wait for register write */
2023 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
2024 data1 = lower_32_bits(pd_addr);
2025 mask = 0xffffffff;
2026 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
2027}
2028
2029void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
2030{
2031 uint32_t reg_offset = (reg << 2);
2032
2033 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
2034 0, 0, PACKETJ_TYPE0));
2035 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
2036 amdgpu_ring_write(ring, 0);
2037 amdgpu_ring_write(ring,
2038 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
2039 } else {
2040 amdgpu_ring_write(ring, reg_offset);
2041 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
2042 0, 0, PACKETJ_TYPE0));
2043 }
2044 amdgpu_ring_write(ring, val);
2045}
2046
2047void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
2048{
2049 int i;
2050
2051 WARN_ON(ring->wptr % 2 || count % 2);
2052
2053 for (i = 0; i < count / 2; i++) {
2054 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
2055 amdgpu_ring_write(ring, 0);
2056 }
2057}
2058
2059static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
2060 struct amdgpu_irq_src *source,
2061 unsigned type,
2062 enum amdgpu_interrupt_state state)
2063{
2064 return 0;
2065}
2066
2067static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
2068 struct amdgpu_irq_src *source,
2069 struct amdgpu_iv_entry *entry)
2070{
2071 DRM_DEBUG("IH: VCN TRAP\n");
2072
2073 switch (entry->src_id) {
2074 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2075 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
2076 break;
2077 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2078 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
2079 break;
2080 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2081 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
2082 break;
2083 case VCN_2_0__SRCID__JPEG_DECODE:
2084 amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
2085 break;
2086 default:
2087 DRM_ERROR("Unhandled interrupt: %d %d\n",
2088 entry->src_id, entry->src_data[0]);
2089 break;
2090 }
2091
2092 return 0;
2093}
2094
2095static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
2096{
2097 struct amdgpu_device *adev = ring->adev;
2098 uint32_t tmp = 0;
2099 unsigned i;
2100 int r;
2101
2102 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
2103 r = amdgpu_ring_alloc(ring, 4);
2104 if (r)
2105 return r;
2106 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
2107 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
2108 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
2109 amdgpu_ring_write(ring, 0xDEADBEEF);
2110 amdgpu_ring_commit(ring);
2111 for (i = 0; i < adev->usec_timeout; i++) {
2112 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
2113 if (tmp == 0xDEADBEEF)
2114 break;
2115 udelay(1);
2116 }
2117
2118 if (i >= adev->usec_timeout)
2119 r = -ETIMEDOUT;
2120
2121 return r;
2122}
2123
2124
2125static int vcn_v2_0_set_powergating_state(void *handle,
2126 enum amd_powergating_state state)
2127{
2128 /* This doesn't actually powergate the VCN block.
2129 * That's done in the dpm code via the SMC. This
2130 * just re-inits the block as necessary. The actual
2131 * gating still happens in the dpm code. We should
2132 * revisit this when there is a cleaner line between
2133 * the smc and the hw blocks
2134 */
2135 int ret;
2136 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2137
2138 if (state == adev->vcn.cur_state)
2139 return 0;
2140
2141 if (state == AMD_PG_STATE_GATE)
2142 ret = vcn_v2_0_stop(adev);
2143 else
2144 ret = vcn_v2_0_start(adev);
2145
2146 if (!ret)
2147 adev->vcn.cur_state = state;
2148 return ret;
2149}
2150
2151static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
2152 .name = "vcn_v2_0",
2153 .early_init = vcn_v2_0_early_init,
2154 .late_init = NULL,
2155 .sw_init = vcn_v2_0_sw_init,
2156 .sw_fini = vcn_v2_0_sw_fini,
2157 .hw_init = vcn_v2_0_hw_init,
2158 .hw_fini = vcn_v2_0_hw_fini,
2159 .suspend = vcn_v2_0_suspend,
2160 .resume = vcn_v2_0_resume,
2161 .is_idle = vcn_v2_0_is_idle,
2162 .wait_for_idle = vcn_v2_0_wait_for_idle,
2163 .check_soft_reset = NULL,
2164 .pre_soft_reset = NULL,
2165 .soft_reset = NULL,
2166 .post_soft_reset = NULL,
2167 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
2168 .set_powergating_state = vcn_v2_0_set_powergating_state,
2169};
2170
2171static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2172 .type = AMDGPU_RING_TYPE_VCN_DEC,
2173 .align_mask = 0xf,
2174 .vmhub = AMDGPU_MMHUB_0,
2175 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2176 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2177 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2178 .emit_frame_size =
2179 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2180 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2181 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2182 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2183 6,
2184 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2185 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2186 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2187 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2188 .test_ring = vcn_v2_0_dec_ring_test_ring,
2189 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2190 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2191 .insert_start = vcn_v2_0_dec_ring_insert_start,
2192 .insert_end = vcn_v2_0_dec_ring_insert_end,
2193 .pad_ib = amdgpu_ring_generic_pad_ib,
2194 .begin_use = amdgpu_vcn_ring_begin_use,
2195 .end_use = amdgpu_vcn_ring_end_use,
2196 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2197 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2198 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2199};
2200
2201static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2202 .type = AMDGPU_RING_TYPE_VCN_ENC,
2203 .align_mask = 0x3f,
2204 .nop = VCN_ENC_CMD_NO_OP,
2205 .vmhub = AMDGPU_MMHUB_0,
2206 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2207 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2208 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2209 .emit_frame_size =
2210 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2211 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2212 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2213 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2214 1, /* vcn_v2_0_enc_ring_insert_end */
2215 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2216 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2217 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2218 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2219 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2220 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2221 .insert_nop = amdgpu_ring_insert_nop,
2222 .insert_end = vcn_v2_0_enc_ring_insert_end,
2223 .pad_ib = amdgpu_ring_generic_pad_ib,
2224 .begin_use = amdgpu_vcn_ring_begin_use,
2225 .end_use = amdgpu_vcn_ring_end_use,
2226 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2227 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2228 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2229};
2230
2231static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
2232 .type = AMDGPU_RING_TYPE_VCN_JPEG,
2233 .align_mask = 0xf,
2234 .vmhub = AMDGPU_MMHUB_0,
2235 .get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
2236 .get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
2237 .set_wptr = vcn_v2_0_jpeg_ring_set_wptr,
2238 .emit_frame_size =
2239 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2240 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2241 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
2242 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
2243 8 + 16,
2244 .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
2245 .emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
2246 .emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
2247 .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
2248 .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2249 .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2250 .insert_nop = vcn_v2_0_jpeg_ring_nop,
2251 .insert_start = vcn_v2_0_jpeg_ring_insert_start,
2252 .insert_end = vcn_v2_0_jpeg_ring_insert_end,
2253 .pad_ib = amdgpu_ring_generic_pad_ib,
2254 .begin_use = amdgpu_vcn_ring_begin_use,
2255 .end_use = amdgpu_vcn_ring_end_use,
2256 .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
2257 .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
2258 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2259};
2260
2261static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2262{
2263 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2264 DRM_INFO("VCN decode is enabled in VM mode\n");
2265}
2266
2267static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2268{
2269 int i;
2270
2271 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2272 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2273
2274 DRM_INFO("VCN encode is enabled in VM mode\n");
2275}
2276
2277static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2278{
2279 adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
2280 DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2281}
2282
2283static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2284 .set = vcn_v2_0_set_interrupt_state,
2285 .process = vcn_v2_0_process_interrupt,
2286};
2287
2288static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2289{
2290 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
2291 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2292}
2293
2294const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2295{
2296 .type = AMD_IP_BLOCK_TYPE_VCN,
2297 .major = 2,
2298 .minor = 0,
2299 .rev = 0,
2300 .funcs = &vcn_v2_0_ip_funcs,
2301};
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drm_drv.h>
26
27#include "amdgpu.h"
28#include "amdgpu_vcn.h"
29#include "soc15.h"
30#include "soc15d.h"
31#include "amdgpu_pm.h"
32#include "amdgpu_psp.h"
33#include "mmsch_v2_0.h"
34#include "vcn_v2_0.h"
35
36#include "vcn/vcn_2_0_0_offset.h"
37#include "vcn/vcn_2_0_0_sh_mask.h"
38#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
41#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42
43#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
44#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
45#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
46#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
47#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
48#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
49#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
50
51#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
52#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
53#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
54#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
55
56static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
57static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
58static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
59static int vcn_v2_0_set_powergating_state(void *handle,
60 enum amd_powergating_state state);
61static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
62 int inst_idx, struct dpg_pause_state *new_state);
63static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
64/**
65 * vcn_v2_0_early_init - set function pointers
66 *
67 * @handle: amdgpu_device pointer
68 *
69 * Set ring and irq function pointers
70 */
71static int vcn_v2_0_early_init(void *handle)
72{
73 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
74
75 if (amdgpu_sriov_vf(adev))
76 adev->vcn.num_enc_rings = 1;
77 else
78 adev->vcn.num_enc_rings = 2;
79
80 vcn_v2_0_set_dec_ring_funcs(adev);
81 vcn_v2_0_set_enc_ring_funcs(adev);
82 vcn_v2_0_set_irq_funcs(adev);
83
84 return 0;
85}
86
87/**
88 * vcn_v2_0_sw_init - sw init for VCN block
89 *
90 * @handle: amdgpu_device pointer
91 *
92 * Load firmware and sw initialization
93 */
94static int vcn_v2_0_sw_init(void *handle)
95{
96 struct amdgpu_ring *ring;
97 int i, r;
98 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
99 volatile struct amdgpu_fw_shared *fw_shared;
100
101 /* VCN DEC TRAP */
102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
103 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
104 &adev->vcn.inst->irq);
105 if (r)
106 return r;
107
108 /* VCN ENC TRAP */
109 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
110 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
111 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
112 &adev->vcn.inst->irq);
113 if (r)
114 return r;
115 }
116
117 r = amdgpu_vcn_sw_init(adev);
118 if (r)
119 return r;
120
121 amdgpu_vcn_setup_ucode(adev);
122
123 r = amdgpu_vcn_resume(adev);
124 if (r)
125 return r;
126
127 ring = &adev->vcn.inst->ring_dec;
128
129 ring->use_doorbell = true;
130 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
131
132 sprintf(ring->name, "vcn_dec");
133 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
134 AMDGPU_RING_PRIO_DEFAULT, NULL);
135 if (r)
136 return r;
137
138 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
139 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
140 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
141 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
142 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
143 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
144
145 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
146 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
147 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
148 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
149 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
150 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
151 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
152 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
153 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
154 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
155
156 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
157 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
158
159 ring = &adev->vcn.inst->ring_enc[i];
160 ring->use_doorbell = true;
161 if (!amdgpu_sriov_vf(adev))
162 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
163 else
164 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
165 sprintf(ring->name, "vcn_enc%d", i);
166 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
167 hw_prio, NULL);
168 if (r)
169 return r;
170 }
171
172 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
173
174 r = amdgpu_virt_alloc_mm_table(adev);
175 if (r)
176 return r;
177
178 fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
179 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
180
181 if (amdgpu_vcnfw_log)
182 amdgpu_vcn_fwlog_init(adev->vcn.inst);
183
184 return 0;
185}
186
187/**
188 * vcn_v2_0_sw_fini - sw fini for VCN block
189 *
190 * @handle: amdgpu_device pointer
191 *
192 * VCN suspend and free up sw allocation
193 */
194static int vcn_v2_0_sw_fini(void *handle)
195{
196 int r, idx;
197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
198 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
199
200 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
201 fw_shared->present_flag_0 = 0;
202 drm_dev_exit(idx);
203 }
204
205 amdgpu_virt_free_mm_table(adev);
206
207 r = amdgpu_vcn_suspend(adev);
208 if (r)
209 return r;
210
211 r = amdgpu_vcn_sw_fini(adev);
212
213 return r;
214}
215
216/**
217 * vcn_v2_0_hw_init - start and test VCN block
218 *
219 * @handle: amdgpu_device pointer
220 *
221 * Initialize the hardware, boot up the VCPU and do some testing
222 */
223static int vcn_v2_0_hw_init(void *handle)
224{
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
226 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
227 int i, r;
228
229 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
230 ring->doorbell_index, 0);
231
232 if (amdgpu_sriov_vf(adev))
233 vcn_v2_0_start_sriov(adev);
234
235 r = amdgpu_ring_test_helper(ring);
236 if (r)
237 goto done;
238
239 //Disable vcn decode for sriov
240 if (amdgpu_sriov_vf(adev))
241 ring->sched.ready = false;
242
243 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
244 ring = &adev->vcn.inst->ring_enc[i];
245 r = amdgpu_ring_test_helper(ring);
246 if (r)
247 goto done;
248 }
249
250done:
251 if (!r)
252 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
253 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
254
255 return r;
256}
257
258/**
259 * vcn_v2_0_hw_fini - stop the hardware block
260 *
261 * @handle: amdgpu_device pointer
262 *
263 * Stop the VCN block, mark ring as not ready any more
264 */
265static int vcn_v2_0_hw_fini(void *handle)
266{
267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
268
269 cancel_delayed_work_sync(&adev->vcn.idle_work);
270
271 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
272 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
273 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
274 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
275
276 return 0;
277}
278
279/**
280 * vcn_v2_0_suspend - suspend VCN block
281 *
282 * @handle: amdgpu_device pointer
283 *
284 * HW fini and suspend VCN block
285 */
286static int vcn_v2_0_suspend(void *handle)
287{
288 int r;
289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
290
291 r = vcn_v2_0_hw_fini(adev);
292 if (r)
293 return r;
294
295 r = amdgpu_vcn_suspend(adev);
296
297 return r;
298}
299
300/**
301 * vcn_v2_0_resume - resume VCN block
302 *
303 * @handle: amdgpu_device pointer
304 *
305 * Resume firmware and hw init VCN block
306 */
307static int vcn_v2_0_resume(void *handle)
308{
309 int r;
310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
311
312 r = amdgpu_vcn_resume(adev);
313 if (r)
314 return r;
315
316 r = vcn_v2_0_hw_init(adev);
317
318 return r;
319}
320
321/**
322 * vcn_v2_0_mc_resume - memory controller programming
323 *
324 * @adev: amdgpu_device pointer
325 *
326 * Let the VCN memory controller know it's offsets
327 */
328static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
329{
330 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
331 uint32_t offset;
332
333 if (amdgpu_sriov_vf(adev))
334 return;
335
336 /* cache window 0: fw */
337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
339 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
340 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
341 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
342 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
343 offset = 0;
344 } else {
345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
346 lower_32_bits(adev->vcn.inst->gpu_addr));
347 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
348 upper_32_bits(adev->vcn.inst->gpu_addr));
349 offset = size;
350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
351 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
352 }
353
354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
355
356 /* cache window 1: stack */
357 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
358 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
359 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
360 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
361 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
363
364 /* cache window 2: context */
365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
366 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
367 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
368 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
369 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
370 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
371
372 /* non-cache window */
373 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
374 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
375 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
376 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
377 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
378 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
379 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
380
381 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
382}
383
384static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
385{
386 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
387 uint32_t offset;
388
389 /* cache window 0: fw */
390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
391 if (!indirect) {
392 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
393 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
394 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
395 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
396 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
397 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
398 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
399 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
400 } else {
401 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
402 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
403 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
404 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
405 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
406 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
407 }
408 offset = 0;
409 } else {
410 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
411 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
412 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
413 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
414 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
415 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
416 offset = size;
417 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
418 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
420 }
421
422 if (!indirect)
423 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
424 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
425 else
426 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
427 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
428
429 /* cache window 1: stack */
430 if (!indirect) {
431 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
432 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
433 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
434 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
435 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
436 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
437 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
438 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
439 } else {
440 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
441 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
442 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
443 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
444 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
445 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
446 }
447 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
448 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
449
450 /* cache window 2: context */
451 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
452 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
453 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
454 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
455 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
456 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
458 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
459 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
460 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
461
462 /* non-cache window */
463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
464 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
465 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
467 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
468 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
469 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
470 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
471 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
472 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
473 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
474
475 /* VCN global tiling registers */
476 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
477 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
478}
479
480/**
481 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
482 *
483 * @adev: amdgpu_device pointer
484 *
485 * Disable clock gating for VCN block
486 */
487static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
488{
489 uint32_t data;
490
491 if (amdgpu_sriov_vf(adev))
492 return;
493
494 /* UVD disable CGC */
495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
496 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
497 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
498 else
499 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
500 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
501 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
502 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
503
504 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
505 data &= ~(UVD_CGC_GATE__SYS_MASK
506 | UVD_CGC_GATE__UDEC_MASK
507 | UVD_CGC_GATE__MPEG2_MASK
508 | UVD_CGC_GATE__REGS_MASK
509 | UVD_CGC_GATE__RBC_MASK
510 | UVD_CGC_GATE__LMI_MC_MASK
511 | UVD_CGC_GATE__LMI_UMC_MASK
512 | UVD_CGC_GATE__IDCT_MASK
513 | UVD_CGC_GATE__MPRD_MASK
514 | UVD_CGC_GATE__MPC_MASK
515 | UVD_CGC_GATE__LBSI_MASK
516 | UVD_CGC_GATE__LRBBM_MASK
517 | UVD_CGC_GATE__UDEC_RE_MASK
518 | UVD_CGC_GATE__UDEC_CM_MASK
519 | UVD_CGC_GATE__UDEC_IT_MASK
520 | UVD_CGC_GATE__UDEC_DB_MASK
521 | UVD_CGC_GATE__UDEC_MP_MASK
522 | UVD_CGC_GATE__WCB_MASK
523 | UVD_CGC_GATE__VCPU_MASK
524 | UVD_CGC_GATE__SCPU_MASK);
525 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
526
527 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
528 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
529 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
530 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
531 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
532 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
533 | UVD_CGC_CTRL__SYS_MODE_MASK
534 | UVD_CGC_CTRL__UDEC_MODE_MASK
535 | UVD_CGC_CTRL__MPEG2_MODE_MASK
536 | UVD_CGC_CTRL__REGS_MODE_MASK
537 | UVD_CGC_CTRL__RBC_MODE_MASK
538 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
539 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
540 | UVD_CGC_CTRL__IDCT_MODE_MASK
541 | UVD_CGC_CTRL__MPRD_MODE_MASK
542 | UVD_CGC_CTRL__MPC_MODE_MASK
543 | UVD_CGC_CTRL__LBSI_MODE_MASK
544 | UVD_CGC_CTRL__LRBBM_MODE_MASK
545 | UVD_CGC_CTRL__WCB_MODE_MASK
546 | UVD_CGC_CTRL__VCPU_MODE_MASK
547 | UVD_CGC_CTRL__SCPU_MODE_MASK);
548 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
549
550 /* turn on */
551 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
552 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
553 | UVD_SUVD_CGC_GATE__SIT_MASK
554 | UVD_SUVD_CGC_GATE__SMP_MASK
555 | UVD_SUVD_CGC_GATE__SCM_MASK
556 | UVD_SUVD_CGC_GATE__SDB_MASK
557 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
558 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
559 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
560 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
561 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
562 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
563 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
564 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
565 | UVD_SUVD_CGC_GATE__SCLR_MASK
566 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
567 | UVD_SUVD_CGC_GATE__ENT_MASK
568 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
569 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
570 | UVD_SUVD_CGC_GATE__SITE_MASK
571 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
572 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
573 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
574 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
575 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
576 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
577
578 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
579 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
580 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
581 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
582 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
583 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
584 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
585 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
586 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
587 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
588 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
589 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
590}
591
592static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
593 uint8_t sram_sel, uint8_t indirect)
594{
595 uint32_t reg_data = 0;
596
597 /* enable sw clock gating control */
598 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
599 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
600 else
601 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
602 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
603 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
604 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
605 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
606 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
607 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
608 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
609 UVD_CGC_CTRL__SYS_MODE_MASK |
610 UVD_CGC_CTRL__UDEC_MODE_MASK |
611 UVD_CGC_CTRL__MPEG2_MODE_MASK |
612 UVD_CGC_CTRL__REGS_MODE_MASK |
613 UVD_CGC_CTRL__RBC_MODE_MASK |
614 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
615 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
616 UVD_CGC_CTRL__IDCT_MODE_MASK |
617 UVD_CGC_CTRL__MPRD_MODE_MASK |
618 UVD_CGC_CTRL__MPC_MODE_MASK |
619 UVD_CGC_CTRL__LBSI_MODE_MASK |
620 UVD_CGC_CTRL__LRBBM_MODE_MASK |
621 UVD_CGC_CTRL__WCB_MODE_MASK |
622 UVD_CGC_CTRL__VCPU_MODE_MASK |
623 UVD_CGC_CTRL__SCPU_MODE_MASK);
624 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
625 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
626
627 /* turn off clock gating */
628 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
629 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
630
631 /* turn on SUVD clock gating */
632 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
633 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
634
635 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
636 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
637 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
638}
639
640/**
641 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
642 *
643 * @adev: amdgpu_device pointer
644 *
645 * Enable clock gating for VCN block
646 */
647static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
648{
649 uint32_t data = 0;
650
651 if (amdgpu_sriov_vf(adev))
652 return;
653
654 /* enable UVD CGC */
655 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
656 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
657 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
658 else
659 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
660 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
661 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
662 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
663
664 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
665 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
666 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
667 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
668 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
669 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
670 | UVD_CGC_CTRL__SYS_MODE_MASK
671 | UVD_CGC_CTRL__UDEC_MODE_MASK
672 | UVD_CGC_CTRL__MPEG2_MODE_MASK
673 | UVD_CGC_CTRL__REGS_MODE_MASK
674 | UVD_CGC_CTRL__RBC_MODE_MASK
675 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
676 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
677 | UVD_CGC_CTRL__IDCT_MODE_MASK
678 | UVD_CGC_CTRL__MPRD_MODE_MASK
679 | UVD_CGC_CTRL__MPC_MODE_MASK
680 | UVD_CGC_CTRL__LBSI_MODE_MASK
681 | UVD_CGC_CTRL__LRBBM_MODE_MASK
682 | UVD_CGC_CTRL__WCB_MODE_MASK
683 | UVD_CGC_CTRL__VCPU_MODE_MASK
684 | UVD_CGC_CTRL__SCPU_MODE_MASK);
685 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
686
687 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
688 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
689 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
690 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
691 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
692 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
693 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
694 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
695 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
696 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
697 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
698 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
699}
700
701static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
702{
703 uint32_t data = 0;
704
705 if (amdgpu_sriov_vf(adev))
706 return;
707
708 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
709 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
710 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
711 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
712 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
713 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
714 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
715 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
716 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
717 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
718 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
719
720 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
721 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
722 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
723 } else {
724 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
725 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
726 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
727 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
728 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
729 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
730 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
731 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
732 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
733 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
734 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
735 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);
736 }
737
738 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
739 * UVDU_PWR_STATUS are 0 (power on) */
740
741 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
742 data &= ~0x103;
743 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
744 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
745 UVD_POWER_STATUS__UVD_PG_EN_MASK;
746
747 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
748}
749
750static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
751{
752 uint32_t data = 0;
753
754 if (amdgpu_sriov_vf(adev))
755 return;
756
757 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
758 /* Before power off, this indicator has to be turned on */
759 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
760 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
761 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
762 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
763
764
765 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
766 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
767 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
768 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
769 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
770 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
771 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
772 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
773 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
774 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
775
776 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
777
778 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
779 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
780 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
781 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
782 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
783 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
784 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
785 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
786 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
787 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
788 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
789 }
790}
791
792static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
793{
794 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
795 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
796 uint32_t rb_bufsz, tmp;
797
798 vcn_v2_0_enable_static_power_gating(adev);
799
800 /* enable dynamic power gating mode */
801 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
802 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
803 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
804 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
805
806 if (indirect)
807 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
808
809 /* enable clock gating */
810 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
811
812 /* enable VCPU clock */
813 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
814 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
815 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
816 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
817 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
818
819 /* disable master interupt */
820 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
821 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
822
823 /* setup mmUVD_LMI_CTRL */
824 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
825 UVD_LMI_CTRL__REQ_MODE_MASK |
826 UVD_LMI_CTRL__CRC_RESET_MASK |
827 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
828 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
829 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
830 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
831 0x00100000L);
832 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
833 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
834
835 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
836 UVD, 0, mmUVD_MPC_CNTL),
837 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
838
839 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
840 UVD, 0, mmUVD_MPC_SET_MUXA0),
841 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
842 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
843 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
844 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
845
846 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
847 UVD, 0, mmUVD_MPC_SET_MUXB0),
848 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
849 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
850 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
851 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
852
853 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
854 UVD, 0, mmUVD_MPC_SET_MUX),
855 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
856 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
857 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
858
859 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
860
861 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
862 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
863 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
864 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
865
866 /* release VCPU reset to boot */
867 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
868 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
869
870 /* enable LMI MC and UMC channels */
871 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
872 UVD, 0, mmUVD_LMI_CTRL2),
873 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
874
875 /* enable master interrupt */
876 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
877 UVD, 0, mmUVD_MASTINT_EN),
878 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
879
880 if (indirect)
881 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
882 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
883 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
884
885 /* force RBC into idle state */
886 rb_bufsz = order_base_2(ring->ring_size);
887 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
888 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
889 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
890 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
891 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
892 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
893
894 /* Stall DPG before WPTR/RPTR reset */
895 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
896 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
897 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
898 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
899
900 /* set the write pointer delay */
901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
902
903 /* set the wb address */
904 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
905 (upper_32_bits(ring->gpu_addr) >> 2));
906
907 /* program the RB_BASE for ring buffer */
908 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
909 lower_32_bits(ring->gpu_addr));
910 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
911 upper_32_bits(ring->gpu_addr));
912
913 /* Initialize the ring buffer's read and write pointers */
914 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
915
916 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
917
918 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
920 lower_32_bits(ring->wptr));
921
922 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
923 /* Unstall DPG */
924 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
925 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
926 return 0;
927}
928
929static int vcn_v2_0_start(struct amdgpu_device *adev)
930{
931 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
932 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
933 uint32_t rb_bufsz, tmp;
934 uint32_t lmi_swap_cntl;
935 int i, j, r;
936
937 if (adev->pm.dpm_enabled)
938 amdgpu_dpm_enable_uvd(adev, true);
939
940 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
941 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
942
943 vcn_v2_0_disable_static_power_gating(adev);
944
945 /* set uvd status busy */
946 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
947 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
948
949 /*SW clock gating */
950 vcn_v2_0_disable_clock_gating(adev);
951
952 /* enable VCPU clock */
953 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
954 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
955
956 /* disable master interrupt */
957 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
958 ~UVD_MASTINT_EN__VCPU_EN_MASK);
959
960 /* setup mmUVD_LMI_CTRL */
961 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
962 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
963 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
964 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
965 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
966 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
967
968 /* setup mmUVD_MPC_CNTL */
969 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
970 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
971 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
972 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
973
974 /* setup UVD_MPC_SET_MUXA0 */
975 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
976 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
977 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
978 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
979 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
980
981 /* setup UVD_MPC_SET_MUXB0 */
982 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
983 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
984 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
985 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
986 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
987
988 /* setup mmUVD_MPC_SET_MUX */
989 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
990 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
991 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
992 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
993
994 vcn_v2_0_mc_resume(adev);
995
996 /* release VCPU reset to boot */
997 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
998 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
999
1000 /* enable LMI MC and UMC channels */
1001 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1002 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1003
1004 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1005 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1006 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1007 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1008
1009 /* disable byte swapping */
1010 lmi_swap_cntl = 0;
1011#ifdef __BIG_ENDIAN
1012 /* swap (8 in 32) RB and IB */
1013 lmi_swap_cntl = 0xa;
1014#endif
1015 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1016
1017 for (i = 0; i < 10; ++i) {
1018 uint32_t status;
1019
1020 for (j = 0; j < 100; ++j) {
1021 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1022 if (status & 2)
1023 break;
1024 mdelay(10);
1025 }
1026 r = 0;
1027 if (status & 2)
1028 break;
1029
1030 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1031 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1032 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1033 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1034 mdelay(10);
1035 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1036 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1037 mdelay(10);
1038 r = -1;
1039 }
1040
1041 if (r) {
1042 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1043 return r;
1044 }
1045
1046 /* enable master interrupt */
1047 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1048 UVD_MASTINT_EN__VCPU_EN_MASK,
1049 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1050
1051 /* clear the busy bit of VCN_STATUS */
1052 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1053 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1054
1055 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1056
1057 /* force RBC into idle state */
1058 rb_bufsz = order_base_2(ring->ring_size);
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1064 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1065
1066 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1067 /* program the RB_BASE for ring buffer */
1068 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1069 lower_32_bits(ring->gpu_addr));
1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1071 upper_32_bits(ring->gpu_addr));
1072
1073 /* Initialize the ring buffer's read and write pointers */
1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1075
1076 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1078 lower_32_bits(ring->wptr));
1079 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1080
1081 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1082 ring = &adev->vcn.inst->ring_enc[0];
1083 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1084 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1085 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1086 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1087 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1088 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1089
1090 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1091 ring = &adev->vcn.inst->ring_enc[1];
1092 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1093 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1094 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1095 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1096 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1097 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1098
1099 return 0;
1100}
1101
1102static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1103{
1104 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1105 uint32_t tmp;
1106
1107 vcn_v2_0_pause_dpg_mode(adev, 0, &state);
1108 /* Wait for power status to be 1 */
1109 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1110 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1111
1112 /* wait for read ptr to be equal to write ptr */
1113 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1115
1116 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1118
1119 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1120 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1121
1122 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1123 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1124
1125 /* disable dynamic power gating mode */
1126 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1127 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1128
1129 return 0;
1130}
1131
1132static int vcn_v2_0_stop(struct amdgpu_device *adev)
1133{
1134 uint32_t tmp;
1135 int r;
1136
1137 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1138 r = vcn_v2_0_stop_dpg_mode(adev);
1139 if (r)
1140 return r;
1141 goto power_off;
1142 }
1143
1144 /* wait for uvd idle */
1145 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1146 if (r)
1147 return r;
1148
1149 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1150 UVD_LMI_STATUS__READ_CLEAN_MASK |
1151 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1152 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1153 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1154 if (r)
1155 return r;
1156
1157 /* stall UMC channel */
1158 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1159 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1160 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1161
1162 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1163 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1164 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1165 if (r)
1166 return r;
1167
1168 /* disable VCPU clock */
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1170 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1171
1172 /* reset LMI UMC */
1173 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1174 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1175 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1176
1177 /* reset LMI */
1178 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1179 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1180 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1181
1182 /* reset VCPU */
1183 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1184 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1185 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1186
1187 /* clear status */
1188 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1189
1190 vcn_v2_0_enable_clock_gating(adev);
1191 vcn_v2_0_enable_static_power_gating(adev);
1192
1193power_off:
1194 if (adev->pm.dpm_enabled)
1195 amdgpu_dpm_enable_uvd(adev, false);
1196
1197 return 0;
1198}
1199
1200static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1201 int inst_idx, struct dpg_pause_state *new_state)
1202{
1203 struct amdgpu_ring *ring;
1204 uint32_t reg_data = 0;
1205 int ret_code;
1206
1207 /* pause/unpause if state is changed */
1208 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1209 DRM_DEBUG("dpg pause state changed %d -> %d",
1210 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1211 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1212 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1213
1214 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1215 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1216 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1217
1218 if (!ret_code) {
1219 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1220 /* pause DPG */
1221 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1222 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1223
1224 /* wait for ACK */
1225 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1226 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1227 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1228
1229 /* Stall DPG before WPTR/RPTR reset */
1230 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1231 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1232 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1233 /* Restore */
1234 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1235 ring = &adev->vcn.inst->ring_enc[0];
1236 ring->wptr = 0;
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1240 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1242 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1243
1244 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1245 ring = &adev->vcn.inst->ring_enc[1];
1246 ring->wptr = 0;
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1252 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1253
1254 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1256 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1257 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1258 /* Unstall DPG */
1259 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1260 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1261
1262 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1263 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1264 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1265 }
1266 } else {
1267 /* unpause dpg, no need to wait */
1268 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1270 }
1271 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1272 }
1273
1274 return 0;
1275}
1276
1277static bool vcn_v2_0_is_idle(void *handle)
1278{
1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1282}
1283
1284static int vcn_v2_0_wait_for_idle(void *handle)
1285{
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 int ret;
1288
1289 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1290 UVD_STATUS__IDLE);
1291
1292 return ret;
1293}
1294
1295static int vcn_v2_0_set_clockgating_state(void *handle,
1296 enum amd_clockgating_state state)
1297{
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299 bool enable = (state == AMD_CG_STATE_GATE);
1300
1301 if (amdgpu_sriov_vf(adev))
1302 return 0;
1303
1304 if (enable) {
1305 /* wait for STATUS to clear */
1306 if (!vcn_v2_0_is_idle(handle))
1307 return -EBUSY;
1308 vcn_v2_0_enable_clock_gating(adev);
1309 } else {
1310 /* disable HW gating and enable Sw gating */
1311 vcn_v2_0_disable_clock_gating(adev);
1312 }
1313 return 0;
1314}
1315
1316/**
1317 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1318 *
1319 * @ring: amdgpu_ring pointer
1320 *
1321 * Returns the current hardware read pointer
1322 */
1323static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1324{
1325 struct amdgpu_device *adev = ring->adev;
1326
1327 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1328}
1329
1330/**
1331 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1332 *
1333 * @ring: amdgpu_ring pointer
1334 *
1335 * Returns the current hardware write pointer
1336 */
1337static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1338{
1339 struct amdgpu_device *adev = ring->adev;
1340
1341 if (ring->use_doorbell)
1342 return *ring->wptr_cpu_addr;
1343 else
1344 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1345}
1346
1347/**
1348 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1349 *
1350 * @ring: amdgpu_ring pointer
1351 *
1352 * Commits the write pointer to the hardware
1353 */
1354static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1355{
1356 struct amdgpu_device *adev = ring->adev;
1357
1358 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1359 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1360 lower_32_bits(ring->wptr) | 0x80000000);
1361
1362 if (ring->use_doorbell) {
1363 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1364 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1365 } else {
1366 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1367 }
1368}
1369
1370/**
1371 * vcn_v2_0_dec_ring_insert_start - insert a start command
1372 *
1373 * @ring: amdgpu_ring pointer
1374 *
1375 * Write a start command to the ring.
1376 */
1377void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1378{
1379 struct amdgpu_device *adev = ring->adev;
1380
1381 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1382 amdgpu_ring_write(ring, 0);
1383 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1384 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1385}
1386
1387/**
1388 * vcn_v2_0_dec_ring_insert_end - insert a end command
1389 *
1390 * @ring: amdgpu_ring pointer
1391 *
1392 * Write a end command to the ring.
1393 */
1394void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1395{
1396 struct amdgpu_device *adev = ring->adev;
1397
1398 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1399 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1400}
1401
1402/**
1403 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1404 *
1405 * @ring: amdgpu_ring pointer
1406 * @count: the number of NOP packets to insert
1407 *
1408 * Write a nop command to the ring.
1409 */
1410void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1411{
1412 struct amdgpu_device *adev = ring->adev;
1413 int i;
1414
1415 WARN_ON(ring->wptr % 2 || count % 2);
1416
1417 for (i = 0; i < count / 2; i++) {
1418 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1419 amdgpu_ring_write(ring, 0);
1420 }
1421}
1422
1423/**
1424 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1425 *
1426 * @ring: amdgpu_ring pointer
1427 * @addr: address
1428 * @seq: sequence number
1429 * @flags: fence related flags
1430 *
1431 * Write a fence and a trap command to the ring.
1432 */
1433void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1434 unsigned flags)
1435{
1436 struct amdgpu_device *adev = ring->adev;
1437
1438 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1440 amdgpu_ring_write(ring, seq);
1441
1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1443 amdgpu_ring_write(ring, addr & 0xffffffff);
1444
1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1446 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1447
1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1449 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1450
1451 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1452 amdgpu_ring_write(ring, 0);
1453
1454 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1455 amdgpu_ring_write(ring, 0);
1456
1457 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1458
1459 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1460}
1461
1462/**
1463 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1464 *
1465 * @ring: amdgpu_ring pointer
1466 * @job: job to retrieve vmid from
1467 * @ib: indirect buffer to execute
1468 * @flags: unused
1469 *
1470 * Write ring commands to execute the indirect buffer
1471 */
1472void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1473 struct amdgpu_job *job,
1474 struct amdgpu_ib *ib,
1475 uint32_t flags)
1476{
1477 struct amdgpu_device *adev = ring->adev;
1478 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1479
1480 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1481 amdgpu_ring_write(ring, vmid);
1482
1483 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1484 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1485 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1486 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1487 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1488 amdgpu_ring_write(ring, ib->length_dw);
1489}
1490
1491void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1492 uint32_t val, uint32_t mask)
1493{
1494 struct amdgpu_device *adev = ring->adev;
1495
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1497 amdgpu_ring_write(ring, reg << 2);
1498
1499 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1500 amdgpu_ring_write(ring, val);
1501
1502 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1503 amdgpu_ring_write(ring, mask);
1504
1505 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1506
1507 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1508}
1509
1510void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1511 unsigned vmid, uint64_t pd_addr)
1512{
1513 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1514 uint32_t data0, data1, mask;
1515
1516 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1517
1518 /* wait for register write */
1519 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1520 data1 = lower_32_bits(pd_addr);
1521 mask = 0xffffffff;
1522 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1523}
1524
1525void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1526 uint32_t reg, uint32_t val)
1527{
1528 struct amdgpu_device *adev = ring->adev;
1529
1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1531 amdgpu_ring_write(ring, reg << 2);
1532
1533 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1534 amdgpu_ring_write(ring, val);
1535
1536 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1537
1538 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1539}
1540
1541/**
1542 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1543 *
1544 * @ring: amdgpu_ring pointer
1545 *
1546 * Returns the current hardware enc read pointer
1547 */
1548static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1549{
1550 struct amdgpu_device *adev = ring->adev;
1551
1552 if (ring == &adev->vcn.inst->ring_enc[0])
1553 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1554 else
1555 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1556}
1557
1558 /**
1559 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1560 *
1561 * @ring: amdgpu_ring pointer
1562 *
1563 * Returns the current hardware enc write pointer
1564 */
1565static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1566{
1567 struct amdgpu_device *adev = ring->adev;
1568
1569 if (ring == &adev->vcn.inst->ring_enc[0]) {
1570 if (ring->use_doorbell)
1571 return *ring->wptr_cpu_addr;
1572 else
1573 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1574 } else {
1575 if (ring->use_doorbell)
1576 return *ring->wptr_cpu_addr;
1577 else
1578 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1579 }
1580}
1581
1582 /**
1583 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1584 *
1585 * @ring: amdgpu_ring pointer
1586 *
1587 * Commits the enc write pointer to the hardware
1588 */
1589static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1590{
1591 struct amdgpu_device *adev = ring->adev;
1592
1593 if (ring == &adev->vcn.inst->ring_enc[0]) {
1594 if (ring->use_doorbell) {
1595 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1596 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1597 } else {
1598 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1599 }
1600 } else {
1601 if (ring->use_doorbell) {
1602 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1603 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1604 } else {
1605 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1606 }
1607 }
1608}
1609
1610/**
1611 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1612 *
1613 * @ring: amdgpu_ring pointer
1614 * @addr: address
1615 * @seq: sequence number
1616 * @flags: fence related flags
1617 *
1618 * Write enc a fence and a trap command to the ring.
1619 */
1620void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1621 u64 seq, unsigned flags)
1622{
1623 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1624
1625 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1626 amdgpu_ring_write(ring, addr);
1627 amdgpu_ring_write(ring, upper_32_bits(addr));
1628 amdgpu_ring_write(ring, seq);
1629 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1630}
1631
1632void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1633{
1634 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1635}
1636
1637/**
1638 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1639 *
1640 * @ring: amdgpu_ring pointer
1641 * @job: job to retrive vmid from
1642 * @ib: indirect buffer to execute
1643 * @flags: unused
1644 *
1645 * Write enc ring commands to execute the indirect buffer
1646 */
1647void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1648 struct amdgpu_job *job,
1649 struct amdgpu_ib *ib,
1650 uint32_t flags)
1651{
1652 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1653
1654 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1655 amdgpu_ring_write(ring, vmid);
1656 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1657 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1658 amdgpu_ring_write(ring, ib->length_dw);
1659}
1660
1661void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1662 uint32_t val, uint32_t mask)
1663{
1664 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1665 amdgpu_ring_write(ring, reg << 2);
1666 amdgpu_ring_write(ring, mask);
1667 amdgpu_ring_write(ring, val);
1668}
1669
1670void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1671 unsigned int vmid, uint64_t pd_addr)
1672{
1673 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1674
1675 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1676
1677 /* wait for reg writes */
1678 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1679 vmid * hub->ctx_addr_distance,
1680 lower_32_bits(pd_addr), 0xffffffff);
1681}
1682
1683void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1684{
1685 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1686 amdgpu_ring_write(ring, reg << 2);
1687 amdgpu_ring_write(ring, val);
1688}
1689
1690static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1691 struct amdgpu_irq_src *source,
1692 unsigned type,
1693 enum amdgpu_interrupt_state state)
1694{
1695 return 0;
1696}
1697
1698static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1699 struct amdgpu_irq_src *source,
1700 struct amdgpu_iv_entry *entry)
1701{
1702 DRM_DEBUG("IH: VCN TRAP\n");
1703
1704 switch (entry->src_id) {
1705 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1706 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1707 break;
1708 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1709 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1710 break;
1711 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1712 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1713 break;
1714 default:
1715 DRM_ERROR("Unhandled interrupt: %d %d\n",
1716 entry->src_id, entry->src_data[0]);
1717 break;
1718 }
1719
1720 return 0;
1721}
1722
1723int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1724{
1725 struct amdgpu_device *adev = ring->adev;
1726 uint32_t tmp = 0;
1727 unsigned i;
1728 int r;
1729
1730 if (amdgpu_sriov_vf(adev))
1731 return 0;
1732
1733 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1734 r = amdgpu_ring_alloc(ring, 4);
1735 if (r)
1736 return r;
1737 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1738 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1739 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1740 amdgpu_ring_write(ring, 0xDEADBEEF);
1741 amdgpu_ring_commit(ring);
1742 for (i = 0; i < adev->usec_timeout; i++) {
1743 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1744 if (tmp == 0xDEADBEEF)
1745 break;
1746 udelay(1);
1747 }
1748
1749 if (i >= adev->usec_timeout)
1750 r = -ETIMEDOUT;
1751
1752 return r;
1753}
1754
1755
1756static int vcn_v2_0_set_powergating_state(void *handle,
1757 enum amd_powergating_state state)
1758{
1759 /* This doesn't actually powergate the VCN block.
1760 * That's done in the dpm code via the SMC. This
1761 * just re-inits the block as necessary. The actual
1762 * gating still happens in the dpm code. We should
1763 * revisit this when there is a cleaner line between
1764 * the smc and the hw blocks
1765 */
1766 int ret;
1767 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1768
1769 if (amdgpu_sriov_vf(adev)) {
1770 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1771 return 0;
1772 }
1773
1774 if (state == adev->vcn.cur_state)
1775 return 0;
1776
1777 if (state == AMD_PG_STATE_GATE)
1778 ret = vcn_v2_0_stop(adev);
1779 else
1780 ret = vcn_v2_0_start(adev);
1781
1782 if (!ret)
1783 adev->vcn.cur_state = state;
1784 return ret;
1785}
1786
1787static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1788 struct amdgpu_mm_table *table)
1789{
1790 uint32_t data = 0, loop;
1791 uint64_t addr = table->gpu_addr;
1792 struct mmsch_v2_0_init_header *header;
1793 uint32_t size;
1794 int i;
1795
1796 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1797 size = header->header_size + header->vcn_table_size;
1798
1799 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1800 * of memory descriptor location
1801 */
1802 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1803 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1804
1805 /* 2, update vmid of descriptor */
1806 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1807 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1808 /* use domain0 for MM scheduler */
1809 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1810 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1811
1812 /* 3, notify mmsch about the size of this descriptor */
1813 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1814
1815 /* 4, set resp to zero */
1816 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1817
1818 adev->vcn.inst->ring_dec.wptr = 0;
1819 adev->vcn.inst->ring_dec.wptr_old = 0;
1820 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1821
1822 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1823 adev->vcn.inst->ring_enc[i].wptr = 0;
1824 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1825 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1826 }
1827
1828 /* 5, kick off the initialization and wait until
1829 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1830 */
1831 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1832
1833 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1834 loop = 1000;
1835 while ((data & 0x10000002) != 0x10000002) {
1836 udelay(10);
1837 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1838 loop--;
1839 if (!loop)
1840 break;
1841 }
1842
1843 if (!loop) {
1844 DRM_ERROR("failed to init MMSCH, " \
1845 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1846 return -EBUSY;
1847 }
1848
1849 return 0;
1850}
1851
1852static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1853{
1854 int r;
1855 uint32_t tmp;
1856 struct amdgpu_ring *ring;
1857 uint32_t offset, size;
1858 uint32_t table_size = 0;
1859 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1860 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1861 struct mmsch_v2_0_cmd_end end = { {0} };
1862 struct mmsch_v2_0_init_header *header;
1863 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1864 uint8_t i = 0;
1865
1866 header = (struct mmsch_v2_0_init_header *)init_table;
1867 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1868 direct_rd_mod_wt.cmd_header.command_type =
1869 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1870 end.cmd_header.command_type = MMSCH_COMMAND__END;
1871
1872 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1873 header->version = MMSCH_VERSION;
1874 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1875
1876 header->vcn_table_offset = header->header_size;
1877
1878 init_table += header->vcn_table_offset;
1879
1880 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1881
1882 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1883 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1884 0xFFFFFFFF, 0x00000004);
1885
1886 /* mc resume*/
1887 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1888 MMSCH_V2_0_INSERT_DIRECT_WT(
1889 SOC15_REG_OFFSET(UVD, i,
1890 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1891 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
1892 MMSCH_V2_0_INSERT_DIRECT_WT(
1893 SOC15_REG_OFFSET(UVD, i,
1894 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1895 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
1896 offset = 0;
1897 } else {
1898 MMSCH_V2_0_INSERT_DIRECT_WT(
1899 SOC15_REG_OFFSET(UVD, i,
1900 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1901 lower_32_bits(adev->vcn.inst->gpu_addr));
1902 MMSCH_V2_0_INSERT_DIRECT_WT(
1903 SOC15_REG_OFFSET(UVD, i,
1904 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1905 upper_32_bits(adev->vcn.inst->gpu_addr));
1906 offset = size;
1907 }
1908
1909 MMSCH_V2_0_INSERT_DIRECT_WT(
1910 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1911 0);
1912 MMSCH_V2_0_INSERT_DIRECT_WT(
1913 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1914 size);
1915
1916 MMSCH_V2_0_INSERT_DIRECT_WT(
1917 SOC15_REG_OFFSET(UVD, i,
1918 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1919 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1920 MMSCH_V2_0_INSERT_DIRECT_WT(
1921 SOC15_REG_OFFSET(UVD, i,
1922 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1923 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1924 MMSCH_V2_0_INSERT_DIRECT_WT(
1925 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1926 0);
1927 MMSCH_V2_0_INSERT_DIRECT_WT(
1928 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1929 AMDGPU_VCN_STACK_SIZE);
1930
1931 MMSCH_V2_0_INSERT_DIRECT_WT(
1932 SOC15_REG_OFFSET(UVD, i,
1933 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1934 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1935 AMDGPU_VCN_STACK_SIZE));
1936 MMSCH_V2_0_INSERT_DIRECT_WT(
1937 SOC15_REG_OFFSET(UVD, i,
1938 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1939 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1940 AMDGPU_VCN_STACK_SIZE));
1941 MMSCH_V2_0_INSERT_DIRECT_WT(
1942 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1943 0);
1944 MMSCH_V2_0_INSERT_DIRECT_WT(
1945 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1946 AMDGPU_VCN_CONTEXT_SIZE);
1947
1948 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1949 ring = &adev->vcn.inst->ring_enc[r];
1950 ring->wptr = 0;
1951 MMSCH_V2_0_INSERT_DIRECT_WT(
1952 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1953 lower_32_bits(ring->gpu_addr));
1954 MMSCH_V2_0_INSERT_DIRECT_WT(
1955 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1956 upper_32_bits(ring->gpu_addr));
1957 MMSCH_V2_0_INSERT_DIRECT_WT(
1958 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1959 ring->ring_size / 4);
1960 }
1961
1962 ring = &adev->vcn.inst->ring_dec;
1963 ring->wptr = 0;
1964 MMSCH_V2_0_INSERT_DIRECT_WT(
1965 SOC15_REG_OFFSET(UVD, i,
1966 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1967 lower_32_bits(ring->gpu_addr));
1968 MMSCH_V2_0_INSERT_DIRECT_WT(
1969 SOC15_REG_OFFSET(UVD, i,
1970 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1971 upper_32_bits(ring->gpu_addr));
1972 /* force RBC into idle state */
1973 tmp = order_base_2(ring->ring_size);
1974 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1975 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1976 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1977 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1978 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1979 MMSCH_V2_0_INSERT_DIRECT_WT(
1980 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1981
1982 /* add end packet */
1983 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1984 memcpy((void *)init_table, &end, tmp);
1985 table_size += (tmp / 4);
1986 header->vcn_table_size = table_size;
1987
1988 }
1989 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1990}
1991
1992static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1993 .name = "vcn_v2_0",
1994 .early_init = vcn_v2_0_early_init,
1995 .late_init = NULL,
1996 .sw_init = vcn_v2_0_sw_init,
1997 .sw_fini = vcn_v2_0_sw_fini,
1998 .hw_init = vcn_v2_0_hw_init,
1999 .hw_fini = vcn_v2_0_hw_fini,
2000 .suspend = vcn_v2_0_suspend,
2001 .resume = vcn_v2_0_resume,
2002 .is_idle = vcn_v2_0_is_idle,
2003 .wait_for_idle = vcn_v2_0_wait_for_idle,
2004 .check_soft_reset = NULL,
2005 .pre_soft_reset = NULL,
2006 .soft_reset = NULL,
2007 .post_soft_reset = NULL,
2008 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
2009 .set_powergating_state = vcn_v2_0_set_powergating_state,
2010};
2011
2012static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2013 .type = AMDGPU_RING_TYPE_VCN_DEC,
2014 .align_mask = 0xf,
2015 .secure_submission_supported = true,
2016 .vmhub = AMDGPU_MMHUB_0,
2017 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2018 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2019 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2020 .emit_frame_size =
2021 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2022 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2023 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2024 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2025 6,
2026 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2027 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2028 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2029 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2030 .test_ring = vcn_v2_0_dec_ring_test_ring,
2031 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2032 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2033 .insert_start = vcn_v2_0_dec_ring_insert_start,
2034 .insert_end = vcn_v2_0_dec_ring_insert_end,
2035 .pad_ib = amdgpu_ring_generic_pad_ib,
2036 .begin_use = amdgpu_vcn_ring_begin_use,
2037 .end_use = amdgpu_vcn_ring_end_use,
2038 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2039 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2040 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2041};
2042
2043static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2044 .type = AMDGPU_RING_TYPE_VCN_ENC,
2045 .align_mask = 0x3f,
2046 .nop = VCN_ENC_CMD_NO_OP,
2047 .vmhub = AMDGPU_MMHUB_0,
2048 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2049 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2050 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2051 .emit_frame_size =
2052 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2053 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2054 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2055 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2056 1, /* vcn_v2_0_enc_ring_insert_end */
2057 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2058 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2059 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2060 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2061 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2062 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2063 .insert_nop = amdgpu_ring_insert_nop,
2064 .insert_end = vcn_v2_0_enc_ring_insert_end,
2065 .pad_ib = amdgpu_ring_generic_pad_ib,
2066 .begin_use = amdgpu_vcn_ring_begin_use,
2067 .end_use = amdgpu_vcn_ring_end_use,
2068 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2069 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2070 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2071};
2072
2073static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2074{
2075 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2076 DRM_INFO("VCN decode is enabled in VM mode\n");
2077}
2078
2079static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2080{
2081 int i;
2082
2083 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2084 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2085
2086 DRM_INFO("VCN encode is enabled in VM mode\n");
2087}
2088
2089static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2090 .set = vcn_v2_0_set_interrupt_state,
2091 .process = vcn_v2_0_process_interrupt,
2092};
2093
2094static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2095{
2096 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
2097 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2098}
2099
2100const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2101{
2102 .type = AMD_IP_BLOCK_TYPE_VCN,
2103 .major = 2,
2104 .minor = 0,
2105 .rev = 0,
2106 .funcs = &vcn_v2_0_ip_funcs,
2107};