1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright 2016 Linaro Ltd.
  4 * Copyright 2016 ZTE Corporation.
  5 */
  6
  7#ifndef __ZX_PLANE_REGS_H__
  8#define __ZX_PLANE_REGS_H__
  9
 10/* GL registers */
 11#define GL_CTRL0			0x00
 12#define GL_UPDATE			BIT(5)
 13#define GL_CTRL1			0x04
 14#define GL_DATA_FMT_SHIFT		0
 15#define GL_DATA_FMT_MASK		(0xf << GL_DATA_FMT_SHIFT)
 16#define GL_FMT_ARGB8888			0
 17#define GL_FMT_RGB888			1
 18#define GL_FMT_RGB565			2
 19#define GL_FMT_ARGB1555			3
 20#define GL_FMT_ARGB4444			4
 21#define GL_CTRL2			0x08
 22#define GL_GLOBAL_ALPHA_SHIFT		8
 23#define GL_GLOBAL_ALPHA_MASK		(0xff << GL_GLOBAL_ALPHA_SHIFT)
 24#define GL_CTRL3			0x0c
 25#define GL_SCALER_BYPASS_MODE		BIT(0)
 26#define GL_STRIDE			0x18
 27#define GL_ADDR				0x1c
 28#define GL_SRC_SIZE			0x38
 29#define GL_SRC_W_SHIFT			16
 30#define GL_SRC_W_MASK			(0x3fff << GL_SRC_W_SHIFT)
 31#define GL_SRC_H_SHIFT			0
 32#define GL_SRC_H_MASK			(0x3fff << GL_SRC_H_SHIFT)
 33#define GL_POS_START			0x9c
 34#define GL_POS_END			0xa0
 35#define GL_POS_X_SHIFT			16
 36#define GL_POS_X_MASK			(0x1fff << GL_POS_X_SHIFT)
 37#define GL_POS_Y_SHIFT			0
 38#define GL_POS_Y_MASK			(0x1fff << GL_POS_Y_SHIFT)
 39
 40#define GL_SRC_W(x)	(((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK)
 41#define GL_SRC_H(x)	(((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK)
 42#define GL_POS_X(x)	(((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
 43#define GL_POS_Y(x)	(((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
 44
 45/* VL registers */
 46#define VL_CTRL0			0x00
 47#define VL_UPDATE			BIT(3)
 48#define VL_CTRL1			0x04
 49#define VL_YUV420_PLANAR		BIT(5)
 50#define VL_YUV422_SHIFT			3
 51#define VL_YUV422_YUYV			(0 << VL_YUV422_SHIFT)
 52#define VL_YUV422_YVYU			(1 << VL_YUV422_SHIFT)
 53#define VL_YUV422_UYVY			(2 << VL_YUV422_SHIFT)
 54#define VL_YUV422_VYUY			(3 << VL_YUV422_SHIFT)
 55#define VL_FMT_YUV420			0
 56#define VL_FMT_YUV422			1
 57#define VL_FMT_YUV420_P010		2
 58#define VL_FMT_YUV420_HANTRO		3
 59#define VL_FMT_YUV444_8BIT		4
 60#define VL_FMT_YUV444_10BIT		5
 61#define VL_CTRL2			0x08
 62#define VL_SCALER_BYPASS_MODE		BIT(0)
 63#define VL_STRIDE			0x0c
 64#define LUMA_STRIDE_SHIFT		16
 65#define LUMA_STRIDE_MASK		(0xffff << LUMA_STRIDE_SHIFT)
 66#define CHROMA_STRIDE_SHIFT		0
 67#define CHROMA_STRIDE_MASK		(0xffff << CHROMA_STRIDE_SHIFT)
 68#define VL_SRC_SIZE			0x10
 69#define VL_Y				0x14
 70#define VL_POS_START			0x30
 71#define VL_POS_END			0x34
 72
 73#define LUMA_STRIDE(x)	 (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK)
 74#define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK)
 75
 76/* RSZ registers */
 77#define RSZ_SRC_CFG			0x00
 78#define RSZ_DEST_CFG			0x04
 79#define RSZ_ENABLE_CFG			0x14
 80
 81#define RSZ_VL_LUMA_HOR			0x08
 82#define RSZ_VL_LUMA_VER			0x0c
 83#define RSZ_VL_CHROMA_HOR		0x10
 84#define RSZ_VL_CHROMA_VER		0x14
 85#define RSZ_VL_CTRL_CFG			0x18
 86#define RSZ_VL_FMT_SHIFT		3
 87#define RSZ_VL_FMT_MASK			(0x3 << RSZ_VL_FMT_SHIFT)
 88#define RSZ_VL_FMT_YCBCR420		(0x0 << RSZ_VL_FMT_SHIFT)
 89#define RSZ_VL_FMT_YCBCR422		(0x1 << RSZ_VL_FMT_SHIFT)
 90#define RSZ_VL_FMT_YCBCR444		(0x2 << RSZ_VL_FMT_SHIFT)
 91#define RSZ_VL_ENABLE_CFG		0x1c
 92
 93#define RSZ_VER_SHIFT			16
 94#define RSZ_VER_MASK			(0xffff << RSZ_VER_SHIFT)
 95#define RSZ_HOR_SHIFT			0
 96#define RSZ_HOR_MASK			(0xffff << RSZ_HOR_SHIFT)
 97
 98#define RSZ_VER(x)	(((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
 99#define RSZ_HOR(x)	(((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
100
101#define RSZ_DATA_STEP_SHIFT		16
102#define RSZ_DATA_STEP_MASK		(0xffff << RSZ_DATA_STEP_SHIFT)
103#define RSZ_PARA_STEP_SHIFT		0
104#define RSZ_PARA_STEP_MASK		(0xffff << RSZ_PARA_STEP_SHIFT)
105
106#define RSZ_DATA_STEP(x) (((x) << RSZ_DATA_STEP_SHIFT) & RSZ_DATA_STEP_MASK)
107#define RSZ_PARA_STEP(x) (((x) << RSZ_PARA_STEP_SHIFT) & RSZ_PARA_STEP_MASK)
108
109/* HBSC registers */
110#define HBSC_SATURATION			0x00
111#define HBSC_HUE			0x04
112#define HBSC_BRIGHT			0x08
113#define HBSC_CONTRAST			0x0c
114#define HBSC_THRESHOLD_COL1		0x10
115#define HBSC_THRESHOLD_COL2		0x14
116#define HBSC_THRESHOLD_COL3		0x18
117#define HBSC_CTRL0			0x28
118#define HBSC_CTRL_EN			BIT(2)
119
120#endif /* __ZX_PLANE_REGS_H__ */