1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#include "xe_tuning.h"
  7
  8#include <kunit/visibility.h>
  9
 10#include "regs/xe_gt_regs.h"
 11#include "xe_gt_types.h"
 12#include "xe_platform_types.h"
 13#include "xe_rtp.h"
 14
 15#undef XE_REG_MCR
 16#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 17
 18static const struct xe_rtp_entry_sr gt_tunings[] = {
 19	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
 20	  XE_RTP_RULES(PLATFORM(DG2)),
 21	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
 22	},
 23	{ XE_RTP_NAME("Tuning: 32B Access Enable"),
 24	  XE_RTP_RULES(PLATFORM(DG2)),
 25	  XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
 26	},
 27
 28	/* Xe2 */
 29
 30	{ XE_RTP_NAME("Tuning: L3 cache"),
 31	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
 32	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 33				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 34	},
 35	{ XE_RTP_NAME("Tuning: L3 cache - media"),
 36	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
 37	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 38				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 39	},
 40	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
 41	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
 42	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
 43			 SET(CCCHKNREG1, L3CMPCTRL))
 44	},
 45	{ XE_RTP_NAME("Tuning: Compression Overfetch - media"),
 46	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
 47	  XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
 48			 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
 49	},
 50	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
 51	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
 52	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
 53	},
 54	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
 55	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
 56	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
 57	},
 58	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
 59	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
 60	  XE_RTP_ACTIONS(SET(L3SQCREG2,
 61			     COMPMEMRD256BOVRFETCHEN))
 62	},
 63	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
 64	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
 65	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
 66			     COMPMEMRD256BOVRFETCHEN))
 67	},
 68	{ XE_RTP_NAME("Tuning: Stateless compression control"),
 69	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
 70	  XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
 71				   REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
 72	},
 73	{ XE_RTP_NAME("Tuning: Stateless compression control - media"),
 74	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, XE_RTP_END_VERSION_UNDEFINED)),
 75	  XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
 76				   REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
 77	},
 78	{ XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
 79	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
 80	  XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
 81	},
 82	{ XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
 83	  XE_RTP_RULES(MEDIA_VERSION(2000)),
 84	  XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
 85	},
 86
 87	{}
 88};
 89
 90static const struct xe_rtp_entry_sr engine_tunings[] = {
 91	{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
 92	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
 93		       ENGINE_CLASS(RENDER)),
 94	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
 95	},
 96	{}
 97};
 98
 99static const struct xe_rtp_entry_sr lrc_tunings[] = {
100	{ XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"),
101	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
102	  /* read verification is ignored due to 1608008084. */
103	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
104						FF_MODE2_GS_TIMER_MASK,
105						FF_MODE2_GS_TIMER_224))
106	},
107
108	/* DG2 */
109
110	{ XE_RTP_NAME("Tuning: L3 cache"),
111	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
112	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
113				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
114	},
115	{ XE_RTP_NAME("Tuning: TDS gang timer"),
116	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
117	  /* read verification is ignored as in i915 - need to check enabling */
118	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
119						FF_MODE2_TDS_TIMER_MASK,
120						FF_MODE2_TDS_TIMER_128))
121	},
122	{ XE_RTP_NAME("Tuning: TBIMR fast clip"),
123	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
124	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
125	},
126
127	/* Xe_LPG */
128
129	{ XE_RTP_NAME("Tuning: L3 cache"),
130	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
131	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
132				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
133	},
134
135	/* Xe2_HPG */
136
137	{ XE_RTP_NAME("Tuning: vs hit max value"),
138	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
139	  XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
140				   REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
141	},
142
143	{}
144};
145
146void xe_tuning_process_gt(struct xe_gt *gt)
147{
148	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
149
150	xe_rtp_process_to_sr(&ctx, gt_tunings, &gt->reg_sr);
151}
152EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
153
154void xe_tuning_process_engine(struct xe_hw_engine *hwe)
155{
156	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
157
158	xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr);
159}
160EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
161
162/**
163 * xe_tuning_process_lrc - process lrc tunings
164 * @hwe: engine instance to process tunings for
165 *
166 * Process LRC table for this platform, saving in @hwe all the tunings that need
167 * to be applied on context restore. These are tunings touching registers that
168 * are part of the HW context image.
169 */
170void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
171{
172	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
173
174	xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc);
175}