Loading...
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "cikd.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v8_0.h"
39
40#include "dce/dce_8_0_d.h"
41#include "dce/dce_8_0_sh_mask.h"
42
43#include "gca/gfx_7_2_enum.h"
44
45#include "gmc/gmc_7_1_d.h"
46#include "gmc/gmc_7_1_sh_mask.h"
47
48#include "oss/oss_2_0_d.h"
49#include "oss/oss_2_0_sh_mask.h"
50
51static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
52static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
53
54static const u32 crtc_offsets[6] =
55{
56 CRTC0_REGISTER_OFFSET,
57 CRTC1_REGISTER_OFFSET,
58 CRTC2_REGISTER_OFFSET,
59 CRTC3_REGISTER_OFFSET,
60 CRTC4_REGISTER_OFFSET,
61 CRTC5_REGISTER_OFFSET
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72};
73
74static const uint32_t dig_offsets[] = {
75 CRTC0_REGISTER_OFFSET,
76 CRTC1_REGISTER_OFFSET,
77 CRTC2_REGISTER_OFFSET,
78 CRTC3_REGISTER_OFFSET,
79 CRTC4_REGISTER_OFFSET,
80 CRTC5_REGISTER_OFFSET,
81 (0x13830 - 0x7030) >> 2,
82};
83
84static const struct {
85 uint32_t reg;
86 uint32_t vblank;
87 uint32_t vline;
88 uint32_t hpd;
89
90} interrupt_status_offsets[6] = { {
91 .reg = mmDISP_INTERRUPT_STATUS,
92 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115}, {
116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120} };
121
122static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
123 u32 block_offset, u32 reg)
124{
125 unsigned long flags;
126 u32 r;
127
128 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
129 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
130 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
131 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132
133 return r;
134}
135
136static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
137 u32 block_offset, u32 reg, u32 v)
138{
139 unsigned long flags;
140
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
145}
146
147static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
148{
149 if (crtc >= adev->mode_info.num_crtc)
150 return 0;
151 else
152 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
153}
154
155static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
156{
157 unsigned i;
158
159 /* Enable pflip interrupts */
160 for (i = 0; i < adev->mode_info.num_crtc; i++)
161 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
162}
163
164static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
165{
166 unsigned i;
167
168 /* Disable pflip interrupts */
169 for (i = 0; i < adev->mode_info.num_crtc; i++)
170 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
171}
172
173/**
174 * dce_v8_0_page_flip - pageflip callback.
175 *
176 * @adev: amdgpu_device pointer
177 * @crtc_id: crtc to cleanup pageflip on
178 * @crtc_base: new address of the crtc (GPU MC address)
179 *
180 * Triggers the actual pageflip by updating the primary
181 * surface base address.
182 */
183static void dce_v8_0_page_flip(struct amdgpu_device *adev,
184 int crtc_id, u64 crtc_base, bool async)
185{
186 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
187 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
188
189 /* flip at hsync for async, default is vsync */
190 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
191 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
192 /* update pitch */
193 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
194 fb->pitches[0] / fb->format->cpp[0]);
195 /* update the primary scanout addresses */
196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
197 upper_32_bits(crtc_base));
198 /* writing to the low address triggers the update */
199 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
200 lower_32_bits(crtc_base));
201 /* post the write */
202 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
203}
204
205static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
206 u32 *vbl, u32 *position)
207{
208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
209 return -EINVAL;
210
211 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
212 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
213
214 return 0;
215}
216
217/**
218 * dce_v8_0_hpd_sense - hpd sense callback.
219 *
220 * @adev: amdgpu_device pointer
221 * @hpd: hpd (hotplug detect) pin
222 *
223 * Checks if a digital monitor is connected (evergreen+).
224 * Returns true if connected, false if not connected.
225 */
226static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
227 enum amdgpu_hpd_id hpd)
228{
229 bool connected = false;
230
231 if (hpd >= adev->mode_info.num_hpd)
232 return connected;
233
234 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
235 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
236 connected = true;
237
238 return connected;
239}
240
241/**
242 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
243 *
244 * @adev: amdgpu_device pointer
245 * @hpd: hpd (hotplug detect) pin
246 *
247 * Set the polarity of the hpd pin (evergreen+).
248 */
249static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
250 enum amdgpu_hpd_id hpd)
251{
252 u32 tmp;
253 bool connected = dce_v8_0_hpd_sense(adev, hpd);
254
255 if (hpd >= adev->mode_info.num_hpd)
256 return;
257
258 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
259 if (connected)
260 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
261 else
262 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
263 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
264}
265
266/**
267 * dce_v8_0_hpd_init - hpd setup callback.
268 *
269 * @adev: amdgpu_device pointer
270 *
271 * Setup the hpd pins used by the card (evergreen+).
272 * Enable the pin, set the polarity, and enable the hpd interrupts.
273 */
274static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
275{
276 struct drm_device *dev = adev->ddev;
277 struct drm_connector *connector;
278 u32 tmp;
279
280 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
281 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
282
283 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
284 continue;
285
286 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
287 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
288 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
289
290 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
291 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
292 /* don't try to enable hpd on eDP or LVDS avoid breaking the
293 * aux dp channel on imac and help (but not completely fix)
294 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
295 * also avoid interrupt storms during dpms.
296 */
297 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
298 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
299 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
300 continue;
301 }
302
303 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
304 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
305 }
306}
307
308/**
309 * dce_v8_0_hpd_fini - hpd tear down callback.
310 *
311 * @adev: amdgpu_device pointer
312 *
313 * Tear down the hpd pins used by the card (evergreen+).
314 * Disable the hpd interrupts.
315 */
316static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
317{
318 struct drm_device *dev = adev->ddev;
319 struct drm_connector *connector;
320 u32 tmp;
321
322 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
323 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
324
325 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
326 continue;
327
328 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
329 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
330 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
331
332 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
333 }
334}
335
336static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
337{
338 return mmDC_GPIO_HPD_A;
339}
340
341static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
342{
343 u32 crtc_hung = 0;
344 u32 crtc_status[6];
345 u32 i, j, tmp;
346
347 for (i = 0; i < adev->mode_info.num_crtc; i++) {
348 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
349 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
350 crtc_hung |= (1 << i);
351 }
352 }
353
354 for (j = 0; j < 10; j++) {
355 for (i = 0; i < adev->mode_info.num_crtc; i++) {
356 if (crtc_hung & (1 << i)) {
357 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
358 if (tmp != crtc_status[i])
359 crtc_hung &= ~(1 << i);
360 }
361 }
362 if (crtc_hung == 0)
363 return false;
364 udelay(100);
365 }
366
367 return true;
368}
369
370static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
371 bool render)
372{
373 u32 tmp;
374
375 /* Lockout access through VGA aperture*/
376 tmp = RREG32(mmVGA_HDP_CONTROL);
377 if (render)
378 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
379 else
380 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
381 WREG32(mmVGA_HDP_CONTROL, tmp);
382
383 /* disable VGA render */
384 tmp = RREG32(mmVGA_RENDER_CONTROL);
385 if (render)
386 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
387 else
388 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
389 WREG32(mmVGA_RENDER_CONTROL, tmp);
390}
391
392static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
393{
394 int num_crtc = 0;
395
396 switch (adev->asic_type) {
397 case CHIP_BONAIRE:
398 case CHIP_HAWAII:
399 num_crtc = 6;
400 break;
401 case CHIP_KAVERI:
402 num_crtc = 4;
403 break;
404 case CHIP_KABINI:
405 case CHIP_MULLINS:
406 num_crtc = 2;
407 break;
408 default:
409 num_crtc = 0;
410 }
411 return num_crtc;
412}
413
414void dce_v8_0_disable_dce(struct amdgpu_device *adev)
415{
416 /*Disable VGA render and enabled crtc, if has DCE engine*/
417 if (amdgpu_atombios_has_dce_engine_info(adev)) {
418 u32 tmp;
419 int crtc_enabled, i;
420
421 dce_v8_0_set_vga_render_state(adev, false);
422
423 /*Disable crtc*/
424 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
425 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
426 CRTC_CONTROL, CRTC_MASTER_EN);
427 if (crtc_enabled) {
428 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
429 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
430 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
431 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
432 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
433 }
434 }
435 }
436}
437
438static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
439{
440 struct drm_device *dev = encoder->dev;
441 struct amdgpu_device *adev = dev->dev_private;
442 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
443 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
444 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
445 int bpc = 0;
446 u32 tmp = 0;
447 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
448
449 if (connector) {
450 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
451 bpc = amdgpu_connector_get_monitor_bpc(connector);
452 dither = amdgpu_connector->dither;
453 }
454
455 /* LVDS/eDP FMT is set up by atom */
456 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
457 return;
458
459 /* not needed for analog */
460 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
461 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
462 return;
463
464 if (bpc == 0)
465 return;
466
467 switch (bpc) {
468 case 6:
469 if (dither == AMDGPU_FMT_DITHER_ENABLE)
470 /* XXX sort out optimal dither settings */
471 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
472 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
473 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
474 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
475 else
476 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
477 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
478 break;
479 case 8:
480 if (dither == AMDGPU_FMT_DITHER_ENABLE)
481 /* XXX sort out optimal dither settings */
482 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
483 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
484 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
485 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
486 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
487 else
488 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
489 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
490 break;
491 case 10:
492 if (dither == AMDGPU_FMT_DITHER_ENABLE)
493 /* XXX sort out optimal dither settings */
494 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
495 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
496 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
497 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
498 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
499 else
500 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
501 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
502 break;
503 default:
504 /* not needed */
505 break;
506 }
507
508 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
509}
510
511
512/* display watermark setup */
513/**
514 * dce_v8_0_line_buffer_adjust - Set up the line buffer
515 *
516 * @adev: amdgpu_device pointer
517 * @amdgpu_crtc: the selected display controller
518 * @mode: the current display mode on the selected display
519 * controller
520 *
521 * Setup up the line buffer allocation for
522 * the selected display controller (CIK).
523 * Returns the line buffer size in pixels.
524 */
525static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
526 struct amdgpu_crtc *amdgpu_crtc,
527 struct drm_display_mode *mode)
528{
529 u32 tmp, buffer_alloc, i;
530 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
531 /*
532 * Line Buffer Setup
533 * There are 6 line buffers, one for each display controllers.
534 * There are 3 partitions per LB. Select the number of partitions
535 * to enable based on the display width. For display widths larger
536 * than 4096, you need use to use 2 display controllers and combine
537 * them using the stereo blender.
538 */
539 if (amdgpu_crtc->base.enabled && mode) {
540 if (mode->crtc_hdisplay < 1920) {
541 tmp = 1;
542 buffer_alloc = 2;
543 } else if (mode->crtc_hdisplay < 2560) {
544 tmp = 2;
545 buffer_alloc = 2;
546 } else if (mode->crtc_hdisplay < 4096) {
547 tmp = 0;
548 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
549 } else {
550 DRM_DEBUG_KMS("Mode too big for LB!\n");
551 tmp = 0;
552 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
553 }
554 } else {
555 tmp = 1;
556 buffer_alloc = 0;
557 }
558
559 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
560 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
561 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
562
563 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
564 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
565 for (i = 0; i < adev->usec_timeout; i++) {
566 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
567 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
568 break;
569 udelay(1);
570 }
571
572 if (amdgpu_crtc->base.enabled && mode) {
573 switch (tmp) {
574 case 0:
575 default:
576 return 4096 * 2;
577 case 1:
578 return 1920 * 2;
579 case 2:
580 return 2560 * 2;
581 }
582 }
583
584 /* controller not enabled, so no lb used */
585 return 0;
586}
587
588/**
589 * cik_get_number_of_dram_channels - get the number of dram channels
590 *
591 * @adev: amdgpu_device pointer
592 *
593 * Look up the number of video ram channels (CIK).
594 * Used for display watermark bandwidth calculations
595 * Returns the number of dram channels
596 */
597static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
598{
599 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
600
601 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
602 case 0:
603 default:
604 return 1;
605 case 1:
606 return 2;
607 case 2:
608 return 4;
609 case 3:
610 return 8;
611 case 4:
612 return 3;
613 case 5:
614 return 6;
615 case 6:
616 return 10;
617 case 7:
618 return 12;
619 case 8:
620 return 16;
621 }
622}
623
624struct dce8_wm_params {
625 u32 dram_channels; /* number of dram channels */
626 u32 yclk; /* bandwidth per dram data pin in kHz */
627 u32 sclk; /* engine clock in kHz */
628 u32 disp_clk; /* display clock in kHz */
629 u32 src_width; /* viewport width */
630 u32 active_time; /* active display time in ns */
631 u32 blank_time; /* blank time in ns */
632 bool interlaced; /* mode is interlaced */
633 fixed20_12 vsc; /* vertical scale ratio */
634 u32 num_heads; /* number of active crtcs */
635 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
636 u32 lb_size; /* line buffer allocated to pipe */
637 u32 vtaps; /* vertical scaler taps */
638};
639
640/**
641 * dce_v8_0_dram_bandwidth - get the dram bandwidth
642 *
643 * @wm: watermark calculation data
644 *
645 * Calculate the raw dram bandwidth (CIK).
646 * Used for display watermark bandwidth calculations
647 * Returns the dram bandwidth in MBytes/s
648 */
649static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
650{
651 /* Calculate raw DRAM Bandwidth */
652 fixed20_12 dram_efficiency; /* 0.7 */
653 fixed20_12 yclk, dram_channels, bandwidth;
654 fixed20_12 a;
655
656 a.full = dfixed_const(1000);
657 yclk.full = dfixed_const(wm->yclk);
658 yclk.full = dfixed_div(yclk, a);
659 dram_channels.full = dfixed_const(wm->dram_channels * 4);
660 a.full = dfixed_const(10);
661 dram_efficiency.full = dfixed_const(7);
662 dram_efficiency.full = dfixed_div(dram_efficiency, a);
663 bandwidth.full = dfixed_mul(dram_channels, yclk);
664 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
665
666 return dfixed_trunc(bandwidth);
667}
668
669/**
670 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
671 *
672 * @wm: watermark calculation data
673 *
674 * Calculate the dram bandwidth used for display (CIK).
675 * Used for display watermark bandwidth calculations
676 * Returns the dram bandwidth for display in MBytes/s
677 */
678static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
679{
680 /* Calculate DRAM Bandwidth and the part allocated to display. */
681 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
682 fixed20_12 yclk, dram_channels, bandwidth;
683 fixed20_12 a;
684
685 a.full = dfixed_const(1000);
686 yclk.full = dfixed_const(wm->yclk);
687 yclk.full = dfixed_div(yclk, a);
688 dram_channels.full = dfixed_const(wm->dram_channels * 4);
689 a.full = dfixed_const(10);
690 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
691 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
692 bandwidth.full = dfixed_mul(dram_channels, yclk);
693 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
694
695 return dfixed_trunc(bandwidth);
696}
697
698/**
699 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
700 *
701 * @wm: watermark calculation data
702 *
703 * Calculate the data return bandwidth used for display (CIK).
704 * Used for display watermark bandwidth calculations
705 * Returns the data return bandwidth in MBytes/s
706 */
707static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
708{
709 /* Calculate the display Data return Bandwidth */
710 fixed20_12 return_efficiency; /* 0.8 */
711 fixed20_12 sclk, bandwidth;
712 fixed20_12 a;
713
714 a.full = dfixed_const(1000);
715 sclk.full = dfixed_const(wm->sclk);
716 sclk.full = dfixed_div(sclk, a);
717 a.full = dfixed_const(10);
718 return_efficiency.full = dfixed_const(8);
719 return_efficiency.full = dfixed_div(return_efficiency, a);
720 a.full = dfixed_const(32);
721 bandwidth.full = dfixed_mul(a, sclk);
722 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
723
724 return dfixed_trunc(bandwidth);
725}
726
727/**
728 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
729 *
730 * @wm: watermark calculation data
731 *
732 * Calculate the dmif bandwidth used for display (CIK).
733 * Used for display watermark bandwidth calculations
734 * Returns the dmif bandwidth in MBytes/s
735 */
736static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
737{
738 /* Calculate the DMIF Request Bandwidth */
739 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
740 fixed20_12 disp_clk, bandwidth;
741 fixed20_12 a, b;
742
743 a.full = dfixed_const(1000);
744 disp_clk.full = dfixed_const(wm->disp_clk);
745 disp_clk.full = dfixed_div(disp_clk, a);
746 a.full = dfixed_const(32);
747 b.full = dfixed_mul(a, disp_clk);
748
749 a.full = dfixed_const(10);
750 disp_clk_request_efficiency.full = dfixed_const(8);
751 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
752
753 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
754
755 return dfixed_trunc(bandwidth);
756}
757
758/**
759 * dce_v8_0_available_bandwidth - get the min available bandwidth
760 *
761 * @wm: watermark calculation data
762 *
763 * Calculate the min available bandwidth used for display (CIK).
764 * Used for display watermark bandwidth calculations
765 * Returns the min available bandwidth in MBytes/s
766 */
767static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
768{
769 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
770 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
771 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
772 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
773
774 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
775}
776
777/**
778 * dce_v8_0_average_bandwidth - get the average available bandwidth
779 *
780 * @wm: watermark calculation data
781 *
782 * Calculate the average available bandwidth used for display (CIK).
783 * Used for display watermark bandwidth calculations
784 * Returns the average available bandwidth in MBytes/s
785 */
786static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
787{
788 /* Calculate the display mode Average Bandwidth
789 * DisplayMode should contain the source and destination dimensions,
790 * timing, etc.
791 */
792 fixed20_12 bpp;
793 fixed20_12 line_time;
794 fixed20_12 src_width;
795 fixed20_12 bandwidth;
796 fixed20_12 a;
797
798 a.full = dfixed_const(1000);
799 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
800 line_time.full = dfixed_div(line_time, a);
801 bpp.full = dfixed_const(wm->bytes_per_pixel);
802 src_width.full = dfixed_const(wm->src_width);
803 bandwidth.full = dfixed_mul(src_width, bpp);
804 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
805 bandwidth.full = dfixed_div(bandwidth, line_time);
806
807 return dfixed_trunc(bandwidth);
808}
809
810/**
811 * dce_v8_0_latency_watermark - get the latency watermark
812 *
813 * @wm: watermark calculation data
814 *
815 * Calculate the latency watermark (CIK).
816 * Used for display watermark bandwidth calculations
817 * Returns the latency watermark in ns
818 */
819static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
820{
821 /* First calculate the latency in ns */
822 u32 mc_latency = 2000; /* 2000 ns. */
823 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
824 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
825 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
826 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
827 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
828 (wm->num_heads * cursor_line_pair_return_time);
829 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
830 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
831 u32 tmp, dmif_size = 12288;
832 fixed20_12 a, b, c;
833
834 if (wm->num_heads == 0)
835 return 0;
836
837 a.full = dfixed_const(2);
838 b.full = dfixed_const(1);
839 if ((wm->vsc.full > a.full) ||
840 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
841 (wm->vtaps >= 5) ||
842 ((wm->vsc.full >= a.full) && wm->interlaced))
843 max_src_lines_per_dst_line = 4;
844 else
845 max_src_lines_per_dst_line = 2;
846
847 a.full = dfixed_const(available_bandwidth);
848 b.full = dfixed_const(wm->num_heads);
849 a.full = dfixed_div(a, b);
850 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
851 tmp = min(dfixed_trunc(a), tmp);
852
853 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
854
855 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
856 b.full = dfixed_const(1000);
857 c.full = dfixed_const(lb_fill_bw);
858 b.full = dfixed_div(c, b);
859 a.full = dfixed_div(a, b);
860 line_fill_time = dfixed_trunc(a);
861
862 if (line_fill_time < wm->active_time)
863 return latency;
864 else
865 return latency + (line_fill_time - wm->active_time);
866
867}
868
869/**
870 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
871 * average and available dram bandwidth
872 *
873 * @wm: watermark calculation data
874 *
875 * Check if the display average bandwidth fits in the display
876 * dram bandwidth (CIK).
877 * Used for display watermark bandwidth calculations
878 * Returns true if the display fits, false if not.
879 */
880static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
881{
882 if (dce_v8_0_average_bandwidth(wm) <=
883 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
884 return true;
885 else
886 return false;
887}
888
889/**
890 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
891 * average and available bandwidth
892 *
893 * @wm: watermark calculation data
894 *
895 * Check if the display average bandwidth fits in the display
896 * available bandwidth (CIK).
897 * Used for display watermark bandwidth calculations
898 * Returns true if the display fits, false if not.
899 */
900static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
901{
902 if (dce_v8_0_average_bandwidth(wm) <=
903 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
904 return true;
905 else
906 return false;
907}
908
909/**
910 * dce_v8_0_check_latency_hiding - check latency hiding
911 *
912 * @wm: watermark calculation data
913 *
914 * Check latency hiding (CIK).
915 * Used for display watermark bandwidth calculations
916 * Returns true if the display fits, false if not.
917 */
918static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
919{
920 u32 lb_partitions = wm->lb_size / wm->src_width;
921 u32 line_time = wm->active_time + wm->blank_time;
922 u32 latency_tolerant_lines;
923 u32 latency_hiding;
924 fixed20_12 a;
925
926 a.full = dfixed_const(1);
927 if (wm->vsc.full > a.full)
928 latency_tolerant_lines = 1;
929 else {
930 if (lb_partitions <= (wm->vtaps + 1))
931 latency_tolerant_lines = 1;
932 else
933 latency_tolerant_lines = 2;
934 }
935
936 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
937
938 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
939 return true;
940 else
941 return false;
942}
943
944/**
945 * dce_v8_0_program_watermarks - program display watermarks
946 *
947 * @adev: amdgpu_device pointer
948 * @amdgpu_crtc: the selected display controller
949 * @lb_size: line buffer size
950 * @num_heads: number of display controllers in use
951 *
952 * Calculate and program the display watermarks for the
953 * selected display controller (CIK).
954 */
955static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
956 struct amdgpu_crtc *amdgpu_crtc,
957 u32 lb_size, u32 num_heads)
958{
959 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
960 struct dce8_wm_params wm_low, wm_high;
961 u32 active_time;
962 u32 line_time = 0;
963 u32 latency_watermark_a = 0, latency_watermark_b = 0;
964 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
965
966 if (amdgpu_crtc->base.enabled && num_heads && mode) {
967 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
968 (u32)mode->clock);
969 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
970 (u32)mode->clock);
971 line_time = min(line_time, (u32)65535);
972
973 /* watermark for high clocks */
974 if (adev->pm.dpm_enabled) {
975 wm_high.yclk =
976 amdgpu_dpm_get_mclk(adev, false) * 10;
977 wm_high.sclk =
978 amdgpu_dpm_get_sclk(adev, false) * 10;
979 } else {
980 wm_high.yclk = adev->pm.current_mclk * 10;
981 wm_high.sclk = adev->pm.current_sclk * 10;
982 }
983
984 wm_high.disp_clk = mode->clock;
985 wm_high.src_width = mode->crtc_hdisplay;
986 wm_high.active_time = active_time;
987 wm_high.blank_time = line_time - wm_high.active_time;
988 wm_high.interlaced = false;
989 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
990 wm_high.interlaced = true;
991 wm_high.vsc = amdgpu_crtc->vsc;
992 wm_high.vtaps = 1;
993 if (amdgpu_crtc->rmx_type != RMX_OFF)
994 wm_high.vtaps = 2;
995 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
996 wm_high.lb_size = lb_size;
997 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
998 wm_high.num_heads = num_heads;
999
1000 /* set for high clocks */
1001 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1002
1003 /* possibly force display priority to high */
1004 /* should really do this at mode validation time... */
1005 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1006 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1007 !dce_v8_0_check_latency_hiding(&wm_high) ||
1008 (adev->mode_info.disp_priority == 2)) {
1009 DRM_DEBUG_KMS("force priority to high\n");
1010 }
1011
1012 /* watermark for low clocks */
1013 if (adev->pm.dpm_enabled) {
1014 wm_low.yclk =
1015 amdgpu_dpm_get_mclk(adev, true) * 10;
1016 wm_low.sclk =
1017 amdgpu_dpm_get_sclk(adev, true) * 10;
1018 } else {
1019 wm_low.yclk = adev->pm.current_mclk * 10;
1020 wm_low.sclk = adev->pm.current_sclk * 10;
1021 }
1022
1023 wm_low.disp_clk = mode->clock;
1024 wm_low.src_width = mode->crtc_hdisplay;
1025 wm_low.active_time = active_time;
1026 wm_low.blank_time = line_time - wm_low.active_time;
1027 wm_low.interlaced = false;
1028 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1029 wm_low.interlaced = true;
1030 wm_low.vsc = amdgpu_crtc->vsc;
1031 wm_low.vtaps = 1;
1032 if (amdgpu_crtc->rmx_type != RMX_OFF)
1033 wm_low.vtaps = 2;
1034 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1035 wm_low.lb_size = lb_size;
1036 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1037 wm_low.num_heads = num_heads;
1038
1039 /* set for low clocks */
1040 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1041
1042 /* possibly force display priority to high */
1043 /* should really do this at mode validation time... */
1044 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1045 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1046 !dce_v8_0_check_latency_hiding(&wm_low) ||
1047 (adev->mode_info.disp_priority == 2)) {
1048 DRM_DEBUG_KMS("force priority to high\n");
1049 }
1050 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1051 }
1052
1053 /* select wm A */
1054 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1055 tmp = wm_mask;
1056 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1057 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1058 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1059 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1060 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1061 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1062 /* select wm B */
1063 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1064 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1065 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1066 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1067 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1068 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1069 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1070 /* restore original selection */
1071 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1072
1073 /* save values for DPM */
1074 amdgpu_crtc->line_time = line_time;
1075 amdgpu_crtc->wm_high = latency_watermark_a;
1076 amdgpu_crtc->wm_low = latency_watermark_b;
1077 /* Save number of lines the linebuffer leads before the scanout */
1078 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1079}
1080
1081/**
1082 * dce_v8_0_bandwidth_update - program display watermarks
1083 *
1084 * @adev: amdgpu_device pointer
1085 *
1086 * Calculate and program the display watermarks and line
1087 * buffer allocation (CIK).
1088 */
1089static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1090{
1091 struct drm_display_mode *mode = NULL;
1092 u32 num_heads = 0, lb_size;
1093 int i;
1094
1095 amdgpu_display_update_priority(adev);
1096
1097 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1098 if (adev->mode_info.crtcs[i]->base.enabled)
1099 num_heads++;
1100 }
1101 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1102 mode = &adev->mode_info.crtcs[i]->base.mode;
1103 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1104 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1105 lb_size, num_heads);
1106 }
1107}
1108
1109static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1110{
1111 int i;
1112 u32 offset, tmp;
1113
1114 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1115 offset = adev->mode_info.audio.pin[i].offset;
1116 tmp = RREG32_AUDIO_ENDPT(offset,
1117 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1118 if (((tmp &
1119 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1120 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1121 adev->mode_info.audio.pin[i].connected = false;
1122 else
1123 adev->mode_info.audio.pin[i].connected = true;
1124 }
1125}
1126
1127static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1128{
1129 int i;
1130
1131 dce_v8_0_audio_get_connected_pins(adev);
1132
1133 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1134 if (adev->mode_info.audio.pin[i].connected)
1135 return &adev->mode_info.audio.pin[i];
1136 }
1137 DRM_ERROR("No connected audio pins found!\n");
1138 return NULL;
1139}
1140
1141static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1142{
1143 struct amdgpu_device *adev = encoder->dev->dev_private;
1144 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1145 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1146 u32 offset;
1147
1148 if (!dig || !dig->afmt || !dig->afmt->pin)
1149 return;
1150
1151 offset = dig->afmt->offset;
1152
1153 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1154 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1155}
1156
1157static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1158 struct drm_display_mode *mode)
1159{
1160 struct amdgpu_device *adev = encoder->dev->dev_private;
1161 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1162 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1163 struct drm_connector *connector;
1164 struct amdgpu_connector *amdgpu_connector = NULL;
1165 u32 tmp = 0, offset;
1166
1167 if (!dig || !dig->afmt || !dig->afmt->pin)
1168 return;
1169
1170 offset = dig->afmt->pin->offset;
1171
1172 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1173 if (connector->encoder == encoder) {
1174 amdgpu_connector = to_amdgpu_connector(connector);
1175 break;
1176 }
1177 }
1178
1179 if (!amdgpu_connector) {
1180 DRM_ERROR("Couldn't find encoder's connector\n");
1181 return;
1182 }
1183
1184 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1185 if (connector->latency_present[1])
1186 tmp =
1187 (connector->video_latency[1] <<
1188 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1189 (connector->audio_latency[1] <<
1190 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1191 else
1192 tmp =
1193 (0 <<
1194 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1195 (0 <<
1196 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1197 } else {
1198 if (connector->latency_present[0])
1199 tmp =
1200 (connector->video_latency[0] <<
1201 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1202 (connector->audio_latency[0] <<
1203 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1204 else
1205 tmp =
1206 (0 <<
1207 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1208 (0 <<
1209 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1210
1211 }
1212 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1213}
1214
1215static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1216{
1217 struct amdgpu_device *adev = encoder->dev->dev_private;
1218 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1219 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1220 struct drm_connector *connector;
1221 struct amdgpu_connector *amdgpu_connector = NULL;
1222 u32 offset, tmp;
1223 u8 *sadb = NULL;
1224 int sad_count;
1225
1226 if (!dig || !dig->afmt || !dig->afmt->pin)
1227 return;
1228
1229 offset = dig->afmt->pin->offset;
1230
1231 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1232 if (connector->encoder == encoder) {
1233 amdgpu_connector = to_amdgpu_connector(connector);
1234 break;
1235 }
1236 }
1237
1238 if (!amdgpu_connector) {
1239 DRM_ERROR("Couldn't find encoder's connector\n");
1240 return;
1241 }
1242
1243 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1244 if (sad_count < 0) {
1245 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1246 sad_count = 0;
1247 }
1248
1249 /* program the speaker allocation */
1250 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1251 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1252 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1253 /* set HDMI mode */
1254 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1255 if (sad_count)
1256 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1257 else
1258 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1259 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1260
1261 kfree(sadb);
1262}
1263
1264static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1265{
1266 struct amdgpu_device *adev = encoder->dev->dev_private;
1267 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1268 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1269 u32 offset;
1270 struct drm_connector *connector;
1271 struct amdgpu_connector *amdgpu_connector = NULL;
1272 struct cea_sad *sads;
1273 int i, sad_count;
1274
1275 static const u16 eld_reg_to_type[][2] = {
1276 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1277 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1278 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1279 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1280 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1281 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1282 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1283 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1284 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1285 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1286 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1287 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1288 };
1289
1290 if (!dig || !dig->afmt || !dig->afmt->pin)
1291 return;
1292
1293 offset = dig->afmt->pin->offset;
1294
1295 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1296 if (connector->encoder == encoder) {
1297 amdgpu_connector = to_amdgpu_connector(connector);
1298 break;
1299 }
1300 }
1301
1302 if (!amdgpu_connector) {
1303 DRM_ERROR("Couldn't find encoder's connector\n");
1304 return;
1305 }
1306
1307 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1308 if (sad_count <= 0) {
1309 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1310 return;
1311 }
1312 BUG_ON(!sads);
1313
1314 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1315 u32 value = 0;
1316 u8 stereo_freqs = 0;
1317 int max_channels = -1;
1318 int j;
1319
1320 for (j = 0; j < sad_count; j++) {
1321 struct cea_sad *sad = &sads[j];
1322
1323 if (sad->format == eld_reg_to_type[i][1]) {
1324 if (sad->channels > max_channels) {
1325 value = (sad->channels <<
1326 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1327 (sad->byte2 <<
1328 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1329 (sad->freq <<
1330 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1331 max_channels = sad->channels;
1332 }
1333
1334 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1335 stereo_freqs |= sad->freq;
1336 else
1337 break;
1338 }
1339 }
1340
1341 value |= (stereo_freqs <<
1342 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1343
1344 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1345 }
1346
1347 kfree(sads);
1348}
1349
1350static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1351 struct amdgpu_audio_pin *pin,
1352 bool enable)
1353{
1354 if (!pin)
1355 return;
1356
1357 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1358 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1359}
1360
1361static const u32 pin_offsets[7] =
1362{
1363 (0x1780 - 0x1780),
1364 (0x1786 - 0x1780),
1365 (0x178c - 0x1780),
1366 (0x1792 - 0x1780),
1367 (0x1798 - 0x1780),
1368 (0x179d - 0x1780),
1369 (0x17a4 - 0x1780),
1370};
1371
1372static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1373{
1374 int i;
1375
1376 if (!amdgpu_audio)
1377 return 0;
1378
1379 adev->mode_info.audio.enabled = true;
1380
1381 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1382 adev->mode_info.audio.num_pins = 7;
1383 else if ((adev->asic_type == CHIP_KABINI) ||
1384 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1385 adev->mode_info.audio.num_pins = 3;
1386 else if ((adev->asic_type == CHIP_BONAIRE) ||
1387 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1388 adev->mode_info.audio.num_pins = 7;
1389 else
1390 adev->mode_info.audio.num_pins = 3;
1391
1392 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1393 adev->mode_info.audio.pin[i].channels = -1;
1394 adev->mode_info.audio.pin[i].rate = -1;
1395 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1396 adev->mode_info.audio.pin[i].status_bits = 0;
1397 adev->mode_info.audio.pin[i].category_code = 0;
1398 adev->mode_info.audio.pin[i].connected = false;
1399 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1400 adev->mode_info.audio.pin[i].id = i;
1401 /* disable audio. it will be set up later */
1402 /* XXX remove once we switch to ip funcs */
1403 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1404 }
1405
1406 return 0;
1407}
1408
1409static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1410{
1411 int i;
1412
1413 if (!amdgpu_audio)
1414 return;
1415
1416 if (!adev->mode_info.audio.enabled)
1417 return;
1418
1419 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1420 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1421
1422 adev->mode_info.audio.enabled = false;
1423}
1424
1425/*
1426 * update the N and CTS parameters for a given pixel clock rate
1427 */
1428static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1429{
1430 struct drm_device *dev = encoder->dev;
1431 struct amdgpu_device *adev = dev->dev_private;
1432 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1433 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1434 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1435 uint32_t offset = dig->afmt->offset;
1436
1437 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1438 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1439
1440 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1441 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1442
1443 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1444 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1445}
1446
1447/*
1448 * build a HDMI Video Info Frame
1449 */
1450static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1451 void *buffer, size_t size)
1452{
1453 struct drm_device *dev = encoder->dev;
1454 struct amdgpu_device *adev = dev->dev_private;
1455 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1456 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1457 uint32_t offset = dig->afmt->offset;
1458 uint8_t *frame = buffer + 3;
1459 uint8_t *header = buffer;
1460
1461 WREG32(mmAFMT_AVI_INFO0 + offset,
1462 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1463 WREG32(mmAFMT_AVI_INFO1 + offset,
1464 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1465 WREG32(mmAFMT_AVI_INFO2 + offset,
1466 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1467 WREG32(mmAFMT_AVI_INFO3 + offset,
1468 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1469}
1470
1471static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1472{
1473 struct drm_device *dev = encoder->dev;
1474 struct amdgpu_device *adev = dev->dev_private;
1475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1476 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1477 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1478 u32 dto_phase = 24 * 1000;
1479 u32 dto_modulo = clock;
1480
1481 if (!dig || !dig->afmt)
1482 return;
1483
1484 /* XXX two dtos; generally use dto0 for hdmi */
1485 /* Express [24MHz / target pixel clock] as an exact rational
1486 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1487 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1488 */
1489 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1490 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1491 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1492}
1493
1494/*
1495 * update the info frames with the data from the current display mode
1496 */
1497static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1498 struct drm_display_mode *mode)
1499{
1500 struct drm_device *dev = encoder->dev;
1501 struct amdgpu_device *adev = dev->dev_private;
1502 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1503 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1504 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1505 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1506 struct hdmi_avi_infoframe frame;
1507 uint32_t offset, val;
1508 ssize_t err;
1509 int bpc = 8;
1510
1511 if (!dig || !dig->afmt)
1512 return;
1513
1514 /* Silent, r600_hdmi_enable will raise WARN for us */
1515 if (!dig->afmt->enabled)
1516 return;
1517
1518 offset = dig->afmt->offset;
1519
1520 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1521 if (encoder->crtc) {
1522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1523 bpc = amdgpu_crtc->bpc;
1524 }
1525
1526 /* disable audio prior to setting up hw */
1527 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1528 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1529
1530 dce_v8_0_audio_set_dto(encoder, mode->clock);
1531
1532 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1533 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1534
1535 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1536
1537 val = RREG32(mmHDMI_CONTROL + offset);
1538 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1539 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1540
1541 switch (bpc) {
1542 case 0:
1543 case 6:
1544 case 8:
1545 case 16:
1546 default:
1547 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1548 connector->name, bpc);
1549 break;
1550 case 10:
1551 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1552 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1553 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1554 connector->name);
1555 break;
1556 case 12:
1557 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1558 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1559 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1560 connector->name);
1561 break;
1562 }
1563
1564 WREG32(mmHDMI_CONTROL + offset, val);
1565
1566 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1567 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1568 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1569 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1570
1571 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1572 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1573 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1574
1575 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1576 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1577
1578 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1579 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1580
1581 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1582
1583 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1584 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1585 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1586
1587 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1588 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1589
1590 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1591
1592 if (bpc > 8)
1593 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1594 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1595 else
1596 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1597 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1598 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1599
1600 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1601
1602 WREG32(mmAFMT_60958_0 + offset,
1603 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1604
1605 WREG32(mmAFMT_60958_1 + offset,
1606 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1607
1608 WREG32(mmAFMT_60958_2 + offset,
1609 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1610 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1611 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1612 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1613 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1614 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1615
1616 dce_v8_0_audio_write_speaker_allocation(encoder);
1617
1618
1619 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1620 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1621
1622 dce_v8_0_afmt_audio_select_pin(encoder);
1623 dce_v8_0_audio_write_sad_regs(encoder);
1624 dce_v8_0_audio_write_latency_fields(encoder, mode);
1625
1626 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1627 if (err < 0) {
1628 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1629 return;
1630 }
1631
1632 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1633 if (err < 0) {
1634 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1635 return;
1636 }
1637
1638 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1639
1640 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1641 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1642 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1643
1644 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1645 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1646 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1647
1648 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1649 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1650
1651 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1652 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1653 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1654 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1655
1656 /* enable audio after setting up hw */
1657 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1658}
1659
1660static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1661{
1662 struct drm_device *dev = encoder->dev;
1663 struct amdgpu_device *adev = dev->dev_private;
1664 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1665 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1666
1667 if (!dig || !dig->afmt)
1668 return;
1669
1670 /* Silent, r600_hdmi_enable will raise WARN for us */
1671 if (enable && dig->afmt->enabled)
1672 return;
1673 if (!enable && !dig->afmt->enabled)
1674 return;
1675
1676 if (!enable && dig->afmt->pin) {
1677 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1678 dig->afmt->pin = NULL;
1679 }
1680
1681 dig->afmt->enabled = enable;
1682
1683 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1684 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1685}
1686
1687static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1688{
1689 int i;
1690
1691 for (i = 0; i < adev->mode_info.num_dig; i++)
1692 adev->mode_info.afmt[i] = NULL;
1693
1694 /* DCE8 has audio blocks tied to DIG encoders */
1695 for (i = 0; i < adev->mode_info.num_dig; i++) {
1696 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1697 if (adev->mode_info.afmt[i]) {
1698 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1699 adev->mode_info.afmt[i]->id = i;
1700 } else {
1701 int j;
1702 for (j = 0; j < i; j++) {
1703 kfree(adev->mode_info.afmt[j]);
1704 adev->mode_info.afmt[j] = NULL;
1705 }
1706 return -ENOMEM;
1707 }
1708 }
1709 return 0;
1710}
1711
1712static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1713{
1714 int i;
1715
1716 for (i = 0; i < adev->mode_info.num_dig; i++) {
1717 kfree(adev->mode_info.afmt[i]);
1718 adev->mode_info.afmt[i] = NULL;
1719 }
1720}
1721
1722static const u32 vga_control_regs[6] =
1723{
1724 mmD1VGA_CONTROL,
1725 mmD2VGA_CONTROL,
1726 mmD3VGA_CONTROL,
1727 mmD4VGA_CONTROL,
1728 mmD5VGA_CONTROL,
1729 mmD6VGA_CONTROL,
1730};
1731
1732static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1733{
1734 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1735 struct drm_device *dev = crtc->dev;
1736 struct amdgpu_device *adev = dev->dev_private;
1737 u32 vga_control;
1738
1739 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1740 if (enable)
1741 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1742 else
1743 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1744}
1745
1746static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1747{
1748 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1749 struct drm_device *dev = crtc->dev;
1750 struct amdgpu_device *adev = dev->dev_private;
1751
1752 if (enable)
1753 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1754 else
1755 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1756}
1757
1758static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1759 struct drm_framebuffer *fb,
1760 int x, int y, int atomic)
1761{
1762 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1763 struct drm_device *dev = crtc->dev;
1764 struct amdgpu_device *adev = dev->dev_private;
1765 struct drm_framebuffer *target_fb;
1766 struct drm_gem_object *obj;
1767 struct amdgpu_bo *abo;
1768 uint64_t fb_location, tiling_flags;
1769 uint32_t fb_format, fb_pitch_pixels;
1770 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1771 u32 pipe_config;
1772 u32 viewport_w, viewport_h;
1773 int r;
1774 bool bypass_lut = false;
1775 struct drm_format_name_buf format_name;
1776
1777 /* no fb bound */
1778 if (!atomic && !crtc->primary->fb) {
1779 DRM_DEBUG_KMS("No FB bound\n");
1780 return 0;
1781 }
1782
1783 if (atomic)
1784 target_fb = fb;
1785 else
1786 target_fb = crtc->primary->fb;
1787
1788 /* If atomic, assume fb object is pinned & idle & fenced and
1789 * just update base pointers
1790 */
1791 obj = target_fb->obj[0];
1792 abo = gem_to_amdgpu_bo(obj);
1793 r = amdgpu_bo_reserve(abo, false);
1794 if (unlikely(r != 0))
1795 return r;
1796
1797 if (!atomic) {
1798 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1799 if (unlikely(r != 0)) {
1800 amdgpu_bo_unreserve(abo);
1801 return -EINVAL;
1802 }
1803 }
1804 fb_location = amdgpu_bo_gpu_offset(abo);
1805
1806 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1807 amdgpu_bo_unreserve(abo);
1808
1809 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1810
1811 switch (target_fb->format->format) {
1812 case DRM_FORMAT_C8:
1813 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1814 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1815 break;
1816 case DRM_FORMAT_XRGB4444:
1817 case DRM_FORMAT_ARGB4444:
1818 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1819 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1820#ifdef __BIG_ENDIAN
1821 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1822#endif
1823 break;
1824 case DRM_FORMAT_XRGB1555:
1825 case DRM_FORMAT_ARGB1555:
1826 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1827 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1828#ifdef __BIG_ENDIAN
1829 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1830#endif
1831 break;
1832 case DRM_FORMAT_BGRX5551:
1833 case DRM_FORMAT_BGRA5551:
1834 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1835 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1836#ifdef __BIG_ENDIAN
1837 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1838#endif
1839 break;
1840 case DRM_FORMAT_RGB565:
1841 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1842 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1843#ifdef __BIG_ENDIAN
1844 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1845#endif
1846 break;
1847 case DRM_FORMAT_XRGB8888:
1848 case DRM_FORMAT_ARGB8888:
1849 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1850 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1851#ifdef __BIG_ENDIAN
1852 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1853#endif
1854 break;
1855 case DRM_FORMAT_XRGB2101010:
1856 case DRM_FORMAT_ARGB2101010:
1857 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1858 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1859#ifdef __BIG_ENDIAN
1860 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1861#endif
1862 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1863 bypass_lut = true;
1864 break;
1865 case DRM_FORMAT_BGRX1010102:
1866 case DRM_FORMAT_BGRA1010102:
1867 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1868 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1869#ifdef __BIG_ENDIAN
1870 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1871#endif
1872 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1873 bypass_lut = true;
1874 break;
1875 case DRM_FORMAT_XBGR8888:
1876 case DRM_FORMAT_ABGR8888:
1877 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1878 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1879 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1880 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1881#ifdef __BIG_ENDIAN
1882 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1883#endif
1884 break;
1885 default:
1886 DRM_ERROR("Unsupported screen format %s\n",
1887 drm_get_format_name(target_fb->format->format, &format_name));
1888 return -EINVAL;
1889 }
1890
1891 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1892 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1893
1894 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1895 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1896 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1897 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1898 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1899
1900 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1901 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1902 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1903 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1904 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1905 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1906 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1907 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1908 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1909 }
1910
1911 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1912
1913 dce_v8_0_vga_enable(crtc, false);
1914
1915 /* Make sure surface address is updated at vertical blank rather than
1916 * horizontal blank
1917 */
1918 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1919
1920 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1921 upper_32_bits(fb_location));
1922 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1923 upper_32_bits(fb_location));
1924 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1925 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1926 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1927 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1928 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1929 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1930
1931 /*
1932 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1933 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1934 * retain the full precision throughout the pipeline.
1935 */
1936 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1937 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1938 ~LUT_10BIT_BYPASS_EN);
1939
1940 if (bypass_lut)
1941 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1942
1943 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1944 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1945 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1946 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1947 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1948 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1949
1950 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1951 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1952
1953 dce_v8_0_grph_enable(crtc, true);
1954
1955 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1956 target_fb->height);
1957
1958 x &= ~3;
1959 y &= ~1;
1960 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1961 (x << 16) | y);
1962 viewport_w = crtc->mode.hdisplay;
1963 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1964 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1965 (viewport_w << 16) | viewport_h);
1966
1967 /* set pageflip to happen anywhere in vblank interval */
1968 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1969
1970 if (!atomic && fb && fb != crtc->primary->fb) {
1971 abo = gem_to_amdgpu_bo(fb->obj[0]);
1972 r = amdgpu_bo_reserve(abo, true);
1973 if (unlikely(r != 0))
1974 return r;
1975 amdgpu_bo_unpin(abo);
1976 amdgpu_bo_unreserve(abo);
1977 }
1978
1979 /* Bytes per pixel may have changed */
1980 dce_v8_0_bandwidth_update(adev);
1981
1982 return 0;
1983}
1984
1985static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
1986 struct drm_display_mode *mode)
1987{
1988 struct drm_device *dev = crtc->dev;
1989 struct amdgpu_device *adev = dev->dev_private;
1990 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1991
1992 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1993 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
1994 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
1995 else
1996 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1997}
1998
1999static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2000{
2001 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2002 struct drm_device *dev = crtc->dev;
2003 struct amdgpu_device *adev = dev->dev_private;
2004 u16 *r, *g, *b;
2005 int i;
2006
2007 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2008
2009 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2010 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2011 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2012 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2013 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2014 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2015 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2016 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2017 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2018 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2019
2020 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2021
2022 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2023 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2024 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2025
2026 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2027 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2028 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2029
2030 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2031 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2032
2033 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2034 r = crtc->gamma_store;
2035 g = r + crtc->gamma_size;
2036 b = g + crtc->gamma_size;
2037 for (i = 0; i < 256; i++) {
2038 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2039 ((*r++ & 0xffc0) << 14) |
2040 ((*g++ & 0xffc0) << 4) |
2041 (*b++ >> 6));
2042 }
2043
2044 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2045 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2046 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2047 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2048 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2049 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2050 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2051 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2052 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2053 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2054 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2055 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2056 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2057 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2058 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2059 /* XXX this only needs to be programmed once per crtc at startup,
2060 * not sure where the best place for it is
2061 */
2062 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2063 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2064}
2065
2066static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2067{
2068 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2069 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2070
2071 switch (amdgpu_encoder->encoder_id) {
2072 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2073 if (dig->linkb)
2074 return 1;
2075 else
2076 return 0;
2077 break;
2078 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2079 if (dig->linkb)
2080 return 3;
2081 else
2082 return 2;
2083 break;
2084 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2085 if (dig->linkb)
2086 return 5;
2087 else
2088 return 4;
2089 break;
2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2091 return 6;
2092 break;
2093 default:
2094 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2095 return 0;
2096 }
2097}
2098
2099/**
2100 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2101 *
2102 * @crtc: drm crtc
2103 *
2104 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2105 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2106 * monitors a dedicated PPLL must be used. If a particular board has
2107 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2108 * as there is no need to program the PLL itself. If we are not able to
2109 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2110 * avoid messing up an existing monitor.
2111 *
2112 * Asic specific PLL information
2113 *
2114 * DCE 8.x
2115 * KB/KV
2116 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2117 * CI
2118 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2119 *
2120 */
2121static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2122{
2123 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2124 struct drm_device *dev = crtc->dev;
2125 struct amdgpu_device *adev = dev->dev_private;
2126 u32 pll_in_use;
2127 int pll;
2128
2129 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2130 if (adev->clock.dp_extclk)
2131 /* skip PPLL programming if using ext clock */
2132 return ATOM_PPLL_INVALID;
2133 else {
2134 /* use the same PPLL for all DP monitors */
2135 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2136 if (pll != ATOM_PPLL_INVALID)
2137 return pll;
2138 }
2139 } else {
2140 /* use the same PPLL for all monitors with the same clock */
2141 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2142 if (pll != ATOM_PPLL_INVALID)
2143 return pll;
2144 }
2145 /* otherwise, pick one of the plls */
2146 if ((adev->asic_type == CHIP_KABINI) ||
2147 (adev->asic_type == CHIP_MULLINS)) {
2148 /* KB/ML has PPLL1 and PPLL2 */
2149 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2150 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2151 return ATOM_PPLL2;
2152 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2153 return ATOM_PPLL1;
2154 DRM_ERROR("unable to allocate a PPLL\n");
2155 return ATOM_PPLL_INVALID;
2156 } else {
2157 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2158 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2159 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2160 return ATOM_PPLL2;
2161 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2162 return ATOM_PPLL1;
2163 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2164 return ATOM_PPLL0;
2165 DRM_ERROR("unable to allocate a PPLL\n");
2166 return ATOM_PPLL_INVALID;
2167 }
2168 return ATOM_PPLL_INVALID;
2169}
2170
2171static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2172{
2173 struct amdgpu_device *adev = crtc->dev->dev_private;
2174 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2175 uint32_t cur_lock;
2176
2177 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2178 if (lock)
2179 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2180 else
2181 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2182 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2183}
2184
2185static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2186{
2187 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2188 struct amdgpu_device *adev = crtc->dev->dev_private;
2189
2190 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2191 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2192 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2193}
2194
2195static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2196{
2197 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2198 struct amdgpu_device *adev = crtc->dev->dev_private;
2199
2200 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2201 upper_32_bits(amdgpu_crtc->cursor_addr));
2202 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2203 lower_32_bits(amdgpu_crtc->cursor_addr));
2204
2205 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2206 CUR_CONTROL__CURSOR_EN_MASK |
2207 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2208 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2209}
2210
2211static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2212 int x, int y)
2213{
2214 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2215 struct amdgpu_device *adev = crtc->dev->dev_private;
2216 int xorigin = 0, yorigin = 0;
2217
2218 amdgpu_crtc->cursor_x = x;
2219 amdgpu_crtc->cursor_y = y;
2220
2221 /* avivo cursor are offset into the total surface */
2222 x += crtc->x;
2223 y += crtc->y;
2224 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2225
2226 if (x < 0) {
2227 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2228 x = 0;
2229 }
2230 if (y < 0) {
2231 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2232 y = 0;
2233 }
2234
2235 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2236 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2237 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2238 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2239
2240 return 0;
2241}
2242
2243static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2244 int x, int y)
2245{
2246 int ret;
2247
2248 dce_v8_0_lock_cursor(crtc, true);
2249 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2250 dce_v8_0_lock_cursor(crtc, false);
2251
2252 return ret;
2253}
2254
2255static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2256 struct drm_file *file_priv,
2257 uint32_t handle,
2258 uint32_t width,
2259 uint32_t height,
2260 int32_t hot_x,
2261 int32_t hot_y)
2262{
2263 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2264 struct drm_gem_object *obj;
2265 struct amdgpu_bo *aobj;
2266 int ret;
2267
2268 if (!handle) {
2269 /* turn off cursor */
2270 dce_v8_0_hide_cursor(crtc);
2271 obj = NULL;
2272 goto unpin;
2273 }
2274
2275 if ((width > amdgpu_crtc->max_cursor_width) ||
2276 (height > amdgpu_crtc->max_cursor_height)) {
2277 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2278 return -EINVAL;
2279 }
2280
2281 obj = drm_gem_object_lookup(file_priv, handle);
2282 if (!obj) {
2283 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2284 return -ENOENT;
2285 }
2286
2287 aobj = gem_to_amdgpu_bo(obj);
2288 ret = amdgpu_bo_reserve(aobj, false);
2289 if (ret != 0) {
2290 drm_gem_object_put_unlocked(obj);
2291 return ret;
2292 }
2293
2294 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2295 amdgpu_bo_unreserve(aobj);
2296 if (ret) {
2297 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2298 drm_gem_object_put_unlocked(obj);
2299 return ret;
2300 }
2301 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2302
2303 dce_v8_0_lock_cursor(crtc, true);
2304
2305 if (width != amdgpu_crtc->cursor_width ||
2306 height != amdgpu_crtc->cursor_height ||
2307 hot_x != amdgpu_crtc->cursor_hot_x ||
2308 hot_y != amdgpu_crtc->cursor_hot_y) {
2309 int x, y;
2310
2311 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2312 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2313
2314 dce_v8_0_cursor_move_locked(crtc, x, y);
2315
2316 amdgpu_crtc->cursor_width = width;
2317 amdgpu_crtc->cursor_height = height;
2318 amdgpu_crtc->cursor_hot_x = hot_x;
2319 amdgpu_crtc->cursor_hot_y = hot_y;
2320 }
2321
2322 dce_v8_0_show_cursor(crtc);
2323 dce_v8_0_lock_cursor(crtc, false);
2324
2325unpin:
2326 if (amdgpu_crtc->cursor_bo) {
2327 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2328 ret = amdgpu_bo_reserve(aobj, true);
2329 if (likely(ret == 0)) {
2330 amdgpu_bo_unpin(aobj);
2331 amdgpu_bo_unreserve(aobj);
2332 }
2333 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2334 }
2335
2336 amdgpu_crtc->cursor_bo = obj;
2337 return 0;
2338}
2339
2340static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2341{
2342 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2343
2344 if (amdgpu_crtc->cursor_bo) {
2345 dce_v8_0_lock_cursor(crtc, true);
2346
2347 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2348 amdgpu_crtc->cursor_y);
2349
2350 dce_v8_0_show_cursor(crtc);
2351
2352 dce_v8_0_lock_cursor(crtc, false);
2353 }
2354}
2355
2356static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2357 u16 *blue, uint32_t size,
2358 struct drm_modeset_acquire_ctx *ctx)
2359{
2360 dce_v8_0_crtc_load_lut(crtc);
2361
2362 return 0;
2363}
2364
2365static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2366{
2367 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2368
2369 drm_crtc_cleanup(crtc);
2370 kfree(amdgpu_crtc);
2371}
2372
2373static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2374 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2375 .cursor_move = dce_v8_0_crtc_cursor_move,
2376 .gamma_set = dce_v8_0_crtc_gamma_set,
2377 .set_config = amdgpu_display_crtc_set_config,
2378 .destroy = dce_v8_0_crtc_destroy,
2379 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2380};
2381
2382static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2383{
2384 struct drm_device *dev = crtc->dev;
2385 struct amdgpu_device *adev = dev->dev_private;
2386 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2387 unsigned type;
2388
2389 switch (mode) {
2390 case DRM_MODE_DPMS_ON:
2391 amdgpu_crtc->enabled = true;
2392 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2393 dce_v8_0_vga_enable(crtc, true);
2394 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2395 dce_v8_0_vga_enable(crtc, false);
2396 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2397 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2398 amdgpu_crtc->crtc_id);
2399 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2400 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2401 drm_crtc_vblank_on(crtc);
2402 dce_v8_0_crtc_load_lut(crtc);
2403 break;
2404 case DRM_MODE_DPMS_STANDBY:
2405 case DRM_MODE_DPMS_SUSPEND:
2406 case DRM_MODE_DPMS_OFF:
2407 drm_crtc_vblank_off(crtc);
2408 if (amdgpu_crtc->enabled) {
2409 dce_v8_0_vga_enable(crtc, true);
2410 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2411 dce_v8_0_vga_enable(crtc, false);
2412 }
2413 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2414 amdgpu_crtc->enabled = false;
2415 break;
2416 }
2417 /* adjust pm to dpms */
2418 amdgpu_pm_compute_clocks(adev);
2419}
2420
2421static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2422{
2423 /* disable crtc pair power gating before programming */
2424 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2425 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2426 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2427}
2428
2429static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2430{
2431 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2432 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2433}
2434
2435static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2436{
2437 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2438 struct drm_device *dev = crtc->dev;
2439 struct amdgpu_device *adev = dev->dev_private;
2440 struct amdgpu_atom_ss ss;
2441 int i;
2442
2443 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2444 if (crtc->primary->fb) {
2445 int r;
2446 struct amdgpu_bo *abo;
2447
2448 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2449 r = amdgpu_bo_reserve(abo, true);
2450 if (unlikely(r))
2451 DRM_ERROR("failed to reserve abo before unpin\n");
2452 else {
2453 amdgpu_bo_unpin(abo);
2454 amdgpu_bo_unreserve(abo);
2455 }
2456 }
2457 /* disable the GRPH */
2458 dce_v8_0_grph_enable(crtc, false);
2459
2460 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2461
2462 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2463 if (adev->mode_info.crtcs[i] &&
2464 adev->mode_info.crtcs[i]->enabled &&
2465 i != amdgpu_crtc->crtc_id &&
2466 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2467 /* one other crtc is using this pll don't turn
2468 * off the pll
2469 */
2470 goto done;
2471 }
2472 }
2473
2474 switch (amdgpu_crtc->pll_id) {
2475 case ATOM_PPLL1:
2476 case ATOM_PPLL2:
2477 /* disable the ppll */
2478 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2479 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2480 break;
2481 case ATOM_PPLL0:
2482 /* disable the ppll */
2483 if ((adev->asic_type == CHIP_KAVERI) ||
2484 (adev->asic_type == CHIP_BONAIRE) ||
2485 (adev->asic_type == CHIP_HAWAII))
2486 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2487 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2488 break;
2489 default:
2490 break;
2491 }
2492done:
2493 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2494 amdgpu_crtc->adjusted_clock = 0;
2495 amdgpu_crtc->encoder = NULL;
2496 amdgpu_crtc->connector = NULL;
2497}
2498
2499static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2500 struct drm_display_mode *mode,
2501 struct drm_display_mode *adjusted_mode,
2502 int x, int y, struct drm_framebuffer *old_fb)
2503{
2504 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2505
2506 if (!amdgpu_crtc->adjusted_clock)
2507 return -EINVAL;
2508
2509 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2510 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2511 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2512 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2513 amdgpu_atombios_crtc_scaler_setup(crtc);
2514 dce_v8_0_cursor_reset(crtc);
2515 /* update the hw version fpr dpm */
2516 amdgpu_crtc->hw_mode = *adjusted_mode;
2517
2518 return 0;
2519}
2520
2521static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2522 const struct drm_display_mode *mode,
2523 struct drm_display_mode *adjusted_mode)
2524{
2525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2526 struct drm_device *dev = crtc->dev;
2527 struct drm_encoder *encoder;
2528
2529 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2531 if (encoder->crtc == crtc) {
2532 amdgpu_crtc->encoder = encoder;
2533 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2534 break;
2535 }
2536 }
2537 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2538 amdgpu_crtc->encoder = NULL;
2539 amdgpu_crtc->connector = NULL;
2540 return false;
2541 }
2542 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2543 return false;
2544 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2545 return false;
2546 /* pick pll */
2547 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2548 /* if we can't get a PPLL for a non-DP encoder, fail */
2549 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2550 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2551 return false;
2552
2553 return true;
2554}
2555
2556static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2557 struct drm_framebuffer *old_fb)
2558{
2559 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2560}
2561
2562static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2563 struct drm_framebuffer *fb,
2564 int x, int y, enum mode_set_atomic state)
2565{
2566 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2567}
2568
2569static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2570 .dpms = dce_v8_0_crtc_dpms,
2571 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2572 .mode_set = dce_v8_0_crtc_mode_set,
2573 .mode_set_base = dce_v8_0_crtc_set_base,
2574 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2575 .prepare = dce_v8_0_crtc_prepare,
2576 .commit = dce_v8_0_crtc_commit,
2577 .disable = dce_v8_0_crtc_disable,
2578};
2579
2580static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2581{
2582 struct amdgpu_crtc *amdgpu_crtc;
2583
2584 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2585 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2586 if (amdgpu_crtc == NULL)
2587 return -ENOMEM;
2588
2589 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2590
2591 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2592 amdgpu_crtc->crtc_id = index;
2593 adev->mode_info.crtcs[index] = amdgpu_crtc;
2594
2595 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2596 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2597 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2598 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2599
2600 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2601
2602 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2603 amdgpu_crtc->adjusted_clock = 0;
2604 amdgpu_crtc->encoder = NULL;
2605 amdgpu_crtc->connector = NULL;
2606 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2607
2608 return 0;
2609}
2610
2611static int dce_v8_0_early_init(void *handle)
2612{
2613 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2614
2615 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2616 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2617
2618 dce_v8_0_set_display_funcs(adev);
2619
2620 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2621
2622 switch (adev->asic_type) {
2623 case CHIP_BONAIRE:
2624 case CHIP_HAWAII:
2625 adev->mode_info.num_hpd = 6;
2626 adev->mode_info.num_dig = 6;
2627 break;
2628 case CHIP_KAVERI:
2629 adev->mode_info.num_hpd = 6;
2630 adev->mode_info.num_dig = 7;
2631 break;
2632 case CHIP_KABINI:
2633 case CHIP_MULLINS:
2634 adev->mode_info.num_hpd = 6;
2635 adev->mode_info.num_dig = 6; /* ? */
2636 break;
2637 default:
2638 /* FIXME: not supported yet */
2639 return -EINVAL;
2640 }
2641
2642 dce_v8_0_set_irq_funcs(adev);
2643
2644 return 0;
2645}
2646
2647static int dce_v8_0_sw_init(void *handle)
2648{
2649 int r, i;
2650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2651
2652 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2653 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2654 if (r)
2655 return r;
2656 }
2657
2658 for (i = 8; i < 20; i += 2) {
2659 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2660 if (r)
2661 return r;
2662 }
2663
2664 /* HPD hotplug */
2665 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2666 if (r)
2667 return r;
2668
2669 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2670
2671 adev->ddev->mode_config.async_page_flip = true;
2672
2673 adev->ddev->mode_config.max_width = 16384;
2674 adev->ddev->mode_config.max_height = 16384;
2675
2676 adev->ddev->mode_config.preferred_depth = 24;
2677 adev->ddev->mode_config.prefer_shadow = 1;
2678
2679 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2680
2681 r = amdgpu_display_modeset_create_props(adev);
2682 if (r)
2683 return r;
2684
2685 adev->ddev->mode_config.max_width = 16384;
2686 adev->ddev->mode_config.max_height = 16384;
2687
2688 /* allocate crtcs */
2689 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2690 r = dce_v8_0_crtc_init(adev, i);
2691 if (r)
2692 return r;
2693 }
2694
2695 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2696 amdgpu_display_print_display_setup(adev->ddev);
2697 else
2698 return -EINVAL;
2699
2700 /* setup afmt */
2701 r = dce_v8_0_afmt_init(adev);
2702 if (r)
2703 return r;
2704
2705 r = dce_v8_0_audio_init(adev);
2706 if (r)
2707 return r;
2708
2709 drm_kms_helper_poll_init(adev->ddev);
2710
2711 adev->mode_info.mode_config_initialized = true;
2712 return 0;
2713}
2714
2715static int dce_v8_0_sw_fini(void *handle)
2716{
2717 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2718
2719 kfree(adev->mode_info.bios_hardcoded_edid);
2720
2721 drm_kms_helper_poll_fini(adev->ddev);
2722
2723 dce_v8_0_audio_fini(adev);
2724
2725 dce_v8_0_afmt_fini(adev);
2726
2727 drm_mode_config_cleanup(adev->ddev);
2728 adev->mode_info.mode_config_initialized = false;
2729
2730 return 0;
2731}
2732
2733static int dce_v8_0_hw_init(void *handle)
2734{
2735 int i;
2736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2737
2738 /* disable vga render */
2739 dce_v8_0_set_vga_render_state(adev, false);
2740 /* init dig PHYs, disp eng pll */
2741 amdgpu_atombios_encoder_init_dig(adev);
2742 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2743
2744 /* initialize hpd */
2745 dce_v8_0_hpd_init(adev);
2746
2747 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2748 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2749 }
2750
2751 dce_v8_0_pageflip_interrupt_init(adev);
2752
2753 return 0;
2754}
2755
2756static int dce_v8_0_hw_fini(void *handle)
2757{
2758 int i;
2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760
2761 dce_v8_0_hpd_fini(adev);
2762
2763 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2764 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2765 }
2766
2767 dce_v8_0_pageflip_interrupt_fini(adev);
2768
2769 return 0;
2770}
2771
2772static int dce_v8_0_suspend(void *handle)
2773{
2774 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2775
2776 adev->mode_info.bl_level =
2777 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2778
2779 return dce_v8_0_hw_fini(handle);
2780}
2781
2782static int dce_v8_0_resume(void *handle)
2783{
2784 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2785 int ret;
2786
2787 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2788 adev->mode_info.bl_level);
2789
2790 ret = dce_v8_0_hw_init(handle);
2791
2792 /* turn on the BL */
2793 if (adev->mode_info.bl_encoder) {
2794 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2795 adev->mode_info.bl_encoder);
2796 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2797 bl_level);
2798 }
2799
2800 return ret;
2801}
2802
2803static bool dce_v8_0_is_idle(void *handle)
2804{
2805 return true;
2806}
2807
2808static int dce_v8_0_wait_for_idle(void *handle)
2809{
2810 return 0;
2811}
2812
2813static int dce_v8_0_soft_reset(void *handle)
2814{
2815 u32 srbm_soft_reset = 0, tmp;
2816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2817
2818 if (dce_v8_0_is_display_hung(adev))
2819 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2820
2821 if (srbm_soft_reset) {
2822 tmp = RREG32(mmSRBM_SOFT_RESET);
2823 tmp |= srbm_soft_reset;
2824 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2825 WREG32(mmSRBM_SOFT_RESET, tmp);
2826 tmp = RREG32(mmSRBM_SOFT_RESET);
2827
2828 udelay(50);
2829
2830 tmp &= ~srbm_soft_reset;
2831 WREG32(mmSRBM_SOFT_RESET, tmp);
2832 tmp = RREG32(mmSRBM_SOFT_RESET);
2833
2834 /* Wait a little for things to settle down */
2835 udelay(50);
2836 }
2837 return 0;
2838}
2839
2840static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2841 int crtc,
2842 enum amdgpu_interrupt_state state)
2843{
2844 u32 reg_block, lb_interrupt_mask;
2845
2846 if (crtc >= adev->mode_info.num_crtc) {
2847 DRM_DEBUG("invalid crtc %d\n", crtc);
2848 return;
2849 }
2850
2851 switch (crtc) {
2852 case 0:
2853 reg_block = CRTC0_REGISTER_OFFSET;
2854 break;
2855 case 1:
2856 reg_block = CRTC1_REGISTER_OFFSET;
2857 break;
2858 case 2:
2859 reg_block = CRTC2_REGISTER_OFFSET;
2860 break;
2861 case 3:
2862 reg_block = CRTC3_REGISTER_OFFSET;
2863 break;
2864 case 4:
2865 reg_block = CRTC4_REGISTER_OFFSET;
2866 break;
2867 case 5:
2868 reg_block = CRTC5_REGISTER_OFFSET;
2869 break;
2870 default:
2871 DRM_DEBUG("invalid crtc %d\n", crtc);
2872 return;
2873 }
2874
2875 switch (state) {
2876 case AMDGPU_IRQ_STATE_DISABLE:
2877 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2878 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2879 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2880 break;
2881 case AMDGPU_IRQ_STATE_ENABLE:
2882 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2883 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2884 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2885 break;
2886 default:
2887 break;
2888 }
2889}
2890
2891static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2892 int crtc,
2893 enum amdgpu_interrupt_state state)
2894{
2895 u32 reg_block, lb_interrupt_mask;
2896
2897 if (crtc >= adev->mode_info.num_crtc) {
2898 DRM_DEBUG("invalid crtc %d\n", crtc);
2899 return;
2900 }
2901
2902 switch (crtc) {
2903 case 0:
2904 reg_block = CRTC0_REGISTER_OFFSET;
2905 break;
2906 case 1:
2907 reg_block = CRTC1_REGISTER_OFFSET;
2908 break;
2909 case 2:
2910 reg_block = CRTC2_REGISTER_OFFSET;
2911 break;
2912 case 3:
2913 reg_block = CRTC3_REGISTER_OFFSET;
2914 break;
2915 case 4:
2916 reg_block = CRTC4_REGISTER_OFFSET;
2917 break;
2918 case 5:
2919 reg_block = CRTC5_REGISTER_OFFSET;
2920 break;
2921 default:
2922 DRM_DEBUG("invalid crtc %d\n", crtc);
2923 return;
2924 }
2925
2926 switch (state) {
2927 case AMDGPU_IRQ_STATE_DISABLE:
2928 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2929 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2930 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2931 break;
2932 case AMDGPU_IRQ_STATE_ENABLE:
2933 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2934 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2935 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2936 break;
2937 default:
2938 break;
2939 }
2940}
2941
2942static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2943 struct amdgpu_irq_src *src,
2944 unsigned type,
2945 enum amdgpu_interrupt_state state)
2946{
2947 u32 dc_hpd_int_cntl;
2948
2949 if (type >= adev->mode_info.num_hpd) {
2950 DRM_DEBUG("invalid hdp %d\n", type);
2951 return 0;
2952 }
2953
2954 switch (state) {
2955 case AMDGPU_IRQ_STATE_DISABLE:
2956 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2957 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2958 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2959 break;
2960 case AMDGPU_IRQ_STATE_ENABLE:
2961 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2962 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2963 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2964 break;
2965 default:
2966 break;
2967 }
2968
2969 return 0;
2970}
2971
2972static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2973 struct amdgpu_irq_src *src,
2974 unsigned type,
2975 enum amdgpu_interrupt_state state)
2976{
2977 switch (type) {
2978 case AMDGPU_CRTC_IRQ_VBLANK1:
2979 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2980 break;
2981 case AMDGPU_CRTC_IRQ_VBLANK2:
2982 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2983 break;
2984 case AMDGPU_CRTC_IRQ_VBLANK3:
2985 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2986 break;
2987 case AMDGPU_CRTC_IRQ_VBLANK4:
2988 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2989 break;
2990 case AMDGPU_CRTC_IRQ_VBLANK5:
2991 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2992 break;
2993 case AMDGPU_CRTC_IRQ_VBLANK6:
2994 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2995 break;
2996 case AMDGPU_CRTC_IRQ_VLINE1:
2997 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
2998 break;
2999 case AMDGPU_CRTC_IRQ_VLINE2:
3000 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3001 break;
3002 case AMDGPU_CRTC_IRQ_VLINE3:
3003 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3004 break;
3005 case AMDGPU_CRTC_IRQ_VLINE4:
3006 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3007 break;
3008 case AMDGPU_CRTC_IRQ_VLINE5:
3009 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3010 break;
3011 case AMDGPU_CRTC_IRQ_VLINE6:
3012 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3013 break;
3014 default:
3015 break;
3016 }
3017 return 0;
3018}
3019
3020static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3021 struct amdgpu_irq_src *source,
3022 struct amdgpu_iv_entry *entry)
3023{
3024 unsigned crtc = entry->src_id - 1;
3025 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3026 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3027 crtc);
3028
3029 switch (entry->src_data[0]) {
3030 case 0: /* vblank */
3031 if (disp_int & interrupt_status_offsets[crtc].vblank)
3032 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3033 else
3034 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3035
3036 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3037 drm_handle_vblank(adev->ddev, crtc);
3038 }
3039 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3040 break;
3041 case 1: /* vline */
3042 if (disp_int & interrupt_status_offsets[crtc].vline)
3043 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3044 else
3045 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3046
3047 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3048 break;
3049 default:
3050 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3051 break;
3052 }
3053
3054 return 0;
3055}
3056
3057static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3058 struct amdgpu_irq_src *src,
3059 unsigned type,
3060 enum amdgpu_interrupt_state state)
3061{
3062 u32 reg;
3063
3064 if (type >= adev->mode_info.num_crtc) {
3065 DRM_ERROR("invalid pageflip crtc %d\n", type);
3066 return -EINVAL;
3067 }
3068
3069 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3070 if (state == AMDGPU_IRQ_STATE_DISABLE)
3071 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3072 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3073 else
3074 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3075 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3076
3077 return 0;
3078}
3079
3080static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3081 struct amdgpu_irq_src *source,
3082 struct amdgpu_iv_entry *entry)
3083{
3084 unsigned long flags;
3085 unsigned crtc_id;
3086 struct amdgpu_crtc *amdgpu_crtc;
3087 struct amdgpu_flip_work *works;
3088
3089 crtc_id = (entry->src_id - 8) >> 1;
3090 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3091
3092 if (crtc_id >= adev->mode_info.num_crtc) {
3093 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3094 return -EINVAL;
3095 }
3096
3097 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3098 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3099 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3100 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3101
3102 /* IRQ could occur when in initial stage */
3103 if (amdgpu_crtc == NULL)
3104 return 0;
3105
3106 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3107 works = amdgpu_crtc->pflip_works;
3108 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3109 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3110 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3111 amdgpu_crtc->pflip_status,
3112 AMDGPU_FLIP_SUBMITTED);
3113 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3114 return 0;
3115 }
3116
3117 /* page flip completed. clean up */
3118 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3119 amdgpu_crtc->pflip_works = NULL;
3120
3121 /* wakeup usersapce */
3122 if (works->event)
3123 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3124
3125 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3126
3127 drm_crtc_vblank_put(&amdgpu_crtc->base);
3128 schedule_work(&works->unpin_work);
3129
3130 return 0;
3131}
3132
3133static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3134 struct amdgpu_irq_src *source,
3135 struct amdgpu_iv_entry *entry)
3136{
3137 uint32_t disp_int, mask, tmp;
3138 unsigned hpd;
3139
3140 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3141 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3142 return 0;
3143 }
3144
3145 hpd = entry->src_data[0];
3146 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3147 mask = interrupt_status_offsets[hpd].hpd;
3148
3149 if (disp_int & mask) {
3150 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3151 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3152 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3153 schedule_work(&adev->hotplug_work);
3154 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3155 }
3156
3157 return 0;
3158
3159}
3160
3161static int dce_v8_0_set_clockgating_state(void *handle,
3162 enum amd_clockgating_state state)
3163{
3164 return 0;
3165}
3166
3167static int dce_v8_0_set_powergating_state(void *handle,
3168 enum amd_powergating_state state)
3169{
3170 return 0;
3171}
3172
3173static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3174 .name = "dce_v8_0",
3175 .early_init = dce_v8_0_early_init,
3176 .late_init = NULL,
3177 .sw_init = dce_v8_0_sw_init,
3178 .sw_fini = dce_v8_0_sw_fini,
3179 .hw_init = dce_v8_0_hw_init,
3180 .hw_fini = dce_v8_0_hw_fini,
3181 .suspend = dce_v8_0_suspend,
3182 .resume = dce_v8_0_resume,
3183 .is_idle = dce_v8_0_is_idle,
3184 .wait_for_idle = dce_v8_0_wait_for_idle,
3185 .soft_reset = dce_v8_0_soft_reset,
3186 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3187 .set_powergating_state = dce_v8_0_set_powergating_state,
3188};
3189
3190static void
3191dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3192 struct drm_display_mode *mode,
3193 struct drm_display_mode *adjusted_mode)
3194{
3195 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3196
3197 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3198
3199 /* need to call this here rather than in prepare() since we need some crtc info */
3200 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3201
3202 /* set scaler clears this on some chips */
3203 dce_v8_0_set_interleave(encoder->crtc, mode);
3204
3205 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3206 dce_v8_0_afmt_enable(encoder, true);
3207 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3208 }
3209}
3210
3211static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3212{
3213 struct amdgpu_device *adev = encoder->dev->dev_private;
3214 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3215 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3216
3217 if ((amdgpu_encoder->active_device &
3218 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3219 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3220 ENCODER_OBJECT_ID_NONE)) {
3221 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3222 if (dig) {
3223 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3224 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3225 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3226 }
3227 }
3228
3229 amdgpu_atombios_scratch_regs_lock(adev, true);
3230
3231 if (connector) {
3232 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3233
3234 /* select the clock/data port if it uses a router */
3235 if (amdgpu_connector->router.cd_valid)
3236 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3237
3238 /* turn eDP panel on for mode set */
3239 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3240 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3241 ATOM_TRANSMITTER_ACTION_POWER_ON);
3242 }
3243
3244 /* this is needed for the pll/ss setup to work correctly in some cases */
3245 amdgpu_atombios_encoder_set_crtc_source(encoder);
3246 /* set up the FMT blocks */
3247 dce_v8_0_program_fmt(encoder);
3248}
3249
3250static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3251{
3252 struct drm_device *dev = encoder->dev;
3253 struct amdgpu_device *adev = dev->dev_private;
3254
3255 /* need to call this here as we need the crtc set up */
3256 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3257 amdgpu_atombios_scratch_regs_lock(adev, false);
3258}
3259
3260static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3261{
3262 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3263 struct amdgpu_encoder_atom_dig *dig;
3264
3265 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3266
3267 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3268 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3269 dce_v8_0_afmt_enable(encoder, false);
3270 dig = amdgpu_encoder->enc_priv;
3271 dig->dig_encoder = -1;
3272 }
3273 amdgpu_encoder->active_device = 0;
3274}
3275
3276/* these are handled by the primary encoders */
3277static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3278{
3279
3280}
3281
3282static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3283{
3284
3285}
3286
3287static void
3288dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3289 struct drm_display_mode *mode,
3290 struct drm_display_mode *adjusted_mode)
3291{
3292
3293}
3294
3295static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3296{
3297
3298}
3299
3300static void
3301dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3302{
3303
3304}
3305
3306static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3307 .dpms = dce_v8_0_ext_dpms,
3308 .prepare = dce_v8_0_ext_prepare,
3309 .mode_set = dce_v8_0_ext_mode_set,
3310 .commit = dce_v8_0_ext_commit,
3311 .disable = dce_v8_0_ext_disable,
3312 /* no detect for TMDS/LVDS yet */
3313};
3314
3315static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3316 .dpms = amdgpu_atombios_encoder_dpms,
3317 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3318 .prepare = dce_v8_0_encoder_prepare,
3319 .mode_set = dce_v8_0_encoder_mode_set,
3320 .commit = dce_v8_0_encoder_commit,
3321 .disable = dce_v8_0_encoder_disable,
3322 .detect = amdgpu_atombios_encoder_dig_detect,
3323};
3324
3325static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3326 .dpms = amdgpu_atombios_encoder_dpms,
3327 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3328 .prepare = dce_v8_0_encoder_prepare,
3329 .mode_set = dce_v8_0_encoder_mode_set,
3330 .commit = dce_v8_0_encoder_commit,
3331 .detect = amdgpu_atombios_encoder_dac_detect,
3332};
3333
3334static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3335{
3336 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3337 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3338 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3339 kfree(amdgpu_encoder->enc_priv);
3340 drm_encoder_cleanup(encoder);
3341 kfree(amdgpu_encoder);
3342}
3343
3344static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3345 .destroy = dce_v8_0_encoder_destroy,
3346};
3347
3348static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3349 uint32_t encoder_enum,
3350 uint32_t supported_device,
3351 u16 caps)
3352{
3353 struct drm_device *dev = adev->ddev;
3354 struct drm_encoder *encoder;
3355 struct amdgpu_encoder *amdgpu_encoder;
3356
3357 /* see if we already added it */
3358 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3359 amdgpu_encoder = to_amdgpu_encoder(encoder);
3360 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3361 amdgpu_encoder->devices |= supported_device;
3362 return;
3363 }
3364
3365 }
3366
3367 /* add a new one */
3368 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3369 if (!amdgpu_encoder)
3370 return;
3371
3372 encoder = &amdgpu_encoder->base;
3373 switch (adev->mode_info.num_crtc) {
3374 case 1:
3375 encoder->possible_crtcs = 0x1;
3376 break;
3377 case 2:
3378 default:
3379 encoder->possible_crtcs = 0x3;
3380 break;
3381 case 4:
3382 encoder->possible_crtcs = 0xf;
3383 break;
3384 case 6:
3385 encoder->possible_crtcs = 0x3f;
3386 break;
3387 }
3388
3389 amdgpu_encoder->enc_priv = NULL;
3390
3391 amdgpu_encoder->encoder_enum = encoder_enum;
3392 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3393 amdgpu_encoder->devices = supported_device;
3394 amdgpu_encoder->rmx_type = RMX_OFF;
3395 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3396 amdgpu_encoder->is_ext_encoder = false;
3397 amdgpu_encoder->caps = caps;
3398
3399 switch (amdgpu_encoder->encoder_id) {
3400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3402 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3403 DRM_MODE_ENCODER_DAC, NULL);
3404 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3405 break;
3406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3407 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3408 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3409 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3411 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3412 amdgpu_encoder->rmx_type = RMX_FULL;
3413 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3414 DRM_MODE_ENCODER_LVDS, NULL);
3415 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3416 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3417 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3418 DRM_MODE_ENCODER_DAC, NULL);
3419 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3420 } else {
3421 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3422 DRM_MODE_ENCODER_TMDS, NULL);
3423 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3424 }
3425 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3426 break;
3427 case ENCODER_OBJECT_ID_SI170B:
3428 case ENCODER_OBJECT_ID_CH7303:
3429 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3430 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3431 case ENCODER_OBJECT_ID_TITFP513:
3432 case ENCODER_OBJECT_ID_VT1623:
3433 case ENCODER_OBJECT_ID_HDMI_SI1930:
3434 case ENCODER_OBJECT_ID_TRAVIS:
3435 case ENCODER_OBJECT_ID_NUTMEG:
3436 /* these are handled by the primary encoders */
3437 amdgpu_encoder->is_ext_encoder = true;
3438 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3439 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3440 DRM_MODE_ENCODER_LVDS, NULL);
3441 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3442 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3443 DRM_MODE_ENCODER_DAC, NULL);
3444 else
3445 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3446 DRM_MODE_ENCODER_TMDS, NULL);
3447 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3448 break;
3449 }
3450}
3451
3452static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3453 .bandwidth_update = &dce_v8_0_bandwidth_update,
3454 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3455 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3456 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3457 .hpd_sense = &dce_v8_0_hpd_sense,
3458 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3459 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3460 .page_flip = &dce_v8_0_page_flip,
3461 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3462 .add_encoder = &dce_v8_0_encoder_add,
3463 .add_connector = &amdgpu_connector_add,
3464};
3465
3466static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3467{
3468 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3469}
3470
3471static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3472 .set = dce_v8_0_set_crtc_interrupt_state,
3473 .process = dce_v8_0_crtc_irq,
3474};
3475
3476static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3477 .set = dce_v8_0_set_pageflip_interrupt_state,
3478 .process = dce_v8_0_pageflip_irq,
3479};
3480
3481static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3482 .set = dce_v8_0_set_hpd_interrupt_state,
3483 .process = dce_v8_0_hpd_irq,
3484};
3485
3486static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3487{
3488 if (adev->mode_info.num_crtc > 0)
3489 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3490 else
3491 adev->crtc_irq.num_types = 0;
3492 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3493
3494 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3495 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3496
3497 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3498 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3499}
3500
3501const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3502{
3503 .type = AMD_IP_BLOCK_TYPE_DCE,
3504 .major = 8,
3505 .minor = 0,
3506 .rev = 0,
3507 .funcs = &dce_v8_0_ip_funcs,
3508};
3509
3510const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3511{
3512 .type = AMD_IP_BLOCK_TYPE_DCE,
3513 .major = 8,
3514 .minor = 1,
3515 .rev = 0,
3516 .funcs = &dce_v8_0_ip_funcs,
3517};
3518
3519const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3520{
3521 .type = AMD_IP_BLOCK_TYPE_DCE,
3522 .major = 8,
3523 .minor = 2,
3524 .rev = 0,
3525 .funcs = &dce_v8_0_ip_funcs,
3526};
3527
3528const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3529{
3530 .type = AMD_IP_BLOCK_TYPE_DCE,
3531 .major = 8,
3532 .minor = 3,
3533 .rev = 0,
3534 .funcs = &dce_v8_0_ip_funcs,
3535};
3536
3537const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3538{
3539 .type = AMD_IP_BLOCK_TYPE_DCE,
3540 .major = 8,
3541 .minor = 5,
3542 .rev = 0,
3543 .funcs = &dce_v8_0_ip_funcs,
3544};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_edid.h>
25#include <drm/drm_fourcc.h>
26#include <drm/drm_modeset_helper.h>
27#include <drm/drm_modeset_helper_vtables.h>
28#include <drm/drm_vblank.h>
29
30#include "amdgpu.h"
31#include "amdgpu_pm.h"
32#include "amdgpu_i2c.h"
33#include "cikd.h"
34#include "atom.h"
35#include "amdgpu_atombios.h"
36#include "atombios_crtc.h"
37#include "atombios_encoders.h"
38#include "amdgpu_pll.h"
39#include "amdgpu_connectors.h"
40#include "amdgpu_display.h"
41#include "dce_v8_0.h"
42
43#include "dce/dce_8_0_d.h"
44#include "dce/dce_8_0_sh_mask.h"
45
46#include "gca/gfx_7_2_enum.h"
47
48#include "gmc/gmc_7_1_d.h"
49#include "gmc/gmc_7_1_sh_mask.h"
50
51#include "oss/oss_2_0_d.h"
52#include "oss/oss_2_0_sh_mask.h"
53
54static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
55static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56
57static const u32 crtc_offsets[6] = {
58 CRTC0_REGISTER_OFFSET,
59 CRTC1_REGISTER_OFFSET,
60 CRTC2_REGISTER_OFFSET,
61 CRTC3_REGISTER_OFFSET,
62 CRTC4_REGISTER_OFFSET,
63 CRTC5_REGISTER_OFFSET
64};
65
66static const u32 hpd_offsets[] = {
67 HPD0_REGISTER_OFFSET,
68 HPD1_REGISTER_OFFSET,
69 HPD2_REGISTER_OFFSET,
70 HPD3_REGISTER_OFFSET,
71 HPD4_REGISTER_OFFSET,
72 HPD5_REGISTER_OFFSET
73};
74
75static const uint32_t dig_offsets[] = {
76 CRTC0_REGISTER_OFFSET,
77 CRTC1_REGISTER_OFFSET,
78 CRTC2_REGISTER_OFFSET,
79 CRTC3_REGISTER_OFFSET,
80 CRTC4_REGISTER_OFFSET,
81 CRTC5_REGISTER_OFFSET,
82 (0x13830 - 0x7030) >> 2,
83};
84
85static const struct {
86 uint32_t reg;
87 uint32_t vblank;
88 uint32_t vline;
89 uint32_t hpd;
90
91} interrupt_status_offsets[6] = { {
92 .reg = mmDISP_INTERRUPT_STATUS,
93 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
116}, {
117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
119 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
121} };
122
123static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
124 u32 block_offset, u32 reg)
125{
126 unsigned long flags;
127 u32 r;
128
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
130 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
131 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
132 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
133
134 return r;
135}
136
137static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
138 u32 block_offset, u32 reg, u32 v)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
144 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
145 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
146}
147
148static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
149{
150 if (crtc >= adev->mode_info.num_crtc)
151 return 0;
152 else
153 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
154}
155
156static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
157{
158 unsigned i;
159
160 /* Enable pflip interrupts */
161 for (i = 0; i < adev->mode_info.num_crtc; i++)
162 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
163}
164
165static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
166{
167 unsigned i;
168
169 /* Disable pflip interrupts */
170 for (i = 0; i < adev->mode_info.num_crtc; i++)
171 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
172}
173
174/**
175 * dce_v8_0_page_flip - pageflip callback.
176 *
177 * @adev: amdgpu_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
180 * @async: asynchronous flip
181 *
182 * Triggers the actual pageflip by updating the primary
183 * surface base address.
184 */
185static void dce_v8_0_page_flip(struct amdgpu_device *adev,
186 int crtc_id, u64 crtc_base, bool async)
187{
188 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
189 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
190
191 /* flip at hsync for async, default is vsync */
192 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
193 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
194 /* update pitch */
195 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
196 fb->pitches[0] / fb->format->cpp[0]);
197 /* update the primary scanout addresses */
198 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
199 upper_32_bits(crtc_base));
200 /* writing to the low address triggers the update */
201 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
202 lower_32_bits(crtc_base));
203 /* post the write */
204 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
205}
206
207static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
208 u32 *vbl, u32 *position)
209{
210 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
211 return -EINVAL;
212
213 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
214 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
215
216 return 0;
217}
218
219/**
220 * dce_v8_0_hpd_sense - hpd sense callback.
221 *
222 * @adev: amdgpu_device pointer
223 * @hpd: hpd (hotplug detect) pin
224 *
225 * Checks if a digital monitor is connected (evergreen+).
226 * Returns true if connected, false if not connected.
227 */
228static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
229 enum amdgpu_hpd_id hpd)
230{
231 bool connected = false;
232
233 if (hpd >= adev->mode_info.num_hpd)
234 return connected;
235
236 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
237 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
238 connected = true;
239
240 return connected;
241}
242
243/**
244 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
245 *
246 * @adev: amdgpu_device pointer
247 * @hpd: hpd (hotplug detect) pin
248 *
249 * Set the polarity of the hpd pin (evergreen+).
250 */
251static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
252 enum amdgpu_hpd_id hpd)
253{
254 u32 tmp;
255 bool connected = dce_v8_0_hpd_sense(adev, hpd);
256
257 if (hpd >= adev->mode_info.num_hpd)
258 return;
259
260 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
261 if (connected)
262 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
263 else
264 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
265 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
266}
267
268static void dce_v8_0_hpd_int_ack(struct amdgpu_device *adev,
269 int hpd)
270{
271 u32 tmp;
272
273 if (hpd >= adev->mode_info.num_hpd) {
274 DRM_DEBUG("invalid hdp %d\n", hpd);
275 return;
276 }
277
278 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
279 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
280 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
281}
282
283/**
284 * dce_v8_0_hpd_init - hpd setup callback.
285 *
286 * @adev: amdgpu_device pointer
287 *
288 * Setup the hpd pins used by the card (evergreen+).
289 * Enable the pin, set the polarity, and enable the hpd interrupts.
290 */
291static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
292{
293 struct drm_device *dev = adev_to_drm(adev);
294 struct drm_connector *connector;
295 struct drm_connector_list_iter iter;
296 u32 tmp;
297
298 drm_connector_list_iter_begin(dev, &iter);
299 drm_for_each_connector_iter(connector, &iter) {
300 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
301
302 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
303 continue;
304
305 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
306 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
307 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
308
309 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
310 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
311 /* don't try to enable hpd on eDP or LVDS avoid breaking the
312 * aux dp channel on imac and help (but not completely fix)
313 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
314 * also avoid interrupt storms during dpms.
315 */
316 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
317 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
318 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
319 continue;
320 }
321
322 dce_v8_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
323 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
324 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
325 }
326 drm_connector_list_iter_end(&iter);
327}
328
329/**
330 * dce_v8_0_hpd_fini - hpd tear down callback.
331 *
332 * @adev: amdgpu_device pointer
333 *
334 * Tear down the hpd pins used by the card (evergreen+).
335 * Disable the hpd interrupts.
336 */
337static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
338{
339 struct drm_device *dev = adev_to_drm(adev);
340 struct drm_connector *connector;
341 struct drm_connector_list_iter iter;
342 u32 tmp;
343
344 drm_connector_list_iter_begin(dev, &iter);
345 drm_for_each_connector_iter(connector, &iter) {
346 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
347
348 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
349 continue;
350
351 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
352 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
353 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
354
355 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
356 }
357 drm_connector_list_iter_end(&iter);
358}
359
360static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
361{
362 return mmDC_GPIO_HPD_A;
363}
364
365static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
366{
367 u32 crtc_hung = 0;
368 u32 crtc_status[6];
369 u32 i, j, tmp;
370
371 for (i = 0; i < adev->mode_info.num_crtc; i++) {
372 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
373 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
374 crtc_hung |= (1 << i);
375 }
376 }
377
378 for (j = 0; j < 10; j++) {
379 for (i = 0; i < adev->mode_info.num_crtc; i++) {
380 if (crtc_hung & (1 << i)) {
381 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
382 if (tmp != crtc_status[i])
383 crtc_hung &= ~(1 << i);
384 }
385 }
386 if (crtc_hung == 0)
387 return false;
388 udelay(100);
389 }
390
391 return true;
392}
393
394static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
395 bool render)
396{
397 u32 tmp;
398
399 /* Lockout access through VGA aperture*/
400 tmp = RREG32(mmVGA_HDP_CONTROL);
401 if (render)
402 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
403 else
404 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
405 WREG32(mmVGA_HDP_CONTROL, tmp);
406
407 /* disable VGA render */
408 tmp = RREG32(mmVGA_RENDER_CONTROL);
409 if (render)
410 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
411 else
412 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
413 WREG32(mmVGA_RENDER_CONTROL, tmp);
414}
415
416static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
417{
418 int num_crtc = 0;
419
420 switch (adev->asic_type) {
421 case CHIP_BONAIRE:
422 case CHIP_HAWAII:
423 num_crtc = 6;
424 break;
425 case CHIP_KAVERI:
426 num_crtc = 4;
427 break;
428 case CHIP_KABINI:
429 case CHIP_MULLINS:
430 num_crtc = 2;
431 break;
432 default:
433 num_crtc = 0;
434 }
435 return num_crtc;
436}
437
438void dce_v8_0_disable_dce(struct amdgpu_device *adev)
439{
440 /*Disable VGA render and enabled crtc, if has DCE engine*/
441 if (amdgpu_atombios_has_dce_engine_info(adev)) {
442 u32 tmp;
443 int crtc_enabled, i;
444
445 dce_v8_0_set_vga_render_state(adev, false);
446
447 /*Disable crtc*/
448 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
449 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
450 CRTC_CONTROL, CRTC_MASTER_EN);
451 if (crtc_enabled) {
452 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
453 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
454 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
455 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
456 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
457 }
458 }
459 }
460}
461
462static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
463{
464 struct drm_device *dev = encoder->dev;
465 struct amdgpu_device *adev = drm_to_adev(dev);
466 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
467 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
468 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
469 int bpc = 0;
470 u32 tmp = 0;
471 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
472
473 if (connector) {
474 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
475 bpc = amdgpu_connector_get_monitor_bpc(connector);
476 dither = amdgpu_connector->dither;
477 }
478
479 /* LVDS/eDP FMT is set up by atom */
480 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
481 return;
482
483 /* not needed for analog */
484 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
485 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
486 return;
487
488 if (bpc == 0)
489 return;
490
491 switch (bpc) {
492 case 6:
493 if (dither == AMDGPU_FMT_DITHER_ENABLE)
494 /* XXX sort out optimal dither settings */
495 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
496 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
497 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
498 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
499 else
500 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
501 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
502 break;
503 case 8:
504 if (dither == AMDGPU_FMT_DITHER_ENABLE)
505 /* XXX sort out optimal dither settings */
506 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
507 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
508 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
509 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
510 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
511 else
512 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
513 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
514 break;
515 case 10:
516 if (dither == AMDGPU_FMT_DITHER_ENABLE)
517 /* XXX sort out optimal dither settings */
518 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
519 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
520 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
521 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
522 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
523 else
524 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
525 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
526 break;
527 default:
528 /* not needed */
529 break;
530 }
531
532 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
533}
534
535
536/* display watermark setup */
537/**
538 * dce_v8_0_line_buffer_adjust - Set up the line buffer
539 *
540 * @adev: amdgpu_device pointer
541 * @amdgpu_crtc: the selected display controller
542 * @mode: the current display mode on the selected display
543 * controller
544 *
545 * Setup up the line buffer allocation for
546 * the selected display controller (CIK).
547 * Returns the line buffer size in pixels.
548 */
549static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
550 struct amdgpu_crtc *amdgpu_crtc,
551 struct drm_display_mode *mode)
552{
553 u32 tmp, buffer_alloc, i;
554 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
555 /*
556 * Line Buffer Setup
557 * There are 6 line buffers, one for each display controllers.
558 * There are 3 partitions per LB. Select the number of partitions
559 * to enable based on the display width. For display widths larger
560 * than 4096, you need use to use 2 display controllers and combine
561 * them using the stereo blender.
562 */
563 if (amdgpu_crtc->base.enabled && mode) {
564 if (mode->crtc_hdisplay < 1920) {
565 tmp = 1;
566 buffer_alloc = 2;
567 } else if (mode->crtc_hdisplay < 2560) {
568 tmp = 2;
569 buffer_alloc = 2;
570 } else if (mode->crtc_hdisplay < 4096) {
571 tmp = 0;
572 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
573 } else {
574 DRM_DEBUG_KMS("Mode too big for LB!\n");
575 tmp = 0;
576 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
577 }
578 } else {
579 tmp = 1;
580 buffer_alloc = 0;
581 }
582
583 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
584 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
585 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
586
587 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
588 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
589 for (i = 0; i < adev->usec_timeout; i++) {
590 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
591 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
592 break;
593 udelay(1);
594 }
595
596 if (amdgpu_crtc->base.enabled && mode) {
597 switch (tmp) {
598 case 0:
599 default:
600 return 4096 * 2;
601 case 1:
602 return 1920 * 2;
603 case 2:
604 return 2560 * 2;
605 }
606 }
607
608 /* controller not enabled, so no lb used */
609 return 0;
610}
611
612/**
613 * cik_get_number_of_dram_channels - get the number of dram channels
614 *
615 * @adev: amdgpu_device pointer
616 *
617 * Look up the number of video ram channels (CIK).
618 * Used for display watermark bandwidth calculations
619 * Returns the number of dram channels
620 */
621static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
622{
623 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
624
625 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
626 case 0:
627 default:
628 return 1;
629 case 1:
630 return 2;
631 case 2:
632 return 4;
633 case 3:
634 return 8;
635 case 4:
636 return 3;
637 case 5:
638 return 6;
639 case 6:
640 return 10;
641 case 7:
642 return 12;
643 case 8:
644 return 16;
645 }
646}
647
648struct dce8_wm_params {
649 u32 dram_channels; /* number of dram channels */
650 u32 yclk; /* bandwidth per dram data pin in kHz */
651 u32 sclk; /* engine clock in kHz */
652 u32 disp_clk; /* display clock in kHz */
653 u32 src_width; /* viewport width */
654 u32 active_time; /* active display time in ns */
655 u32 blank_time; /* blank time in ns */
656 bool interlaced; /* mode is interlaced */
657 fixed20_12 vsc; /* vertical scale ratio */
658 u32 num_heads; /* number of active crtcs */
659 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
660 u32 lb_size; /* line buffer allocated to pipe */
661 u32 vtaps; /* vertical scaler taps */
662};
663
664/**
665 * dce_v8_0_dram_bandwidth - get the dram bandwidth
666 *
667 * @wm: watermark calculation data
668 *
669 * Calculate the raw dram bandwidth (CIK).
670 * Used for display watermark bandwidth calculations
671 * Returns the dram bandwidth in MBytes/s
672 */
673static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
674{
675 /* Calculate raw DRAM Bandwidth */
676 fixed20_12 dram_efficiency; /* 0.7 */
677 fixed20_12 yclk, dram_channels, bandwidth;
678 fixed20_12 a;
679
680 a.full = dfixed_const(1000);
681 yclk.full = dfixed_const(wm->yclk);
682 yclk.full = dfixed_div(yclk, a);
683 dram_channels.full = dfixed_const(wm->dram_channels * 4);
684 a.full = dfixed_const(10);
685 dram_efficiency.full = dfixed_const(7);
686 dram_efficiency.full = dfixed_div(dram_efficiency, a);
687 bandwidth.full = dfixed_mul(dram_channels, yclk);
688 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
689
690 return dfixed_trunc(bandwidth);
691}
692
693/**
694 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
695 *
696 * @wm: watermark calculation data
697 *
698 * Calculate the dram bandwidth used for display (CIK).
699 * Used for display watermark bandwidth calculations
700 * Returns the dram bandwidth for display in MBytes/s
701 */
702static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
703{
704 /* Calculate DRAM Bandwidth and the part allocated to display. */
705 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
706 fixed20_12 yclk, dram_channels, bandwidth;
707 fixed20_12 a;
708
709 a.full = dfixed_const(1000);
710 yclk.full = dfixed_const(wm->yclk);
711 yclk.full = dfixed_div(yclk, a);
712 dram_channels.full = dfixed_const(wm->dram_channels * 4);
713 a.full = dfixed_const(10);
714 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
715 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
716 bandwidth.full = dfixed_mul(dram_channels, yclk);
717 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
718
719 return dfixed_trunc(bandwidth);
720}
721
722/**
723 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
724 *
725 * @wm: watermark calculation data
726 *
727 * Calculate the data return bandwidth used for display (CIK).
728 * Used for display watermark bandwidth calculations
729 * Returns the data return bandwidth in MBytes/s
730 */
731static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
732{
733 /* Calculate the display Data return Bandwidth */
734 fixed20_12 return_efficiency; /* 0.8 */
735 fixed20_12 sclk, bandwidth;
736 fixed20_12 a;
737
738 a.full = dfixed_const(1000);
739 sclk.full = dfixed_const(wm->sclk);
740 sclk.full = dfixed_div(sclk, a);
741 a.full = dfixed_const(10);
742 return_efficiency.full = dfixed_const(8);
743 return_efficiency.full = dfixed_div(return_efficiency, a);
744 a.full = dfixed_const(32);
745 bandwidth.full = dfixed_mul(a, sclk);
746 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
747
748 return dfixed_trunc(bandwidth);
749}
750
751/**
752 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
753 *
754 * @wm: watermark calculation data
755 *
756 * Calculate the dmif bandwidth used for display (CIK).
757 * Used for display watermark bandwidth calculations
758 * Returns the dmif bandwidth in MBytes/s
759 */
760static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
761{
762 /* Calculate the DMIF Request Bandwidth */
763 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
764 fixed20_12 disp_clk, bandwidth;
765 fixed20_12 a, b;
766
767 a.full = dfixed_const(1000);
768 disp_clk.full = dfixed_const(wm->disp_clk);
769 disp_clk.full = dfixed_div(disp_clk, a);
770 a.full = dfixed_const(32);
771 b.full = dfixed_mul(a, disp_clk);
772
773 a.full = dfixed_const(10);
774 disp_clk_request_efficiency.full = dfixed_const(8);
775 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
776
777 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
778
779 return dfixed_trunc(bandwidth);
780}
781
782/**
783 * dce_v8_0_available_bandwidth - get the min available bandwidth
784 *
785 * @wm: watermark calculation data
786 *
787 * Calculate the min available bandwidth used for display (CIK).
788 * Used for display watermark bandwidth calculations
789 * Returns the min available bandwidth in MBytes/s
790 */
791static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
792{
793 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
794 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
795 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
796 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
797
798 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
799}
800
801/**
802 * dce_v8_0_average_bandwidth - get the average available bandwidth
803 *
804 * @wm: watermark calculation data
805 *
806 * Calculate the average available bandwidth used for display (CIK).
807 * Used for display watermark bandwidth calculations
808 * Returns the average available bandwidth in MBytes/s
809 */
810static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
811{
812 /* Calculate the display mode Average Bandwidth
813 * DisplayMode should contain the source and destination dimensions,
814 * timing, etc.
815 */
816 fixed20_12 bpp;
817 fixed20_12 line_time;
818 fixed20_12 src_width;
819 fixed20_12 bandwidth;
820 fixed20_12 a;
821
822 a.full = dfixed_const(1000);
823 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
824 line_time.full = dfixed_div(line_time, a);
825 bpp.full = dfixed_const(wm->bytes_per_pixel);
826 src_width.full = dfixed_const(wm->src_width);
827 bandwidth.full = dfixed_mul(src_width, bpp);
828 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
829 bandwidth.full = dfixed_div(bandwidth, line_time);
830
831 return dfixed_trunc(bandwidth);
832}
833
834/**
835 * dce_v8_0_latency_watermark - get the latency watermark
836 *
837 * @wm: watermark calculation data
838 *
839 * Calculate the latency watermark (CIK).
840 * Used for display watermark bandwidth calculations
841 * Returns the latency watermark in ns
842 */
843static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
844{
845 /* First calculate the latency in ns */
846 u32 mc_latency = 2000; /* 2000 ns. */
847 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
848 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
849 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
850 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
851 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
852 (wm->num_heads * cursor_line_pair_return_time);
853 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
854 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
855 u32 tmp, dmif_size = 12288;
856 fixed20_12 a, b, c;
857
858 if (wm->num_heads == 0)
859 return 0;
860
861 a.full = dfixed_const(2);
862 b.full = dfixed_const(1);
863 if ((wm->vsc.full > a.full) ||
864 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
865 (wm->vtaps >= 5) ||
866 ((wm->vsc.full >= a.full) && wm->interlaced))
867 max_src_lines_per_dst_line = 4;
868 else
869 max_src_lines_per_dst_line = 2;
870
871 a.full = dfixed_const(available_bandwidth);
872 b.full = dfixed_const(wm->num_heads);
873 a.full = dfixed_div(a, b);
874 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
875 tmp = min(dfixed_trunc(a), tmp);
876
877 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
878
879 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
880 b.full = dfixed_const(1000);
881 c.full = dfixed_const(lb_fill_bw);
882 b.full = dfixed_div(c, b);
883 a.full = dfixed_div(a, b);
884 line_fill_time = dfixed_trunc(a);
885
886 if (line_fill_time < wm->active_time)
887 return latency;
888 else
889 return latency + (line_fill_time - wm->active_time);
890
891}
892
893/**
894 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
895 * average and available dram bandwidth
896 *
897 * @wm: watermark calculation data
898 *
899 * Check if the display average bandwidth fits in the display
900 * dram bandwidth (CIK).
901 * Used for display watermark bandwidth calculations
902 * Returns true if the display fits, false if not.
903 */
904static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
905{
906 if (dce_v8_0_average_bandwidth(wm) <=
907 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
908 return true;
909 else
910 return false;
911}
912
913/**
914 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
915 * average and available bandwidth
916 *
917 * @wm: watermark calculation data
918 *
919 * Check if the display average bandwidth fits in the display
920 * available bandwidth (CIK).
921 * Used for display watermark bandwidth calculations
922 * Returns true if the display fits, false if not.
923 */
924static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
925{
926 if (dce_v8_0_average_bandwidth(wm) <=
927 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
928 return true;
929 else
930 return false;
931}
932
933/**
934 * dce_v8_0_check_latency_hiding - check latency hiding
935 *
936 * @wm: watermark calculation data
937 *
938 * Check latency hiding (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns true if the display fits, false if not.
941 */
942static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
943{
944 u32 lb_partitions = wm->lb_size / wm->src_width;
945 u32 line_time = wm->active_time + wm->blank_time;
946 u32 latency_tolerant_lines;
947 u32 latency_hiding;
948 fixed20_12 a;
949
950 a.full = dfixed_const(1);
951 if (wm->vsc.full > a.full)
952 latency_tolerant_lines = 1;
953 else {
954 if (lb_partitions <= (wm->vtaps + 1))
955 latency_tolerant_lines = 1;
956 else
957 latency_tolerant_lines = 2;
958 }
959
960 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
961
962 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
963 return true;
964 else
965 return false;
966}
967
968/**
969 * dce_v8_0_program_watermarks - program display watermarks
970 *
971 * @adev: amdgpu_device pointer
972 * @amdgpu_crtc: the selected display controller
973 * @lb_size: line buffer size
974 * @num_heads: number of display controllers in use
975 *
976 * Calculate and program the display watermarks for the
977 * selected display controller (CIK).
978 */
979static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
980 struct amdgpu_crtc *amdgpu_crtc,
981 u32 lb_size, u32 num_heads)
982{
983 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
984 struct dce8_wm_params wm_low, wm_high;
985 u32 active_time;
986 u32 line_time = 0;
987 u32 latency_watermark_a = 0, latency_watermark_b = 0;
988 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
989
990 if (amdgpu_crtc->base.enabled && num_heads && mode) {
991 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
992 (u32)mode->clock);
993 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
994 (u32)mode->clock);
995 line_time = min_t(u32, line_time, 65535);
996
997 /* watermark for high clocks */
998 if (adev->pm.dpm_enabled) {
999 wm_high.yclk =
1000 amdgpu_dpm_get_mclk(adev, false) * 10;
1001 wm_high.sclk =
1002 amdgpu_dpm_get_sclk(adev, false) * 10;
1003 } else {
1004 wm_high.yclk = adev->pm.current_mclk * 10;
1005 wm_high.sclk = adev->pm.current_sclk * 10;
1006 }
1007
1008 wm_high.disp_clk = mode->clock;
1009 wm_high.src_width = mode->crtc_hdisplay;
1010 wm_high.active_time = active_time;
1011 wm_high.blank_time = line_time - wm_high.active_time;
1012 wm_high.interlaced = false;
1013 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1014 wm_high.interlaced = true;
1015 wm_high.vsc = amdgpu_crtc->vsc;
1016 wm_high.vtaps = 1;
1017 if (amdgpu_crtc->rmx_type != RMX_OFF)
1018 wm_high.vtaps = 2;
1019 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1020 wm_high.lb_size = lb_size;
1021 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1022 wm_high.num_heads = num_heads;
1023
1024 /* set for high clocks */
1025 latency_watermark_a = min_t(u32, dce_v8_0_latency_watermark(&wm_high), 65535);
1026
1027 /* possibly force display priority to high */
1028 /* should really do this at mode validation time... */
1029 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1030 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1031 !dce_v8_0_check_latency_hiding(&wm_high) ||
1032 (adev->mode_info.disp_priority == 2)) {
1033 DRM_DEBUG_KMS("force priority to high\n");
1034 }
1035
1036 /* watermark for low clocks */
1037 if (adev->pm.dpm_enabled) {
1038 wm_low.yclk =
1039 amdgpu_dpm_get_mclk(adev, true) * 10;
1040 wm_low.sclk =
1041 amdgpu_dpm_get_sclk(adev, true) * 10;
1042 } else {
1043 wm_low.yclk = adev->pm.current_mclk * 10;
1044 wm_low.sclk = adev->pm.current_sclk * 10;
1045 }
1046
1047 wm_low.disp_clk = mode->clock;
1048 wm_low.src_width = mode->crtc_hdisplay;
1049 wm_low.active_time = active_time;
1050 wm_low.blank_time = line_time - wm_low.active_time;
1051 wm_low.interlaced = false;
1052 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1053 wm_low.interlaced = true;
1054 wm_low.vsc = amdgpu_crtc->vsc;
1055 wm_low.vtaps = 1;
1056 if (amdgpu_crtc->rmx_type != RMX_OFF)
1057 wm_low.vtaps = 2;
1058 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1059 wm_low.lb_size = lb_size;
1060 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1061 wm_low.num_heads = num_heads;
1062
1063 /* set for low clocks */
1064 latency_watermark_b = min_t(u32, dce_v8_0_latency_watermark(&wm_low), 65535);
1065
1066 /* possibly force display priority to high */
1067 /* should really do this at mode validation time... */
1068 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1069 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1070 !dce_v8_0_check_latency_hiding(&wm_low) ||
1071 (adev->mode_info.disp_priority == 2)) {
1072 DRM_DEBUG_KMS("force priority to high\n");
1073 }
1074 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1075 }
1076
1077 /* select wm A */
1078 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1079 tmp = wm_mask;
1080 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1081 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1082 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1083 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1084 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1085 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1086 /* select wm B */
1087 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1088 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1089 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1090 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1091 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1092 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1093 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1094 /* restore original selection */
1095 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1096
1097 /* save values for DPM */
1098 amdgpu_crtc->line_time = line_time;
1099 amdgpu_crtc->wm_high = latency_watermark_a;
1100 amdgpu_crtc->wm_low = latency_watermark_b;
1101 /* Save number of lines the linebuffer leads before the scanout */
1102 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1103}
1104
1105/**
1106 * dce_v8_0_bandwidth_update - program display watermarks
1107 *
1108 * @adev: amdgpu_device pointer
1109 *
1110 * Calculate and program the display watermarks and line
1111 * buffer allocation (CIK).
1112 */
1113static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1114{
1115 struct drm_display_mode *mode = NULL;
1116 u32 num_heads = 0, lb_size;
1117 int i;
1118
1119 amdgpu_display_update_priority(adev);
1120
1121 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1122 if (adev->mode_info.crtcs[i]->base.enabled)
1123 num_heads++;
1124 }
1125 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1126 mode = &adev->mode_info.crtcs[i]->base.mode;
1127 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1128 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1129 lb_size, num_heads);
1130 }
1131}
1132
1133static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1134{
1135 int i;
1136 u32 offset, tmp;
1137
1138 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1139 offset = adev->mode_info.audio.pin[i].offset;
1140 tmp = RREG32_AUDIO_ENDPT(offset,
1141 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1142 if (((tmp &
1143 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1144 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1145 adev->mode_info.audio.pin[i].connected = false;
1146 else
1147 adev->mode_info.audio.pin[i].connected = true;
1148 }
1149}
1150
1151static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1152{
1153 int i;
1154
1155 dce_v8_0_audio_get_connected_pins(adev);
1156
1157 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1158 if (adev->mode_info.audio.pin[i].connected)
1159 return &adev->mode_info.audio.pin[i];
1160 }
1161 DRM_ERROR("No connected audio pins found!\n");
1162 return NULL;
1163}
1164
1165static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1166{
1167 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1168 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1169 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1170 u32 offset;
1171
1172 if (!dig || !dig->afmt || !dig->afmt->pin)
1173 return;
1174
1175 offset = dig->afmt->offset;
1176
1177 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1178 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1179}
1180
1181static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1182 struct drm_display_mode *mode)
1183{
1184 struct drm_device *dev = encoder->dev;
1185 struct amdgpu_device *adev = drm_to_adev(dev);
1186 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1187 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1188 struct drm_connector *connector;
1189 struct drm_connector_list_iter iter;
1190 struct amdgpu_connector *amdgpu_connector = NULL;
1191 u32 tmp = 0, offset;
1192
1193 if (!dig || !dig->afmt || !dig->afmt->pin)
1194 return;
1195
1196 offset = dig->afmt->pin->offset;
1197
1198 drm_connector_list_iter_begin(dev, &iter);
1199 drm_for_each_connector_iter(connector, &iter) {
1200 if (connector->encoder == encoder) {
1201 amdgpu_connector = to_amdgpu_connector(connector);
1202 break;
1203 }
1204 }
1205 drm_connector_list_iter_end(&iter);
1206
1207 if (!amdgpu_connector) {
1208 DRM_ERROR("Couldn't find encoder's connector\n");
1209 return;
1210 }
1211
1212 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1213 if (connector->latency_present[1])
1214 tmp =
1215 (connector->video_latency[1] <<
1216 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1217 (connector->audio_latency[1] <<
1218 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1219 else
1220 tmp =
1221 (0 <<
1222 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1223 (0 <<
1224 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1225 } else {
1226 if (connector->latency_present[0])
1227 tmp =
1228 (connector->video_latency[0] <<
1229 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1230 (connector->audio_latency[0] <<
1231 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1232 else
1233 tmp =
1234 (0 <<
1235 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1236 (0 <<
1237 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1238
1239 }
1240 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1241}
1242
1243static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1244{
1245 struct drm_device *dev = encoder->dev;
1246 struct amdgpu_device *adev = drm_to_adev(dev);
1247 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1248 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1249 struct drm_connector *connector;
1250 struct drm_connector_list_iter iter;
1251 struct amdgpu_connector *amdgpu_connector = NULL;
1252 u32 offset, tmp;
1253 u8 *sadb = NULL;
1254 int sad_count;
1255
1256 if (!dig || !dig->afmt || !dig->afmt->pin)
1257 return;
1258
1259 offset = dig->afmt->pin->offset;
1260
1261 drm_connector_list_iter_begin(dev, &iter);
1262 drm_for_each_connector_iter(connector, &iter) {
1263 if (connector->encoder == encoder) {
1264 amdgpu_connector = to_amdgpu_connector(connector);
1265 break;
1266 }
1267 }
1268 drm_connector_list_iter_end(&iter);
1269
1270 if (!amdgpu_connector) {
1271 DRM_ERROR("Couldn't find encoder's connector\n");
1272 return;
1273 }
1274
1275 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1276 if (sad_count < 0) {
1277 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1278 sad_count = 0;
1279 }
1280
1281 /* program the speaker allocation */
1282 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1283 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1284 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1285 /* set HDMI mode */
1286 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1287 if (sad_count)
1288 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1289 else
1290 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1291 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1292
1293 kfree(sadb);
1294}
1295
1296static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1297{
1298 struct drm_device *dev = encoder->dev;
1299 struct amdgpu_device *adev = drm_to_adev(dev);
1300 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1301 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1302 u32 offset;
1303 struct drm_connector *connector;
1304 struct drm_connector_list_iter iter;
1305 struct amdgpu_connector *amdgpu_connector = NULL;
1306 struct cea_sad *sads;
1307 int i, sad_count;
1308
1309 static const u16 eld_reg_to_type[][2] = {
1310 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1311 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1312 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1313 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1314 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1315 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1316 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1319 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1320 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1321 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1322 };
1323
1324 if (!dig || !dig->afmt || !dig->afmt->pin)
1325 return;
1326
1327 offset = dig->afmt->pin->offset;
1328
1329 drm_connector_list_iter_begin(dev, &iter);
1330 drm_for_each_connector_iter(connector, &iter) {
1331 if (connector->encoder == encoder) {
1332 amdgpu_connector = to_amdgpu_connector(connector);
1333 break;
1334 }
1335 }
1336 drm_connector_list_iter_end(&iter);
1337
1338 if (!amdgpu_connector) {
1339 DRM_ERROR("Couldn't find encoder's connector\n");
1340 return;
1341 }
1342
1343 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1344 if (sad_count < 0)
1345 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1346 if (sad_count <= 0)
1347 return;
1348 BUG_ON(!sads);
1349
1350 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1351 u32 value = 0;
1352 u8 stereo_freqs = 0;
1353 int max_channels = -1;
1354 int j;
1355
1356 for (j = 0; j < sad_count; j++) {
1357 struct cea_sad *sad = &sads[j];
1358
1359 if (sad->format == eld_reg_to_type[i][1]) {
1360 if (sad->channels > max_channels) {
1361 value = (sad->channels <<
1362 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1363 (sad->byte2 <<
1364 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1365 (sad->freq <<
1366 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1367 max_channels = sad->channels;
1368 }
1369
1370 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1371 stereo_freqs |= sad->freq;
1372 else
1373 break;
1374 }
1375 }
1376
1377 value |= (stereo_freqs <<
1378 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1379
1380 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1381 }
1382
1383 kfree(sads);
1384}
1385
1386static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1387 struct amdgpu_audio_pin *pin,
1388 bool enable)
1389{
1390 if (!pin)
1391 return;
1392
1393 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1394 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1395}
1396
1397static const u32 pin_offsets[7] = {
1398 (0x1780 - 0x1780),
1399 (0x1786 - 0x1780),
1400 (0x178c - 0x1780),
1401 (0x1792 - 0x1780),
1402 (0x1798 - 0x1780),
1403 (0x179d - 0x1780),
1404 (0x17a4 - 0x1780),
1405};
1406
1407static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1408{
1409 int i;
1410
1411 if (!amdgpu_audio)
1412 return 0;
1413
1414 adev->mode_info.audio.enabled = true;
1415
1416 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1417 adev->mode_info.audio.num_pins = 7;
1418 else if ((adev->asic_type == CHIP_KABINI) ||
1419 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1420 adev->mode_info.audio.num_pins = 3;
1421 else if ((adev->asic_type == CHIP_BONAIRE) ||
1422 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1423 adev->mode_info.audio.num_pins = 7;
1424 else
1425 adev->mode_info.audio.num_pins = 3;
1426
1427 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1428 adev->mode_info.audio.pin[i].channels = -1;
1429 adev->mode_info.audio.pin[i].rate = -1;
1430 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1431 adev->mode_info.audio.pin[i].status_bits = 0;
1432 adev->mode_info.audio.pin[i].category_code = 0;
1433 adev->mode_info.audio.pin[i].connected = false;
1434 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1435 adev->mode_info.audio.pin[i].id = i;
1436 /* disable audio. it will be set up later */
1437 /* XXX remove once we switch to ip funcs */
1438 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1439 }
1440
1441 return 0;
1442}
1443
1444static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1445{
1446 int i;
1447
1448 if (!amdgpu_audio)
1449 return;
1450
1451 if (!adev->mode_info.audio.enabled)
1452 return;
1453
1454 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1455 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1456
1457 adev->mode_info.audio.enabled = false;
1458}
1459
1460/*
1461 * update the N and CTS parameters for a given pixel clock rate
1462 */
1463static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1464{
1465 struct drm_device *dev = encoder->dev;
1466 struct amdgpu_device *adev = drm_to_adev(dev);
1467 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1468 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1469 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1470 uint32_t offset = dig->afmt->offset;
1471
1472 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1473 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1474
1475 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1476 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1477
1478 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1479 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1480}
1481
1482/*
1483 * build a HDMI Video Info Frame
1484 */
1485static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1486 void *buffer, size_t size)
1487{
1488 struct drm_device *dev = encoder->dev;
1489 struct amdgpu_device *adev = drm_to_adev(dev);
1490 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1491 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1492 uint32_t offset = dig->afmt->offset;
1493 uint8_t *frame = buffer + 3;
1494 uint8_t *header = buffer;
1495
1496 WREG32(mmAFMT_AVI_INFO0 + offset,
1497 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1498 WREG32(mmAFMT_AVI_INFO1 + offset,
1499 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1500 WREG32(mmAFMT_AVI_INFO2 + offset,
1501 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1502 WREG32(mmAFMT_AVI_INFO3 + offset,
1503 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1504}
1505
1506static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1507{
1508 struct drm_device *dev = encoder->dev;
1509 struct amdgpu_device *adev = drm_to_adev(dev);
1510 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1511 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1513 u32 dto_phase = 24 * 1000;
1514 u32 dto_modulo = clock;
1515
1516 if (!dig || !dig->afmt)
1517 return;
1518
1519 /* XXX two dtos; generally use dto0 for hdmi */
1520 /* Express [24MHz / target pixel clock] as an exact rational
1521 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1522 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1523 */
1524 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1525 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1526 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1527}
1528
1529/*
1530 * update the info frames with the data from the current display mode
1531 */
1532static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1533 struct drm_display_mode *mode)
1534{
1535 struct drm_device *dev = encoder->dev;
1536 struct amdgpu_device *adev = drm_to_adev(dev);
1537 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1538 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1539 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1540 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1541 struct hdmi_avi_infoframe frame;
1542 uint32_t offset, val;
1543 ssize_t err;
1544 int bpc = 8;
1545
1546 if (!dig || !dig->afmt)
1547 return;
1548
1549 /* Silent, r600_hdmi_enable will raise WARN for us */
1550 if (!dig->afmt->enabled)
1551 return;
1552
1553 offset = dig->afmt->offset;
1554
1555 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1556 if (encoder->crtc) {
1557 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1558 bpc = amdgpu_crtc->bpc;
1559 }
1560
1561 /* disable audio prior to setting up hw */
1562 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1563 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1564
1565 dce_v8_0_audio_set_dto(encoder, mode->clock);
1566
1567 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1568 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1569
1570 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1571
1572 val = RREG32(mmHDMI_CONTROL + offset);
1573 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1574 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1575
1576 switch (bpc) {
1577 case 0:
1578 case 6:
1579 case 8:
1580 case 16:
1581 default:
1582 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1583 connector->name, bpc);
1584 break;
1585 case 10:
1586 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1587 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1588 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1589 connector->name);
1590 break;
1591 case 12:
1592 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1593 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1594 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1595 connector->name);
1596 break;
1597 }
1598
1599 WREG32(mmHDMI_CONTROL + offset, val);
1600
1601 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1602 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1603 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1604 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1605
1606 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1607 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1608 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1609
1610 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1611 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1612
1613 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1614 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1615
1616 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1617
1618 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1619 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1620 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1621
1622 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1623 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1624
1625 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1626
1627 if (bpc > 8)
1628 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1629 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1630 else
1631 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1632 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1633 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1634
1635 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1636
1637 WREG32(mmAFMT_60958_0 + offset,
1638 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1639
1640 WREG32(mmAFMT_60958_1 + offset,
1641 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1642
1643 WREG32(mmAFMT_60958_2 + offset,
1644 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1645 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1646 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1647 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1648 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1649 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1650
1651 dce_v8_0_audio_write_speaker_allocation(encoder);
1652
1653
1654 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1655 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1656
1657 dce_v8_0_afmt_audio_select_pin(encoder);
1658 dce_v8_0_audio_write_sad_regs(encoder);
1659 dce_v8_0_audio_write_latency_fields(encoder, mode);
1660
1661 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1662 if (err < 0) {
1663 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1664 return;
1665 }
1666
1667 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1668 if (err < 0) {
1669 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1670 return;
1671 }
1672
1673 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1674
1675 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1676 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1677 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1678
1679 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1680 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1681 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1682
1683 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1684 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1685
1686 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1687 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1688 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1689 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1690
1691 /* enable audio after setting up hw */
1692 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1693}
1694
1695static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1696{
1697 struct drm_device *dev = encoder->dev;
1698 struct amdgpu_device *adev = drm_to_adev(dev);
1699 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1700 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1701
1702 if (!dig || !dig->afmt)
1703 return;
1704
1705 /* Silent, r600_hdmi_enable will raise WARN for us */
1706 if (enable && dig->afmt->enabled)
1707 return;
1708 if (!enable && !dig->afmt->enabled)
1709 return;
1710
1711 if (!enable && dig->afmt->pin) {
1712 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1713 dig->afmt->pin = NULL;
1714 }
1715
1716 dig->afmt->enabled = enable;
1717
1718 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1719 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1720}
1721
1722static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1723{
1724 int i;
1725
1726 for (i = 0; i < adev->mode_info.num_dig; i++)
1727 adev->mode_info.afmt[i] = NULL;
1728
1729 /* DCE8 has audio blocks tied to DIG encoders */
1730 for (i = 0; i < adev->mode_info.num_dig; i++) {
1731 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1732 if (adev->mode_info.afmt[i]) {
1733 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1734 adev->mode_info.afmt[i]->id = i;
1735 } else {
1736 int j;
1737 for (j = 0; j < i; j++) {
1738 kfree(adev->mode_info.afmt[j]);
1739 adev->mode_info.afmt[j] = NULL;
1740 }
1741 return -ENOMEM;
1742 }
1743 }
1744 return 0;
1745}
1746
1747static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1748{
1749 int i;
1750
1751 for (i = 0; i < adev->mode_info.num_dig; i++) {
1752 kfree(adev->mode_info.afmt[i]);
1753 adev->mode_info.afmt[i] = NULL;
1754 }
1755}
1756
1757static const u32 vga_control_regs[6] = {
1758 mmD1VGA_CONTROL,
1759 mmD2VGA_CONTROL,
1760 mmD3VGA_CONTROL,
1761 mmD4VGA_CONTROL,
1762 mmD5VGA_CONTROL,
1763 mmD6VGA_CONTROL,
1764};
1765
1766static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1767{
1768 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1769 struct drm_device *dev = crtc->dev;
1770 struct amdgpu_device *adev = drm_to_adev(dev);
1771 u32 vga_control;
1772
1773 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1774 if (enable)
1775 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1776 else
1777 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1778}
1779
1780static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1781{
1782 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1783 struct drm_device *dev = crtc->dev;
1784 struct amdgpu_device *adev = drm_to_adev(dev);
1785
1786 if (enable)
1787 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1788 else
1789 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1790}
1791
1792static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1793 struct drm_framebuffer *fb,
1794 int x, int y, int atomic)
1795{
1796 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1797 struct drm_device *dev = crtc->dev;
1798 struct amdgpu_device *adev = drm_to_adev(dev);
1799 struct drm_framebuffer *target_fb;
1800 struct drm_gem_object *obj;
1801 struct amdgpu_bo *abo;
1802 uint64_t fb_location, tiling_flags;
1803 uint32_t fb_format, fb_pitch_pixels;
1804 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1805 u32 pipe_config;
1806 u32 viewport_w, viewport_h;
1807 int r;
1808 bool bypass_lut = false;
1809
1810 /* no fb bound */
1811 if (!atomic && !crtc->primary->fb) {
1812 DRM_DEBUG_KMS("No FB bound\n");
1813 return 0;
1814 }
1815
1816 if (atomic)
1817 target_fb = fb;
1818 else
1819 target_fb = crtc->primary->fb;
1820
1821 /* If atomic, assume fb object is pinned & idle & fenced and
1822 * just update base pointers
1823 */
1824 obj = target_fb->obj[0];
1825 abo = gem_to_amdgpu_bo(obj);
1826 r = amdgpu_bo_reserve(abo, false);
1827 if (unlikely(r != 0))
1828 return r;
1829
1830 if (!atomic) {
1831 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1832 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1833 if (unlikely(r != 0)) {
1834 amdgpu_bo_unreserve(abo);
1835 return -EINVAL;
1836 }
1837 }
1838 fb_location = amdgpu_bo_gpu_offset(abo);
1839
1840 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1841 amdgpu_bo_unreserve(abo);
1842
1843 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1844
1845 switch (target_fb->format->format) {
1846 case DRM_FORMAT_C8:
1847 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1848 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1849 break;
1850 case DRM_FORMAT_XRGB4444:
1851 case DRM_FORMAT_ARGB4444:
1852 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1853 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1854#ifdef __BIG_ENDIAN
1855 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1856#endif
1857 break;
1858 case DRM_FORMAT_XRGB1555:
1859 case DRM_FORMAT_ARGB1555:
1860 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1861 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1862#ifdef __BIG_ENDIAN
1863 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1864#endif
1865 break;
1866 case DRM_FORMAT_BGRX5551:
1867 case DRM_FORMAT_BGRA5551:
1868 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1869 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1870#ifdef __BIG_ENDIAN
1871 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1872#endif
1873 break;
1874 case DRM_FORMAT_RGB565:
1875 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1876 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1877#ifdef __BIG_ENDIAN
1878 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1879#endif
1880 break;
1881 case DRM_FORMAT_XRGB8888:
1882 case DRM_FORMAT_ARGB8888:
1883 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1884 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1885#ifdef __BIG_ENDIAN
1886 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1887#endif
1888 break;
1889 case DRM_FORMAT_XRGB2101010:
1890 case DRM_FORMAT_ARGB2101010:
1891 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1892 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1893#ifdef __BIG_ENDIAN
1894 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1895#endif
1896 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1897 bypass_lut = true;
1898 break;
1899 case DRM_FORMAT_BGRX1010102:
1900 case DRM_FORMAT_BGRA1010102:
1901 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1902 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1903#ifdef __BIG_ENDIAN
1904 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1905#endif
1906 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1907 bypass_lut = true;
1908 break;
1909 case DRM_FORMAT_XBGR8888:
1910 case DRM_FORMAT_ABGR8888:
1911 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1912 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1913 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1914 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1915#ifdef __BIG_ENDIAN
1916 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1917#endif
1918 break;
1919 default:
1920 DRM_ERROR("Unsupported screen format %p4cc\n",
1921 &target_fb->format->format);
1922 return -EINVAL;
1923 }
1924
1925 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1926 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1927
1928 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1929 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1930 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1931 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1932 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1933
1934 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1935 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1936 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1937 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1938 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1939 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1940 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1941 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1942 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1943 }
1944
1945 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1946
1947 dce_v8_0_vga_enable(crtc, false);
1948
1949 /* Make sure surface address is updated at vertical blank rather than
1950 * horizontal blank
1951 */
1952 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1953
1954 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1955 upper_32_bits(fb_location));
1956 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1957 upper_32_bits(fb_location));
1958 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1959 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1960 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1961 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1962 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1963 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1964
1965 /*
1966 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1967 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1968 * retain the full precision throughout the pipeline.
1969 */
1970 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1971 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1972 ~LUT_10BIT_BYPASS_EN);
1973
1974 if (bypass_lut)
1975 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1976
1977 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1978 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1979 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1980 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1981 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1982 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1983
1984 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1985 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1986
1987 dce_v8_0_grph_enable(crtc, true);
1988
1989 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1990 target_fb->height);
1991
1992 x &= ~3;
1993 y &= ~1;
1994 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1995 (x << 16) | y);
1996 viewport_w = crtc->mode.hdisplay;
1997 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1998 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1999 (viewport_w << 16) | viewport_h);
2000
2001 /* set pageflip to happen anywhere in vblank interval */
2002 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2003
2004 if (!atomic && fb && fb != crtc->primary->fb) {
2005 abo = gem_to_amdgpu_bo(fb->obj[0]);
2006 r = amdgpu_bo_reserve(abo, true);
2007 if (unlikely(r != 0))
2008 return r;
2009 amdgpu_bo_unpin(abo);
2010 amdgpu_bo_unreserve(abo);
2011 }
2012
2013 /* Bytes per pixel may have changed */
2014 dce_v8_0_bandwidth_update(adev);
2015
2016 return 0;
2017}
2018
2019static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2020 struct drm_display_mode *mode)
2021{
2022 struct drm_device *dev = crtc->dev;
2023 struct amdgpu_device *adev = drm_to_adev(dev);
2024 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2025
2026 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2027 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2028 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2029 else
2030 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2031}
2032
2033static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2034{
2035 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2036 struct drm_device *dev = crtc->dev;
2037 struct amdgpu_device *adev = drm_to_adev(dev);
2038 u16 *r, *g, *b;
2039 int i;
2040
2041 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2042
2043 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2044 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2045 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2046 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2047 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2048 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2049 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2050 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2051 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2052 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2053
2054 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2055
2056 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2057 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2058 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2059
2060 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2061 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2062 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2063
2064 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2065 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2066
2067 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2068 r = crtc->gamma_store;
2069 g = r + crtc->gamma_size;
2070 b = g + crtc->gamma_size;
2071 for (i = 0; i < 256; i++) {
2072 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2073 ((*r++ & 0xffc0) << 14) |
2074 ((*g++ & 0xffc0) << 4) |
2075 (*b++ >> 6));
2076 }
2077
2078 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2079 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2080 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2081 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2082 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2083 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2084 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2085 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2086 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2087 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2088 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2089 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2090 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2091 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2092 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2093 /* XXX this only needs to be programmed once per crtc at startup,
2094 * not sure where the best place for it is
2095 */
2096 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2097 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2098}
2099
2100static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2101{
2102 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2103 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2104
2105 switch (amdgpu_encoder->encoder_id) {
2106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2107 if (dig->linkb)
2108 return 1;
2109 else
2110 return 0;
2111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2112 if (dig->linkb)
2113 return 3;
2114 else
2115 return 2;
2116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2117 if (dig->linkb)
2118 return 5;
2119 else
2120 return 4;
2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2122 return 6;
2123 default:
2124 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2125 return 0;
2126 }
2127}
2128
2129/**
2130 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2131 *
2132 * @crtc: drm crtc
2133 *
2134 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2135 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2136 * monitors a dedicated PPLL must be used. If a particular board has
2137 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2138 * as there is no need to program the PLL itself. If we are not able to
2139 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2140 * avoid messing up an existing monitor.
2141 *
2142 * Asic specific PLL information
2143 *
2144 * DCE 8.x
2145 * KB/KV
2146 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2147 * CI
2148 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2149 *
2150 */
2151static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2152{
2153 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2154 struct drm_device *dev = crtc->dev;
2155 struct amdgpu_device *adev = drm_to_adev(dev);
2156 u32 pll_in_use;
2157 int pll;
2158
2159 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2160 if (adev->clock.dp_extclk)
2161 /* skip PPLL programming if using ext clock */
2162 return ATOM_PPLL_INVALID;
2163 else {
2164 /* use the same PPLL for all DP monitors */
2165 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2166 if (pll != ATOM_PPLL_INVALID)
2167 return pll;
2168 }
2169 } else {
2170 /* use the same PPLL for all monitors with the same clock */
2171 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2172 if (pll != ATOM_PPLL_INVALID)
2173 return pll;
2174 }
2175 /* otherwise, pick one of the plls */
2176 if ((adev->asic_type == CHIP_KABINI) ||
2177 (adev->asic_type == CHIP_MULLINS)) {
2178 /* KB/ML has PPLL1 and PPLL2 */
2179 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2180 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2181 return ATOM_PPLL2;
2182 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2183 return ATOM_PPLL1;
2184 DRM_ERROR("unable to allocate a PPLL\n");
2185 return ATOM_PPLL_INVALID;
2186 } else {
2187 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2188 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2189 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2190 return ATOM_PPLL2;
2191 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2192 return ATOM_PPLL1;
2193 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2194 return ATOM_PPLL0;
2195 DRM_ERROR("unable to allocate a PPLL\n");
2196 return ATOM_PPLL_INVALID;
2197 }
2198 return ATOM_PPLL_INVALID;
2199}
2200
2201static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2202{
2203 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2204 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2205 uint32_t cur_lock;
2206
2207 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2208 if (lock)
2209 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2210 else
2211 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2212 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2213}
2214
2215static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2216{
2217 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2218 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2219
2220 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2221 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2222 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2223}
2224
2225static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2226{
2227 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2228 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2229
2230 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2231 upper_32_bits(amdgpu_crtc->cursor_addr));
2232 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2233 lower_32_bits(amdgpu_crtc->cursor_addr));
2234
2235 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2236 CUR_CONTROL__CURSOR_EN_MASK |
2237 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2238 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2239}
2240
2241static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2242 int x, int y)
2243{
2244 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2245 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2246 int xorigin = 0, yorigin = 0;
2247
2248 amdgpu_crtc->cursor_x = x;
2249 amdgpu_crtc->cursor_y = y;
2250
2251 /* avivo cursor are offset into the total surface */
2252 x += crtc->x;
2253 y += crtc->y;
2254 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2255
2256 if (x < 0) {
2257 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2258 x = 0;
2259 }
2260 if (y < 0) {
2261 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2262 y = 0;
2263 }
2264
2265 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2266 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2267 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2268 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2269
2270 return 0;
2271}
2272
2273static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2274 int x, int y)
2275{
2276 int ret;
2277
2278 dce_v8_0_lock_cursor(crtc, true);
2279 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2280 dce_v8_0_lock_cursor(crtc, false);
2281
2282 return ret;
2283}
2284
2285static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2286 struct drm_file *file_priv,
2287 uint32_t handle,
2288 uint32_t width,
2289 uint32_t height,
2290 int32_t hot_x,
2291 int32_t hot_y)
2292{
2293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2294 struct drm_gem_object *obj;
2295 struct amdgpu_bo *aobj;
2296 int ret;
2297
2298 if (!handle) {
2299 /* turn off cursor */
2300 dce_v8_0_hide_cursor(crtc);
2301 obj = NULL;
2302 goto unpin;
2303 }
2304
2305 if ((width > amdgpu_crtc->max_cursor_width) ||
2306 (height > amdgpu_crtc->max_cursor_height)) {
2307 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2308 return -EINVAL;
2309 }
2310
2311 obj = drm_gem_object_lookup(file_priv, handle);
2312 if (!obj) {
2313 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2314 return -ENOENT;
2315 }
2316
2317 aobj = gem_to_amdgpu_bo(obj);
2318 ret = amdgpu_bo_reserve(aobj, false);
2319 if (ret != 0) {
2320 drm_gem_object_put(obj);
2321 return ret;
2322 }
2323
2324 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2325 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2326 amdgpu_bo_unreserve(aobj);
2327 if (ret) {
2328 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2329 drm_gem_object_put(obj);
2330 return ret;
2331 }
2332 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2333
2334 dce_v8_0_lock_cursor(crtc, true);
2335
2336 if (width != amdgpu_crtc->cursor_width ||
2337 height != amdgpu_crtc->cursor_height ||
2338 hot_x != amdgpu_crtc->cursor_hot_x ||
2339 hot_y != amdgpu_crtc->cursor_hot_y) {
2340 int x, y;
2341
2342 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2343 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2344
2345 dce_v8_0_cursor_move_locked(crtc, x, y);
2346
2347 amdgpu_crtc->cursor_width = width;
2348 amdgpu_crtc->cursor_height = height;
2349 amdgpu_crtc->cursor_hot_x = hot_x;
2350 amdgpu_crtc->cursor_hot_y = hot_y;
2351 }
2352
2353 dce_v8_0_show_cursor(crtc);
2354 dce_v8_0_lock_cursor(crtc, false);
2355
2356unpin:
2357 if (amdgpu_crtc->cursor_bo) {
2358 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2359 ret = amdgpu_bo_reserve(aobj, true);
2360 if (likely(ret == 0)) {
2361 amdgpu_bo_unpin(aobj);
2362 amdgpu_bo_unreserve(aobj);
2363 }
2364 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2365 }
2366
2367 amdgpu_crtc->cursor_bo = obj;
2368 return 0;
2369}
2370
2371static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2372{
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374
2375 if (amdgpu_crtc->cursor_bo) {
2376 dce_v8_0_lock_cursor(crtc, true);
2377
2378 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2379 amdgpu_crtc->cursor_y);
2380
2381 dce_v8_0_show_cursor(crtc);
2382
2383 dce_v8_0_lock_cursor(crtc, false);
2384 }
2385}
2386
2387static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2388 u16 *blue, uint32_t size,
2389 struct drm_modeset_acquire_ctx *ctx)
2390{
2391 dce_v8_0_crtc_load_lut(crtc);
2392
2393 return 0;
2394}
2395
2396static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2397{
2398 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2399
2400 drm_crtc_cleanup(crtc);
2401 kfree(amdgpu_crtc);
2402}
2403
2404static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2405 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2406 .cursor_move = dce_v8_0_crtc_cursor_move,
2407 .gamma_set = dce_v8_0_crtc_gamma_set,
2408 .set_config = amdgpu_display_crtc_set_config,
2409 .destroy = dce_v8_0_crtc_destroy,
2410 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2411 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2412 .enable_vblank = amdgpu_enable_vblank_kms,
2413 .disable_vblank = amdgpu_disable_vblank_kms,
2414 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2415};
2416
2417static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2418{
2419 struct drm_device *dev = crtc->dev;
2420 struct amdgpu_device *adev = drm_to_adev(dev);
2421 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2422 unsigned type;
2423
2424 switch (mode) {
2425 case DRM_MODE_DPMS_ON:
2426 amdgpu_crtc->enabled = true;
2427 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2428 dce_v8_0_vga_enable(crtc, true);
2429 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2430 dce_v8_0_vga_enable(crtc, false);
2431 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2432 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2433 amdgpu_crtc->crtc_id);
2434 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2435 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2436 drm_crtc_vblank_on(crtc);
2437 dce_v8_0_crtc_load_lut(crtc);
2438 break;
2439 case DRM_MODE_DPMS_STANDBY:
2440 case DRM_MODE_DPMS_SUSPEND:
2441 case DRM_MODE_DPMS_OFF:
2442 drm_crtc_vblank_off(crtc);
2443 if (amdgpu_crtc->enabled) {
2444 dce_v8_0_vga_enable(crtc, true);
2445 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2446 dce_v8_0_vga_enable(crtc, false);
2447 }
2448 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2449 amdgpu_crtc->enabled = false;
2450 break;
2451 }
2452 /* adjust pm to dpms */
2453 amdgpu_dpm_compute_clocks(adev);
2454}
2455
2456static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2457{
2458 /* disable crtc pair power gating before programming */
2459 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2460 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2461 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2462}
2463
2464static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2465{
2466 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2467 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2468}
2469
2470static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2471{
2472 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2473 struct drm_device *dev = crtc->dev;
2474 struct amdgpu_device *adev = drm_to_adev(dev);
2475 struct amdgpu_atom_ss ss;
2476 int i;
2477
2478 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2479 if (crtc->primary->fb) {
2480 int r;
2481 struct amdgpu_bo *abo;
2482
2483 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2484 r = amdgpu_bo_reserve(abo, true);
2485 if (unlikely(r))
2486 DRM_ERROR("failed to reserve abo before unpin\n");
2487 else {
2488 amdgpu_bo_unpin(abo);
2489 amdgpu_bo_unreserve(abo);
2490 }
2491 }
2492 /* disable the GRPH */
2493 dce_v8_0_grph_enable(crtc, false);
2494
2495 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2496
2497 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2498 if (adev->mode_info.crtcs[i] &&
2499 adev->mode_info.crtcs[i]->enabled &&
2500 i != amdgpu_crtc->crtc_id &&
2501 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2502 /* one other crtc is using this pll don't turn
2503 * off the pll
2504 */
2505 goto done;
2506 }
2507 }
2508
2509 switch (amdgpu_crtc->pll_id) {
2510 case ATOM_PPLL1:
2511 case ATOM_PPLL2:
2512 /* disable the ppll */
2513 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2514 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2515 break;
2516 case ATOM_PPLL0:
2517 /* disable the ppll */
2518 if ((adev->asic_type == CHIP_KAVERI) ||
2519 (adev->asic_type == CHIP_BONAIRE) ||
2520 (adev->asic_type == CHIP_HAWAII))
2521 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2522 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2523 break;
2524 default:
2525 break;
2526 }
2527done:
2528 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2529 amdgpu_crtc->adjusted_clock = 0;
2530 amdgpu_crtc->encoder = NULL;
2531 amdgpu_crtc->connector = NULL;
2532}
2533
2534static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2535 struct drm_display_mode *mode,
2536 struct drm_display_mode *adjusted_mode,
2537 int x, int y, struct drm_framebuffer *old_fb)
2538{
2539 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2540
2541 if (!amdgpu_crtc->adjusted_clock)
2542 return -EINVAL;
2543
2544 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2545 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2546 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2547 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2548 amdgpu_atombios_crtc_scaler_setup(crtc);
2549 dce_v8_0_cursor_reset(crtc);
2550 /* update the hw version fpr dpm */
2551 amdgpu_crtc->hw_mode = *adjusted_mode;
2552
2553 return 0;
2554}
2555
2556static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2557 const struct drm_display_mode *mode,
2558 struct drm_display_mode *adjusted_mode)
2559{
2560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_encoder *encoder;
2563
2564 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2565 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2566 if (encoder->crtc == crtc) {
2567 amdgpu_crtc->encoder = encoder;
2568 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2569 break;
2570 }
2571 }
2572 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2573 amdgpu_crtc->encoder = NULL;
2574 amdgpu_crtc->connector = NULL;
2575 return false;
2576 }
2577 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2578 return false;
2579 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2580 return false;
2581 /* pick pll */
2582 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2583 /* if we can't get a PPLL for a non-DP encoder, fail */
2584 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2585 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2586 return false;
2587
2588 return true;
2589}
2590
2591static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2592 struct drm_framebuffer *old_fb)
2593{
2594 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2595}
2596
2597static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2598 struct drm_framebuffer *fb,
2599 int x, int y, enum mode_set_atomic state)
2600{
2601 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2602}
2603
2604static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2605 .dpms = dce_v8_0_crtc_dpms,
2606 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2607 .mode_set = dce_v8_0_crtc_mode_set,
2608 .mode_set_base = dce_v8_0_crtc_set_base,
2609 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2610 .prepare = dce_v8_0_crtc_prepare,
2611 .commit = dce_v8_0_crtc_commit,
2612 .disable = dce_v8_0_crtc_disable,
2613 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2614};
2615
2616static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2617{
2618 struct amdgpu_crtc *amdgpu_crtc;
2619
2620 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2621 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2622 if (amdgpu_crtc == NULL)
2623 return -ENOMEM;
2624
2625 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2626
2627 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2628 amdgpu_crtc->crtc_id = index;
2629 adev->mode_info.crtcs[index] = amdgpu_crtc;
2630
2631 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2632 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2633 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2634 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2635
2636 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2637
2638 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2639 amdgpu_crtc->adjusted_clock = 0;
2640 amdgpu_crtc->encoder = NULL;
2641 amdgpu_crtc->connector = NULL;
2642 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2643
2644 return 0;
2645}
2646
2647static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block)
2648{
2649 struct amdgpu_device *adev = ip_block->adev;
2650
2651 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2652 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2653
2654 dce_v8_0_set_display_funcs(adev);
2655
2656 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2657
2658 switch (adev->asic_type) {
2659 case CHIP_BONAIRE:
2660 case CHIP_HAWAII:
2661 adev->mode_info.num_hpd = 6;
2662 adev->mode_info.num_dig = 6;
2663 break;
2664 case CHIP_KAVERI:
2665 adev->mode_info.num_hpd = 6;
2666 adev->mode_info.num_dig = 7;
2667 break;
2668 case CHIP_KABINI:
2669 case CHIP_MULLINS:
2670 adev->mode_info.num_hpd = 6;
2671 adev->mode_info.num_dig = 6; /* ? */
2672 break;
2673 default:
2674 /* FIXME: not supported yet */
2675 return -EINVAL;
2676 }
2677
2678 dce_v8_0_set_irq_funcs(adev);
2679
2680 return 0;
2681}
2682
2683static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block)
2684{
2685 int r, i;
2686 struct amdgpu_device *adev = ip_block->adev;
2687
2688 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2689 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2690 if (r)
2691 return r;
2692 }
2693
2694 for (i = 8; i < 20; i += 2) {
2695 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2696 if (r)
2697 return r;
2698 }
2699
2700 /* HPD hotplug */
2701 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2702 if (r)
2703 return r;
2704
2705 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2706
2707 adev_to_drm(adev)->mode_config.async_page_flip = true;
2708
2709 adev_to_drm(adev)->mode_config.max_width = 16384;
2710 adev_to_drm(adev)->mode_config.max_height = 16384;
2711
2712 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2713 if (adev->asic_type == CHIP_HAWAII)
2714 /* disable prefer shadow for now due to hibernation issues */
2715 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
2716 else
2717 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2718
2719 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2720
2721 r = amdgpu_display_modeset_create_props(adev);
2722 if (r)
2723 return r;
2724
2725 adev_to_drm(adev)->mode_config.max_width = 16384;
2726 adev_to_drm(adev)->mode_config.max_height = 16384;
2727
2728 /* allocate crtcs */
2729 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2730 r = dce_v8_0_crtc_init(adev, i);
2731 if (r)
2732 return r;
2733 }
2734
2735 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2736 amdgpu_display_print_display_setup(adev_to_drm(adev));
2737 else
2738 return -EINVAL;
2739
2740 /* setup afmt */
2741 r = dce_v8_0_afmt_init(adev);
2742 if (r)
2743 return r;
2744
2745 r = dce_v8_0_audio_init(adev);
2746 if (r)
2747 return r;
2748
2749 /* Disable vblank IRQs aggressively for power-saving */
2750 /* XXX: can this be enabled for DC? */
2751 adev_to_drm(adev)->vblank_disable_immediate = true;
2752
2753 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2754 if (r)
2755 return r;
2756
2757 /* Pre-DCE11 */
2758 INIT_DELAYED_WORK(&adev->hotplug_work,
2759 amdgpu_display_hotplug_work_func);
2760
2761 drm_kms_helper_poll_init(adev_to_drm(adev));
2762
2763 adev->mode_info.mode_config_initialized = true;
2764 return 0;
2765}
2766
2767static int dce_v8_0_sw_fini(struct amdgpu_ip_block *ip_block)
2768{
2769 struct amdgpu_device *adev = ip_block->adev;
2770
2771 drm_edid_free(adev->mode_info.bios_hardcoded_edid);
2772
2773 drm_kms_helper_poll_fini(adev_to_drm(adev));
2774
2775 dce_v8_0_audio_fini(adev);
2776
2777 dce_v8_0_afmt_fini(adev);
2778
2779 drm_mode_config_cleanup(adev_to_drm(adev));
2780 adev->mode_info.mode_config_initialized = false;
2781
2782 return 0;
2783}
2784
2785static int dce_v8_0_hw_init(struct amdgpu_ip_block *ip_block)
2786{
2787 int i;
2788 struct amdgpu_device *adev = ip_block->adev;
2789
2790 /* disable vga render */
2791 dce_v8_0_set_vga_render_state(adev, false);
2792 /* init dig PHYs, disp eng pll */
2793 amdgpu_atombios_encoder_init_dig(adev);
2794 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2795
2796 /* initialize hpd */
2797 dce_v8_0_hpd_init(adev);
2798
2799 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2800 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2801 }
2802
2803 dce_v8_0_pageflip_interrupt_init(adev);
2804
2805 return 0;
2806}
2807
2808static int dce_v8_0_hw_fini(struct amdgpu_ip_block *ip_block)
2809{
2810 int i;
2811 struct amdgpu_device *adev = ip_block->adev;
2812
2813 dce_v8_0_hpd_fini(adev);
2814
2815 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2816 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2817 }
2818
2819 dce_v8_0_pageflip_interrupt_fini(adev);
2820
2821 flush_delayed_work(&adev->hotplug_work);
2822
2823 return 0;
2824}
2825
2826static int dce_v8_0_suspend(struct amdgpu_ip_block *ip_block)
2827{
2828 struct amdgpu_device *adev = ip_block->adev;
2829 int r;
2830
2831 r = amdgpu_display_suspend_helper(adev);
2832 if (r)
2833 return r;
2834
2835 adev->mode_info.bl_level =
2836 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2837
2838 return dce_v8_0_hw_fini(ip_block);
2839}
2840
2841static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block)
2842{
2843 struct amdgpu_device *adev = ip_block->adev;
2844 int ret;
2845
2846 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2847 adev->mode_info.bl_level);
2848
2849 ret = dce_v8_0_hw_init(ip_block);
2850
2851 /* turn on the BL */
2852 if (adev->mode_info.bl_encoder) {
2853 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2854 adev->mode_info.bl_encoder);
2855 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2856 bl_level);
2857 }
2858 if (ret)
2859 return ret;
2860
2861 return amdgpu_display_resume_helper(adev);
2862}
2863
2864static bool dce_v8_0_is_idle(void *handle)
2865{
2866 return true;
2867}
2868
2869static int dce_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)
2870{
2871 u32 srbm_soft_reset = 0, tmp;
2872 struct amdgpu_device *adev = ip_block->adev;
2873
2874 if (dce_v8_0_is_display_hung(adev))
2875 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2876
2877 if (srbm_soft_reset) {
2878 tmp = RREG32(mmSRBM_SOFT_RESET);
2879 tmp |= srbm_soft_reset;
2880 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2881 WREG32(mmSRBM_SOFT_RESET, tmp);
2882 tmp = RREG32(mmSRBM_SOFT_RESET);
2883
2884 udelay(50);
2885
2886 tmp &= ~srbm_soft_reset;
2887 WREG32(mmSRBM_SOFT_RESET, tmp);
2888 tmp = RREG32(mmSRBM_SOFT_RESET);
2889
2890 /* Wait a little for things to settle down */
2891 udelay(50);
2892 }
2893 return 0;
2894}
2895
2896static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2897 int crtc,
2898 enum amdgpu_interrupt_state state)
2899{
2900 u32 reg_block, lb_interrupt_mask;
2901
2902 if (crtc >= adev->mode_info.num_crtc) {
2903 DRM_DEBUG("invalid crtc %d\n", crtc);
2904 return;
2905 }
2906
2907 switch (crtc) {
2908 case 0:
2909 reg_block = CRTC0_REGISTER_OFFSET;
2910 break;
2911 case 1:
2912 reg_block = CRTC1_REGISTER_OFFSET;
2913 break;
2914 case 2:
2915 reg_block = CRTC2_REGISTER_OFFSET;
2916 break;
2917 case 3:
2918 reg_block = CRTC3_REGISTER_OFFSET;
2919 break;
2920 case 4:
2921 reg_block = CRTC4_REGISTER_OFFSET;
2922 break;
2923 case 5:
2924 reg_block = CRTC5_REGISTER_OFFSET;
2925 break;
2926 default:
2927 DRM_DEBUG("invalid crtc %d\n", crtc);
2928 return;
2929 }
2930
2931 switch (state) {
2932 case AMDGPU_IRQ_STATE_DISABLE:
2933 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2934 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2935 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2936 break;
2937 case AMDGPU_IRQ_STATE_ENABLE:
2938 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2939 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2940 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2941 break;
2942 default:
2943 break;
2944 }
2945}
2946
2947static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2948 int crtc,
2949 enum amdgpu_interrupt_state state)
2950{
2951 u32 reg_block, lb_interrupt_mask;
2952
2953 if (crtc >= adev->mode_info.num_crtc) {
2954 DRM_DEBUG("invalid crtc %d\n", crtc);
2955 return;
2956 }
2957
2958 switch (crtc) {
2959 case 0:
2960 reg_block = CRTC0_REGISTER_OFFSET;
2961 break;
2962 case 1:
2963 reg_block = CRTC1_REGISTER_OFFSET;
2964 break;
2965 case 2:
2966 reg_block = CRTC2_REGISTER_OFFSET;
2967 break;
2968 case 3:
2969 reg_block = CRTC3_REGISTER_OFFSET;
2970 break;
2971 case 4:
2972 reg_block = CRTC4_REGISTER_OFFSET;
2973 break;
2974 case 5:
2975 reg_block = CRTC5_REGISTER_OFFSET;
2976 break;
2977 default:
2978 DRM_DEBUG("invalid crtc %d\n", crtc);
2979 return;
2980 }
2981
2982 switch (state) {
2983 case AMDGPU_IRQ_STATE_DISABLE:
2984 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2985 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2986 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2987 break;
2988 case AMDGPU_IRQ_STATE_ENABLE:
2989 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2990 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2991 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2992 break;
2993 default:
2994 break;
2995 }
2996}
2997
2998static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2999 struct amdgpu_irq_src *src,
3000 unsigned type,
3001 enum amdgpu_interrupt_state state)
3002{
3003 u32 dc_hpd_int_cntl;
3004
3005 if (type >= adev->mode_info.num_hpd) {
3006 DRM_DEBUG("invalid hdp %d\n", type);
3007 return 0;
3008 }
3009
3010 switch (state) {
3011 case AMDGPU_IRQ_STATE_DISABLE:
3012 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3013 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3014 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3015 break;
3016 case AMDGPU_IRQ_STATE_ENABLE:
3017 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3018 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3019 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3020 break;
3021 default:
3022 break;
3023 }
3024
3025 return 0;
3026}
3027
3028static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3029 struct amdgpu_irq_src *src,
3030 unsigned type,
3031 enum amdgpu_interrupt_state state)
3032{
3033 switch (type) {
3034 case AMDGPU_CRTC_IRQ_VBLANK1:
3035 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3036 break;
3037 case AMDGPU_CRTC_IRQ_VBLANK2:
3038 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3039 break;
3040 case AMDGPU_CRTC_IRQ_VBLANK3:
3041 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3042 break;
3043 case AMDGPU_CRTC_IRQ_VBLANK4:
3044 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3045 break;
3046 case AMDGPU_CRTC_IRQ_VBLANK5:
3047 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3048 break;
3049 case AMDGPU_CRTC_IRQ_VBLANK6:
3050 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3051 break;
3052 case AMDGPU_CRTC_IRQ_VLINE1:
3053 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3054 break;
3055 case AMDGPU_CRTC_IRQ_VLINE2:
3056 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3057 break;
3058 case AMDGPU_CRTC_IRQ_VLINE3:
3059 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3060 break;
3061 case AMDGPU_CRTC_IRQ_VLINE4:
3062 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3063 break;
3064 case AMDGPU_CRTC_IRQ_VLINE5:
3065 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3066 break;
3067 case AMDGPU_CRTC_IRQ_VLINE6:
3068 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3069 break;
3070 default:
3071 break;
3072 }
3073 return 0;
3074}
3075
3076static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3077 struct amdgpu_irq_src *source,
3078 struct amdgpu_iv_entry *entry)
3079{
3080 unsigned crtc = entry->src_id - 1;
3081 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3082 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3083 crtc);
3084
3085 switch (entry->src_data[0]) {
3086 case 0: /* vblank */
3087 if (disp_int & interrupt_status_offsets[crtc].vblank)
3088 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3089 else
3090 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3091
3092 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3093 drm_handle_vblank(adev_to_drm(adev), crtc);
3094 }
3095 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3096 break;
3097 case 1: /* vline */
3098 if (disp_int & interrupt_status_offsets[crtc].vline)
3099 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3100 else
3101 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3102
3103 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3104 break;
3105 default:
3106 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3107 break;
3108 }
3109
3110 return 0;
3111}
3112
3113static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3114 struct amdgpu_irq_src *src,
3115 unsigned type,
3116 enum amdgpu_interrupt_state state)
3117{
3118 u32 reg;
3119
3120 if (type >= adev->mode_info.num_crtc) {
3121 DRM_ERROR("invalid pageflip crtc %d\n", type);
3122 return -EINVAL;
3123 }
3124
3125 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3126 if (state == AMDGPU_IRQ_STATE_DISABLE)
3127 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3128 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3129 else
3130 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3131 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3132
3133 return 0;
3134}
3135
3136static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3137 struct amdgpu_irq_src *source,
3138 struct amdgpu_iv_entry *entry)
3139{
3140 unsigned long flags;
3141 unsigned crtc_id;
3142 struct amdgpu_crtc *amdgpu_crtc;
3143 struct amdgpu_flip_work *works;
3144
3145 crtc_id = (entry->src_id - 8) >> 1;
3146 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3147
3148 if (crtc_id >= adev->mode_info.num_crtc) {
3149 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3150 return -EINVAL;
3151 }
3152
3153 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3154 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3155 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3156 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3157
3158 /* IRQ could occur when in initial stage */
3159 if (amdgpu_crtc == NULL)
3160 return 0;
3161
3162 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3163 works = amdgpu_crtc->pflip_works;
3164 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3165 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3166 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3167 amdgpu_crtc->pflip_status,
3168 AMDGPU_FLIP_SUBMITTED);
3169 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3170 return 0;
3171 }
3172
3173 /* page flip completed. clean up */
3174 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3175 amdgpu_crtc->pflip_works = NULL;
3176
3177 /* wakeup usersapce */
3178 if (works->event)
3179 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3180
3181 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3182
3183 drm_crtc_vblank_put(&amdgpu_crtc->base);
3184 schedule_work(&works->unpin_work);
3185
3186 return 0;
3187}
3188
3189static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3190 struct amdgpu_irq_src *source,
3191 struct amdgpu_iv_entry *entry)
3192{
3193 uint32_t disp_int, mask;
3194 unsigned hpd;
3195
3196 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3197 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3198 return 0;
3199 }
3200
3201 hpd = entry->src_data[0];
3202 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3203 mask = interrupt_status_offsets[hpd].hpd;
3204
3205 if (disp_int & mask) {
3206 dce_v8_0_hpd_int_ack(adev, hpd);
3207 schedule_delayed_work(&adev->hotplug_work, 0);
3208 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3209 }
3210
3211 return 0;
3212
3213}
3214
3215static int dce_v8_0_set_clockgating_state(void *handle,
3216 enum amd_clockgating_state state)
3217{
3218 return 0;
3219}
3220
3221static int dce_v8_0_set_powergating_state(void *handle,
3222 enum amd_powergating_state state)
3223{
3224 return 0;
3225}
3226
3227static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3228 .name = "dce_v8_0",
3229 .early_init = dce_v8_0_early_init,
3230 .sw_init = dce_v8_0_sw_init,
3231 .sw_fini = dce_v8_0_sw_fini,
3232 .hw_init = dce_v8_0_hw_init,
3233 .hw_fini = dce_v8_0_hw_fini,
3234 .suspend = dce_v8_0_suspend,
3235 .resume = dce_v8_0_resume,
3236 .is_idle = dce_v8_0_is_idle,
3237 .soft_reset = dce_v8_0_soft_reset,
3238 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3239 .set_powergating_state = dce_v8_0_set_powergating_state,
3240};
3241
3242static void
3243dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3244 struct drm_display_mode *mode,
3245 struct drm_display_mode *adjusted_mode)
3246{
3247 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3248
3249 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3250
3251 /* need to call this here rather than in prepare() since we need some crtc info */
3252 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3253
3254 /* set scaler clears this on some chips */
3255 dce_v8_0_set_interleave(encoder->crtc, mode);
3256
3257 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3258 dce_v8_0_afmt_enable(encoder, true);
3259 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3260 }
3261}
3262
3263static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3264{
3265 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3266 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3267 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3268
3269 if ((amdgpu_encoder->active_device &
3270 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3271 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3272 ENCODER_OBJECT_ID_NONE)) {
3273 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3274 if (dig) {
3275 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3276 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3277 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3278 }
3279 }
3280
3281 amdgpu_atombios_scratch_regs_lock(adev, true);
3282
3283 if (connector) {
3284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3285
3286 /* select the clock/data port if it uses a router */
3287 if (amdgpu_connector->router.cd_valid)
3288 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3289
3290 /* turn eDP panel on for mode set */
3291 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3292 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3293 ATOM_TRANSMITTER_ACTION_POWER_ON);
3294 }
3295
3296 /* this is needed for the pll/ss setup to work correctly in some cases */
3297 amdgpu_atombios_encoder_set_crtc_source(encoder);
3298 /* set up the FMT blocks */
3299 dce_v8_0_program_fmt(encoder);
3300}
3301
3302static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3303{
3304 struct drm_device *dev = encoder->dev;
3305 struct amdgpu_device *adev = drm_to_adev(dev);
3306
3307 /* need to call this here as we need the crtc set up */
3308 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3309 amdgpu_atombios_scratch_regs_lock(adev, false);
3310}
3311
3312static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3313{
3314 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3315 struct amdgpu_encoder_atom_dig *dig;
3316
3317 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3318
3319 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3320 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3321 dce_v8_0_afmt_enable(encoder, false);
3322 dig = amdgpu_encoder->enc_priv;
3323 dig->dig_encoder = -1;
3324 }
3325 amdgpu_encoder->active_device = 0;
3326}
3327
3328/* these are handled by the primary encoders */
3329static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3330{
3331
3332}
3333
3334static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3335{
3336
3337}
3338
3339static void
3340dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3341 struct drm_display_mode *mode,
3342 struct drm_display_mode *adjusted_mode)
3343{
3344
3345}
3346
3347static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3348{
3349
3350}
3351
3352static void
3353dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3354{
3355
3356}
3357
3358static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3359 .dpms = dce_v8_0_ext_dpms,
3360 .prepare = dce_v8_0_ext_prepare,
3361 .mode_set = dce_v8_0_ext_mode_set,
3362 .commit = dce_v8_0_ext_commit,
3363 .disable = dce_v8_0_ext_disable,
3364 /* no detect for TMDS/LVDS yet */
3365};
3366
3367static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3368 .dpms = amdgpu_atombios_encoder_dpms,
3369 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3370 .prepare = dce_v8_0_encoder_prepare,
3371 .mode_set = dce_v8_0_encoder_mode_set,
3372 .commit = dce_v8_0_encoder_commit,
3373 .disable = dce_v8_0_encoder_disable,
3374 .detect = amdgpu_atombios_encoder_dig_detect,
3375};
3376
3377static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3378 .dpms = amdgpu_atombios_encoder_dpms,
3379 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3380 .prepare = dce_v8_0_encoder_prepare,
3381 .mode_set = dce_v8_0_encoder_mode_set,
3382 .commit = dce_v8_0_encoder_commit,
3383 .detect = amdgpu_atombios_encoder_dac_detect,
3384};
3385
3386static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3387{
3388 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3389 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3390 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3391 kfree(amdgpu_encoder->enc_priv);
3392 drm_encoder_cleanup(encoder);
3393 kfree(amdgpu_encoder);
3394}
3395
3396static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3397 .destroy = dce_v8_0_encoder_destroy,
3398};
3399
3400static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3401 uint32_t encoder_enum,
3402 uint32_t supported_device,
3403 u16 caps)
3404{
3405 struct drm_device *dev = adev_to_drm(adev);
3406 struct drm_encoder *encoder;
3407 struct amdgpu_encoder *amdgpu_encoder;
3408
3409 /* see if we already added it */
3410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3411 amdgpu_encoder = to_amdgpu_encoder(encoder);
3412 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3413 amdgpu_encoder->devices |= supported_device;
3414 return;
3415 }
3416
3417 }
3418
3419 /* add a new one */
3420 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3421 if (!amdgpu_encoder)
3422 return;
3423
3424 encoder = &amdgpu_encoder->base;
3425 switch (adev->mode_info.num_crtc) {
3426 case 1:
3427 encoder->possible_crtcs = 0x1;
3428 break;
3429 case 2:
3430 default:
3431 encoder->possible_crtcs = 0x3;
3432 break;
3433 case 4:
3434 encoder->possible_crtcs = 0xf;
3435 break;
3436 case 6:
3437 encoder->possible_crtcs = 0x3f;
3438 break;
3439 }
3440
3441 amdgpu_encoder->enc_priv = NULL;
3442
3443 amdgpu_encoder->encoder_enum = encoder_enum;
3444 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3445 amdgpu_encoder->devices = supported_device;
3446 amdgpu_encoder->rmx_type = RMX_OFF;
3447 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3448 amdgpu_encoder->is_ext_encoder = false;
3449 amdgpu_encoder->caps = caps;
3450
3451 switch (amdgpu_encoder->encoder_id) {
3452 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3454 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3455 DRM_MODE_ENCODER_DAC, NULL);
3456 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3457 break;
3458 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3459 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3460 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3461 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3462 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3463 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3464 amdgpu_encoder->rmx_type = RMX_FULL;
3465 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3466 DRM_MODE_ENCODER_LVDS, NULL);
3467 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3468 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3469 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3470 DRM_MODE_ENCODER_DAC, NULL);
3471 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3472 } else {
3473 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3474 DRM_MODE_ENCODER_TMDS, NULL);
3475 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3476 }
3477 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3478 break;
3479 case ENCODER_OBJECT_ID_SI170B:
3480 case ENCODER_OBJECT_ID_CH7303:
3481 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3482 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3483 case ENCODER_OBJECT_ID_TITFP513:
3484 case ENCODER_OBJECT_ID_VT1623:
3485 case ENCODER_OBJECT_ID_HDMI_SI1930:
3486 case ENCODER_OBJECT_ID_TRAVIS:
3487 case ENCODER_OBJECT_ID_NUTMEG:
3488 /* these are handled by the primary encoders */
3489 amdgpu_encoder->is_ext_encoder = true;
3490 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3491 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3492 DRM_MODE_ENCODER_LVDS, NULL);
3493 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3494 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3495 DRM_MODE_ENCODER_DAC, NULL);
3496 else
3497 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3498 DRM_MODE_ENCODER_TMDS, NULL);
3499 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3500 break;
3501 }
3502}
3503
3504static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3505 .bandwidth_update = &dce_v8_0_bandwidth_update,
3506 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3507 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3508 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3509 .hpd_sense = &dce_v8_0_hpd_sense,
3510 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3511 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3512 .page_flip = &dce_v8_0_page_flip,
3513 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3514 .add_encoder = &dce_v8_0_encoder_add,
3515 .add_connector = &amdgpu_connector_add,
3516};
3517
3518static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3519{
3520 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3521}
3522
3523static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3524 .set = dce_v8_0_set_crtc_interrupt_state,
3525 .process = dce_v8_0_crtc_irq,
3526};
3527
3528static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3529 .set = dce_v8_0_set_pageflip_interrupt_state,
3530 .process = dce_v8_0_pageflip_irq,
3531};
3532
3533static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3534 .set = dce_v8_0_set_hpd_interrupt_state,
3535 .process = dce_v8_0_hpd_irq,
3536};
3537
3538static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3539{
3540 if (adev->mode_info.num_crtc > 0)
3541 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3542 else
3543 adev->crtc_irq.num_types = 0;
3544 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3545
3546 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3547 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3548
3549 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3550 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3551}
3552
3553const struct amdgpu_ip_block_version dce_v8_0_ip_block = {
3554 .type = AMD_IP_BLOCK_TYPE_DCE,
3555 .major = 8,
3556 .minor = 0,
3557 .rev = 0,
3558 .funcs = &dce_v8_0_ip_funcs,
3559};
3560
3561const struct amdgpu_ip_block_version dce_v8_1_ip_block = {
3562 .type = AMD_IP_BLOCK_TYPE_DCE,
3563 .major = 8,
3564 .minor = 1,
3565 .rev = 0,
3566 .funcs = &dce_v8_0_ip_funcs,
3567};
3568
3569const struct amdgpu_ip_block_version dce_v8_2_ip_block = {
3570 .type = AMD_IP_BLOCK_TYPE_DCE,
3571 .major = 8,
3572 .minor = 2,
3573 .rev = 0,
3574 .funcs = &dce_v8_0_ip_funcs,
3575};
3576
3577const struct amdgpu_ip_block_version dce_v8_3_ip_block = {
3578 .type = AMD_IP_BLOCK_TYPE_DCE,
3579 .major = 8,
3580 .minor = 3,
3581 .rev = 0,
3582 .funcs = &dce_v8_0_ip_funcs,
3583};
3584
3585const struct amdgpu_ip_block_version dce_v8_5_ip_block = {
3586 .type = AMD_IP_BLOCK_TYPE_DCE,
3587 .major = 8,
3588 .minor = 5,
3589 .rev = 0,
3590 .funcs = &dce_v8_0_ip_funcs,
3591};