1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26
 
 
  27#include <drm/drm_edid.h>
  28#include <drm/drm_fb_helper.h>
  29#include <drm/drm_probe_helper.h>
  30#include <drm/amdgpu_drm.h>
  31#include "amdgpu.h"
  32#include "atom.h"
  33#include "atombios_encoders.h"
  34#include "atombios_dp.h"
  35#include "amdgpu_connectors.h"
  36#include "amdgpu_i2c.h"
  37#include "amdgpu_display.h"
  38
  39#include <linux/pm_runtime.h>
  40
  41void amdgpu_connector_hotplug(struct drm_connector *connector)
  42{
  43	struct drm_device *dev = connector->dev;
  44	struct amdgpu_device *adev = dev->dev_private;
  45	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  46
  47	/* bail if the connector does not have hpd pin, e.g.,
  48	 * VGA, TV, etc.
  49	 */
  50	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  51		return;
  52
  53	amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  54
  55	/* if the connector is already off, don't turn it back on */
  56	if (connector->dpms != DRM_MODE_DPMS_ON)
  57		return;
  58
  59	/* just deal with DP (not eDP) here. */
  60	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  61		struct amdgpu_connector_atom_dig *dig_connector =
  62			amdgpu_connector->con_priv;
  63
  64		/* if existing sink type was not DP no need to retrain */
  65		if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  66			return;
  67
  68		/* first get sink type as it may be reset after (un)plug */
  69		dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  70		/* don't do anything if sink is not display port, i.e.,
  71		 * passive dp->(dvi|hdmi) adaptor
  72		 */
  73		if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  74		    amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  75		    amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  76			/* Don't start link training before we have the DPCD */
  77			if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  78				return;
  79
  80			/* Turn the connector off and back on immediately, which
  81			 * will trigger link training
  82			 */
  83			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  84			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  85		}
  86	}
  87}
  88
  89static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  90{
  91	struct drm_crtc *crtc = encoder->crtc;
  92
  93	if (crtc && crtc->enabled) {
  94		drm_crtc_helper_set_mode(crtc, &crtc->mode,
  95					 crtc->x, crtc->y, crtc->primary->fb);
  96	}
  97}
  98
  99int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 100{
 101	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 102	struct amdgpu_connector_atom_dig *dig_connector;
 103	int bpc = 8;
 104	unsigned mode_clock, max_tmds_clock;
 105
 106	switch (connector->connector_type) {
 107	case DRM_MODE_CONNECTOR_DVII:
 108	case DRM_MODE_CONNECTOR_HDMIB:
 109		if (amdgpu_connector->use_digital) {
 110			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 111				if (connector->display_info.bpc)
 112					bpc = connector->display_info.bpc;
 113			}
 114		}
 115		break;
 116	case DRM_MODE_CONNECTOR_DVID:
 117	case DRM_MODE_CONNECTOR_HDMIA:
 118		if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 119			if (connector->display_info.bpc)
 120				bpc = connector->display_info.bpc;
 121		}
 122		break;
 123	case DRM_MODE_CONNECTOR_DisplayPort:
 124		dig_connector = amdgpu_connector->con_priv;
 125		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 126		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 127		    drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 128			if (connector->display_info.bpc)
 129				bpc = connector->display_info.bpc;
 130		}
 131		break;
 132	case DRM_MODE_CONNECTOR_eDP:
 133	case DRM_MODE_CONNECTOR_LVDS:
 134		if (connector->display_info.bpc)
 135			bpc = connector->display_info.bpc;
 136		else {
 137			const struct drm_connector_helper_funcs *connector_funcs =
 138				connector->helper_private;
 139			struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 140			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 141			struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 142
 143			if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 144				bpc = 6;
 145			else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 146				bpc = 8;
 147		}
 148		break;
 149	}
 150
 151	if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 152		/*
 153		 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 154		 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 155		 * 12 bpc is always supported on hdmi deep color sinks, as this is
 156		 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 157		 */
 158		if (bpc > 12) {
 159			DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 160				  connector->name, bpc);
 161			bpc = 12;
 162		}
 163
 164		/* Any defined maximum tmds clock limit we must not exceed? */
 165		if (connector->display_info.max_tmds_clock > 0) {
 166			/* mode_clock is clock in kHz for mode to be modeset on this connector */
 167			mode_clock = amdgpu_connector->pixelclock_for_modeset;
 168
 169			/* Maximum allowable input clock in kHz */
 170			max_tmds_clock = connector->display_info.max_tmds_clock;
 171
 172			DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 173				  connector->name, mode_clock, max_tmds_clock);
 174
 175			/* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 176			if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 177				if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 178				    (mode_clock * 5/4 <= max_tmds_clock))
 179					bpc = 10;
 180				else
 181					bpc = 8;
 182
 183				DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 184					  connector->name, bpc);
 185			}
 186
 187			if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 188				bpc = 8;
 189				DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 190					  connector->name, bpc);
 191			}
 192		} else if (bpc > 8) {
 193			/* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 194			DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 195				  connector->name);
 196			bpc = 8;
 197		}
 198	}
 199
 200	if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 201		DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 202			  connector->name);
 203		bpc = 8;
 204	}
 205
 206	DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 207		  connector->name, connector->display_info.bpc, bpc);
 208
 209	return bpc;
 210}
 211
 212static void
 213amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 214				      enum drm_connector_status status)
 215{
 216	struct drm_encoder *best_encoder;
 217	struct drm_encoder *encoder;
 218	const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 219	bool connected;
 220	int i;
 221
 222	best_encoder = connector_funcs->best_encoder(connector);
 223
 224	drm_connector_for_each_possible_encoder(connector, encoder, i) {
 225		if ((encoder == best_encoder) && (status == connector_status_connected))
 226			connected = true;
 227		else
 228			connected = false;
 229
 230		amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 231	}
 232}
 233
 234static struct drm_encoder *
 235amdgpu_connector_find_encoder(struct drm_connector *connector,
 236			       int encoder_type)
 237{
 238	struct drm_encoder *encoder;
 239	int i;
 240
 241	drm_connector_for_each_possible_encoder(connector, encoder, i) {
 242		if (encoder->encoder_type == encoder_type)
 243			return encoder;
 244	}
 245
 246	return NULL;
 247}
 248
 249struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 250{
 251	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 252	struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 253
 254	if (amdgpu_connector->edid) {
 255		return amdgpu_connector->edid;
 256	} else if (edid_blob) {
 257		struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 258		if (edid)
 259			amdgpu_connector->edid = edid;
 260	}
 261	return amdgpu_connector->edid;
 262}
 263
 264static struct edid *
 265amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 266{
 267	struct edid *edid;
 268
 269	if (adev->mode_info.bios_hardcoded_edid) {
 270		edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 271		if (edid) {
 272			memcpy((unsigned char *)edid,
 273			       (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 274			       adev->mode_info.bios_hardcoded_edid_size);
 275			return edid;
 276		}
 277	}
 278	return NULL;
 279}
 280
 281static void amdgpu_connector_get_edid(struct drm_connector *connector)
 282{
 283	struct drm_device *dev = connector->dev;
 284	struct amdgpu_device *adev = dev->dev_private;
 285	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 286
 287	if (amdgpu_connector->edid)
 288		return;
 289
 290	/* on hw with routers, select right port */
 291	if (amdgpu_connector->router.ddc_valid)
 292		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 293
 294	if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 295	     ENCODER_OBJECT_ID_NONE) &&
 296	    amdgpu_connector->ddc_bus->has_aux) {
 297		amdgpu_connector->edid = drm_get_edid(connector,
 298						      &amdgpu_connector->ddc_bus->aux.ddc);
 299	} else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 300		   (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 301		struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 302
 303		if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 304		     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 305		    amdgpu_connector->ddc_bus->has_aux)
 306			amdgpu_connector->edid = drm_get_edid(connector,
 307							      &amdgpu_connector->ddc_bus->aux.ddc);
 308		else if (amdgpu_connector->ddc_bus)
 309			amdgpu_connector->edid = drm_get_edid(connector,
 310							      &amdgpu_connector->ddc_bus->adapter);
 311	} else if (amdgpu_connector->ddc_bus) {
 312		amdgpu_connector->edid = drm_get_edid(connector,
 313						      &amdgpu_connector->ddc_bus->adapter);
 314	}
 315
 316	if (!amdgpu_connector->edid) {
 317		/* some laptops provide a hardcoded edid in rom for LCDs */
 318		if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 319		     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 320			amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 
 
 321	}
 322}
 323
 324static void amdgpu_connector_free_edid(struct drm_connector *connector)
 325{
 326	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 327
 328	kfree(amdgpu_connector->edid);
 329	amdgpu_connector->edid = NULL;
 330}
 331
 332static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 333{
 334	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 335	int ret;
 336
 337	if (amdgpu_connector->edid) {
 338		drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 339		ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 340		return ret;
 341	}
 342	drm_connector_update_edid_property(connector, NULL);
 343	return 0;
 344}
 345
 346static struct drm_encoder *
 347amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 348{
 349	struct drm_encoder *encoder;
 350	int i;
 351
 352	/* pick the first one */
 353	drm_connector_for_each_possible_encoder(connector, encoder, i)
 354		return encoder;
 355
 356	return NULL;
 357}
 358
 359static void amdgpu_get_native_mode(struct drm_connector *connector)
 360{
 361	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 362	struct amdgpu_encoder *amdgpu_encoder;
 363
 364	if (encoder == NULL)
 365		return;
 366
 367	amdgpu_encoder = to_amdgpu_encoder(encoder);
 368
 369	if (!list_empty(&connector->probed_modes)) {
 370		struct drm_display_mode *preferred_mode =
 371			list_first_entry(&connector->probed_modes,
 372					 struct drm_display_mode, head);
 373
 374		amdgpu_encoder->native_mode = *preferred_mode;
 375	} else {
 376		amdgpu_encoder->native_mode.clock = 0;
 377	}
 378}
 379
 380static struct drm_display_mode *
 381amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 382{
 383	struct drm_device *dev = encoder->dev;
 384	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 385	struct drm_display_mode *mode = NULL;
 386	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 387
 388	if (native_mode->hdisplay != 0 &&
 389	    native_mode->vdisplay != 0 &&
 390	    native_mode->clock != 0) {
 391		mode = drm_mode_duplicate(dev, native_mode);
 
 
 
 392		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 393		drm_mode_set_name(mode);
 394
 395		DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 396	} else if (native_mode->hdisplay != 0 &&
 397		   native_mode->vdisplay != 0) {
 398		/* mac laptops without an edid */
 399		/* Note that this is not necessarily the exact panel mode,
 400		 * but an approximation based on the cvt formula.  For these
 401		 * systems we should ideally read the mode info out of the
 402		 * registers or add a mode table, but this works and is much
 403		 * simpler.
 404		 */
 405		mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 
 
 
 406		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 407		DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 408	}
 409	return mode;
 410}
 411
 412static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 413					       struct drm_connector *connector)
 414{
 415	struct drm_device *dev = encoder->dev;
 416	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 417	struct drm_display_mode *mode = NULL;
 418	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 419	int i;
 420	static const struct mode_size {
 421		int w;
 422		int h;
 423	} common_modes[17] = {
 424		{ 640,  480},
 425		{ 720,  480},
 426		{ 800,  600},
 427		{ 848,  480},
 428		{1024,  768},
 429		{1152,  768},
 430		{1280,  720},
 431		{1280,  800},
 432		{1280,  854},
 433		{1280,  960},
 434		{1280, 1024},
 435		{1440,  900},
 436		{1400, 1050},
 437		{1680, 1050},
 438		{1600, 1200},
 439		{1920, 1080},
 440		{1920, 1200}
 441	};
 442
 443	for (i = 0; i < 17; i++) {
 444		if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 445			if (common_modes[i].w > 1024 ||
 446			    common_modes[i].h > 768)
 447				continue;
 448		}
 449		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 450			if (common_modes[i].w > native_mode->hdisplay ||
 451			    common_modes[i].h > native_mode->vdisplay ||
 452			    (common_modes[i].w == native_mode->hdisplay &&
 453			     common_modes[i].h == native_mode->vdisplay))
 454				continue;
 455		}
 456		if (common_modes[i].w < 320 || common_modes[i].h < 200)
 457			continue;
 458
 459		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 
 
 
 460		drm_mode_probed_add(connector, mode);
 461	}
 462}
 463
 464static int amdgpu_connector_set_property(struct drm_connector *connector,
 465					  struct drm_property *property,
 466					  uint64_t val)
 467{
 468	struct drm_device *dev = connector->dev;
 469	struct amdgpu_device *adev = dev->dev_private;
 470	struct drm_encoder *encoder;
 471	struct amdgpu_encoder *amdgpu_encoder;
 472
 473	if (property == adev->mode_info.coherent_mode_property) {
 474		struct amdgpu_encoder_atom_dig *dig;
 475		bool new_coherent_mode;
 476
 477		/* need to find digital encoder on connector */
 478		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 479		if (!encoder)
 480			return 0;
 481
 482		amdgpu_encoder = to_amdgpu_encoder(encoder);
 483
 484		if (!amdgpu_encoder->enc_priv)
 485			return 0;
 486
 487		dig = amdgpu_encoder->enc_priv;
 488		new_coherent_mode = val ? true : false;
 489		if (dig->coherent_mode != new_coherent_mode) {
 490			dig->coherent_mode = new_coherent_mode;
 491			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 492		}
 493	}
 494
 495	if (property == adev->mode_info.audio_property) {
 496		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 497		/* need to find digital encoder on connector */
 498		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 499		if (!encoder)
 500			return 0;
 501
 502		amdgpu_encoder = to_amdgpu_encoder(encoder);
 503
 504		if (amdgpu_connector->audio != val) {
 505			amdgpu_connector->audio = val;
 506			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 507		}
 508	}
 509
 510	if (property == adev->mode_info.dither_property) {
 511		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 512		/* need to find digital encoder on connector */
 513		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 514		if (!encoder)
 515			return 0;
 516
 517		amdgpu_encoder = to_amdgpu_encoder(encoder);
 518
 519		if (amdgpu_connector->dither != val) {
 520			amdgpu_connector->dither = val;
 521			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 522		}
 523	}
 524
 525	if (property == adev->mode_info.underscan_property) {
 526		/* need to find digital encoder on connector */
 527		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 528		if (!encoder)
 529			return 0;
 530
 531		amdgpu_encoder = to_amdgpu_encoder(encoder);
 532
 533		if (amdgpu_encoder->underscan_type != val) {
 534			amdgpu_encoder->underscan_type = val;
 535			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 536		}
 537	}
 538
 539	if (property == adev->mode_info.underscan_hborder_property) {
 540		/* need to find digital encoder on connector */
 541		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 542		if (!encoder)
 543			return 0;
 544
 545		amdgpu_encoder = to_amdgpu_encoder(encoder);
 546
 547		if (amdgpu_encoder->underscan_hborder != val) {
 548			amdgpu_encoder->underscan_hborder = val;
 549			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 550		}
 551	}
 552
 553	if (property == adev->mode_info.underscan_vborder_property) {
 554		/* need to find digital encoder on connector */
 555		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 556		if (!encoder)
 557			return 0;
 558
 559		amdgpu_encoder = to_amdgpu_encoder(encoder);
 560
 561		if (amdgpu_encoder->underscan_vborder != val) {
 562			amdgpu_encoder->underscan_vborder = val;
 563			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 564		}
 565	}
 566
 567	if (property == adev->mode_info.load_detect_property) {
 568		struct amdgpu_connector *amdgpu_connector =
 569			to_amdgpu_connector(connector);
 570
 571		if (val == 0)
 572			amdgpu_connector->dac_load_detect = false;
 573		else
 574			amdgpu_connector->dac_load_detect = true;
 575	}
 576
 577	if (property == dev->mode_config.scaling_mode_property) {
 578		enum amdgpu_rmx_type rmx_type;
 579
 580		if (connector->encoder) {
 581			amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 582		} else {
 583			const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 
 584			amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 585		}
 586
 587		switch (val) {
 588		default:
 589		case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 590		case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 591		case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 592		case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 
 
 
 
 
 
 
 
 593		}
 
 594		if (amdgpu_encoder->rmx_type == rmx_type)
 595			return 0;
 596
 597		if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 598		    (amdgpu_encoder->native_mode.clock == 0))
 599			return 0;
 600
 601		amdgpu_encoder->rmx_type = rmx_type;
 602
 603		amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 604	}
 605
 606	return 0;
 607}
 608
 609static void
 610amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 611					struct drm_connector *connector)
 612{
 613	struct amdgpu_encoder *amdgpu_encoder =	to_amdgpu_encoder(encoder);
 614	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 615	struct drm_display_mode *t, *mode;
 616
 617	/* If the EDID preferred mode doesn't match the native mode, use it */
 618	list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 619		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 620			if (mode->hdisplay != native_mode->hdisplay ||
 621			    mode->vdisplay != native_mode->vdisplay)
 622				memcpy(native_mode, mode, sizeof(*mode));
 623		}
 624	}
 625
 626	/* Try to get native mode details from EDID if necessary */
 627	if (!native_mode->clock) {
 628		list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 629			if (mode->hdisplay == native_mode->hdisplay &&
 630			    mode->vdisplay == native_mode->vdisplay) {
 631				*native_mode = *mode;
 632				drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 633				DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 634				break;
 635			}
 636		}
 637	}
 638
 639	if (!native_mode->clock) {
 640		DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 641		amdgpu_encoder->rmx_type = RMX_OFF;
 642	}
 643}
 644
 645static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 646{
 647	struct drm_encoder *encoder;
 648	int ret = 0;
 649	struct drm_display_mode *mode;
 650
 651	amdgpu_connector_get_edid(connector);
 652	ret = amdgpu_connector_ddc_get_modes(connector);
 653	if (ret > 0) {
 654		encoder = amdgpu_connector_best_single_encoder(connector);
 655		if (encoder) {
 656			amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 657			/* add scaled modes */
 658			amdgpu_connector_add_common_modes(encoder, connector);
 659		}
 660		return ret;
 661	}
 662
 663	encoder = amdgpu_connector_best_single_encoder(connector);
 664	if (!encoder)
 665		return 0;
 666
 667	/* we have no EDID modes */
 668	mode = amdgpu_connector_lcd_native_mode(encoder);
 669	if (mode) {
 670		ret = 1;
 671		drm_mode_probed_add(connector, mode);
 672		/* add the width/height from vbios tables if available */
 673		connector->display_info.width_mm = mode->width_mm;
 674		connector->display_info.height_mm = mode->height_mm;
 675		/* add scaled modes */
 676		amdgpu_connector_add_common_modes(encoder, connector);
 677	}
 678
 679	return ret;
 680}
 681
 682static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 683					     struct drm_display_mode *mode)
 684{
 685	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 686
 687	if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 688		return MODE_PANEL;
 689
 690	if (encoder) {
 691		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 692		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 693
 694		/* AVIVO hardware supports downscaling modes larger than the panel
 695		 * to the panel size, but I'm not sure this is desirable.
 696		 */
 697		if ((mode->hdisplay > native_mode->hdisplay) ||
 698		    (mode->vdisplay > native_mode->vdisplay))
 699			return MODE_PANEL;
 700
 701		/* if scaling is disabled, block non-native modes */
 702		if (amdgpu_encoder->rmx_type == RMX_OFF) {
 703			if ((mode->hdisplay != native_mode->hdisplay) ||
 704			    (mode->vdisplay != native_mode->vdisplay))
 705				return MODE_PANEL;
 706		}
 707	}
 708
 709	return MODE_OK;
 710}
 711
 712static enum drm_connector_status
 713amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 714{
 715	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 716	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 717	enum drm_connector_status ret = connector_status_disconnected;
 718	int r;
 719
 720	if (!drm_kms_helper_is_poll_worker()) {
 721		r = pm_runtime_get_sync(connector->dev->dev);
 722		if (r < 0)
 
 723			return connector_status_disconnected;
 
 724	}
 725
 726	if (encoder) {
 727		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 728		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 729
 730		/* check if panel is valid */
 731		if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 732			ret = connector_status_connected;
 733
 734	}
 735
 736	/* check for edid as well */
 737	amdgpu_connector_get_edid(connector);
 738	if (amdgpu_connector->edid)
 739		ret = connector_status_connected;
 740	/* check acpi lid status ??? */
 741
 742	amdgpu_connector_update_scratch_regs(connector, ret);
 743
 744	if (!drm_kms_helper_is_poll_worker()) {
 745		pm_runtime_mark_last_busy(connector->dev->dev);
 746		pm_runtime_put_autosuspend(connector->dev->dev);
 747	}
 748
 749	return ret;
 750}
 751
 752static void amdgpu_connector_unregister(struct drm_connector *connector)
 753{
 754	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 755
 756	if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 757		drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 758		amdgpu_connector->ddc_bus->has_aux = false;
 759	}
 760}
 761
 762static void amdgpu_connector_destroy(struct drm_connector *connector)
 763{
 764	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 765
 766	amdgpu_connector_free_edid(connector);
 767	kfree(amdgpu_connector->con_priv);
 768	drm_connector_unregister(connector);
 769	drm_connector_cleanup(connector);
 770	kfree(connector);
 771}
 772
 773static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 774					      struct drm_property *property,
 775					      uint64_t value)
 776{
 777	struct drm_device *dev = connector->dev;
 778	struct amdgpu_encoder *amdgpu_encoder;
 779	enum amdgpu_rmx_type rmx_type;
 780
 781	DRM_DEBUG_KMS("\n");
 782	if (property != dev->mode_config.scaling_mode_property)
 783		return 0;
 784
 785	if (connector->encoder)
 786		amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 787	else {
 788		const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 
 789		amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 790	}
 791
 792	switch (value) {
 793	case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 794	case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 795	case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 
 
 
 
 
 
 796	default:
 797	case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 
 
 798	}
 
 799	if (amdgpu_encoder->rmx_type == rmx_type)
 800		return 0;
 801
 802	amdgpu_encoder->rmx_type = rmx_type;
 803
 804	amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 805	return 0;
 806}
 807
 808
 809static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 810	.get_modes = amdgpu_connector_lvds_get_modes,
 811	.mode_valid = amdgpu_connector_lvds_mode_valid,
 812	.best_encoder = amdgpu_connector_best_single_encoder,
 813};
 814
 815static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 816	.dpms = drm_helper_connector_dpms,
 817	.detect = amdgpu_connector_lvds_detect,
 818	.fill_modes = drm_helper_probe_single_connector_modes,
 819	.early_unregister = amdgpu_connector_unregister,
 820	.destroy = amdgpu_connector_destroy,
 821	.set_property = amdgpu_connector_set_lcd_property,
 822};
 823
 824static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 825{
 826	int ret;
 827
 828	amdgpu_connector_get_edid(connector);
 829	ret = amdgpu_connector_ddc_get_modes(connector);
 
 830
 831	return ret;
 832}
 833
 834static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 835					    struct drm_display_mode *mode)
 836{
 837	struct drm_device *dev = connector->dev;
 838	struct amdgpu_device *adev = dev->dev_private;
 839
 840	/* XXX check mode bandwidth */
 841
 842	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 843		return MODE_CLOCK_HIGH;
 844
 845	return MODE_OK;
 846}
 847
 848static enum drm_connector_status
 849amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 850{
 851	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 852	struct drm_encoder *encoder;
 853	const struct drm_encoder_helper_funcs *encoder_funcs;
 854	bool dret = false;
 855	enum drm_connector_status ret = connector_status_disconnected;
 856	int r;
 857
 858	if (!drm_kms_helper_is_poll_worker()) {
 859		r = pm_runtime_get_sync(connector->dev->dev);
 860		if (r < 0)
 
 861			return connector_status_disconnected;
 
 862	}
 863
 864	encoder = amdgpu_connector_best_single_encoder(connector);
 865	if (!encoder)
 866		ret = connector_status_disconnected;
 867
 868	if (amdgpu_connector->ddc_bus)
 869		dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 870	if (dret) {
 871		amdgpu_connector->detected_by_load = false;
 872		amdgpu_connector_free_edid(connector);
 873		amdgpu_connector_get_edid(connector);
 874
 875		if (!amdgpu_connector->edid) {
 876			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 877					connector->name);
 878			ret = connector_status_connected;
 879		} else {
 880			amdgpu_connector->use_digital =
 881				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 882
 883			/* some oems have boards with separate digital and analog connectors
 884			 * with a shared ddc line (often vga + hdmi)
 885			 */
 886			if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 887				amdgpu_connector_free_edid(connector);
 888				ret = connector_status_disconnected;
 889			} else {
 890				ret = connector_status_connected;
 891			}
 892		}
 893	} else {
 894
 895		/* if we aren't forcing don't do destructive polling */
 896		if (!force) {
 897			/* only return the previous status if we last
 898			 * detected a monitor via load.
 899			 */
 900			if (amdgpu_connector->detected_by_load)
 901				ret = connector->status;
 902			goto out;
 903		}
 904
 905		if (amdgpu_connector->dac_load_detect && encoder) {
 906			encoder_funcs = encoder->helper_private;
 907			ret = encoder_funcs->detect(encoder, connector);
 908			if (ret != connector_status_disconnected)
 909				amdgpu_connector->detected_by_load = true;
 910		}
 911	}
 912
 913	amdgpu_connector_update_scratch_regs(connector, ret);
 914
 915out:
 916	if (!drm_kms_helper_is_poll_worker()) {
 917		pm_runtime_mark_last_busy(connector->dev->dev);
 918		pm_runtime_put_autosuspend(connector->dev->dev);
 919	}
 920
 921	return ret;
 922}
 923
 924static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 925	.get_modes = amdgpu_connector_vga_get_modes,
 926	.mode_valid = amdgpu_connector_vga_mode_valid,
 927	.best_encoder = amdgpu_connector_best_single_encoder,
 928};
 929
 930static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 931	.dpms = drm_helper_connector_dpms,
 932	.detect = amdgpu_connector_vga_detect,
 933	.fill_modes = drm_helper_probe_single_connector_modes,
 934	.early_unregister = amdgpu_connector_unregister,
 935	.destroy = amdgpu_connector_destroy,
 936	.set_property = amdgpu_connector_set_property,
 937};
 938
 939static bool
 940amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 941{
 942	struct drm_device *dev = connector->dev;
 943	struct amdgpu_device *adev = dev->dev_private;
 944	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 945	enum drm_connector_status status;
 946
 947	if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 948		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 949			status = connector_status_connected;
 950		else
 951			status = connector_status_disconnected;
 952		if (connector->status == status)
 953			return true;
 954	}
 955
 956	return false;
 957}
 958
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 959/*
 960 * DVI is complicated
 961 * Do a DDC probe, if DDC probe passes, get the full EDID so
 962 * we can do analog/digital monitor detection at this point.
 963 * If the monitor is an analog monitor or we got no DDC,
 964 * we need to find the DAC encoder object for this connector.
 965 * If we got no DDC, we do load detection on the DAC encoder object.
 966 * If we got analog DDC or load detection passes on the DAC encoder
 967 * we have to check if this analog encoder is shared with anyone else (TV)
 968 * if its shared we have to set the other connector to disconnected.
 969 */
 970static enum drm_connector_status
 971amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 972{
 973	struct drm_device *dev = connector->dev;
 974	struct amdgpu_device *adev = dev->dev_private;
 975	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 976	const struct drm_encoder_helper_funcs *encoder_funcs;
 977	int r;
 978	enum drm_connector_status ret = connector_status_disconnected;
 979	bool dret = false, broken_edid = false;
 980
 981	if (!drm_kms_helper_is_poll_worker()) {
 982		r = pm_runtime_get_sync(connector->dev->dev);
 983		if (r < 0)
 
 984			return connector_status_disconnected;
 
 
 
 
 
 
 985	}
 986
 987	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
 988		ret = connector->status;
 989		goto exit;
 990	}
 991
 992	if (amdgpu_connector->ddc_bus)
 993		dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 994	if (dret) {
 995		amdgpu_connector->detected_by_load = false;
 996		amdgpu_connector_free_edid(connector);
 997		amdgpu_connector_get_edid(connector);
 998
 999		if (!amdgpu_connector->edid) {
1000			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1001					connector->name);
1002			ret = connector_status_connected;
1003			broken_edid = true; /* defer use_digital to later */
1004		} else {
1005			amdgpu_connector->use_digital =
1006				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1007
1008			/* some oems have boards with separate digital and analog connectors
1009			 * with a shared ddc line (often vga + hdmi)
1010			 */
1011			if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1012				amdgpu_connector_free_edid(connector);
1013				ret = connector_status_disconnected;
1014			} else {
1015				ret = connector_status_connected;
1016			}
1017
1018			/* This gets complicated.  We have boards with VGA + HDMI with a
1019			 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1020			 * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1021			 * you don't really know what's connected to which port as both are digital.
1022			 */
1023			if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1024				struct drm_connector *list_connector;
1025				struct amdgpu_connector *list_amdgpu_connector;
1026				list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1027					if (connector == list_connector)
1028						continue;
1029					list_amdgpu_connector = to_amdgpu_connector(list_connector);
1030					if (list_amdgpu_connector->shared_ddc &&
1031					    (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1032					     amdgpu_connector->ddc_bus->rec.i2c_id)) {
1033						/* cases where both connectors are digital */
1034						if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1035							/* hpd is our only option in this case */
1036							if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1037								amdgpu_connector_free_edid(connector);
1038								ret = connector_status_disconnected;
1039							}
1040						}
1041					}
1042				}
1043			}
1044		}
1045	}
1046
1047	if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1048		goto out;
1049
1050	/* DVI-D and HDMI-A are digital only */
1051	if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1052	    (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1053		goto out;
1054
1055	/* if we aren't forcing don't do destructive polling */
1056	if (!force) {
1057		/* only return the previous status if we last
1058		 * detected a monitor via load.
1059		 */
1060		if (amdgpu_connector->detected_by_load)
1061			ret = connector->status;
1062		goto out;
1063	}
1064
1065	/* find analog encoder */
1066	if (amdgpu_connector->dac_load_detect) {
1067		struct drm_encoder *encoder;
1068		int i;
1069
1070		drm_connector_for_each_possible_encoder(connector, encoder, i) {
1071			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1072			    encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1073				continue;
1074
1075			encoder_funcs = encoder->helper_private;
1076			if (encoder_funcs->detect) {
1077				if (!broken_edid) {
1078					if (ret != connector_status_connected) {
1079						/* deal with analog monitors without DDC */
1080						ret = encoder_funcs->detect(encoder, connector);
1081						if (ret == connector_status_connected) {
1082							amdgpu_connector->use_digital = false;
1083						}
1084						if (ret != connector_status_disconnected)
1085							amdgpu_connector->detected_by_load = true;
1086					}
1087				} else {
1088					enum drm_connector_status lret;
1089					/* assume digital unless load detected otherwise */
1090					amdgpu_connector->use_digital = true;
1091					lret = encoder_funcs->detect(encoder, connector);
1092					DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
 
1093					if (lret == connector_status_connected)
1094						amdgpu_connector->use_digital = false;
1095				}
1096				break;
1097			}
1098		}
1099	}
1100
1101out:
1102	/* updated in get modes as well since we need to know if it's analog or digital */
1103	amdgpu_connector_update_scratch_regs(connector, ret);
1104
1105exit:
1106	if (!drm_kms_helper_is_poll_worker()) {
1107		pm_runtime_mark_last_busy(connector->dev->dev);
1108		pm_runtime_put_autosuspend(connector->dev->dev);
1109	}
1110
1111	return ret;
1112}
1113
1114/* okay need to be smart in here about which encoder to pick */
1115static struct drm_encoder *
1116amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1117{
1118	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1119	struct drm_encoder *encoder;
1120	int i;
1121
1122	drm_connector_for_each_possible_encoder(connector, encoder, i) {
1123		if (amdgpu_connector->use_digital == true) {
1124			if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1125				return encoder;
1126		} else {
1127			if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1128			    encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1129				return encoder;
1130		}
1131	}
1132
1133	/* see if we have a default encoder  TODO */
1134
1135	/* then check use digitial */
1136	/* pick the first one */
1137	drm_connector_for_each_possible_encoder(connector, encoder, i)
1138		return encoder;
1139
1140	return NULL;
1141}
1142
1143static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1144{
1145	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 
1146	if (connector->force == DRM_FORCE_ON)
1147		amdgpu_connector->use_digital = false;
1148	if (connector->force == DRM_FORCE_ON_DIGITAL)
1149		amdgpu_connector->use_digital = true;
1150}
1151
1152static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1153					    struct drm_display_mode *mode)
1154{
1155	struct drm_device *dev = connector->dev;
1156	struct amdgpu_device *adev = dev->dev_private;
1157	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1158
1159	/* XXX check mode bandwidth */
1160
1161	if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1162		if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1163		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1164		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1165			return MODE_OK;
1166		} else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1167			/* HDMI 1.3+ supports max clock of 340 Mhz */
1168			if (mode->clock > 340000)
1169				return MODE_CLOCK_HIGH;
1170			else
1171				return MODE_OK;
1172		} else {
1173			return MODE_CLOCK_HIGH;
1174		}
1175	}
1176
1177	/* check against the max pixel clock */
1178	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1179		return MODE_CLOCK_HIGH;
1180
1181	return MODE_OK;
1182}
1183
1184static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1185	.get_modes = amdgpu_connector_vga_get_modes,
1186	.mode_valid = amdgpu_connector_dvi_mode_valid,
1187	.best_encoder = amdgpu_connector_dvi_encoder,
1188};
1189
1190static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1191	.dpms = drm_helper_connector_dpms,
1192	.detect = amdgpu_connector_dvi_detect,
1193	.fill_modes = drm_helper_probe_single_connector_modes,
1194	.set_property = amdgpu_connector_set_property,
1195	.early_unregister = amdgpu_connector_unregister,
1196	.destroy = amdgpu_connector_destroy,
1197	.force = amdgpu_connector_dvi_force,
1198};
1199
1200static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1201{
1202	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1203	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1204	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1205	int ret;
1206
1207	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1208	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1209		struct drm_display_mode *mode;
1210
1211		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1212			if (!amdgpu_dig_connector->edp_on)
1213				amdgpu_atombios_encoder_set_edp_panel_power(connector,
1214								     ATOM_TRANSMITTER_ACTION_POWER_ON);
1215			amdgpu_connector_get_edid(connector);
1216			ret = amdgpu_connector_ddc_get_modes(connector);
1217			if (!amdgpu_dig_connector->edp_on)
1218				amdgpu_atombios_encoder_set_edp_panel_power(connector,
1219								     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1220		} else {
1221			/* need to setup ddc on the bridge */
1222			if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1223			    ENCODER_OBJECT_ID_NONE) {
1224				if (encoder)
1225					amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1226			}
1227			amdgpu_connector_get_edid(connector);
1228			ret = amdgpu_connector_ddc_get_modes(connector);
1229		}
1230
1231		if (ret > 0) {
1232			if (encoder) {
1233				amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1234				/* add scaled modes */
1235				amdgpu_connector_add_common_modes(encoder, connector);
1236			}
1237			return ret;
1238		}
1239
1240		if (!encoder)
1241			return 0;
1242
1243		/* we have no EDID modes */
1244		mode = amdgpu_connector_lcd_native_mode(encoder);
1245		if (mode) {
1246			ret = 1;
1247			drm_mode_probed_add(connector, mode);
1248			/* add the width/height from vbios tables if available */
1249			connector->display_info.width_mm = mode->width_mm;
1250			connector->display_info.height_mm = mode->height_mm;
1251			/* add scaled modes */
1252			amdgpu_connector_add_common_modes(encoder, connector);
1253		}
1254	} else {
1255		/* need to setup ddc on the bridge */
1256		if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1257			ENCODER_OBJECT_ID_NONE) {
1258			if (encoder)
1259				amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1260		}
1261		amdgpu_connector_get_edid(connector);
1262		ret = amdgpu_connector_ddc_get_modes(connector);
1263
1264		amdgpu_get_native_mode(connector);
1265	}
1266
1267	return ret;
1268}
1269
1270u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1271{
1272	struct drm_encoder *encoder;
1273	struct amdgpu_encoder *amdgpu_encoder;
1274	int i;
1275
1276	drm_connector_for_each_possible_encoder(connector, encoder, i) {
1277		amdgpu_encoder = to_amdgpu_encoder(encoder);
1278
1279		switch (amdgpu_encoder->encoder_id) {
1280		case ENCODER_OBJECT_ID_TRAVIS:
1281		case ENCODER_OBJECT_ID_NUTMEG:
1282			return amdgpu_encoder->encoder_id;
1283		default:
1284			break;
1285		}
1286	}
1287
1288	return ENCODER_OBJECT_ID_NONE;
1289}
1290
1291static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1292{
1293	struct drm_encoder *encoder;
1294	struct amdgpu_encoder *amdgpu_encoder;
1295	int i;
1296	bool found = false;
1297
1298	drm_connector_for_each_possible_encoder(connector, encoder, i) {
1299		amdgpu_encoder = to_amdgpu_encoder(encoder);
1300		if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1301			found = true;
1302	}
1303
1304	return found;
1305}
1306
1307bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1308{
1309	struct drm_device *dev = connector->dev;
1310	struct amdgpu_device *adev = dev->dev_private;
1311
1312	if ((adev->clock.default_dispclk >= 53900) &&
1313	    amdgpu_connector_encoder_is_hbr2(connector)) {
1314		return true;
1315	}
1316
1317	return false;
1318}
1319
1320static enum drm_connector_status
1321amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1322{
1323	struct drm_device *dev = connector->dev;
1324	struct amdgpu_device *adev = dev->dev_private;
1325	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1326	enum drm_connector_status ret = connector_status_disconnected;
1327	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1328	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1329	int r;
1330
1331	if (!drm_kms_helper_is_poll_worker()) {
1332		r = pm_runtime_get_sync(connector->dev->dev);
1333		if (r < 0)
 
1334			return connector_status_disconnected;
 
1335	}
1336
1337	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1338		ret = connector->status;
1339		goto out;
1340	}
1341
1342	amdgpu_connector_free_edid(connector);
1343
1344	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1345	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1346		if (encoder) {
1347			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1348			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1349
1350			/* check if panel is valid */
1351			if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1352				ret = connector_status_connected;
1353		}
1354		/* eDP is always DP */
1355		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1356		if (!amdgpu_dig_connector->edp_on)
1357			amdgpu_atombios_encoder_set_edp_panel_power(connector,
1358							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1359		if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1360			ret = connector_status_connected;
1361		if (!amdgpu_dig_connector->edp_on)
1362			amdgpu_atombios_encoder_set_edp_panel_power(connector,
1363							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1364	} else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1365		   ENCODER_OBJECT_ID_NONE) {
1366		/* DP bridges are always DP */
1367		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1368		/* get the DPCD from the bridge */
1369		amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1370
1371		if (encoder) {
1372			/* setup ddc on the bridge */
1373			amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1374			/* bridge chips are always aux */
1375			/* try DDC */
1376			if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1377				ret = connector_status_connected;
1378			else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1379				const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 
1380				ret = encoder_funcs->detect(encoder, connector);
1381			}
1382		}
1383	} else {
1384		amdgpu_dig_connector->dp_sink_type =
1385			amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1386		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1387			ret = connector_status_connected;
1388			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1389				amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1390		} else {
1391			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1392				if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1393					ret = connector_status_connected;
1394			} else {
1395				/* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1396				if (amdgpu_display_ddc_probe(amdgpu_connector,
1397							     false))
1398					ret = connector_status_connected;
1399			}
1400		}
1401	}
1402
1403	amdgpu_connector_update_scratch_regs(connector, ret);
1404out:
1405	if (!drm_kms_helper_is_poll_worker()) {
1406		pm_runtime_mark_last_busy(connector->dev->dev);
1407		pm_runtime_put_autosuspend(connector->dev->dev);
1408	}
1409
 
 
 
 
 
 
1410	return ret;
1411}
1412
1413static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1414					   struct drm_display_mode *mode)
1415{
1416	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1417	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1418
1419	/* XXX check mode bandwidth */
1420
1421	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1422	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1423		struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1424
1425		if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1426			return MODE_PANEL;
1427
1428		if (encoder) {
1429			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1430			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1431
1432			/* AVIVO hardware supports downscaling modes larger than the panel
1433			 * to the panel size, but I'm not sure this is desirable.
1434			 */
1435			if ((mode->hdisplay > native_mode->hdisplay) ||
1436			    (mode->vdisplay > native_mode->vdisplay))
1437				return MODE_PANEL;
1438
1439			/* if scaling is disabled, block non-native modes */
1440			if (amdgpu_encoder->rmx_type == RMX_OFF) {
1441				if ((mode->hdisplay != native_mode->hdisplay) ||
1442				    (mode->vdisplay != native_mode->vdisplay))
1443					return MODE_PANEL;
1444			}
1445		}
1446		return MODE_OK;
1447	} else {
1448		if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1449		    (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1450			return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1451		} else {
1452			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1453				/* HDMI 1.3+ supports max clock of 340 Mhz */
1454				if (mode->clock > 340000)
1455					return MODE_CLOCK_HIGH;
1456			} else {
1457				if (mode->clock > 165000)
1458					return MODE_CLOCK_HIGH;
1459			}
1460		}
1461	}
1462
1463	return MODE_OK;
1464}
1465
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1466static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1467	.get_modes = amdgpu_connector_dp_get_modes,
1468	.mode_valid = amdgpu_connector_dp_mode_valid,
1469	.best_encoder = amdgpu_connector_dvi_encoder,
1470};
1471
1472static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1473	.dpms = drm_helper_connector_dpms,
1474	.detect = amdgpu_connector_dp_detect,
1475	.fill_modes = drm_helper_probe_single_connector_modes,
1476	.set_property = amdgpu_connector_set_property,
1477	.early_unregister = amdgpu_connector_unregister,
1478	.destroy = amdgpu_connector_destroy,
1479	.force = amdgpu_connector_dvi_force,
 
1480};
1481
1482static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1483	.dpms = drm_helper_connector_dpms,
1484	.detect = amdgpu_connector_dp_detect,
1485	.fill_modes = drm_helper_probe_single_connector_modes,
1486	.set_property = amdgpu_connector_set_lcd_property,
1487	.early_unregister = amdgpu_connector_unregister,
1488	.destroy = amdgpu_connector_destroy,
1489	.force = amdgpu_connector_dvi_force,
 
1490};
1491
1492void
1493amdgpu_connector_add(struct amdgpu_device *adev,
1494		      uint32_t connector_id,
1495		      uint32_t supported_device,
1496		      int connector_type,
1497		      struct amdgpu_i2c_bus_rec *i2c_bus,
1498		      uint16_t connector_object_id,
1499		      struct amdgpu_hpd *hpd,
1500		      struct amdgpu_router *router)
1501{
1502	struct drm_device *dev = adev->ddev;
1503	struct drm_connector *connector;
 
1504	struct amdgpu_connector *amdgpu_connector;
1505	struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1506	struct drm_encoder *encoder;
1507	struct amdgpu_encoder *amdgpu_encoder;
1508	struct i2c_adapter *ddc = NULL;
1509	uint32_t subpixel_order = SubPixelNone;
1510	bool shared_ddc = false;
1511	bool is_dp_bridge = false;
1512	bool has_aux = false;
1513
1514	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1515		return;
1516
1517	/* see if we already added it */
1518	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 
1519		amdgpu_connector = to_amdgpu_connector(connector);
1520		if (amdgpu_connector->connector_id == connector_id) {
1521			amdgpu_connector->devices |= supported_device;
 
1522			return;
1523		}
1524		if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1525			if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1526				amdgpu_connector->shared_ddc = true;
1527				shared_ddc = true;
1528			}
1529			if (amdgpu_connector->router_bus && router->ddc_valid &&
1530			    (amdgpu_connector->router.router_id == router->router_id)) {
1531				amdgpu_connector->shared_ddc = false;
1532				shared_ddc = false;
1533			}
1534		}
1535	}
 
1536
1537	/* check if it's a dp bridge */
1538	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1539		amdgpu_encoder = to_amdgpu_encoder(encoder);
1540		if (amdgpu_encoder->devices & supported_device) {
1541			switch (amdgpu_encoder->encoder_id) {
1542			case ENCODER_OBJECT_ID_TRAVIS:
1543			case ENCODER_OBJECT_ID_NUTMEG:
1544				is_dp_bridge = true;
1545				break;
1546			default:
1547				break;
1548			}
1549		}
1550	}
1551
1552	amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1553	if (!amdgpu_connector)
1554		return;
1555
1556	connector = &amdgpu_connector->base;
1557
1558	amdgpu_connector->connector_id = connector_id;
1559	amdgpu_connector->devices = supported_device;
1560	amdgpu_connector->shared_ddc = shared_ddc;
1561	amdgpu_connector->connector_object_id = connector_object_id;
1562	amdgpu_connector->hpd = *hpd;
1563
1564	amdgpu_connector->router = *router;
1565	if (router->ddc_valid || router->cd_valid) {
1566		amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1567		if (!amdgpu_connector->router_bus)
1568			DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1569	}
1570
1571	if (is_dp_bridge) {
1572		amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1573		if (!amdgpu_dig_connector)
1574			goto failed;
1575		amdgpu_connector->con_priv = amdgpu_dig_connector;
1576		if (i2c_bus->valid) {
1577			amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1578			if (amdgpu_connector->ddc_bus) {
1579				has_aux = true;
1580				ddc = &amdgpu_connector->ddc_bus->adapter;
1581			} else {
1582				DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1583			}
1584		}
1585		switch (connector_type) {
1586		case DRM_MODE_CONNECTOR_VGA:
1587		case DRM_MODE_CONNECTOR_DVIA:
1588		default:
1589			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1590						    &amdgpu_connector_dp_funcs,
1591						    connector_type,
1592						    ddc);
1593			drm_connector_helper_add(&amdgpu_connector->base,
1594						 &amdgpu_connector_dp_helper_funcs);
1595			connector->interlace_allowed = true;
1596			connector->doublescan_allowed = true;
1597			amdgpu_connector->dac_load_detect = true;
1598			drm_object_attach_property(&amdgpu_connector->base.base,
1599						      adev->mode_info.load_detect_property,
1600						      1);
1601			drm_object_attach_property(&amdgpu_connector->base.base,
1602						   dev->mode_config.scaling_mode_property,
1603						   DRM_MODE_SCALE_NONE);
1604			break;
1605		case DRM_MODE_CONNECTOR_DVII:
1606		case DRM_MODE_CONNECTOR_DVID:
1607		case DRM_MODE_CONNECTOR_HDMIA:
1608		case DRM_MODE_CONNECTOR_HDMIB:
1609		case DRM_MODE_CONNECTOR_DisplayPort:
1610			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1611						    &amdgpu_connector_dp_funcs,
1612						    connector_type,
1613						    ddc);
1614			drm_connector_helper_add(&amdgpu_connector->base,
1615						 &amdgpu_connector_dp_helper_funcs);
1616			drm_object_attach_property(&amdgpu_connector->base.base,
1617						      adev->mode_info.underscan_property,
1618						      UNDERSCAN_OFF);
1619			drm_object_attach_property(&amdgpu_connector->base.base,
1620						      adev->mode_info.underscan_hborder_property,
1621						      0);
1622			drm_object_attach_property(&amdgpu_connector->base.base,
1623						      adev->mode_info.underscan_vborder_property,
1624						      0);
1625
1626			drm_object_attach_property(&amdgpu_connector->base.base,
1627						   dev->mode_config.scaling_mode_property,
1628						   DRM_MODE_SCALE_NONE);
1629
1630			drm_object_attach_property(&amdgpu_connector->base.base,
1631						   adev->mode_info.dither_property,
1632						   AMDGPU_FMT_DITHER_DISABLE);
1633
1634			if (amdgpu_audio != 0)
1635				drm_object_attach_property(&amdgpu_connector->base.base,
1636							   adev->mode_info.audio_property,
1637							   AMDGPU_AUDIO_AUTO);
 
 
1638
1639			subpixel_order = SubPixelHorizontalRGB;
1640			connector->interlace_allowed = true;
1641			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1642				connector->doublescan_allowed = true;
1643			else
1644				connector->doublescan_allowed = false;
1645			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1646				amdgpu_connector->dac_load_detect = true;
1647				drm_object_attach_property(&amdgpu_connector->base.base,
1648							      adev->mode_info.load_detect_property,
1649							      1);
1650			}
1651			break;
1652		case DRM_MODE_CONNECTOR_LVDS:
1653		case DRM_MODE_CONNECTOR_eDP:
1654			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1655						    &amdgpu_connector_edp_funcs,
1656						    connector_type,
1657						    ddc);
1658			drm_connector_helper_add(&amdgpu_connector->base,
1659						 &amdgpu_connector_dp_helper_funcs);
1660			drm_object_attach_property(&amdgpu_connector->base.base,
1661						      dev->mode_config.scaling_mode_property,
1662						      DRM_MODE_SCALE_FULLSCREEN);
1663			subpixel_order = SubPixelHorizontalRGB;
1664			connector->interlace_allowed = false;
1665			connector->doublescan_allowed = false;
1666			break;
1667		}
1668	} else {
1669		switch (connector_type) {
1670		case DRM_MODE_CONNECTOR_VGA:
1671			if (i2c_bus->valid) {
1672				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1673				if (!amdgpu_connector->ddc_bus)
1674					DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1675				else
1676					ddc = &amdgpu_connector->ddc_bus->adapter;
1677			}
1678			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1679						    &amdgpu_connector_vga_funcs,
1680						    connector_type,
1681						    ddc);
1682			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1683			amdgpu_connector->dac_load_detect = true;
1684			drm_object_attach_property(&amdgpu_connector->base.base,
1685						      adev->mode_info.load_detect_property,
1686						      1);
1687			drm_object_attach_property(&amdgpu_connector->base.base,
1688						   dev->mode_config.scaling_mode_property,
1689						   DRM_MODE_SCALE_NONE);
1690			/* no HPD on analog connectors */
1691			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1692			connector->interlace_allowed = true;
1693			connector->doublescan_allowed = true;
1694			break;
1695		case DRM_MODE_CONNECTOR_DVIA:
1696			if (i2c_bus->valid) {
1697				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1698				if (!amdgpu_connector->ddc_bus)
1699					DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1700				else
1701					ddc = &amdgpu_connector->ddc_bus->adapter;
1702			}
1703			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1704						    &amdgpu_connector_vga_funcs,
1705						    connector_type,
1706						    ddc);
1707			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1708			amdgpu_connector->dac_load_detect = true;
1709			drm_object_attach_property(&amdgpu_connector->base.base,
1710						      adev->mode_info.load_detect_property,
1711						      1);
1712			drm_object_attach_property(&amdgpu_connector->base.base,
1713						   dev->mode_config.scaling_mode_property,
1714						   DRM_MODE_SCALE_NONE);
1715			/* no HPD on analog connectors */
1716			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1717			connector->interlace_allowed = true;
1718			connector->doublescan_allowed = true;
1719			break;
1720		case DRM_MODE_CONNECTOR_DVII:
1721		case DRM_MODE_CONNECTOR_DVID:
1722			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1723			if (!amdgpu_dig_connector)
1724				goto failed;
1725			amdgpu_connector->con_priv = amdgpu_dig_connector;
1726			if (i2c_bus->valid) {
1727				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1728				if (!amdgpu_connector->ddc_bus)
1729					DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1730				else
1731					ddc = &amdgpu_connector->ddc_bus->adapter;
1732			}
1733			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1734						    &amdgpu_connector_dvi_funcs,
1735						    connector_type,
1736						    ddc);
1737			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1738			subpixel_order = SubPixelHorizontalRGB;
1739			drm_object_attach_property(&amdgpu_connector->base.base,
1740						      adev->mode_info.coherent_mode_property,
1741						      1);
1742			drm_object_attach_property(&amdgpu_connector->base.base,
1743						   adev->mode_info.underscan_property,
1744						   UNDERSCAN_OFF);
1745			drm_object_attach_property(&amdgpu_connector->base.base,
1746						   adev->mode_info.underscan_hborder_property,
1747						   0);
1748			drm_object_attach_property(&amdgpu_connector->base.base,
1749						   adev->mode_info.underscan_vborder_property,
1750						   0);
1751			drm_object_attach_property(&amdgpu_connector->base.base,
1752						   dev->mode_config.scaling_mode_property,
1753						   DRM_MODE_SCALE_NONE);
1754
1755			if (amdgpu_audio != 0) {
1756				drm_object_attach_property(&amdgpu_connector->base.base,
1757							   adev->mode_info.audio_property,
1758							   AMDGPU_AUDIO_AUTO);
 
1759			}
1760			drm_object_attach_property(&amdgpu_connector->base.base,
1761						   adev->mode_info.dither_property,
1762						   AMDGPU_FMT_DITHER_DISABLE);
1763			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1764				amdgpu_connector->dac_load_detect = true;
1765				drm_object_attach_property(&amdgpu_connector->base.base,
1766							   adev->mode_info.load_detect_property,
1767							   1);
1768			}
1769			connector->interlace_allowed = true;
1770			if (connector_type == DRM_MODE_CONNECTOR_DVII)
1771				connector->doublescan_allowed = true;
1772			else
1773				connector->doublescan_allowed = false;
1774			break;
1775		case DRM_MODE_CONNECTOR_HDMIA:
1776		case DRM_MODE_CONNECTOR_HDMIB:
1777			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1778			if (!amdgpu_dig_connector)
1779				goto failed;
1780			amdgpu_connector->con_priv = amdgpu_dig_connector;
1781			if (i2c_bus->valid) {
1782				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1783				if (!amdgpu_connector->ddc_bus)
1784					DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1785				else
1786					ddc = &amdgpu_connector->ddc_bus->adapter;
1787			}
1788			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1789						    &amdgpu_connector_dvi_funcs,
1790						    connector_type,
1791						    ddc);
1792			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1793			drm_object_attach_property(&amdgpu_connector->base.base,
1794						      adev->mode_info.coherent_mode_property,
1795						      1);
1796			drm_object_attach_property(&amdgpu_connector->base.base,
1797						   adev->mode_info.underscan_property,
1798						   UNDERSCAN_OFF);
1799			drm_object_attach_property(&amdgpu_connector->base.base,
1800						   adev->mode_info.underscan_hborder_property,
1801						   0);
1802			drm_object_attach_property(&amdgpu_connector->base.base,
1803						   adev->mode_info.underscan_vborder_property,
1804						   0);
1805			drm_object_attach_property(&amdgpu_connector->base.base,
1806						   dev->mode_config.scaling_mode_property,
1807						   DRM_MODE_SCALE_NONE);
1808			if (amdgpu_audio != 0) {
1809				drm_object_attach_property(&amdgpu_connector->base.base,
1810							   adev->mode_info.audio_property,
1811							   AMDGPU_AUDIO_AUTO);
 
1812			}
1813			drm_object_attach_property(&amdgpu_connector->base.base,
1814						   adev->mode_info.dither_property,
1815						   AMDGPU_FMT_DITHER_DISABLE);
1816			subpixel_order = SubPixelHorizontalRGB;
1817			connector->interlace_allowed = true;
1818			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1819				connector->doublescan_allowed = true;
1820			else
1821				connector->doublescan_allowed = false;
1822			break;
1823		case DRM_MODE_CONNECTOR_DisplayPort:
1824			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1825			if (!amdgpu_dig_connector)
1826				goto failed;
1827			amdgpu_connector->con_priv = amdgpu_dig_connector;
1828			if (i2c_bus->valid) {
1829				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1830				if (amdgpu_connector->ddc_bus) {
1831					has_aux = true;
1832					ddc = &amdgpu_connector->ddc_bus->adapter;
1833				} else {
1834					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1835				}
1836			}
1837			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1838						    &amdgpu_connector_dp_funcs,
1839						    connector_type,
1840						    ddc);
1841			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1842			subpixel_order = SubPixelHorizontalRGB;
1843			drm_object_attach_property(&amdgpu_connector->base.base,
1844						      adev->mode_info.coherent_mode_property,
1845						      1);
1846			drm_object_attach_property(&amdgpu_connector->base.base,
1847						   adev->mode_info.underscan_property,
1848						   UNDERSCAN_OFF);
1849			drm_object_attach_property(&amdgpu_connector->base.base,
1850						   adev->mode_info.underscan_hborder_property,
1851						   0);
1852			drm_object_attach_property(&amdgpu_connector->base.base,
1853						   adev->mode_info.underscan_vborder_property,
1854						   0);
1855			drm_object_attach_property(&amdgpu_connector->base.base,
1856						   dev->mode_config.scaling_mode_property,
1857						   DRM_MODE_SCALE_NONE);
1858			if (amdgpu_audio != 0) {
1859				drm_object_attach_property(&amdgpu_connector->base.base,
1860							   adev->mode_info.audio_property,
1861							   AMDGPU_AUDIO_AUTO);
 
1862			}
1863			drm_object_attach_property(&amdgpu_connector->base.base,
1864						   adev->mode_info.dither_property,
1865						   AMDGPU_FMT_DITHER_DISABLE);
1866			connector->interlace_allowed = true;
1867			/* in theory with a DP to VGA converter... */
1868			connector->doublescan_allowed = false;
1869			break;
1870		case DRM_MODE_CONNECTOR_eDP:
1871			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1872			if (!amdgpu_dig_connector)
1873				goto failed;
1874			amdgpu_connector->con_priv = amdgpu_dig_connector;
1875			if (i2c_bus->valid) {
1876				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1877				if (amdgpu_connector->ddc_bus) {
1878					has_aux = true;
1879					ddc = &amdgpu_connector->ddc_bus->adapter;
1880				} else {
1881					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1882				}
1883			}
1884			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1885						    &amdgpu_connector_edp_funcs,
1886						    connector_type,
1887						    ddc);
1888			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1889			drm_object_attach_property(&amdgpu_connector->base.base,
1890						      dev->mode_config.scaling_mode_property,
1891						      DRM_MODE_SCALE_FULLSCREEN);
1892			subpixel_order = SubPixelHorizontalRGB;
1893			connector->interlace_allowed = false;
1894			connector->doublescan_allowed = false;
1895			break;
1896		case DRM_MODE_CONNECTOR_LVDS:
1897			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1898			if (!amdgpu_dig_connector)
1899				goto failed;
1900			amdgpu_connector->con_priv = amdgpu_dig_connector;
1901			if (i2c_bus->valid) {
1902				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1903				if (!amdgpu_connector->ddc_bus)
1904					DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1905				else
1906					ddc = &amdgpu_connector->ddc_bus->adapter;
1907			}
1908			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1909						    &amdgpu_connector_lvds_funcs,
1910						    connector_type,
1911						    ddc);
1912			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1913			drm_object_attach_property(&amdgpu_connector->base.base,
1914						      dev->mode_config.scaling_mode_property,
1915						      DRM_MODE_SCALE_FULLSCREEN);
1916			subpixel_order = SubPixelHorizontalRGB;
1917			connector->interlace_allowed = false;
1918			connector->doublescan_allowed = false;
1919			break;
1920		}
1921	}
1922
1923	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1924		if (i2c_bus->valid) {
1925			connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1926			                    DRM_CONNECTOR_POLL_DISCONNECT;
1927		}
1928	} else
1929		connector->polled = DRM_CONNECTOR_POLL_HPD;
1930
1931	connector->display_info.subpixel_order = subpixel_order;
1932	drm_connector_register(connector);
1933
1934	if (has_aux)
1935		amdgpu_atombios_dp_aux_init(amdgpu_connector);
 
 
 
 
 
1936
1937	return;
1938
1939failed:
1940	drm_connector_cleanup(connector);
1941	kfree(connector);
1942}