Loading...
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2017 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#ifndef __MIPS_ASM_MIPS_CPS_H__
8#define __MIPS_ASM_MIPS_CPS_H__
9
10#include <linux/io.h>
11#include <linux/types.h>
12
13extern unsigned long __cps_access_bad_size(void)
14 __compiletime_error("Bad size for CPS accessor");
15
16#define CPS_ACCESSOR_A(unit, off, name) \
17static inline void *addr_##unit##_##name(void) \
18{ \
19 return mips_##unit##_base + (off); \
20}
21
22#define CPS_ACCESSOR_R(unit, sz, name) \
23static inline uint##sz##_t read_##unit##_##name(void) \
24{ \
25 uint64_t val64; \
26 \
27 switch (sz) { \
28 case 32: \
29 return __raw_readl(addr_##unit##_##name()); \
30 \
31 case 64: \
32 if (mips_cm_is64) \
33 return __raw_readq(addr_##unit##_##name()); \
34 \
35 val64 = __raw_readl(addr_##unit##_##name() + 4); \
36 val64 <<= 32; \
37 val64 |= __raw_readl(addr_##unit##_##name()); \
38 return val64; \
39 \
40 default: \
41 return __cps_access_bad_size(); \
42 } \
43}
44
45#define CPS_ACCESSOR_W(unit, sz, name) \
46static inline void write_##unit##_##name(uint##sz##_t val) \
47{ \
48 switch (sz) { \
49 case 32: \
50 __raw_writel(val, addr_##unit##_##name()); \
51 break; \
52 \
53 case 64: \
54 if (mips_cm_is64) { \
55 __raw_writeq(val, addr_##unit##_##name()); \
56 break; \
57 } \
58 \
59 __raw_writel((uint64_t)val >> 32, \
60 addr_##unit##_##name() + 4); \
61 __raw_writel(val, addr_##unit##_##name()); \
62 break; \
63 \
64 default: \
65 __cps_access_bad_size(); \
66 break; \
67 } \
68}
69
70#define CPS_ACCESSOR_M(unit, sz, name) \
71static inline void change_##unit##_##name(uint##sz##_t mask, \
72 uint##sz##_t val) \
73{ \
74 uint##sz##_t reg_val = read_##unit##_##name(); \
75 reg_val &= ~mask; \
76 reg_val |= val; \
77 write_##unit##_##name(reg_val); \
78} \
79 \
80static inline void set_##unit##_##name(uint##sz##_t val) \
81{ \
82 change_##unit##_##name(val, val); \
83} \
84 \
85static inline void clear_##unit##_##name(uint##sz##_t val) \
86{ \
87 change_##unit##_##name(val, 0); \
88}
89
90#define CPS_ACCESSOR_RO(unit, sz, off, name) \
91 CPS_ACCESSOR_A(unit, off, name) \
92 CPS_ACCESSOR_R(unit, sz, name)
93
94#define CPS_ACCESSOR_WO(unit, sz, off, name) \
95 CPS_ACCESSOR_A(unit, off, name) \
96 CPS_ACCESSOR_W(unit, sz, name)
97
98#define CPS_ACCESSOR_RW(unit, sz, off, name) \
99 CPS_ACCESSOR_A(unit, off, name) \
100 CPS_ACCESSOR_R(unit, sz, name) \
101 CPS_ACCESSOR_W(unit, sz, name) \
102 CPS_ACCESSOR_M(unit, sz, name)
103
104#include <asm/mips-cm.h>
105#include <asm/mips-cpc.h>
106#include <asm/mips-gic.h>
107
108/**
109 * mips_cps_numclusters - return the number of clusters present in the system
110 *
111 * Returns the number of clusters in the system.
112 */
113static inline unsigned int mips_cps_numclusters(void)
114{
115 unsigned int num_clusters;
116
117 if (mips_cm_revision() < CM_REV_CM3_5)
118 return 1;
119
120 num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
121 num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
122 return num_clusters;
123}
124
125/**
126 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
127 * @cluster: the ID of the cluster whose config we want
128 *
129 * Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
130 *
131 * Returns the value of GCR_CONFIG.
132 */
133static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
134{
135 uint64_t config;
136
137 if (mips_cm_revision() < CM_REV_CM3_5) {
138 /*
139 * Prior to CM 3.5 we don't have the notion of multiple
140 * clusters so we can trivially read the GCR_CONFIG register
141 * within this cluster.
142 */
143 WARN_ON(cluster != 0);
144 config = read_gcr_config();
145 } else {
146 /*
147 * From CM 3.5 onwards we read the CPC_CONFIG mirror of
148 * GCR_CONFIG via the redirect region, since the CPC is always
149 * powered up allowing us not to need to power up the CM.
150 */
151 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
152 config = read_cpc_redir_config();
153 mips_cm_unlock_other();
154 }
155
156 return config;
157}
158
159/**
160 * mips_cps_numcores - return the number of cores present in a cluster
161 * @cluster: the ID of the cluster whose core count we want
162 *
163 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
164 * zero if no Coherence Manager is present.
165 */
166static inline unsigned int mips_cps_numcores(unsigned int cluster)
167{
168 if (!mips_cm_present())
169 return 0;
170
171 /* Add one before masking to handle 0xff indicating no cores */
172 return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
173}
174
175/**
176 * mips_cps_numiocu - return the number of IOCUs present in a cluster
177 * @cluster: the ID of the cluster whose IOCU count we want
178 *
179 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
180 * if no Coherence Manager is present.
181 */
182static inline unsigned int mips_cps_numiocu(unsigned int cluster)
183{
184 unsigned int num_iocu;
185
186 if (!mips_cm_present())
187 return 0;
188
189 num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
190 num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
191 return num_iocu;
192}
193
194/**
195 * mips_cps_numvps - return the number of VPs (threads) supported by a core
196 * @cluster: the ID of the cluster containing the core we want to examine
197 * @core: the ID of the core whose VP count we want
198 *
199 * Returns the number of Virtual Processors (VPs, ie. hardware threads) that
200 * are supported by the given @core in the given @cluster. If the core or the
201 * kernel do not support hardware mutlti-threading this returns 1.
202 */
203static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
204{
205 unsigned int cfg;
206
207 if (!mips_cm_present())
208 return 1;
209
210 if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
211 && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
212 return 1;
213
214 mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
215
216 if (mips_cm_revision() < CM_REV_CM3_5) {
217 /*
218 * Prior to CM 3.5 we can only have one cluster & don't have
219 * CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
220 */
221 cfg = read_gcr_co_config();
222 } else {
223 /*
224 * From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
225 * always powered, which allows us to not worry about powering
226 * up the cluster's CM here.
227 */
228 cfg = read_cpc_co_config();
229 }
230
231 mips_cm_unlock_other();
232
233 return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
234}
235
236#endif /* __MIPS_ASM_MIPS_CPS_H__ */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2017 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#ifndef __MIPS_ASM_MIPS_CPS_H__
8#define __MIPS_ASM_MIPS_CPS_H__
9
10#include <linux/bitfield.h>
11#include <linux/cpumask.h>
12#include <linux/io.h>
13#include <linux/types.h>
14
15extern unsigned long __cps_access_bad_size(void)
16 __compiletime_error("Bad size for CPS accessor");
17
18#define CPS_ACCESSOR_A(unit, off, name) \
19static inline void *addr_##unit##_##name(void) \
20{ \
21 return mips_##unit##_base + (off); \
22}
23
24#define CPS_ACCESSOR_R(unit, sz, name) \
25static inline uint##sz##_t read_##unit##_##name(void) \
26{ \
27 uint64_t val64; \
28 \
29 switch (sz) { \
30 case 32: \
31 return __raw_readl(addr_##unit##_##name()); \
32 \
33 case 64: \
34 if (mips_cm_is64) \
35 return __raw_readq(addr_##unit##_##name()); \
36 \
37 val64 = __raw_readl(addr_##unit##_##name() + 4); \
38 val64 <<= 32; \
39 val64 |= __raw_readl(addr_##unit##_##name()); \
40 return val64; \
41 \
42 default: \
43 return __cps_access_bad_size(); \
44 } \
45}
46
47#define CPS_ACCESSOR_W(unit, sz, name) \
48static inline void write_##unit##_##name(uint##sz##_t val) \
49{ \
50 switch (sz) { \
51 case 32: \
52 __raw_writel(val, addr_##unit##_##name()); \
53 break; \
54 \
55 case 64: \
56 if (mips_cm_is64) { \
57 __raw_writeq(val, addr_##unit##_##name()); \
58 break; \
59 } \
60 \
61 __raw_writel((uint64_t)val >> 32, \
62 addr_##unit##_##name() + 4); \
63 __raw_writel(val, addr_##unit##_##name()); \
64 break; \
65 \
66 default: \
67 __cps_access_bad_size(); \
68 break; \
69 } \
70}
71
72#define CPS_ACCESSOR_M(unit, sz, name) \
73static inline void change_##unit##_##name(uint##sz##_t mask, \
74 uint##sz##_t val) \
75{ \
76 uint##sz##_t reg_val = read_##unit##_##name(); \
77 reg_val &= ~mask; \
78 reg_val |= val; \
79 write_##unit##_##name(reg_val); \
80} \
81 \
82static inline void set_##unit##_##name(uint##sz##_t val) \
83{ \
84 change_##unit##_##name(val, val); \
85} \
86 \
87static inline void clear_##unit##_##name(uint##sz##_t val) \
88{ \
89 change_##unit##_##name(val, 0); \
90}
91
92#define CPS_ACCESSOR_RO(unit, sz, off, name) \
93 CPS_ACCESSOR_A(unit, off, name) \
94 CPS_ACCESSOR_R(unit, sz, name)
95
96#define CPS_ACCESSOR_WO(unit, sz, off, name) \
97 CPS_ACCESSOR_A(unit, off, name) \
98 CPS_ACCESSOR_W(unit, sz, name)
99
100#define CPS_ACCESSOR_RW(unit, sz, off, name) \
101 CPS_ACCESSOR_A(unit, off, name) \
102 CPS_ACCESSOR_R(unit, sz, name) \
103 CPS_ACCESSOR_W(unit, sz, name) \
104 CPS_ACCESSOR_M(unit, sz, name)
105
106#include <asm/mips-cm.h>
107#include <asm/mips-cpc.h>
108#include <asm/mips-gic.h>
109
110/**
111 * mips_cps_numclusters - return the number of clusters present in the system
112 *
113 * Returns the number of clusters in the system.
114 */
115static inline unsigned int mips_cps_numclusters(void)
116{
117 if (mips_cm_revision() < CM_REV_CM3_5)
118 return 1;
119
120 return FIELD_GET(CM_GCR_CONFIG_NUM_CLUSTERS, read_gcr_config());
121}
122
123/**
124 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
125 * @cluster: the ID of the cluster whose config we want
126 *
127 * Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
128 *
129 * Returns the value of GCR_CONFIG.
130 */
131static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
132{
133 uint64_t config;
134
135 if (mips_cm_revision() < CM_REV_CM3_5) {
136 /*
137 * Prior to CM 3.5 we don't have the notion of multiple
138 * clusters so we can trivially read the GCR_CONFIG register
139 * within this cluster.
140 */
141 WARN_ON(cluster != 0);
142 config = read_gcr_config();
143 } else {
144 /*
145 * From CM 3.5 onwards we read the CPC_CONFIG mirror of
146 * GCR_CONFIG via the redirect region, since the CPC is always
147 * powered up allowing us not to need to power up the CM.
148 */
149 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
150 config = read_cpc_redir_config();
151 mips_cm_unlock_other();
152 }
153
154 return config;
155}
156
157/**
158 * mips_cps_numcores - return the number of cores present in a cluster
159 * @cluster: the ID of the cluster whose core count we want
160 *
161 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
162 * zero if no Coherence Manager is present.
163 */
164static inline unsigned int mips_cps_numcores(unsigned int cluster)
165{
166 if (!mips_cm_present())
167 return 0;
168
169 /* Add one before masking to handle 0xff indicating no cores */
170 return FIELD_GET(CM_GCR_CONFIG_PCORES,
171 mips_cps_cluster_config(cluster) + 1);
172}
173
174/**
175 * mips_cps_numiocu - return the number of IOCUs present in a cluster
176 * @cluster: the ID of the cluster whose IOCU count we want
177 *
178 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
179 * if no Coherence Manager is present.
180 */
181static inline unsigned int mips_cps_numiocu(unsigned int cluster)
182{
183 if (!mips_cm_present())
184 return 0;
185
186 return FIELD_GET(CM_GCR_CONFIG_NUMIOCU,
187 mips_cps_cluster_config(cluster));
188}
189
190/**
191 * mips_cps_numvps - return the number of VPs (threads) supported by a core
192 * @cluster: the ID of the cluster containing the core we want to examine
193 * @core: the ID of the core whose VP count we want
194 *
195 * Returns the number of Virtual Processors (VPs, ie. hardware threads) that
196 * are supported by the given @core in the given @cluster. If the core or the
197 * kernel do not support hardware mutlti-threading this returns 1.
198 */
199static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
200{
201 unsigned int cfg;
202
203 if (!mips_cm_present())
204 return 1;
205
206 if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
207 && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
208 return 1;
209
210 mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
211
212 if (mips_cm_revision() < CM_REV_CM3_5) {
213 /*
214 * Prior to CM 3.5 we can only have one cluster & don't have
215 * CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
216 */
217 cfg = read_gcr_co_config();
218 } else {
219 /*
220 * From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
221 * always powered, which allows us to not worry about powering
222 * up the cluster's CM here.
223 */
224 cfg = read_cpc_co_config();
225 }
226
227 mips_cm_unlock_other();
228
229 return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1);
230}
231
232/**
233 * mips_cps_multicluster_cpus() - Detect whether CPUs are in multiple clusters
234 *
235 * Determine whether the system includes CPUs in multiple clusters - ie.
236 * whether we can treat the system as single or multi-cluster as far as CPUs
237 * are concerned. Note that this is slightly different to simply checking
238 * whether multiple clusters are present - it is possible for there to be
239 * clusters which contain no CPUs, which this function will effectively ignore.
240 *
241 * Returns true if CPUs are spread across multiple clusters, else false.
242 */
243static inline bool mips_cps_multicluster_cpus(void)
244{
245 unsigned int first_cl, last_cl;
246
247 /*
248 * CPUs are numbered sequentially by cluster - ie. CPUs 0..X will be in
249 * cluster 0, CPUs X+1..Y in cluster 1, CPUs Y+1..Z in cluster 2 etc.
250 *
251 * Thus we can detect multiple clusters trivially by checking whether
252 * the first & last CPUs belong to the same cluster.
253 */
254 first_cl = cpu_cluster(&boot_cpu_data);
255 last_cl = cpu_cluster(&cpu_data[nr_cpu_ids - 1]);
256 return first_cl != last_cl;
257}
258
259/**
260 * mips_cps_first_online_in_cluster() - Detect if CPU is first online in cluster
261 *
262 * Determine whether the local CPU is the first to be brought online in its
263 * cluster - that is, whether there are any other online CPUs in the local
264 * cluster.
265 *
266 * Returns true if this CPU is first online, else false.
267 */
268extern unsigned int mips_cps_first_online_in_cluster(void);
269
270#endif /* __MIPS_ASM_MIPS_CPS_H__ */