1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *
 4 * Copyright (C) 2015 John Crispin <john@phrozen.org>
 5 */
 6
 7#ifndef _MT7621_REGS_H_
 8#define _MT7621_REGS_H_
 9
 
 
10#define MT7621_PALMBUS_BASE		0x1C000000
11#define MT7621_PALMBUS_SIZE		0x03FFFFFF
12
13#define MT7621_SYSC_BASE		0x1E000000
14
15#define SYSC_REG_CHIP_NAME0		0x00
16#define SYSC_REG_CHIP_NAME1		0x04
17#define SYSC_REG_CHIP_REV		0x0c
18#define SYSC_REG_SYSTEM_CONFIG0		0x10
19#define SYSC_REG_SYSTEM_CONFIG1		0x14
20
21#define CHIP_REV_PKG_MASK		0x1
22#define CHIP_REV_PKG_SHIFT		16
23#define CHIP_REV_VER_MASK		0xf
24#define CHIP_REV_VER_SHIFT		8
25#define CHIP_REV_ECO_MASK		0xf
26
27#define MT7621_DRAM_BASE                0x0
28#define MT7621_DDR2_SIZE_MIN		32
29#define MT7621_DDR2_SIZE_MAX		256
 
30
31#define MT7621_CHIP_NAME0		0x3637544D
32#define MT7621_CHIP_NAME1		0x20203132
33
34#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
35
36#endif

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *
 4 * Copyright (C) 2015 John Crispin <john@phrozen.org>
 5 */
 6
 7#ifndef _MT7621_REGS_H_
 8#define _MT7621_REGS_H_
 9
10#define IOMEM(x)			((void __iomem *)(KSEG1ADDR(x)))
11
12#define MT7621_PALMBUS_BASE		0x1C000000
13#define MT7621_PALMBUS_SIZE		0x03FFFFFF
14
15#define MT7621_SYSC_BASE		IOMEM(0x1E000000)
16
17#define SYSC_REG_CHIP_NAME0		0x00
18#define SYSC_REG_CHIP_NAME1		0x04
19#define SYSC_REG_CHIP_REV		0x0c
20#define SYSC_REG_SYSTEM_CONFIG0		0x10
21#define SYSC_REG_SYSTEM_CONFIG1		0x14
22
23#define CHIP_REV_PKG_MASK		0x1
24#define CHIP_REV_PKG_SHIFT		16
25#define CHIP_REV_VER_MASK		0xf
26#define CHIP_REV_VER_SHIFT		8
27#define CHIP_REV_ECO_MASK		0xf
28
29#define MT7621_LOWMEM_BASE		0x0
30#define MT7621_LOWMEM_MAX_SIZE		0x1C000000
31#define MT7621_HIGHMEM_BASE		0x20000000
32#define MT7621_HIGHMEM_SIZE		0x4000000
33
34#define MT7621_CHIP_NAME0		0x3637544D
35#define MT7621_CHIP_NAME1		0x20203132
 
 
36
37#endif