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v5.4
  1// SPDX-License-Identifier: GPL-2.0
 
 
 
 
  2/ {
  3	#address-cells = <1>;
  4	#size-cells = <1>;
  5	compatible = "brcm,bcm6358";
  6
  7	cpus {
  8		#address-cells = <1>;
  9		#size-cells = <0>;
 10
 11		mips-hpt-frequency = <150000000>;
 
 12
 13		cpu@0 {
 14			compatible = "brcm,bmips4350";
 15			device_type = "cpu";
 16			reg = <0>;
 17		};
 18
 19		cpu@1 {
 20			compatible = "brcm,bmips4350";
 21			device_type = "cpu";
 22			reg = <1>;
 23		};
 24	};
 25
 26	clocks {
 27		periph_clk: periph-clk {
 28			compatible = "fixed-clock";
 29			#clock-cells = <0>;
 30			clock-frequency = <50000000>;
 
 31		};
 32	};
 33
 34	aliases {
 
 35		serial0 = &uart0;
 36		serial1 = &uart1;
 
 37	};
 38
 39	cpu_intc: interrupt-controller {
 40		#address-cells = <0>;
 41		compatible = "mti,cpu-interrupt-controller";
 42
 43		interrupt-controller;
 44		#interrupt-cells = <1>;
 45	};
 46
 47	ubus {
 48		#address-cells = <1>;
 49		#size-cells = <1>;
 50
 51		compatible = "simple-bus";
 52		ranges;
 53
 54		clkctl: clock-controller@fffe0004 {
 55			compatible = "brcm,bcm6358-clocks";
 56			reg = <0xfffe0004 0x4>;
 57			#clock-cells = <1>;
 58		};
 59
 60		periph_cntl: syscon@fffe0008 {
 61			compatible = "syscon";
 62			reg = <0xfffe0000 0x4>;
 63			native-endian;
 64		};
 65
 66		reboot: syscon-reboot@fffe0008 {
 67			compatible = "syscon-reboot";
 68			regmap = <&periph_cntl>;
 69			offset = <0x0>;
 70			mask = <0x1>;
 71		};
 72
 73		periph_intc: interrupt-controller@fffe000c {
 74			compatible = "brcm,bcm6345-l1-intc";
 75			reg = <0xfffe000c 0x8>,
 76			      <0xfffe0038 0x8>;
 77
 78			interrupt-controller;
 79			#interrupt-cells = <1>;
 80
 81			interrupt-parent = <&cpu_intc>;
 82			interrupts = <2>, <3>;
 83		};
 84
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 85		leds0: led-controller@fffe00d0 {
 86			#address-cells = <1>;
 87			#size-cells = <0>;
 88			compatible = "brcm,bcm6358-leds";
 89			reg = <0xfffe00d0 0x8>;
 90
 91			status = "disabled";
 92		};
 93
 94		uart0: serial@fffe0100 {
 95			compatible = "brcm,bcm6345-uart";
 96			reg = <0xfffe0100 0x18>;
 97
 98			interrupt-parent = <&periph_intc>;
 99			interrupts = <2>;
100
101			clocks = <&periph_clk>;
102			clock-names = "refclk";
103
104			status = "disabled";
105		};
106
107		uart1: serial@fffe0120 {
108			compatible = "brcm,bcm6345-uart";
109			reg = <0xfffe0120 0x18>;
110
111			interrupt-parent = <&periph_intc>;
112			interrupts = <3>;
113
114			clocks = <&periph_clk>;
115			clock-names = "refclk";
116
117			status = "disabled";
118		};
119
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
120		ehci: usb@fffe1300 {
121			compatible = "brcm,bcm6358-ehci", "generic-ehci";
122			reg = <0xfffe1300 0x100>;
123			big-endian;
 
124			interrupt-parent = <&periph_intc>;
125			interrupts = <10>;
 
 
 
 
126			status = "disabled";
127		};
128
129		ohci: usb@fffe1400 {
130			compatible = "brcm,bcm6358-ohci", "generic-ohci";
131			reg = <0xfffe1400 0x100>;
132			big-endian;
133			no-big-frame-no;
 
134			interrupt-parent = <&periph_intc>;
135			interrupts = <5>;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
136			status = "disabled";
137		};
 
 
 
 
 
 
 
 
 
 
138	};
139};
v6.13.7
  1// SPDX-License-Identifier: GPL-2.0
  2
  3#include "dt-bindings/clock/bcm6358-clock.h"
  4#include "dt-bindings/reset/bcm6358-reset.h"
  5
  6/ {
  7	#address-cells = <1>;
  8	#size-cells = <1>;
  9	compatible = "brcm,bcm6358";
 10
 11	cpus {
 12		#address-cells = <1>;
 13		#size-cells = <0>;
 14
 15		mips-hpt-frequency = <150000000>;
 16		brcm,bmips-cbr-reg = <0xff400000>;
 17
 18		cpu@0 {
 19			compatible = "brcm,bmips4350";
 20			device_type = "cpu";
 21			reg = <0>;
 22		};
 23
 24		cpu@1 {
 25			compatible = "brcm,bmips4350";
 26			device_type = "cpu";
 27			reg = <1>;
 28		};
 29	};
 30
 31	clocks {
 32		periph_osc: periph-osc {
 33			compatible = "fixed-clock";
 34			#clock-cells = <0>;
 35			clock-frequency = <50000000>;
 36			clock-output-names = "periph";
 37		};
 38	};
 39
 40	aliases {
 41		pflash = &pflash;
 42		serial0 = &uart0;
 43		serial1 = &uart1;
 44		spi0 = &lsspi;
 45	};
 46
 47	cpu_intc: interrupt-controller {
 48		#address-cells = <0>;
 49		compatible = "mti,cpu-interrupt-controller";
 50
 51		interrupt-controller;
 52		#interrupt-cells = <1>;
 53	};
 54
 55	ubus {
 56		#address-cells = <1>;
 57		#size-cells = <1>;
 58
 59		compatible = "simple-bus";
 60		ranges;
 61
 62		periph_clk: clock-controller@fffe0004 {
 63			compatible = "brcm,bcm6358-clocks";
 64			reg = <0xfffe0004 0x4>;
 65			#clock-cells = <1>;
 66		};
 67
 68		pll_cntl: syscon@fffe0008 {
 69			compatible = "syscon";
 70			reg = <0xfffe0008 0x4>;
 71			native-endian;
 
 72
 73			reboot {
 74				compatible = "syscon-reboot";
 75				offset = <0x0>;
 76				mask = <0x1>;
 77			};
 78		};
 79
 80		periph_intc: interrupt-controller@fffe000c {
 81			compatible = "brcm,bcm6345-l1-intc";
 82			reg = <0xfffe000c 0x8>,
 83			      <0xfffe0038 0x8>;
 84
 85			interrupt-controller;
 86			#interrupt-cells = <1>;
 87
 88			interrupt-parent = <&cpu_intc>;
 89			interrupts = <2>, <3>;
 90		};
 91
 92		periph_rst: reset-controller@fffe0034 {
 93			compatible = "brcm,bcm6345-reset";
 94			reg = <0xfffe0034 0x4>;
 95			#reset-cells = <1>;
 96		};
 97
 98		wdt: watchdog@fffe005c {
 99			compatible = "brcm,bcm7038-wdt";
100			reg = <0xfffe005c 0xc>;
101
102			clocks = <&periph_osc>;
103			clock-names = "refclk";
104
105			timeout-sec = <30>;
106		};
107
108		leds0: led-controller@fffe00d0 {
109			#address-cells = <1>;
110			#size-cells = <0>;
111			compatible = "brcm,bcm6358-leds";
112			reg = <0xfffe00d0 0x8>;
113
114			status = "disabled";
115		};
116
117		uart0: serial@fffe0100 {
118			compatible = "brcm,bcm6345-uart";
119			reg = <0xfffe0100 0x18>;
120
121			interrupt-parent = <&periph_intc>;
122			interrupts = <2>;
123
124			clocks = <&periph_osc>;
125			clock-names = "refclk";
126
127			status = "disabled";
128		};
129
130		uart1: serial@fffe0120 {
131			compatible = "brcm,bcm6345-uart";
132			reg = <0xfffe0120 0x18>;
133
134			interrupt-parent = <&periph_intc>;
135			interrupts = <3>;
136
137			clocks = <&periph_osc>;
138			clock-names = "refclk";
139
140			status = "disabled";
141		};
142
143		lsspi: spi@fffe0800 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			compatible = "brcm,bcm6358-spi";
147			reg = <0xfffe0800 0x70c>;
148
149			interrupt-parent = <&periph_intc>;
150			interrupts = <1>;
151
152			clocks = <&periph_clk BCM6358_CLK_SPI>;
153			clock-names = "spi";
154
155			resets = <&periph_rst BCM6358_RST_SPI>;
156			reset-names = "spi";
157
158			status = "disabled";
159		};
160
161		ehci: usb@fffe1300 {
162			compatible = "brcm,bcm6358-ehci", "generic-ehci";
163			reg = <0xfffe1300 0x100>;
164			big-endian;
165
166			interrupt-parent = <&periph_intc>;
167			interrupts = <10>;
168
169			phys = <&usbh 0>;
170			phy-names = "usb";
171
172			status = "disabled";
173		};
174
175		ohci: usb@fffe1400 {
176			compatible = "brcm,bcm6358-ohci", "generic-ohci";
177			reg = <0xfffe1400 0x100>;
178			big-endian;
179			no-big-frame-no;
180
181			interrupt-parent = <&periph_intc>;
182			interrupts = <5>;
183
184			phys = <&usbh 0>;
185			phy-names = "usb";
186
187			status = "disabled";
188		};
189
190		usbh: usb-phy@fffe1500 {
191			compatible = "brcm,bcm6358-usbh-phy";
192			reg = <0xfffe1500 0x38>;
193			#phy-cells = <1>;
194
195			resets = <&periph_rst BCM6358_RST_USBH>;
196			reset-names = "usbh";
197
198			status = "disabled";
199		};
200	};
201
202	pflash: nor@1e000000 {
203		#address-cells = <1>;
204		#size-cells = <1>;
205		compatible = "cfi-flash";
206		reg = <0x1e000000 0x2000000>;
207		bank-width = <2>;
208
209		status = "disabled";
210	};
211};