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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 *
5 * Heavily based on proc-arm926.S
6 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 */
8
9#include <linux/linkage.h>
10#include <linux/init.h>
11#include <asm/assembler.h>
12#include <asm/hwcap.h>
13#include <asm/pgtable-hwdef.h>
14#include <asm/pgtable.h>
15#include <asm/page.h>
16#include <asm/ptrace.h>
17#include "proc-macros.S"
18
19/*
20 * This is the maximum size of an area which will be invalidated
21 * using the single invalidate entry instructions. Anything larger
22 * than this, and we go for the whole cache.
23 *
24 * This value should be chosen such that we choose the cheapest
25 * alternative.
26 */
27#define CACHE_DLIMIT 16384
28
29/*
30 * the cache line size of the I and D cache
31 */
32#define CACHE_DLINESIZE 32
33
34 .bss
35 .align 3
36__cache_params_loc:
37 .space 8
38
39 .text
40__cache_params:
41 .word __cache_params_loc
42
43/*
44 * cpu_feroceon_proc_init()
45 */
46ENTRY(cpu_feroceon_proc_init)
47 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
48 ldr r1, __cache_params
49 mov r2, #(16 << 5)
50 tst r0, #(1 << 16) @ get way
51 mov r0, r0, lsr #18 @ get cache size order
52 movne r3, #((4 - 1) << 30) @ 4-way
53 and r0, r0, #0xf
54 moveq r3, #0 @ 1-way
55 mov r2, r2, lsl r0 @ actual cache size
56 movne r2, r2, lsr #2 @ turned into # of sets
57 sub r2, r2, #(1 << 5)
58 stmia r1, {r2, r3}
59 ret lr
60
61/*
62 * cpu_feroceon_proc_fin()
63 */
64ENTRY(cpu_feroceon_proc_fin)
65#if defined(CONFIG_CACHE_FEROCEON_L2) && \
66 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
67 mov r0, #0
68 mcr p15, 1, r0, c15, c9, 0 @ clean L2
69 mcr p15, 0, r0, c7, c10, 4 @ drain WB
70#endif
71
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 ret lr
77
78/*
79 * cpu_feroceon_reset(loc)
80 *
81 * Perform a soft reset of the system. Put the CPU into the
82 * same state as it would be if it had been reset, and branch
83 * to what would be the reset vector.
84 *
85 * loc: location to jump to for soft reset
86 */
87 .align 5
88 .pushsection .idmap.text, "ax"
89ENTRY(cpu_feroceon_reset)
90 mov ip, #0
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93#ifdef CONFIG_MMU
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95#endif
96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
97 bic ip, ip, #0x000f @ ............wcam
98 bic ip, ip, #0x1100 @ ...i...s........
99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
100 ret r0
101ENDPROC(cpu_feroceon_reset)
102 .popsection
103
104/*
105 * cpu_feroceon_do_idle()
106 *
107 * Called with IRQs disabled
108 */
109 .align 5
110ENTRY(cpu_feroceon_do_idle)
111 mov r0, #0
112 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
113 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
114 ret lr
115
116/*
117 * flush_icache_all()
118 *
119 * Unconditionally clean and invalidate the entire icache.
120 */
121ENTRY(feroceon_flush_icache_all)
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
124 ret lr
125ENDPROC(feroceon_flush_icache_all)
126
127/*
128 * flush_user_cache_all()
129 *
130 * Clean and invalidate all cache entries in a particular
131 * address space.
132 */
133 .align 5
134ENTRY(feroceon_flush_user_cache_all)
135 /* FALLTHROUGH */
136
137/*
138 * flush_kern_cache_all()
139 *
140 * Clean and invalidate the entire cache.
141 */
142ENTRY(feroceon_flush_kern_cache_all)
143 mov r2, #VM_EXEC
144
145__flush_whole_cache:
146 ldr r1, __cache_params
147 ldmia r1, {r1, r3}
1481: orr ip, r1, r3
1492: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
150 subs ip, ip, #(1 << 30) @ next way
151 bcs 2b
152 subs r1, r1, #(1 << 5) @ next set
153 bcs 1b
154
155 tst r2, #VM_EXEC
156 mov ip, #0
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 ret lr
160
161/*
162 * flush_user_cache_range(start, end, flags)
163 *
164 * Clean and invalidate a range of cache entries in the
165 * specified address range.
166 *
167 * - start - start address (inclusive)
168 * - end - end address (exclusive)
169 * - flags - vm_flags describing address space
170 */
171 .align 5
172ENTRY(feroceon_flush_user_cache_range)
173 sub r3, r1, r0 @ calculate total size
174 cmp r3, #CACHE_DLIMIT
175 bgt __flush_whole_cache
1761: tst r2, #VM_EXEC
177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
182 add r0, r0, #CACHE_DLINESIZE
183 cmp r0, r1
184 blo 1b
185 tst r2, #VM_EXEC
186 mov ip, #0
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 ret lr
189
190/*
191 * coherent_kern_range(start, end)
192 *
193 * Ensure coherency between the Icache and the Dcache in the
194 * region described by start, end. If you have non-snooping
195 * Harvard caches, you need to implement this function.
196 *
197 * - start - virtual start address
198 * - end - virtual end address
199 */
200 .align 5
201ENTRY(feroceon_coherent_kern_range)
202 /* FALLTHROUGH */
203
204/*
205 * coherent_user_range(start, end)
206 *
207 * Ensure coherency between the Icache and the Dcache in the
208 * region described by start, end. If you have non-snooping
209 * Harvard caches, you need to implement this function.
210 *
211 * - start - virtual start address
212 * - end - virtual end address
213 */
214ENTRY(feroceon_coherent_user_range)
215 bic r0, r0, #CACHE_DLINESIZE - 1
2161: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
217 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
218 add r0, r0, #CACHE_DLINESIZE
219 cmp r0, r1
220 blo 1b
221 mcr p15, 0, r0, c7, c10, 4 @ drain WB
222 mov r0, #0
223 ret lr
224
225/*
226 * flush_kern_dcache_area(void *addr, size_t size)
227 *
228 * Ensure no D cache aliasing occurs, either with itself or
229 * the I cache
230 *
231 * - addr - kernel address
232 * - size - region size
233 */
234 .align 5
235ENTRY(feroceon_flush_kern_dcache_area)
236 add r1, r0, r1
2371: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
238 add r0, r0, #CACHE_DLINESIZE
239 cmp r0, r1
240 blo 1b
241 mov r0, #0
242 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
243 mcr p15, 0, r0, c7, c10, 4 @ drain WB
244 ret lr
245
246 .align 5
247ENTRY(feroceon_range_flush_kern_dcache_area)
248 mrs r2, cpsr
249 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
250 orr r3, r2, #PSR_I_BIT
251 msr cpsr_c, r3 @ disable interrupts
252 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
253 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
254 msr cpsr_c, r2 @ restore interrupts
255 mov r0, #0
256 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
257 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 ret lr
259
260/*
261 * dma_inv_range(start, end)
262 *
263 * Invalidate (discard) the specified virtual address range.
264 * May not write back any entries. If 'start' or 'end'
265 * are not cache line aligned, those lines must be written
266 * back.
267 *
268 * - start - virtual start address
269 * - end - virtual end address
270 *
271 * (same as v4wb)
272 */
273 .align 5
274feroceon_dma_inv_range:
275 tst r0, #CACHE_DLINESIZE - 1
276 bic r0, r0, #CACHE_DLINESIZE - 1
277 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
278 tst r1, #CACHE_DLINESIZE - 1
279 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2801: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
281 add r0, r0, #CACHE_DLINESIZE
282 cmp r0, r1
283 blo 1b
284 mcr p15, 0, r0, c7, c10, 4 @ drain WB
285 ret lr
286
287 .align 5
288feroceon_range_dma_inv_range:
289 mrs r2, cpsr
290 tst r0, #CACHE_DLINESIZE - 1
291 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
292 tst r1, #CACHE_DLINESIZE - 1
293 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
294 cmp r1, r0
295 subne r1, r1, #1 @ top address is inclusive
296 orr r3, r2, #PSR_I_BIT
297 msr cpsr_c, r3 @ disable interrupts
298 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
299 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
300 msr cpsr_c, r2 @ restore interrupts
301 ret lr
302
303/*
304 * dma_clean_range(start, end)
305 *
306 * Clean the specified virtual address range.
307 *
308 * - start - virtual start address
309 * - end - virtual end address
310 *
311 * (same as v4wb)
312 */
313 .align 5
314feroceon_dma_clean_range:
315 bic r0, r0, #CACHE_DLINESIZE - 1
3161: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
317 add r0, r0, #CACHE_DLINESIZE
318 cmp r0, r1
319 blo 1b
320 mcr p15, 0, r0, c7, c10, 4 @ drain WB
321 ret lr
322
323 .align 5
324feroceon_range_dma_clean_range:
325 mrs r2, cpsr
326 cmp r1, r0
327 subne r1, r1, #1 @ top address is inclusive
328 orr r3, r2, #PSR_I_BIT
329 msr cpsr_c, r3 @ disable interrupts
330 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
331 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
332 msr cpsr_c, r2 @ restore interrupts
333 mcr p15, 0, r0, c7, c10, 4 @ drain WB
334 ret lr
335
336/*
337 * dma_flush_range(start, end)
338 *
339 * Clean and invalidate the specified virtual address range.
340 *
341 * - start - virtual start address
342 * - end - virtual end address
343 */
344 .align 5
345ENTRY(feroceon_dma_flush_range)
346 bic r0, r0, #CACHE_DLINESIZE - 1
3471: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
348 add r0, r0, #CACHE_DLINESIZE
349 cmp r0, r1
350 blo 1b
351 mcr p15, 0, r0, c7, c10, 4 @ drain WB
352 ret lr
353
354 .align 5
355ENTRY(feroceon_range_dma_flush_range)
356 mrs r2, cpsr
357 cmp r1, r0
358 subne r1, r1, #1 @ top address is inclusive
359 orr r3, r2, #PSR_I_BIT
360 msr cpsr_c, r3 @ disable interrupts
361 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
362 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
363 msr cpsr_c, r2 @ restore interrupts
364 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 ret lr
366
367/*
368 * dma_map_area(start, size, dir)
369 * - start - kernel virtual start address
370 * - size - size of region
371 * - dir - DMA direction
372 */
373ENTRY(feroceon_dma_map_area)
374 add r1, r1, r0
375 cmp r2, #DMA_TO_DEVICE
376 beq feroceon_dma_clean_range
377 bcs feroceon_dma_inv_range
378 b feroceon_dma_flush_range
379ENDPROC(feroceon_dma_map_area)
380
381/*
382 * dma_map_area(start, size, dir)
383 * - start - kernel virtual start address
384 * - size - size of region
385 * - dir - DMA direction
386 */
387ENTRY(feroceon_range_dma_map_area)
388 add r1, r1, r0
389 cmp r2, #DMA_TO_DEVICE
390 beq feroceon_range_dma_clean_range
391 bcs feroceon_range_dma_inv_range
392 b feroceon_range_dma_flush_range
393ENDPROC(feroceon_range_dma_map_area)
394
395/*
396 * dma_unmap_area(start, size, dir)
397 * - start - kernel virtual start address
398 * - size - size of region
399 * - dir - DMA direction
400 */
401ENTRY(feroceon_dma_unmap_area)
402 ret lr
403ENDPROC(feroceon_dma_unmap_area)
404
405 .globl feroceon_flush_kern_cache_louis
406 .equ feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all
407
408 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
409 define_cache_functions feroceon
410
411.macro range_alias basename
412 .globl feroceon_range_\basename
413 .type feroceon_range_\basename , %function
414 .equ feroceon_range_\basename , feroceon_\basename
415.endm
416
417/*
418 * Most of the cache functions are unchanged for this case.
419 * Export suitable alias symbols for the unchanged functions:
420 */
421 range_alias flush_icache_all
422 range_alias flush_user_cache_all
423 range_alias flush_kern_cache_all
424 range_alias flush_kern_cache_louis
425 range_alias flush_user_cache_range
426 range_alias coherent_kern_range
427 range_alias coherent_user_range
428 range_alias dma_unmap_area
429
430 define_cache_functions feroceon_range
431
432 .align 5
433ENTRY(cpu_feroceon_dcache_clean_area)
434#if defined(CONFIG_CACHE_FEROCEON_L2) && \
435 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
436 mov r2, r0
437 mov r3, r1
438#endif
4391: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
440 add r0, r0, #CACHE_DLINESIZE
441 subs r1, r1, #CACHE_DLINESIZE
442 bhi 1b
443#if defined(CONFIG_CACHE_FEROCEON_L2) && \
444 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
4451: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
446 add r2, r2, #CACHE_DLINESIZE
447 subs r3, r3, #CACHE_DLINESIZE
448 bhi 1b
449#endif
450 mcr p15, 0, r0, c7, c10, 4 @ drain WB
451 ret lr
452
453/* =============================== PageTable ============================== */
454
455/*
456 * cpu_feroceon_switch_mm(pgd)
457 *
458 * Set the translation base pointer to be as described by pgd.
459 *
460 * pgd: new page tables
461 */
462 .align 5
463ENTRY(cpu_feroceon_switch_mm)
464#ifdef CONFIG_MMU
465 /*
466 * Note: we wish to call __flush_whole_cache but we need to preserve
467 * lr to do so. The only way without touching main memory is to
468 * use r2 which is normally used to test the VM_EXEC flag, and
469 * compensate locally for the skipped ops if it is not set.
470 */
471 mov r2, lr @ abuse r2 to preserve lr
472 bl __flush_whole_cache
473 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
474 tst r2, #VM_EXEC
475 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
476 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
477
478 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
479 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
480 ret r2
481#else
482 ret lr
483#endif
484
485/*
486 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
487 *
488 * Set a PTE and flush it out
489 */
490 .align 5
491ENTRY(cpu_feroceon_set_pte_ext)
492#ifdef CONFIG_MMU
493 armv3_set_pte_ext wc_disable=0
494 mov r0, r0
495 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
496#if defined(CONFIG_CACHE_FEROCEON_L2) && \
497 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
498 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
499#endif
500 mcr p15, 0, r0, c7, c10, 4 @ drain WB
501#endif
502 ret lr
503
504/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
505.globl cpu_feroceon_suspend_size
506.equ cpu_feroceon_suspend_size, 4 * 3
507#ifdef CONFIG_ARM_CPU_SUSPEND
508ENTRY(cpu_feroceon_do_suspend)
509 stmfd sp!, {r4 - r6, lr}
510 mrc p15, 0, r4, c13, c0, 0 @ PID
511 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
512 mrc p15, 0, r6, c1, c0, 0 @ Control register
513 stmia r0, {r4 - r6}
514 ldmfd sp!, {r4 - r6, pc}
515ENDPROC(cpu_feroceon_do_suspend)
516
517ENTRY(cpu_feroceon_do_resume)
518 mov ip, #0
519 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
520 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
521 ldmia r0, {r4 - r6}
522 mcr p15, 0, r4, c13, c0, 0 @ PID
523 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
524 mcr p15, 0, r1, c2, c0, 0 @ TTB address
525 mov r0, r6 @ control register
526 b cpu_resume_mmu
527ENDPROC(cpu_feroceon_do_resume)
528#endif
529
530 .type __feroceon_setup, #function
531__feroceon_setup:
532 mov r0, #0
533 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
534 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
535#ifdef CONFIG_MMU
536 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
537#endif
538
539 adr r5, feroceon_crval
540 ldmia r5, {r5, r6}
541 mrc p15, 0, r0, c1, c0 @ get control register v4
542 bic r0, r0, r5
543 orr r0, r0, r6
544 ret lr
545 .size __feroceon_setup, . - __feroceon_setup
546
547 /*
548 * B
549 * R P
550 * .RVI UFRS BLDP WCAM
551 * .011 .001 ..11 0101
552 *
553 */
554 .type feroceon_crval, #object
555feroceon_crval:
556 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
557
558 __INITDATA
559
560 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
561 define_processor_functions feroceon, dabort=v5t_early_abort, pabort=legacy_pabort
562
563 .section ".rodata"
564
565 string cpu_arch_name, "armv5te"
566 string cpu_elf_name, "v5"
567 string cpu_feroceon_name, "Feroceon"
568 string cpu_88fr531_name, "Feroceon 88FR531-vd"
569 string cpu_88fr571_name, "Feroceon 88FR571-vd"
570 string cpu_88fr131_name, "Feroceon 88FR131"
571
572 .align
573
574 .section ".proc.info.init", #alloc
575
576.macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
577 .type __\name\()_proc_info,#object
578__\name\()_proc_info:
579 .long \cpu_val
580 .long \cpu_mask
581 .long PMD_TYPE_SECT | \
582 PMD_SECT_BUFFERABLE | \
583 PMD_SECT_CACHEABLE | \
584 PMD_BIT4 | \
585 PMD_SECT_AP_WRITE | \
586 PMD_SECT_AP_READ
587 .long PMD_TYPE_SECT | \
588 PMD_BIT4 | \
589 PMD_SECT_AP_WRITE | \
590 PMD_SECT_AP_READ
591 initfn __feroceon_setup, __\name\()_proc_info
592 .long cpu_arch_name
593 .long cpu_elf_name
594 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
595 .long \cpu_name
596 .long feroceon_processor_functions
597 .long v4wbi_tlb_fns
598 .long feroceon_user_fns
599 .long \cache
600 .size __\name\()_proc_info, . - __\name\()_proc_info
601.endm
602
603#ifdef CONFIG_CPU_FEROCEON_OLD_ID
604 feroceon_proc_info feroceon_old_id, 0x41009260, 0xff00fff0, \
605 cpu_name=cpu_feroceon_name, cache=feroceon_cache_fns
606#endif
607
608 feroceon_proc_info 88fr531, 0x56055310, 0xfffffff0, cpu_88fr531_name, \
609 cache=feroceon_cache_fns
610 feroceon_proc_info 88fr571, 0x56155710, 0xfffffff0, cpu_88fr571_name, \
611 cache=feroceon_range_cache_fns
612 feroceon_proc_info 88fr131, 0x56251310, 0xfffffff0, cpu_88fr131_name, \
613 cache=feroceon_range_cache_fns
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 *
5 * Heavily based on proc-arm926.S
6 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 */
8
9#include <linux/linkage.h>
10#include <linux/init.h>
11#include <linux/cfi_types.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/hwcap.h>
15#include <asm/pgtable-hwdef.h>
16#include <asm/page.h>
17#include <asm/ptrace.h>
18#include "proc-macros.S"
19
20/*
21 * This is the maximum size of an area which will be invalidated
22 * using the single invalidate entry instructions. Anything larger
23 * than this, and we go for the whole cache.
24 *
25 * This value should be chosen such that we choose the cheapest
26 * alternative.
27 */
28#define CACHE_DLIMIT 16384
29
30/*
31 * the cache line size of the I and D cache
32 */
33#define CACHE_DLINESIZE 32
34
35 .bss
36 .align 3
37__cache_params_loc:
38 .space 8
39
40 .text
41__cache_params:
42 .word __cache_params_loc
43
44/*
45 * cpu_feroceon_proc_init()
46 */
47SYM_TYPED_FUNC_START(cpu_feroceon_proc_init)
48 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
49 ldr r1, __cache_params
50 mov r2, #(16 << 5)
51 tst r0, #(1 << 16) @ get way
52 mov r0, r0, lsr #18 @ get cache size order
53 movne r3, #((4 - 1) << 30) @ 4-way
54 and r0, r0, #0xf
55 moveq r3, #0 @ 1-way
56 mov r2, r2, lsl r0 @ actual cache size
57 movne r2, r2, lsr #2 @ turned into # of sets
58 sub r2, r2, #(1 << 5)
59 stmia r1, {r2, r3}
60#ifdef CONFIG_VFP
61 mov r1, #1 @ disable quirky VFP
62 str_l r1, VFP_arch_feroceon, r2
63#endif
64 ret lr
65SYM_FUNC_END(cpu_feroceon_proc_init)
66
67/*
68 * cpu_feroceon_proc_fin()
69 */
70SYM_TYPED_FUNC_START(cpu_feroceon_proc_fin)
71#if defined(CONFIG_CACHE_FEROCEON_L2) && \
72 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
73 mov r0, #0
74 mcr p15, 1, r0, c15, c9, 0 @ clean L2
75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
76#endif
77
78 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
79 bic r0, r0, #0x1000 @ ...i............
80 bic r0, r0, #0x000e @ ............wca.
81 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 ret lr
83SYM_FUNC_END(cpu_feroceon_proc_fin)
84
85/*
86 * cpu_feroceon_reset(loc)
87 *
88 * Perform a soft reset of the system. Put the CPU into the
89 * same state as it would be if it had been reset, and branch
90 * to what would be the reset vector.
91 *
92 * loc: location to jump to for soft reset
93 */
94 .align 5
95 .pushsection .idmap.text, "ax"
96SYM_TYPED_FUNC_START(cpu_feroceon_reset)
97 mov ip, #0
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
100#ifdef CONFIG_MMU
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
102#endif
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 bic ip, ip, #0x000f @ ............wcam
105 bic ip, ip, #0x1100 @ ...i...s........
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
107 ret r0
108SYM_FUNC_END(cpu_feroceon_reset)
109 .popsection
110
111/*
112 * cpu_feroceon_do_idle()
113 *
114 * Called with IRQs disabled
115 */
116 .align 5
117SYM_TYPED_FUNC_START(cpu_feroceon_do_idle)
118 mov r0, #0
119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 ret lr
122SYM_FUNC_END(cpu_feroceon_do_idle)
123
124/*
125 * flush_icache_all()
126 *
127 * Unconditionally clean and invalidate the entire icache.
128 */
129SYM_TYPED_FUNC_START(feroceon_flush_icache_all)
130 mov r0, #0
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 ret lr
133SYM_FUNC_END(feroceon_flush_icache_all)
134
135/*
136 * flush_user_cache_all()
137 *
138 * Clean and invalidate all cache entries in a particular
139 * address space.
140 */
141 .align 5
142SYM_FUNC_ALIAS(feroceon_flush_user_cache_all, feroceon_flush_kern_cache_all)
143
144/*
145 * flush_kern_cache_all()
146 *
147 * Clean and invalidate the entire cache.
148 */
149SYM_TYPED_FUNC_START(feroceon_flush_kern_cache_all)
150 mov r2, #VM_EXEC
151
152__flush_whole_cache:
153 ldr r1, __cache_params
154 ldmia r1, {r1, r3}
1551: orr ip, r1, r3
1562: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
157 subs ip, ip, #(1 << 30) @ next way
158 bcs 2b
159 subs r1, r1, #(1 << 5) @ next set
160 bcs 1b
161
162 tst r2, #VM_EXEC
163 mov ip, #0
164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
166 ret lr
167SYM_FUNC_END(feroceon_flush_kern_cache_all)
168
169/*
170 * flush_user_cache_range(start, end, flags)
171 *
172 * Clean and invalidate a range of cache entries in the
173 * specified address range.
174 *
175 * - start - start address (inclusive)
176 * - end - end address (exclusive)
177 * - flags - vm_flags describing address space
178 */
179 .align 5
180SYM_TYPED_FUNC_START(feroceon_flush_user_cache_range)
181 sub r3, r1, r0 @ calculate total size
182 cmp r3, #CACHE_DLIMIT
183 bgt __flush_whole_cache
1841: tst r2, #VM_EXEC
185 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
187 add r0, r0, #CACHE_DLINESIZE
188 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
189 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
190 add r0, r0, #CACHE_DLINESIZE
191 cmp r0, r1
192 blo 1b
193 tst r2, #VM_EXEC
194 mov ip, #0
195 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
196 ret lr
197SYM_FUNC_END(feroceon_flush_user_cache_range)
198
199/*
200 * coherent_kern_range(start, end)
201 *
202 * Ensure coherency between the Icache and the Dcache in the
203 * region described by start, end. If you have non-snooping
204 * Harvard caches, you need to implement this function.
205 *
206 * - start - virtual start address
207 * - end - virtual end address
208 */
209 .align 5
210SYM_TYPED_FUNC_START(feroceon_coherent_kern_range)
211#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
212 b feroceon_coherent_user_range
213#endif
214SYM_FUNC_END(feroceon_coherent_kern_range)
215
216/*
217 * coherent_user_range(start, end)
218 *
219 * Ensure coherency between the Icache and the Dcache in the
220 * region described by start, end. If you have non-snooping
221 * Harvard caches, you need to implement this function.
222 *
223 * - start - virtual start address
224 * - end - virtual end address
225 */
226SYM_TYPED_FUNC_START(feroceon_coherent_user_range)
227 bic r0, r0, #CACHE_DLINESIZE - 1
2281: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
230 add r0, r0, #CACHE_DLINESIZE
231 cmp r0, r1
232 blo 1b
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
234 mov r0, #0
235 ret lr
236SYM_FUNC_END(feroceon_coherent_user_range)
237
238/*
239 * flush_kern_dcache_area(void *addr, size_t size)
240 *
241 * Ensure no D cache aliasing occurs, either with itself or
242 * the I cache
243 *
244 * - addr - kernel address
245 * - size - region size
246 */
247 .align 5
248SYM_TYPED_FUNC_START(feroceon_flush_kern_dcache_area)
249 add r1, r0, r1
2501: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
253 blo 1b
254 mov r0, #0
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 ret lr
258SYM_FUNC_END(feroceon_flush_kern_dcache_area)
259
260 .align 5
261SYM_TYPED_FUNC_START(feroceon_range_flush_kern_dcache_area)
262 mrs r2, cpsr
263 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
264 orr r3, r2, #PSR_I_BIT
265 msr cpsr_c, r3 @ disable interrupts
266 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
267 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
268 msr cpsr_c, r2 @ restore interrupts
269 mov r0, #0
270 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
271 mcr p15, 0, r0, c7, c10, 4 @ drain WB
272 ret lr
273SYM_FUNC_END(feroceon_range_flush_kern_dcache_area)
274
275/*
276 * dma_inv_range(start, end)
277 *
278 * Invalidate (discard) the specified virtual address range.
279 * May not write back any entries. If 'start' or 'end'
280 * are not cache line aligned, those lines must be written
281 * back.
282 *
283 * - start - virtual start address
284 * - end - virtual end address
285 *
286 * (same as v4wb)
287 */
288 .align 5
289feroceon_dma_inv_range:
290 tst r0, #CACHE_DLINESIZE - 1
291 bic r0, r0, #CACHE_DLINESIZE - 1
292 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
293 tst r1, #CACHE_DLINESIZE - 1
294 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2951: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
296 add r0, r0, #CACHE_DLINESIZE
297 cmp r0, r1
298 blo 1b
299 mcr p15, 0, r0, c7, c10, 4 @ drain WB
300 ret lr
301
302 .align 5
303feroceon_range_dma_inv_range:
304 mrs r2, cpsr
305 tst r0, #CACHE_DLINESIZE - 1
306 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
307 tst r1, #CACHE_DLINESIZE - 1
308 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
309 cmp r1, r0
310 subne r1, r1, #1 @ top address is inclusive
311 orr r3, r2, #PSR_I_BIT
312 msr cpsr_c, r3 @ disable interrupts
313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
315 msr cpsr_c, r2 @ restore interrupts
316 ret lr
317
318/*
319 * dma_clean_range(start, end)
320 *
321 * Clean the specified virtual address range.
322 *
323 * - start - virtual start address
324 * - end - virtual end address
325 *
326 * (same as v4wb)
327 */
328 .align 5
329feroceon_dma_clean_range:
330 bic r0, r0, #CACHE_DLINESIZE - 1
3311: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 add r0, r0, #CACHE_DLINESIZE
333 cmp r0, r1
334 blo 1b
335 mcr p15, 0, r0, c7, c10, 4 @ drain WB
336 ret lr
337
338 .align 5
339feroceon_range_dma_clean_range:
340 mrs r2, cpsr
341 cmp r1, r0
342 subne r1, r1, #1 @ top address is inclusive
343 orr r3, r2, #PSR_I_BIT
344 msr cpsr_c, r3 @ disable interrupts
345 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
346 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
347 msr cpsr_c, r2 @ restore interrupts
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
349 ret lr
350
351/*
352 * dma_flush_range(start, end)
353 *
354 * Clean and invalidate the specified virtual address range.
355 *
356 * - start - virtual start address
357 * - end - virtual end address
358 */
359 .align 5
360SYM_TYPED_FUNC_START(feroceon_dma_flush_range)
361 bic r0, r0, #CACHE_DLINESIZE - 1
3621: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
363 add r0, r0, #CACHE_DLINESIZE
364 cmp r0, r1
365 blo 1b
366 mcr p15, 0, r0, c7, c10, 4 @ drain WB
367 ret lr
368SYM_FUNC_END(feroceon_dma_flush_range)
369
370 .align 5
371SYM_TYPED_FUNC_START(feroceon_range_dma_flush_range)
372 mrs r2, cpsr
373 cmp r1, r0
374 subne r1, r1, #1 @ top address is inclusive
375 orr r3, r2, #PSR_I_BIT
376 msr cpsr_c, r3 @ disable interrupts
377 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
378 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
379 msr cpsr_c, r2 @ restore interrupts
380 mcr p15, 0, r0, c7, c10, 4 @ drain WB
381 ret lr
382SYM_FUNC_END(feroceon_range_dma_flush_range)
383
384/*
385 * dma_map_area(start, size, dir)
386 * - start - kernel virtual start address
387 * - size - size of region
388 * - dir - DMA direction
389 */
390SYM_TYPED_FUNC_START(feroceon_dma_map_area)
391 add r1, r1, r0
392 cmp r2, #DMA_TO_DEVICE
393 beq feroceon_dma_clean_range
394 bcs feroceon_dma_inv_range
395 b feroceon_dma_flush_range
396SYM_FUNC_END(feroceon_dma_map_area)
397
398/*
399 * dma_map_area(start, size, dir)
400 * - start - kernel virtual start address
401 * - size - size of region
402 * - dir - DMA direction
403 */
404SYM_TYPED_FUNC_START(feroceon_range_dma_map_area)
405 add r1, r1, r0
406 cmp r2, #DMA_TO_DEVICE
407 beq feroceon_range_dma_clean_range
408 bcs feroceon_range_dma_inv_range
409 b feroceon_range_dma_flush_range
410SYM_FUNC_END(feroceon_range_dma_map_area)
411
412/*
413 * dma_unmap_area(start, size, dir)
414 * - start - kernel virtual start address
415 * - size - size of region
416 * - dir - DMA direction
417 */
418SYM_TYPED_FUNC_START(feroceon_dma_unmap_area)
419 ret lr
420SYM_FUNC_END(feroceon_dma_unmap_area)
421
422 .align 5
423SYM_TYPED_FUNC_START(cpu_feroceon_dcache_clean_area)
424#if defined(CONFIG_CACHE_FEROCEON_L2) && \
425 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
426 mov r2, r0
427 mov r3, r1
428#endif
4291: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
430 add r0, r0, #CACHE_DLINESIZE
431 subs r1, r1, #CACHE_DLINESIZE
432 bhi 1b
433#if defined(CONFIG_CACHE_FEROCEON_L2) && \
434 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
4351: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
436 add r2, r2, #CACHE_DLINESIZE
437 subs r3, r3, #CACHE_DLINESIZE
438 bhi 1b
439#endif
440 mcr p15, 0, r0, c7, c10, 4 @ drain WB
441 ret lr
442SYM_FUNC_END(cpu_feroceon_dcache_clean_area)
443
444/* =============================== PageTable ============================== */
445
446/*
447 * cpu_feroceon_switch_mm(pgd)
448 *
449 * Set the translation base pointer to be as described by pgd.
450 *
451 * pgd: new page tables
452 */
453 .align 5
454SYM_TYPED_FUNC_START(cpu_feroceon_switch_mm)
455#ifdef CONFIG_MMU
456 /*
457 * Note: we wish to call __flush_whole_cache but we need to preserve
458 * lr to do so. The only way without touching main memory is to
459 * use r2 which is normally used to test the VM_EXEC flag, and
460 * compensate locally for the skipped ops if it is not set.
461 */
462 mov r2, lr @ abuse r2 to preserve lr
463 bl __flush_whole_cache
464 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
465 tst r2, #VM_EXEC
466 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
467 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
468
469 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
470 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
471 ret r2
472#else
473 ret lr
474#endif
475SYM_FUNC_END(cpu_feroceon_switch_mm)
476
477/*
478 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
479 *
480 * Set a PTE and flush it out
481 */
482 .align 5
483SYM_TYPED_FUNC_START(cpu_feroceon_set_pte_ext)
484#ifdef CONFIG_MMU
485 armv3_set_pte_ext wc_disable=0
486 mov r0, r0
487 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
488#if defined(CONFIG_CACHE_FEROCEON_L2) && \
489 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
490 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
491#endif
492 mcr p15, 0, r0, c7, c10, 4 @ drain WB
493#endif
494 ret lr
495SYM_FUNC_END(cpu_feroceon_set_pte_ext)
496
497/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
498.globl cpu_feroceon_suspend_size
499.equ cpu_feroceon_suspend_size, 4 * 3
500#ifdef CONFIG_ARM_CPU_SUSPEND
501SYM_TYPED_FUNC_START(cpu_feroceon_do_suspend)
502 stmfd sp!, {r4 - r6, lr}
503 mrc p15, 0, r4, c13, c0, 0 @ PID
504 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
505 mrc p15, 0, r6, c1, c0, 0 @ Control register
506 stmia r0, {r4 - r6}
507 ldmfd sp!, {r4 - r6, pc}
508SYM_FUNC_END(cpu_feroceon_do_suspend)
509
510SYM_TYPED_FUNC_START(cpu_feroceon_do_resume)
511 mov ip, #0
512 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
513 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
514 ldmia r0, {r4 - r6}
515 mcr p15, 0, r4, c13, c0, 0 @ PID
516 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
517 mcr p15, 0, r1, c2, c0, 0 @ TTB address
518 mov r0, r6 @ control register
519 b cpu_resume_mmu
520SYM_FUNC_END(cpu_feroceon_do_resume)
521#endif
522
523 .type __feroceon_setup, #function
524__feroceon_setup:
525 mov r0, #0
526 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
527 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
528#ifdef CONFIG_MMU
529 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
530#endif
531
532 adr r5, feroceon_crval
533 ldmia r5, {r5, r6}
534 mrc p15, 0, r0, c1, c0 @ get control register v4
535 bic r0, r0, r5
536 orr r0, r0, r6
537 ret lr
538 .size __feroceon_setup, . - __feroceon_setup
539
540 /*
541 * B
542 * R P
543 * .RVI UFRS BLDP WCAM
544 * .011 .001 ..11 0101
545 *
546 */
547 .type feroceon_crval, #object
548feroceon_crval:
549 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
550
551 __INITDATA
552
553 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
554 define_processor_functions feroceon, dabort=v5t_early_abort, pabort=legacy_pabort
555
556 .section ".rodata"
557
558 string cpu_arch_name, "armv5te"
559 string cpu_elf_name, "v5"
560 string cpu_feroceon_name, "Feroceon"
561 string cpu_88fr531_name, "Feroceon 88FR531-vd"
562 string cpu_88fr571_name, "Feroceon 88FR571-vd"
563 string cpu_88fr131_name, "Feroceon 88FR131"
564
565 .align
566
567 .section ".proc.info.init", "a"
568
569.macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
570 .type __\name\()_proc_info,#object
571__\name\()_proc_info:
572 .long \cpu_val
573 .long \cpu_mask
574 .long PMD_TYPE_SECT | \
575 PMD_SECT_BUFFERABLE | \
576 PMD_SECT_CACHEABLE | \
577 PMD_BIT4 | \
578 PMD_SECT_AP_WRITE | \
579 PMD_SECT_AP_READ
580 .long PMD_TYPE_SECT | \
581 PMD_BIT4 | \
582 PMD_SECT_AP_WRITE | \
583 PMD_SECT_AP_READ
584 initfn __feroceon_setup, __\name\()_proc_info
585 .long cpu_arch_name
586 .long cpu_elf_name
587 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
588 .long \cpu_name
589 .long feroceon_processor_functions
590 .long v4wbi_tlb_fns
591 .long feroceon_user_fns
592 .long \cache
593 .size __\name\()_proc_info, . - __\name\()_proc_info
594.endm
595
596#ifdef CONFIG_CPU_FEROCEON_OLD_ID
597 feroceon_proc_info feroceon_old_id, 0x41009260, 0xff00fff0, \
598 cpu_name=cpu_feroceon_name, cache=feroceon_cache_fns
599#endif
600
601 feroceon_proc_info 88fr531, 0x56055310, 0xfffffff0, cpu_88fr531_name, \
602 cache=feroceon_cache_fns
603 feroceon_proc_info 88fr571, 0x56155710, 0xfffffff0, cpu_88fr571_name, \
604 cache=feroceon_range_cache_fns
605 feroceon_proc_info 88fr131, 0x56251310, 0xfffffff0, cpu_88fr131_name, \
606 cache=feroceon_range_cache_fns