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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/cache-v7m.S
4 *
5 * Based on linux/arch/arm/mm/cache-v7.S
6 *
7 * Copyright (C) 2001 Deep Blue Solutions Ltd.
8 * Copyright (C) 2005 ARM Ltd.
9 *
10 * This is the "shell" of the ARMv7M processor support.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <asm/assembler.h>
15#include <asm/errno.h>
16#include <asm/unwind.h>
17#include <asm/v7m.h>
18
19#include "proc-macros.S"
20
21/* Generic V7M read/write macros for memory mapped cache operations */
22.macro v7m_cache_read, rt, reg
23 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
24 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
25 ldr \rt, [\rt]
26.endm
27
28.macro v7m_cacheop, rt, tmp, op, c = al
29 movw\c \tmp, #:lower16:BASEADDR_V7M_SCB + \op
30 movt\c \tmp, #:upper16:BASEADDR_V7M_SCB + \op
31 str\c \rt, [\tmp]
32.endm
33
34
35.macro read_ccsidr, rt
36 v7m_cache_read \rt, V7M_SCB_CCSIDR
37.endm
38
39.macro read_clidr, rt
40 v7m_cache_read \rt, V7M_SCB_CLIDR
41.endm
42
43.macro write_csselr, rt, tmp
44 v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
45.endm
46
47/*
48 * dcisw: Invalidate data cache by set/way
49 */
50.macro dcisw, rt, tmp
51 v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
52.endm
53
54/*
55 * dccisw: Clean and invalidate data cache by set/way
56 */
57.macro dccisw, rt, tmp
58 v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
59.endm
60
61/*
62 * dccimvac: Clean and invalidate data cache line by MVA to PoC.
63 */
64.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
65.macro dccimvac\c, rt, tmp
66 v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
67.endm
68.endr
69
70/*
71 * dcimvac: Invalidate data cache line by MVA to PoC
72 */
73.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
74.macro dcimvac\c, rt, tmp
75 v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
76.endm
77.endr
78
79/*
80 * dccmvau: Clean data cache line by MVA to PoU
81 */
82.macro dccmvau, rt, tmp
83 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
84.endm
85
86/*
87 * dccmvac: Clean data cache line by MVA to PoC
88 */
89.macro dccmvac, rt, tmp
90 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
91.endm
92
93/*
94 * icimvau: Invalidate instruction caches by MVA to PoU
95 */
96.macro icimvau, rt, tmp
97 v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
98.endm
99
100/*
101 * Invalidate the icache, inner shareable if SMP, invalidate BTB for UP.
102 * rt data ignored by ICIALLU(IS), so can be used for the address
103 */
104.macro invalidate_icache, rt
105 v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
106 mov \rt, #0
107.endm
108
109/*
110 * Invalidate the BTB, inner shareable if SMP.
111 * rt data ignored by BPIALL, so it can be used for the address
112 */
113.macro invalidate_bp, rt
114 v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
115 mov \rt, #0
116.endm
117
118ENTRY(v7m_invalidate_l1)
119 mov r0, #0
120
121 write_csselr r0, r1
122 read_ccsidr r0
123
124 movw r1, #0x7fff
125 and r2, r1, r0, lsr #13
126
127 movw r1, #0x3ff
128
129 and r3, r1, r0, lsr #3 @ NumWays - 1
130 add r2, r2, #1 @ NumSets
131
132 and r0, r0, #0x7
133 add r0, r0, #4 @ SetShift
134
135 clz r1, r3 @ WayShift
136 add r4, r3, #1 @ NumWays
1371: sub r2, r2, #1 @ NumSets--
138 mov r3, r4 @ Temp = NumWays
1392: subs r3, r3, #1 @ Temp--
140 mov r5, r3, lsl r1
141 mov r6, r2, lsl r0
142 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
143 dcisw r5, r6
144 bgt 2b
145 cmp r2, #0
146 bgt 1b
147 dsb st
148 isb
149 ret lr
150ENDPROC(v7m_invalidate_l1)
151
152/*
153 * v7m_flush_icache_all()
154 *
155 * Flush the whole I-cache.
156 *
157 * Registers:
158 * r0 - set to 0
159 */
160ENTRY(v7m_flush_icache_all)
161 invalidate_icache r0
162 ret lr
163ENDPROC(v7m_flush_icache_all)
164
165/*
166 * v7m_flush_dcache_all()
167 *
168 * Flush the whole D-cache.
169 *
170 * Corrupted registers: r0-r7, r9-r11
171 */
172ENTRY(v7m_flush_dcache_all)
173 dmb @ ensure ordering with previous memory accesses
174 read_clidr r0
175 mov r3, r0, lsr #23 @ move LoC into position
176 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
177 beq finished @ if loc is 0, then no need to clean
178start_flush_levels:
179 mov r10, #0 @ start clean at cache level 0
180flush_levels:
181 add r2, r10, r10, lsr #1 @ work out 3x current cache level
182 mov r1, r0, lsr r2 @ extract cache type bits from clidr
183 and r1, r1, #7 @ mask of the bits for current cache only
184 cmp r1, #2 @ see what cache we have at this level
185 blt skip @ skip if no cache, or just i-cache
186#ifdef CONFIG_PREEMPT
187 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
188#endif
189 write_csselr r10, r1 @ set current cache level
190 isb @ isb to sych the new cssr&csidr
191 read_ccsidr r1 @ read the new csidr
192#ifdef CONFIG_PREEMPT
193 restore_irqs_notrace r9
194#endif
195 and r2, r1, #7 @ extract the length of the cache lines
196 add r2, r2, #4 @ add 4 (line length offset)
197 movw r4, #0x3ff
198 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
199 clz r5, r4 @ find bit position of way size increment
200 movw r7, #0x7fff
201 ands r7, r7, r1, lsr #13 @ extract max number of the index size
202loop1:
203 mov r9, r7 @ create working copy of max index
204loop2:
205 lsl r6, r4, r5
206 orr r11, r10, r6 @ factor way and cache number into r11
207 lsl r6, r9, r2
208 orr r11, r11, r6 @ factor index number into r11
209 dccisw r11, r6 @ clean/invalidate by set/way
210 subs r9, r9, #1 @ decrement the index
211 bge loop2
212 subs r4, r4, #1 @ decrement the way
213 bge loop1
214skip:
215 add r10, r10, #2 @ increment cache number
216 cmp r3, r10
217 bgt flush_levels
218finished:
219 mov r10, #0 @ switch back to cache level 0
220 write_csselr r10, r3 @ select current cache level in cssr
221 dsb st
222 isb
223 ret lr
224ENDPROC(v7m_flush_dcache_all)
225
226/*
227 * v7m_flush_cache_all()
228 *
229 * Flush the entire cache system.
230 * The data cache flush is now achieved using atomic clean / invalidates
231 * working outwards from L1 cache. This is done using Set/Way based cache
232 * maintenance instructions.
233 * The instruction cache can still be invalidated back to the point of
234 * unification in a single instruction.
235 *
236 */
237ENTRY(v7m_flush_kern_cache_all)
238 stmfd sp!, {r4-r7, r9-r11, lr}
239 bl v7m_flush_dcache_all
240 invalidate_icache r0
241 ldmfd sp!, {r4-r7, r9-r11, lr}
242 ret lr
243ENDPROC(v7m_flush_kern_cache_all)
244
245/*
246 * v7m_flush_cache_all()
247 *
248 * Flush all TLB entries in a particular address space
249 *
250 * - mm - mm_struct describing address space
251 */
252ENTRY(v7m_flush_user_cache_all)
253 /*FALLTHROUGH*/
254
255/*
256 * v7m_flush_cache_range(start, end, flags)
257 *
258 * Flush a range of TLB entries in the specified address space.
259 *
260 * - start - start address (may not be aligned)
261 * - end - end address (exclusive, may not be aligned)
262 * - flags - vm_area_struct flags describing address space
263 *
264 * It is assumed that:
265 * - we have a VIPT cache.
266 */
267ENTRY(v7m_flush_user_cache_range)
268 ret lr
269ENDPROC(v7m_flush_user_cache_all)
270ENDPROC(v7m_flush_user_cache_range)
271
272/*
273 * v7m_coherent_kern_range(start,end)
274 *
275 * Ensure that the I and D caches are coherent within specified
276 * region. This is typically used when code has been written to
277 * a memory region, and will be executed.
278 *
279 * - start - virtual start address of region
280 * - end - virtual end address of region
281 *
282 * It is assumed that:
283 * - the Icache does not read data from the write buffer
284 */
285ENTRY(v7m_coherent_kern_range)
286 /* FALLTHROUGH */
287
288/*
289 * v7m_coherent_user_range(start,end)
290 *
291 * Ensure that the I and D caches are coherent within specified
292 * region. This is typically used when code has been written to
293 * a memory region, and will be executed.
294 *
295 * - start - virtual start address of region
296 * - end - virtual end address of region
297 *
298 * It is assumed that:
299 * - the Icache does not read data from the write buffer
300 */
301ENTRY(v7m_coherent_user_range)
302 UNWIND(.fnstart )
303 dcache_line_size r2, r3
304 sub r3, r2, #1
305 bic r12, r0, r3
3061:
307/*
308 * We use open coded version of dccmvau otherwise USER() would
309 * point at movw instruction.
310 */
311 dccmvau r12, r3
312 add r12, r12, r2
313 cmp r12, r1
314 blo 1b
315 dsb ishst
316 icache_line_size r2, r3
317 sub r3, r2, #1
318 bic r12, r0, r3
3192:
320 icimvau r12, r3
321 add r12, r12, r2
322 cmp r12, r1
323 blo 2b
324 invalidate_bp r0
325 dsb ishst
326 isb
327 ret lr
328 UNWIND(.fnend )
329ENDPROC(v7m_coherent_kern_range)
330ENDPROC(v7m_coherent_user_range)
331
332/*
333 * v7m_flush_kern_dcache_area(void *addr, size_t size)
334 *
335 * Ensure that the data held in the page kaddr is written back
336 * to the page in question.
337 *
338 * - addr - kernel address
339 * - size - region size
340 */
341ENTRY(v7m_flush_kern_dcache_area)
342 dcache_line_size r2, r3
343 add r1, r0, r1
344 sub r3, r2, #1
345 bic r0, r0, r3
3461:
347 dccimvac r0, r3 @ clean & invalidate D line / unified line
348 add r0, r0, r2
349 cmp r0, r1
350 blo 1b
351 dsb st
352 ret lr
353ENDPROC(v7m_flush_kern_dcache_area)
354
355/*
356 * v7m_dma_inv_range(start,end)
357 *
358 * Invalidate the data cache within the specified region; we will
359 * be performing a DMA operation in this region and we want to
360 * purge old data in the cache.
361 *
362 * - start - virtual start address of region
363 * - end - virtual end address of region
364 */
365v7m_dma_inv_range:
366 dcache_line_size r2, r3
367 sub r3, r2, #1
368 tst r0, r3
369 bic r0, r0, r3
370 dccimvacne r0, r3
371 addne r0, r0, r2
372 subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac
373 tst r1, r3
374 bic r1, r1, r3
375 dccimvacne r1, r3
376 cmp r0, r1
3771:
378 dcimvaclo r0, r3
379 addlo r0, r0, r2
380 cmplo r0, r1
381 blo 1b
382 dsb st
383 ret lr
384ENDPROC(v7m_dma_inv_range)
385
386/*
387 * v7m_dma_clean_range(start,end)
388 * - start - virtual start address of region
389 * - end - virtual end address of region
390 */
391v7m_dma_clean_range:
392 dcache_line_size r2, r3
393 sub r3, r2, #1
394 bic r0, r0, r3
3951:
396 dccmvac r0, r3 @ clean D / U line
397 add r0, r0, r2
398 cmp r0, r1
399 blo 1b
400 dsb st
401 ret lr
402ENDPROC(v7m_dma_clean_range)
403
404/*
405 * v7m_dma_flush_range(start,end)
406 * - start - virtual start address of region
407 * - end - virtual end address of region
408 */
409ENTRY(v7m_dma_flush_range)
410 dcache_line_size r2, r3
411 sub r3, r2, #1
412 bic r0, r0, r3
4131:
414 dccimvac r0, r3 @ clean & invalidate D / U line
415 add r0, r0, r2
416 cmp r0, r1
417 blo 1b
418 dsb st
419 ret lr
420ENDPROC(v7m_dma_flush_range)
421
422/*
423 * dma_map_area(start, size, dir)
424 * - start - kernel virtual start address
425 * - size - size of region
426 * - dir - DMA direction
427 */
428ENTRY(v7m_dma_map_area)
429 add r1, r1, r0
430 teq r2, #DMA_FROM_DEVICE
431 beq v7m_dma_inv_range
432 b v7m_dma_clean_range
433ENDPROC(v7m_dma_map_area)
434
435/*
436 * dma_unmap_area(start, size, dir)
437 * - start - kernel virtual start address
438 * - size - size of region
439 * - dir - DMA direction
440 */
441ENTRY(v7m_dma_unmap_area)
442 add r1, r1, r0
443 teq r2, #DMA_TO_DEVICE
444 bne v7m_dma_inv_range
445 ret lr
446ENDPROC(v7m_dma_unmap_area)
447
448 .globl v7m_flush_kern_cache_louis
449 .equ v7m_flush_kern_cache_louis, v7m_flush_kern_cache_all
450
451 __INITDATA
452
453 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
454 define_cache_functions v7m
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/cache-v7m.S
4 *
5 * Based on linux/arch/arm/mm/cache-v7.S
6 *
7 * Copyright (C) 2001 Deep Blue Solutions Ltd.
8 * Copyright (C) 2005 ARM Ltd.
9 *
10 * This is the "shell" of the ARMv7M processor support.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/cfi_types.h>
15#include <asm/assembler.h>
16#include <asm/errno.h>
17#include <asm/unwind.h>
18#include <asm/v7m.h>
19
20#include "proc-macros.S"
21
22.arch armv7-m
23
24/* Generic V7M read/write macros for memory mapped cache operations */
25.macro v7m_cache_read, rt, reg
26 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
27 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
28 ldr \rt, [\rt]
29.endm
30
31.macro v7m_cacheop, rt, tmp, op, c = al
32 movw\c \tmp, #:lower16:BASEADDR_V7M_SCB + \op
33 movt\c \tmp, #:upper16:BASEADDR_V7M_SCB + \op
34 str\c \rt, [\tmp]
35.endm
36
37
38.macro read_ccsidr, rt
39 v7m_cache_read \rt, V7M_SCB_CCSIDR
40.endm
41
42.macro read_clidr, rt
43 v7m_cache_read \rt, V7M_SCB_CLIDR
44.endm
45
46.macro write_csselr, rt, tmp
47 v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
48.endm
49
50/*
51 * dcisw: Invalidate data cache by set/way
52 */
53.macro dcisw, rt, tmp
54 v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
55.endm
56
57/*
58 * dccisw: Clean and invalidate data cache by set/way
59 */
60.macro dccisw, rt, tmp
61 v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
62.endm
63
64/*
65 * dccimvac: Clean and invalidate data cache line by MVA to PoC.
66 */
67.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
68.macro dccimvac\c, rt, tmp
69 v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
70.endm
71.endr
72
73/*
74 * dcimvac: Invalidate data cache line by MVA to PoC
75 */
76.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
77.macro dcimvac\c, rt, tmp
78 v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
79.endm
80.endr
81
82/*
83 * dccmvau: Clean data cache line by MVA to PoU
84 */
85.macro dccmvau, rt, tmp
86 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
87.endm
88
89/*
90 * dccmvac: Clean data cache line by MVA to PoC
91 */
92.macro dccmvac, rt, tmp
93 v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
94.endm
95
96/*
97 * icimvau: Invalidate instruction caches by MVA to PoU
98 */
99.macro icimvau, rt, tmp
100 v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
101.endm
102
103/*
104 * Invalidate the icache, inner shareable if SMP, invalidate BTB for UP.
105 * rt data ignored by ICIALLU(IS), so can be used for the address
106 */
107.macro invalidate_icache, rt
108 v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
109 mov \rt, #0
110.endm
111
112/*
113 * Invalidate the BTB, inner shareable if SMP.
114 * rt data ignored by BPIALL, so it can be used for the address
115 */
116.macro invalidate_bp, rt
117 v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
118 mov \rt, #0
119.endm
120
121ENTRY(v7m_invalidate_l1)
122 mov r0, #0
123
124 write_csselr r0, r1
125 read_ccsidr r0
126
127 movw r1, #0x7fff
128 and r2, r1, r0, lsr #13
129
130 movw r1, #0x3ff
131
132 and r3, r1, r0, lsr #3 @ NumWays - 1
133 add r2, r2, #1 @ NumSets
134
135 and r0, r0, #0x7
136 add r0, r0, #4 @ SetShift
137
138 clz r1, r3 @ WayShift
139 add r4, r3, #1 @ NumWays
1401: sub r2, r2, #1 @ NumSets--
141 mov r3, r4 @ Temp = NumWays
1422: subs r3, r3, #1 @ Temp--
143 mov r5, r3, lsl r1
144 mov r6, r2, lsl r0
145 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
146 dcisw r5, r6
147 bgt 2b
148 cmp r2, #0
149 bgt 1b
150 dsb st
151 isb
152 ret lr
153ENDPROC(v7m_invalidate_l1)
154
155/*
156 * v7m_flush_icache_all()
157 *
158 * Flush the whole I-cache.
159 *
160 * Registers:
161 * r0 - set to 0
162 */
163SYM_TYPED_FUNC_START(v7m_flush_icache_all)
164 invalidate_icache r0
165 ret lr
166SYM_FUNC_END(v7m_flush_icache_all)
167
168/*
169 * v7m_flush_dcache_all()
170 *
171 * Flush the whole D-cache.
172 *
173 * Corrupted registers: r0-r7, r9-r11
174 */
175ENTRY(v7m_flush_dcache_all)
176 dmb @ ensure ordering with previous memory accesses
177 read_clidr r0
178 mov r3, r0, lsr #23 @ move LoC into position
179 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
180 beq finished @ if loc is 0, then no need to clean
181start_flush_levels:
182 mov r10, #0 @ start clean at cache level 0
183flush_levels:
184 add r2, r10, r10, lsr #1 @ work out 3x current cache level
185 mov r1, r0, lsr r2 @ extract cache type bits from clidr
186 and r1, r1, #7 @ mask of the bits for current cache only
187 cmp r1, #2 @ see what cache we have at this level
188 blt skip @ skip if no cache, or just i-cache
189#ifdef CONFIG_PREEMPTION
190 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
191#endif
192 write_csselr r10, r1 @ set current cache level
193 isb @ isb to sych the new cssr&csidr
194 read_ccsidr r1 @ read the new csidr
195#ifdef CONFIG_PREEMPTION
196 restore_irqs_notrace r9
197#endif
198 and r2, r1, #7 @ extract the length of the cache lines
199 add r2, r2, #4 @ add 4 (line length offset)
200 movw r4, #0x3ff
201 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
202 clz r5, r4 @ find bit position of way size increment
203 movw r7, #0x7fff
204 ands r7, r7, r1, lsr #13 @ extract max number of the index size
205loop1:
206 mov r9, r7 @ create working copy of max index
207loop2:
208 lsl r6, r4, r5
209 orr r11, r10, r6 @ factor way and cache number into r11
210 lsl r6, r9, r2
211 orr r11, r11, r6 @ factor index number into r11
212 dccisw r11, r6 @ clean/invalidate by set/way
213 subs r9, r9, #1 @ decrement the index
214 bge loop2
215 subs r4, r4, #1 @ decrement the way
216 bge loop1
217skip:
218 add r10, r10, #2 @ increment cache number
219 cmp r3, r10
220 bgt flush_levels
221finished:
222 mov r10, #0 @ switch back to cache level 0
223 write_csselr r10, r3 @ select current cache level in cssr
224 dsb st
225 isb
226 ret lr
227ENDPROC(v7m_flush_dcache_all)
228
229/*
230 * v7m_flush_cache_all()
231 *
232 * Flush the entire cache system.
233 * The data cache flush is now achieved using atomic clean / invalidates
234 * working outwards from L1 cache. This is done using Set/Way based cache
235 * maintenance instructions.
236 * The instruction cache can still be invalidated back to the point of
237 * unification in a single instruction.
238 *
239 */
240SYM_TYPED_FUNC_START(v7m_flush_kern_cache_all)
241 stmfd sp!, {r4-r7, r9-r11, lr}
242 bl v7m_flush_dcache_all
243 invalidate_icache r0
244 ldmfd sp!, {r4-r7, r9-r11, lr}
245 ret lr
246SYM_FUNC_END(v7m_flush_kern_cache_all)
247
248/*
249 * v7m_flush_cache_all()
250 *
251 * Flush all TLB entries in a particular address space
252 *
253 * - mm - mm_struct describing address space
254 */
255SYM_TYPED_FUNC_START(v7m_flush_user_cache_all)
256 ret lr
257SYM_FUNC_END(v7m_flush_user_cache_all)
258
259/*
260 * v7m_flush_cache_range(start, end, flags)
261 *
262 * Flush a range of TLB entries in the specified address space.
263 *
264 * - start - start address (may not be aligned)
265 * - end - end address (exclusive, may not be aligned)
266 * - flags - vm_area_struct flags describing address space
267 *
268 * It is assumed that:
269 * - we have a VIPT cache.
270 */
271SYM_TYPED_FUNC_START(v7m_flush_user_cache_range)
272 ret lr
273SYM_FUNC_END(v7m_flush_user_cache_range)
274
275/*
276 * v7m_coherent_kern_range(start,end)
277 *
278 * Ensure that the I and D caches are coherent within specified
279 * region. This is typically used when code has been written to
280 * a memory region, and will be executed.
281 *
282 * - start - virtual start address of region
283 * - end - virtual end address of region
284 *
285 * It is assumed that:
286 * - the Icache does not read data from the write buffer
287 */
288SYM_TYPED_FUNC_START(v7m_coherent_kern_range)
289#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
290 b v7m_coherent_user_range
291#endif
292SYM_FUNC_END(v7m_coherent_kern_range)
293
294/*
295 * v7m_coherent_user_range(start,end)
296 *
297 * Ensure that the I and D caches are coherent within specified
298 * region. This is typically used when code has been written to
299 * a memory region, and will be executed.
300 *
301 * - start - virtual start address of region
302 * - end - virtual end address of region
303 *
304 * It is assumed that:
305 * - the Icache does not read data from the write buffer
306 */
307SYM_TYPED_FUNC_START(v7m_coherent_user_range)
308 UNWIND(.fnstart )
309 dcache_line_size r2, r3
310 sub r3, r2, #1
311 bic r12, r0, r3
3121:
313/*
314 * We use open coded version of dccmvau otherwise USER() would
315 * point at movw instruction.
316 */
317 dccmvau r12, r3
318 add r12, r12, r2
319 cmp r12, r1
320 blo 1b
321 dsb ishst
322 icache_line_size r2, r3
323 sub r3, r2, #1
324 bic r12, r0, r3
3252:
326 icimvau r12, r3
327 add r12, r12, r2
328 cmp r12, r1
329 blo 2b
330 invalidate_bp r0
331 dsb ishst
332 isb
333 ret lr
334 UNWIND(.fnend )
335SYM_FUNC_END(v7m_coherent_user_range)
336
337/*
338 * v7m_flush_kern_dcache_area(void *addr, size_t size)
339 *
340 * Ensure that the data held in the page kaddr is written back
341 * to the page in question.
342 *
343 * - addr - kernel address
344 * - size - region size
345 */
346SYM_TYPED_FUNC_START(v7m_flush_kern_dcache_area)
347 dcache_line_size r2, r3
348 add r1, r0, r1
349 sub r3, r2, #1
350 bic r0, r0, r3
3511:
352 dccimvac r0, r3 @ clean & invalidate D line / unified line
353 add r0, r0, r2
354 cmp r0, r1
355 blo 1b
356 dsb st
357 ret lr
358SYM_FUNC_END(v7m_flush_kern_dcache_area)
359
360/*
361 * v7m_dma_inv_range(start,end)
362 *
363 * Invalidate the data cache within the specified region; we will
364 * be performing a DMA operation in this region and we want to
365 * purge old data in the cache.
366 *
367 * - start - virtual start address of region
368 * - end - virtual end address of region
369 */
370v7m_dma_inv_range:
371 dcache_line_size r2, r3
372 sub r3, r2, #1
373 tst r0, r3
374 bic r0, r0, r3
375 dccimvacne r0, r3
376 addne r0, r0, r2
377 subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac
378 tst r1, r3
379 bic r1, r1, r3
380 dccimvacne r1, r3
381 cmp r0, r1
3821:
383 dcimvaclo r0, r3
384 addlo r0, r0, r2
385 cmplo r0, r1
386 blo 1b
387 dsb st
388 ret lr
389ENDPROC(v7m_dma_inv_range)
390
391/*
392 * v7m_dma_clean_range(start,end)
393 * - start - virtual start address of region
394 * - end - virtual end address of region
395 */
396v7m_dma_clean_range:
397 dcache_line_size r2, r3
398 sub r3, r2, #1
399 bic r0, r0, r3
4001:
401 dccmvac r0, r3 @ clean D / U line
402 add r0, r0, r2
403 cmp r0, r1
404 blo 1b
405 dsb st
406 ret lr
407ENDPROC(v7m_dma_clean_range)
408
409/*
410 * v7m_dma_flush_range(start,end)
411 * - start - virtual start address of region
412 * - end - virtual end address of region
413 */
414SYM_TYPED_FUNC_START(v7m_dma_flush_range)
415 dcache_line_size r2, r3
416 sub r3, r2, #1
417 bic r0, r0, r3
4181:
419 dccimvac r0, r3 @ clean & invalidate D / U line
420 add r0, r0, r2
421 cmp r0, r1
422 blo 1b
423 dsb st
424 ret lr
425SYM_FUNC_END(v7m_dma_flush_range)
426
427/*
428 * dma_map_area(start, size, dir)
429 * - start - kernel virtual start address
430 * - size - size of region
431 * - dir - DMA direction
432 */
433SYM_TYPED_FUNC_START(v7m_dma_map_area)
434 add r1, r1, r0
435 teq r2, #DMA_FROM_DEVICE
436 beq v7m_dma_inv_range
437 b v7m_dma_clean_range
438SYM_FUNC_END(v7m_dma_map_area)
439
440/*
441 * dma_unmap_area(start, size, dir)
442 * - start - kernel virtual start address
443 * - size - size of region
444 * - dir - DMA direction
445 */
446SYM_TYPED_FUNC_START(v7m_dma_unmap_area)
447 add r1, r1, r0
448 teq r2, #DMA_TO_DEVICE
449 bne v7m_dma_inv_range
450 ret lr
451SYM_FUNC_END(v7m_dma_unmap_area)