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1/*
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/clock/sun8i-de2.h>
46#include <dt-bindings/clock/sun8i-r40-ccu.h>
47#include <dt-bindings/reset/sun8i-r40-ccu.h>
48#include <dt-bindings/reset/sun8i-de2.h>
49
50/ {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
54
55 clocks {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60 osc24M: osc24M {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-accuracy = <50000>;
65 clock-output-names = "osc24M";
66 };
67
68 osc32k: osc32k {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 clock-accuracy = <20000>;
73 clock-output-names = "ext-osc32k";
74 };
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu@0 {
82 compatible = "arm,cortex-a7";
83 device_type = "cpu";
84 reg = <0>;
85 };
86
87 cpu@1 {
88 compatible = "arm,cortex-a7";
89 device_type = "cpu";
90 reg = <1>;
91 };
92
93 cpu@2 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <2>;
97 };
98
99 cpu@3 {
100 compatible = "arm,cortex-a7";
101 device_type = "cpu";
102 reg = <3>;
103 };
104 };
105
106 de: display-engine {
107 compatible = "allwinner,sun8i-r40-display-engine";
108 allwinner,pipelines = <&mixer0>, <&mixer1>;
109 status = "disabled";
110 };
111
112 soc {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges;
117
118 display_clocks: clock@1000000 {
119 compatible = "allwinner,sun8i-r40-de2-clk",
120 "allwinner,sun8i-h3-de2-clk";
121 reg = <0x01000000 0x100000>;
122 clocks = <&ccu CLK_BUS_DE>,
123 <&ccu CLK_DE>;
124 clock-names = "bus",
125 "mod";
126 resets = <&ccu RST_BUS_DE>;
127 #clock-cells = <1>;
128 #reset-cells = <1>;
129 };
130
131 mixer0: mixer@1100000 {
132 compatible = "allwinner,sun8i-r40-de2-mixer-0";
133 reg = <0x01100000 0x100000>;
134 clocks = <&display_clocks CLK_BUS_MIXER0>,
135 <&display_clocks CLK_MIXER0>;
136 clock-names = "bus",
137 "mod";
138 resets = <&display_clocks RST_MIXER0>;
139
140 ports {
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 mixer0_out: port@1 {
145 reg = <1>;
146 mixer0_out_tcon_top: endpoint {
147 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
148 };
149 };
150 };
151 };
152
153 mixer1: mixer@1200000 {
154 compatible = "allwinner,sun8i-r40-de2-mixer-1";
155 reg = <0x01200000 0x100000>;
156 clocks = <&display_clocks CLK_BUS_MIXER1>,
157 <&display_clocks CLK_MIXER1>;
158 clock-names = "bus",
159 "mod";
160 resets = <&display_clocks RST_WB>;
161
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 mixer1_out: port@1 {
167 reg = <1>;
168 mixer1_out_tcon_top: endpoint {
169 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
170 };
171 };
172 };
173 };
174
175 nmi_intc: interrupt-controller@1c00030 {
176 compatible = "allwinner,sun7i-a20-sc-nmi";
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 reg = <0x01c00030 0x0c>;
180 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
181 };
182
183 mmc0: mmc@1c0f000 {
184 compatible = "allwinner,sun8i-r40-mmc",
185 "allwinner,sun50i-a64-mmc";
186 reg = <0x01c0f000 0x1000>;
187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
188 clock-names = "ahb", "mmc";
189 resets = <&ccu RST_BUS_MMC0>;
190 reset-names = "ahb";
191 pinctrl-0 = <&mmc0_pins>;
192 pinctrl-names = "default";
193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
194 status = "disabled";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198
199 mmc1: mmc@1c10000 {
200 compatible = "allwinner,sun8i-r40-mmc",
201 "allwinner,sun50i-a64-mmc";
202 reg = <0x01c10000 0x1000>;
203 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
204 clock-names = "ahb", "mmc";
205 resets = <&ccu RST_BUS_MMC1>;
206 reset-names = "ahb";
207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
208 status = "disabled";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 };
212
213 mmc2: mmc@1c11000 {
214 compatible = "allwinner,sun8i-r40-emmc",
215 "allwinner,sun50i-a64-emmc";
216 reg = <0x01c11000 0x1000>;
217 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
218 clock-names = "ahb", "mmc";
219 resets = <&ccu RST_BUS_MMC2>;
220 reset-names = "ahb";
221 pinctrl-0 = <&mmc2_pins>;
222 pinctrl-names = "default";
223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
224 status = "disabled";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 };
228
229 mmc3: mmc@1c12000 {
230 compatible = "allwinner,sun8i-r40-mmc",
231 "allwinner,sun50i-a64-mmc";
232 reg = <0x01c12000 0x1000>;
233 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
234 clock-names = "ahb", "mmc";
235 resets = <&ccu RST_BUS_MMC3>;
236 reset-names = "ahb";
237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
238 status = "disabled";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 };
242
243 usbphy: phy@1c13400 {
244 compatible = "allwinner,sun8i-r40-usb-phy";
245 reg = <0x01c13400 0x14>,
246 <0x01c14800 0x4>,
247 <0x01c19800 0x4>,
248 <0x01c1c800 0x4>;
249 reg-names = "phy_ctrl",
250 "pmu0",
251 "pmu1",
252 "pmu2";
253 clocks = <&ccu CLK_USB_PHY0>,
254 <&ccu CLK_USB_PHY1>,
255 <&ccu CLK_USB_PHY2>;
256 clock-names = "usb0_phy",
257 "usb1_phy",
258 "usb2_phy";
259 resets = <&ccu RST_USB_PHY0>,
260 <&ccu RST_USB_PHY1>,
261 <&ccu RST_USB_PHY2>;
262 reset-names = "usb0_reset",
263 "usb1_reset",
264 "usb2_reset";
265 status = "disabled";
266 #phy-cells = <1>;
267 };
268
269 ehci1: usb@1c19000 {
270 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
271 reg = <0x01c19000 0x100>;
272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_EHCI1>;
274 resets = <&ccu RST_BUS_EHCI1>;
275 phys = <&usbphy 1>;
276 phy-names = "usb";
277 status = "disabled";
278 };
279
280 ohci1: usb@1c19400 {
281 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
282 reg = <0x01c19400 0x100>;
283 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&ccu CLK_BUS_OHCI1>,
285 <&ccu CLK_USB_OHCI1>;
286 resets = <&ccu RST_BUS_OHCI1>;
287 phys = <&usbphy 1>;
288 phy-names = "usb";
289 status = "disabled";
290 };
291
292 ehci2: usb@1c1c000 {
293 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
294 reg = <0x01c1c000 0x100>;
295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&ccu CLK_BUS_EHCI2>;
297 resets = <&ccu RST_BUS_EHCI2>;
298 phys = <&usbphy 2>;
299 phy-names = "usb";
300 status = "disabled";
301 };
302
303 ohci2: usb@1c1c400 {
304 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
305 reg = <0x01c1c400 0x100>;
306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&ccu CLK_BUS_OHCI2>,
308 <&ccu CLK_USB_OHCI2>;
309 resets = <&ccu RST_BUS_OHCI2>;
310 phys = <&usbphy 2>;
311 phy-names = "usb";
312 status = "disabled";
313 };
314
315 ccu: clock@1c20000 {
316 compatible = "allwinner,sun8i-r40-ccu";
317 reg = <0x01c20000 0x400>;
318 clocks = <&osc24M>, <&rtc 0>;
319 clock-names = "hosc", "losc";
320 #clock-cells = <1>;
321 #reset-cells = <1>;
322 };
323
324 rtc: rtc@1c20400 {
325 compatible = "allwinner,sun8i-r40-rtc";
326 reg = <0x01c20400 0x400>;
327 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
328 clock-output-names = "osc32k", "osc32k-out";
329 clocks = <&osc32k>;
330 #clock-cells = <1>;
331 };
332
333 pio: pinctrl@1c20800 {
334 compatible = "allwinner,sun8i-r40-pinctrl";
335 reg = <0x01c20800 0x400>;
336 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
338 clock-names = "apb", "hosc", "losc";
339 gpio-controller;
340 interrupt-controller;
341 #interrupt-cells = <3>;
342 #gpio-cells = <3>;
343
344 clk_out_a_pin: clk-out-a-pin {
345 pins = "PI12";
346 function = "clk_out_a";
347 };
348
349 gmac_rgmii_pins: gmac-rgmii-pins {
350 pins = "PA0", "PA1", "PA2", "PA3",
351 "PA4", "PA5", "PA6", "PA7",
352 "PA8", "PA10", "PA11", "PA12",
353 "PA13", "PA15", "PA16";
354 function = "gmac";
355 /*
356 * data lines in RGMII mode use DDR mode
357 * and need a higher signal drive strength
358 */
359 drive-strength = <40>;
360 };
361
362 i2c0_pins: i2c0-pins {
363 pins = "PB0", "PB1";
364 function = "i2c0";
365 };
366
367 mmc0_pins: mmc0-pins {
368 pins = "PF0", "PF1", "PF2",
369 "PF3", "PF4", "PF5";
370 function = "mmc0";
371 drive-strength = <30>;
372 bias-pull-up;
373 };
374
375 mmc1_pg_pins: mmc1-pg-pins {
376 pins = "PG0", "PG1", "PG2",
377 "PG3", "PG4", "PG5";
378 function = "mmc1";
379 drive-strength = <30>;
380 bias-pull-up;
381 };
382
383 mmc2_pins: mmc2-pins {
384 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
385 "PC10", "PC11", "PC12", "PC13", "PC14",
386 "PC15", "PC24";
387 function = "mmc2";
388 drive-strength = <30>;
389 bias-pull-up;
390 };
391
392 uart0_pb_pins: uart0-pb-pins {
393 pins = "PB22", "PB23";
394 function = "uart0";
395 };
396
397 uart3_pg_pins: uart3-pg-pins {
398 pins = "PG6", "PG7";
399 function = "uart3";
400 };
401
402 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
403 pins = "PG8", "PG9";
404 function = "uart3";
405 };
406 };
407
408 wdt: watchdog@1c20c90 {
409 compatible = "allwinner,sun4i-a10-wdt";
410 reg = <0x01c20c90 0x10>;
411 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&osc24M>;
413 };
414
415 uart0: serial@1c28000 {
416 compatible = "snps,dw-apb-uart";
417 reg = <0x01c28000 0x400>;
418 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
419 reg-shift = <2>;
420 reg-io-width = <4>;
421 clocks = <&ccu CLK_BUS_UART0>;
422 resets = <&ccu RST_BUS_UART0>;
423 status = "disabled";
424 };
425
426 uart1: serial@1c28400 {
427 compatible = "snps,dw-apb-uart";
428 reg = <0x01c28400 0x400>;
429 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
430 reg-shift = <2>;
431 reg-io-width = <4>;
432 clocks = <&ccu CLK_BUS_UART1>;
433 resets = <&ccu RST_BUS_UART1>;
434 status = "disabled";
435 };
436
437 uart2: serial@1c28800 {
438 compatible = "snps,dw-apb-uart";
439 reg = <0x01c28800 0x400>;
440 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
441 reg-shift = <2>;
442 reg-io-width = <4>;
443 clocks = <&ccu CLK_BUS_UART2>;
444 resets = <&ccu RST_BUS_UART2>;
445 status = "disabled";
446 };
447
448 uart3: serial@1c28c00 {
449 compatible = "snps,dw-apb-uart";
450 reg = <0x01c28c00 0x400>;
451 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 clocks = <&ccu CLK_BUS_UART3>;
455 resets = <&ccu RST_BUS_UART3>;
456 status = "disabled";
457 };
458
459 uart4: serial@1c29000 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0x01c29000 0x400>;
462 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
463 reg-shift = <2>;
464 reg-io-width = <4>;
465 clocks = <&ccu CLK_BUS_UART4>;
466 resets = <&ccu RST_BUS_UART4>;
467 status = "disabled";
468 };
469
470 uart5: serial@1c29400 {
471 compatible = "snps,dw-apb-uart";
472 reg = <0x01c29400 0x400>;
473 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
474 reg-shift = <2>;
475 reg-io-width = <4>;
476 clocks = <&ccu CLK_BUS_UART5>;
477 resets = <&ccu RST_BUS_UART5>;
478 status = "disabled";
479 };
480
481 uart6: serial@1c29800 {
482 compatible = "snps,dw-apb-uart";
483 reg = <0x01c29800 0x400>;
484 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
485 reg-shift = <2>;
486 reg-io-width = <4>;
487 clocks = <&ccu CLK_BUS_UART6>;
488 resets = <&ccu RST_BUS_UART6>;
489 status = "disabled";
490 };
491
492 uart7: serial@1c29c00 {
493 compatible = "snps,dw-apb-uart";
494 reg = <0x01c29c00 0x400>;
495 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
496 reg-shift = <2>;
497 reg-io-width = <4>;
498 clocks = <&ccu CLK_BUS_UART7>;
499 resets = <&ccu RST_BUS_UART7>;
500 status = "disabled";
501 };
502
503 i2c0: i2c@1c2ac00 {
504 compatible = "allwinner,sun6i-a31-i2c";
505 reg = <0x01c2ac00 0x400>;
506 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&ccu CLK_BUS_I2C0>;
508 resets = <&ccu RST_BUS_I2C0>;
509 pinctrl-0 = <&i2c0_pins>;
510 pinctrl-names = "default";
511 status = "disabled";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 };
515
516 i2c1: i2c@1c2b000 {
517 compatible = "allwinner,sun6i-a31-i2c";
518 reg = <0x01c2b000 0x400>;
519 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&ccu CLK_BUS_I2C1>;
521 resets = <&ccu RST_BUS_I2C1>;
522 status = "disabled";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 };
526
527 i2c2: i2c@1c2b400 {
528 compatible = "allwinner,sun6i-a31-i2c";
529 reg = <0x01c2b400 0x400>;
530 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&ccu CLK_BUS_I2C2>;
532 resets = <&ccu RST_BUS_I2C2>;
533 status = "disabled";
534 #address-cells = <1>;
535 #size-cells = <0>;
536 };
537
538 i2c3: i2c@1c2b800 {
539 compatible = "allwinner,sun6i-a31-i2c";
540 reg = <0x01c2b800 0x400>;
541 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&ccu CLK_BUS_I2C3>;
543 resets = <&ccu RST_BUS_I2C3>;
544 status = "disabled";
545 #address-cells = <1>;
546 #size-cells = <0>;
547 };
548
549 i2c4: i2c@1c2c000 {
550 compatible = "allwinner,sun6i-a31-i2c";
551 reg = <0x01c2c000 0x400>;
552 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_BUS_I2C4>;
554 resets = <&ccu RST_BUS_I2C4>;
555 status = "disabled";
556 #address-cells = <1>;
557 #size-cells = <0>;
558 };
559
560 ahci: sata@1c18000 {
561 compatible = "allwinner,sun8i-r40-ahci";
562 reg = <0x01c18000 0x1000>;
563 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
565 resets = <&ccu RST_BUS_SATA>;
566 reset-names = "ahci";
567 status = "disabled";
568
569 };
570
571 gmac: ethernet@1c50000 {
572 compatible = "allwinner,sun8i-r40-gmac";
573 syscon = <&ccu>;
574 reg = <0x01c50000 0x10000>;
575 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-names = "macirq";
577 resets = <&ccu RST_BUS_GMAC>;
578 reset-names = "stmmaceth";
579 clocks = <&ccu CLK_BUS_GMAC>;
580 clock-names = "stmmaceth";
581 status = "disabled";
582
583 gmac_mdio: mdio {
584 compatible = "snps,dwmac-mdio";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 };
588 };
589
590 tcon_top: tcon-top@1c70000 {
591 compatible = "allwinner,sun8i-r40-tcon-top";
592 reg = <0x01c70000 0x1000>;
593 clocks = <&ccu CLK_BUS_TCON_TOP>,
594 <&ccu CLK_TCON_TV0>,
595 <&ccu CLK_TVE0>,
596 <&ccu CLK_TCON_TV1>,
597 <&ccu CLK_TVE1>,
598 <&ccu CLK_DSI_DPHY>;
599 clock-names = "bus",
600 "tcon-tv0",
601 "tve0",
602 "tcon-tv1",
603 "tve1",
604 "dsi";
605 clock-output-names = "tcon-top-tv0",
606 "tcon-top-tv1",
607 "tcon-top-dsi";
608 resets = <&ccu RST_BUS_TCON_TOP>;
609 #clock-cells = <1>;
610
611 ports {
612 #address-cells = <1>;
613 #size-cells = <0>;
614
615 tcon_top_mixer0_in: port@0 {
616 reg = <0>;
617
618 tcon_top_mixer0_in_mixer0: endpoint {
619 remote-endpoint = <&mixer0_out_tcon_top>;
620 };
621 };
622
623 tcon_top_mixer0_out: port@1 {
624 #address-cells = <1>;
625 #size-cells = <0>;
626 reg = <1>;
627
628 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
629 reg = <0>;
630 };
631
632 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
633 reg = <1>;
634 };
635
636 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
637 reg = <2>;
638 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
639 };
640
641 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
642 reg = <3>;
643 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
644 };
645 };
646
647 tcon_top_mixer1_in: port@2 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <2>;
651
652 tcon_top_mixer1_in_mixer1: endpoint@1 {
653 reg = <1>;
654 remote-endpoint = <&mixer1_out_tcon_top>;
655 };
656 };
657
658 tcon_top_mixer1_out: port@3 {
659 #address-cells = <1>;
660 #size-cells = <0>;
661 reg = <3>;
662
663 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
664 reg = <0>;
665 };
666
667 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
668 reg = <1>;
669 };
670
671 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
672 reg = <2>;
673 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
674 };
675
676 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
677 reg = <3>;
678 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
679 };
680 };
681
682 tcon_top_hdmi_in: port@4 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 reg = <4>;
686
687 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
688 reg = <0>;
689 remote-endpoint = <&tcon_tv0_out_tcon_top>;
690 };
691
692 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
693 reg = <1>;
694 remote-endpoint = <&tcon_tv1_out_tcon_top>;
695 };
696 };
697
698 tcon_top_hdmi_out: port@5 {
699 reg = <5>;
700
701 tcon_top_hdmi_out_hdmi: endpoint {
702 remote-endpoint = <&hdmi_in_tcon_top>;
703 };
704 };
705 };
706 };
707
708 tcon_tv0: lcd-controller@1c73000 {
709 compatible = "allwinner,sun8i-r40-tcon-tv";
710 reg = <0x01c73000 0x1000>;
711 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
713 clock-names = "ahb", "tcon-ch1";
714 resets = <&ccu RST_BUS_TCON_TV0>;
715 reset-names = "lcd";
716 status = "disabled";
717
718 ports {
719 #address-cells = <1>;
720 #size-cells = <0>;
721
722 tcon_tv0_in: port@0 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 reg = <0>;
726
727 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
728 reg = <0>;
729 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
730 };
731
732 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
733 reg = <1>;
734 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
735 };
736 };
737
738 tcon_tv0_out: port@1 {
739 #address-cells = <1>;
740 #size-cells = <0>;
741 reg = <1>;
742
743 tcon_tv0_out_tcon_top: endpoint@1 {
744 reg = <1>;
745 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
746 };
747 };
748 };
749 };
750
751 tcon_tv1: lcd-controller@1c74000 {
752 compatible = "allwinner,sun8i-r40-tcon-tv";
753 reg = <0x01c74000 0x1000>;
754 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
756 clock-names = "ahb", "tcon-ch1";
757 resets = <&ccu RST_BUS_TCON_TV1>;
758 reset-names = "lcd";
759 status = "disabled";
760
761 ports {
762 #address-cells = <1>;
763 #size-cells = <0>;
764
765 tcon_tv1_in: port@0 {
766 #address-cells = <1>;
767 #size-cells = <0>;
768 reg = <0>;
769
770 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
771 reg = <0>;
772 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
773 };
774
775 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
776 reg = <1>;
777 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
778 };
779 };
780
781 tcon_tv1_out: port@1 {
782 #address-cells = <1>;
783 #size-cells = <0>;
784 reg = <1>;
785
786 tcon_tv1_out_tcon_top: endpoint@1 {
787 reg = <1>;
788 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
789 };
790 };
791 };
792 };
793
794 gic: interrupt-controller@1c81000 {
795 compatible = "arm,gic-400";
796 reg = <0x01c81000 0x1000>,
797 <0x01c82000 0x1000>,
798 <0x01c84000 0x2000>,
799 <0x01c86000 0x2000>;
800 interrupt-controller;
801 #interrupt-cells = <3>;
802 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
803 };
804
805 hdmi: hdmi@1ee0000 {
806 compatible = "allwinner,sun8i-r40-dw-hdmi",
807 "allwinner,sun8i-a83t-dw-hdmi";
808 reg = <0x01ee0000 0x10000>;
809 reg-io-width = <1>;
810 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
812 <&ccu CLK_HDMI>;
813 clock-names = "iahb", "isfr", "tmds";
814 resets = <&ccu RST_BUS_HDMI1>;
815 reset-names = "ctrl";
816 phys = <&hdmi_phy>;
817 phy-names = "phy";
818 status = "disabled";
819
820 ports {
821 #address-cells = <1>;
822 #size-cells = <0>;
823
824 hdmi_in: port@0 {
825 reg = <0>;
826
827 hdmi_in_tcon_top: endpoint {
828 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
829 };
830 };
831
832 hdmi_out: port@1 {
833 reg = <1>;
834 };
835 };
836 };
837
838 hdmi_phy: hdmi-phy@1ef0000 {
839 compatible = "allwinner,sun8i-r40-hdmi-phy";
840 reg = <0x01ef0000 0x10000>;
841 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
842 <&ccu 7>, <&ccu 16>;
843 clock-names = "bus", "mod", "pll-0", "pll-1";
844 resets = <&ccu RST_BUS_HDMI0>;
845 reset-names = "phy";
846 #phy-cells = <0>;
847 };
848 };
849
850 timer {
851 compatible = "arm,armv7-timer";
852 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
853 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
854 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
855 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
856 };
857};