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1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sunxi-h3-h5.dtsi"
44
45/ {
46 cpu0_opp_table: opp_table0 {
47 compatible = "operating-points-v2";
48 opp-shared;
49
50 opp-648000000 {
51 opp-hz = /bits/ 64 <648000000>;
52 opp-microvolt = <1040000 1040000 1300000>;
53 clock-latency-ns = <244144>; /* 8 32k periods */
54 };
55
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1100000 1100000 1300000>;
59 clock-latency-ns = <244144>; /* 8 32k periods */
60 };
61
62 opp-1008000000 {
63 opp-hz = /bits/ 64 <1008000000>;
64 opp-microvolt = <1200000 1200000 1300000>;
65 clock-latency-ns = <244144>; /* 8 32k periods */
66 };
67 };
68
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu0: cpu@0 {
74 compatible = "arm,cortex-a7";
75 device_type = "cpu";
76 reg = <0>;
77 clocks = <&ccu CLK_CPUX>;
78 clock-names = "cpu";
79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>;
81 };
82
83 cpu@1 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <1>;
87 clocks = <&ccu CLK_CPUX>;
88 clock-names = "cpu";
89 operating-points-v2 = <&cpu0_opp_table>;
90 #cooling-cells = <2>;
91 };
92
93 cpu@2 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <2>;
97 clocks = <&ccu CLK_CPUX>;
98 clock-names = "cpu";
99 operating-points-v2 = <&cpu0_opp_table>;
100 #cooling-cells = <2>;
101 };
102
103 cpu@3 {
104 compatible = "arm,cortex-a7";
105 device_type = "cpu";
106 reg = <3>;
107 clocks = <&ccu CLK_CPUX>;
108 clock-names = "cpu";
109 operating-points-v2 = <&cpu0_opp_table>;
110 #cooling-cells = <2>;
111 };
112 };
113
114 timer {
115 compatible = "arm,armv7-timer";
116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
120 };
121
122 soc {
123 syscon: system-control@1c00000 {
124 compatible = "allwinner,sun8i-h3-system-control";
125 reg = <0x01c00000 0x1000>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129
130 sram_c: sram@1d00000 {
131 compatible = "mmio-sram";
132 reg = <0x01d00000 0x80000>;
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0 0x01d00000 0x80000>;
136
137 ve_sram: sram-section@0 {
138 compatible = "allwinner,sun8i-h3-sram-c1",
139 "allwinner,sun4i-a10-sram-c1";
140 reg = <0x000000 0x80000>;
141 };
142 };
143 };
144
145 video-codec@1c0e000 {
146 compatible = "allwinner,sun8i-h3-video-engine";
147 reg = <0x01c0e000 0x1000>;
148 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
149 <&ccu CLK_DRAM_VE>;
150 clock-names = "ahb", "mod", "ram";
151 resets = <&ccu RST_BUS_VE>;
152 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
153 allwinner,sram = <&ve_sram 1>;
154 };
155
156 mali: gpu@1c40000 {
157 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
158 reg = <0x01c40000 0x10000>;
159 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "gp",
167 "gpmmu",
168 "pp0",
169 "ppmmu0",
170 "pp1",
171 "ppmmu1",
172 "pmu";
173 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
174 clock-names = "bus", "core";
175 resets = <&ccu RST_BUS_GPU>;
176
177 assigned-clocks = <&ccu CLK_GPU>;
178 assigned-clock-rates = <384000000>;
179 };
180 };
181};
182
183&ccu {
184 compatible = "allwinner,sun8i-h3-ccu";
185};
186
187&display_clocks {
188 compatible = "allwinner,sun8i-h3-de2-clk";
189};
190
191&mmc0 {
192 compatible = "allwinner,sun7i-a20-mmc";
193 clocks = <&ccu CLK_BUS_MMC0>,
194 <&ccu CLK_MMC0>,
195 <&ccu CLK_MMC0_OUTPUT>,
196 <&ccu CLK_MMC0_SAMPLE>;
197 clock-names = "ahb",
198 "mmc",
199 "output",
200 "sample";
201};
202
203&mmc1 {
204 compatible = "allwinner,sun7i-a20-mmc";
205 clocks = <&ccu CLK_BUS_MMC1>,
206 <&ccu CLK_MMC1>,
207 <&ccu CLK_MMC1_OUTPUT>,
208 <&ccu CLK_MMC1_SAMPLE>;
209 clock-names = "ahb",
210 "mmc",
211 "output",
212 "sample";
213};
214
215&mmc2 {
216 compatible = "allwinner,sun7i-a20-mmc";
217 clocks = <&ccu CLK_BUS_MMC2>,
218 <&ccu CLK_MMC2>,
219 <&ccu CLK_MMC2_OUTPUT>,
220 <&ccu CLK_MMC2_SAMPLE>;
221 clock-names = "ahb",
222 "mmc",
223 "output",
224 "sample";
225};
226
227&pio {
228 compatible = "allwinner,sun8i-h3-pinctrl";
229};
230
231&rtc {
232 compatible = "allwinner,sun8i-h3-rtc";
233};
234
235&sid {
236 compatible = "allwinner,sun8i-h3-sid";
237};