Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
4 */
5#include <dt-bindings/clock/stih407-clks.h>
6/ {
7 /*
8 * Fixed 30MHz oscillator inputs to SoC
9 */
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 };
15
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
20 };
21
22 clocks {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 /*
28 * A9 PLL.
29 */
30 clockgen-a9@92b0000 {
31 compatible = "st,clkgen-c32";
32 reg = <0x92b0000 0xffff>;
33
34 clockgen_a9_pll: clockgen-a9-pll {
35 #clock-cells = <1>;
36 compatible = "st,stih407-clkgen-plla9";
37
38 clocks = <&clk_sysin>;
39
40 clock-output-names = "clockgen-a9-pll-odf";
41 };
42 };
43
44 /*
45 * ARM CPU related clocks.
46 */
47 clk_m_a9: clk-m-a9@92b0000 {
48 #clock-cells = <0>;
49 compatible = "st,stih407-clkgen-a9-mux";
50 reg = <0x92b0000 0x10000>;
51
52 clocks = <&clockgen_a9_pll 0>,
53 <&clockgen_a9_pll 0>,
54 <&clk_s_c0_flexgen 13>,
55 <&clk_m_a9_ext2f_div2>;
56
57
58 /*
59 * ARM Peripheral clock for timers
60 */
61 arm_periph_clk: clk-m-a9-periphs {
62 #clock-cells = <0>;
63 compatible = "fixed-factor-clock";
64
65 clocks = <&clk_m_a9>;
66 clock-div = <2>;
67 clock-mult = <1>;
68 };
69 };
70
71 clockgen-a@90ff000 {
72 compatible = "st,clkgen-c32";
73 reg = <0x90ff000 0x1000>;
74
75 clk_s_a0_pll: clk-s-a0-pll {
76 #clock-cells = <1>;
77 compatible = "st,clkgen-pll0";
78
79 clocks = <&clk_sysin>;
80
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
83 };
84
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
86 compatible = "st,flexgen";
87
88 #clock-cells = <1>;
89
90 clocks = <&clk_s_a0_pll 0>,
91 <&clk_sysin>;
92
93 clock-output-names = "clk-ic-lmi0";
94 clock-critical = <CLK_IC_LMI0>;
95 };
96 };
97
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
99 #clock-cells = <1>;
100 compatible = "st,quadfs-pll";
101 reg = <0x9103000 0x1000>;
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
110 };
111
112 clk_s_c0: clockgen-c@9103000 {
113 compatible = "st,clkgen-c32";
114 reg = <0x9103000 0x1000>;
115
116 clk_s_c0_pll0: clk-s-c0-pll0 {
117 #clock-cells = <1>;
118 compatible = "st,clkgen-pll0";
119
120 clocks = <&clk_sysin>;
121
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
124 };
125
126 clk_s_c0_pll1: clk-s-c0-pll1 {
127 #clock-cells = <1>;
128 compatible = "st,clkgen-pll1";
129
130 clocks = <&clk_sysin>;
131
132 clock-output-names = "clk-s-c0-pll1-odf-0";
133 };
134
135 clk_s_c0_flexgen: clk-s-c0-flexgen {
136 #clock-cells = <1>;
137 compatible = "st,flexgen";
138
139 clocks = <&clk_s_c0_pll0 0>,
140 <&clk_s_c0_pll1 0>,
141 <&clk_s_c0_quadfs 0>,
142 <&clk_s_c0_quadfs 1>,
143 <&clk_s_c0_quadfs 2>,
144 <&clk_s_c0_quadfs 3>,
145 <&clk_sysin>;
146
147 clock-output-names = "clk-icn-gpu",
148 "clk-fdma",
149 "clk-nand",
150 "clk-hva",
151 "clk-proc-stfe",
152 "clk-proc-tp",
153 "clk-rx-icn-dmu",
154 "clk-rx-icn-hva",
155 "clk-icn-cpu",
156 "clk-tx-icn-dmu",
157 "clk-mmc-0",
158 "clk-mmc-1",
159 "clk-jpegdec",
160 "clk-ext2fa9",
161 "clk-ic-bdisp-0",
162 "clk-ic-bdisp-1",
163 "clk-pp-dmu",
164 "clk-vid-dmu",
165 "clk-dss-lpc",
166 "clk-st231-aud-0",
167 "clk-st231-gp-1",
168 "clk-st231-dmu",
169 "clk-icn-lmi",
170 "clk-tx-icn-disp-1",
171 "clk-icn-sbc",
172 "clk-stfe-frc2",
173 "clk-eth-phy",
174 "clk-eth-ref-phyclk",
175 "clk-flash-promip",
176 "clk-main-disp",
177 "clk-aux-disp",
178 "clk-compo-dvp";
179 clock-critical = <CLK_PROC_STFE>,
180 <CLK_ICN_CPU>,
181 <CLK_TX_ICN_DMU>,
182 <CLK_EXT2F_A9>,
183 <CLK_ICN_LMI>,
184 <CLK_ICN_SBC>;
185
186 /*
187 * ARM Peripheral clock for timers
188 */
189 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
190 #clock-cells = <0>;
191 compatible = "fixed-factor-clock";
192
193 clocks = <&clk_s_c0_flexgen 13>;
194
195 clock-output-names = "clk-m-a9-ext2f-div2";
196
197 clock-div = <2>;
198 clock-mult = <1>;
199 };
200 };
201 };
202
203 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
204 #clock-cells = <1>;
205 compatible = "st,quadfs";
206 reg = <0x9104000 0x1000>;
207
208 clocks = <&clk_sysin>;
209
210 clock-output-names = "clk-s-d0-fs0-ch0",
211 "clk-s-d0-fs0-ch1",
212 "clk-s-d0-fs0-ch2",
213 "clk-s-d0-fs0-ch3";
214 };
215
216 clockgen-d0@9104000 {
217 compatible = "st,clkgen-c32";
218 reg = <0x9104000 0x1000>;
219
220 clk_s_d0_flexgen: clk-s-d0-flexgen {
221 #clock-cells = <1>;
222 compatible = "st,flexgen-audio", "st,flexgen";
223
224 clocks = <&clk_s_d0_quadfs 0>,
225 <&clk_s_d0_quadfs 1>,
226 <&clk_s_d0_quadfs 2>,
227 <&clk_s_d0_quadfs 3>,
228 <&clk_sysin>;
229
230 clock-output-names = "clk-pcm-0",
231 "clk-pcm-1",
232 "clk-pcm-2",
233 "clk-spdiff";
234 };
235 };
236
237 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
238 #clock-cells = <1>;
239 compatible = "st,quadfs";
240 reg = <0x9106000 0x1000>;
241
242 clocks = <&clk_sysin>;
243
244 clock-output-names = "clk-s-d2-fs0-ch0",
245 "clk-s-d2-fs0-ch1",
246 "clk-s-d2-fs0-ch2",
247 "clk-s-d2-fs0-ch3";
248 };
249
250 clockgen-d2@9106000 {
251 compatible = "st,clkgen-c32";
252 reg = <0x9106000 0x1000>;
253
254 clk_s_d2_flexgen: clk-s-d2-flexgen {
255 #clock-cells = <1>;
256 compatible = "st,flexgen-video", "st,flexgen";
257
258 clocks = <&clk_s_d2_quadfs 0>,
259 <&clk_s_d2_quadfs 1>,
260 <&clk_s_d2_quadfs 2>,
261 <&clk_s_d2_quadfs 3>,
262 <&clk_sysin>,
263 <&clk_sysin>,
264 <&clk_tmdsout_hdmi>;
265
266 clock-output-names = "clk-pix-main-disp",
267 "clk-pix-pip",
268 "clk-pix-gdp1",
269 "clk-pix-gdp2",
270 "clk-pix-gdp3",
271 "clk-pix-gdp4",
272 "clk-pix-aux-disp",
273 "clk-denc",
274 "clk-pix-hddac",
275 "clk-hddac",
276 "clk-sddac",
277 "clk-pix-dvo",
278 "clk-dvo",
279 "clk-pix-hdmi",
280 "clk-tmds-hdmi",
281 "clk-ref-hdmiphy";
282 };
283 };
284
285 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
286 #clock-cells = <1>;
287 compatible = "st,quadfs";
288 reg = <0x9107000 0x1000>;
289
290 clocks = <&clk_sysin>;
291
292 clock-output-names = "clk-s-d3-fs0-ch0",
293 "clk-s-d3-fs0-ch1",
294 "clk-s-d3-fs0-ch2",
295 "clk-s-d3-fs0-ch3";
296 };
297
298 clockgen-d3@9107000 {
299 compatible = "st,clkgen-c32";
300 reg = <0x9107000 0x1000>;
301
302 clk_s_d3_flexgen: clk-s-d3-flexgen {
303 #clock-cells = <1>;
304 compatible = "st,flexgen";
305
306 clocks = <&clk_s_d3_quadfs 0>,
307 <&clk_s_d3_quadfs 1>,
308 <&clk_s_d3_quadfs 2>,
309 <&clk_s_d3_quadfs 3>,
310 <&clk_sysin>;
311
312 clock-output-names = "clk-stfe-frc1",
313 "clk-tsout-0",
314 "clk-tsout-1",
315 "clk-mchi",
316 "clk-vsens-compo",
317 "clk-frc1-remote",
318 "clk-lpc-0",
319 "clk-lpc-1";
320 };
321 };
322 };
323};