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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DTS file for all SPEAr1310 SoCs
4 *
5 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
6 */
7
8/include/ "spear13xx.dtsi"
9
10/ {
11 compatible = "st,spear1310";
12
13 ahb {
14 spics: spics@e0700000{
15 compatible = "st,spear-spics-gpio";
16 reg = <0xe0700000 0x1000>;
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 miphy0: miphy@eb800000 {
27 compatible = "st,spear1310-miphy";
28 reg = <0xeb800000 0x4000>;
29 misc = <&misc>;
30 phy-id = <0>;
31 #phy-cells = <1>;
32 status = "disabled";
33 };
34
35 miphy1: miphy@eb804000 {
36 compatible = "st,spear1310-miphy";
37 reg = <0xeb804000 0x4000>;
38 misc = <&misc>;
39 phy-id = <1>;
40 #phy-cells = <1>;
41 status = "disabled";
42 };
43
44 miphy2: miphy@eb808000 {
45 compatible = "st,spear1310-miphy";
46 reg = <0xeb808000 0x4000>;
47 misc = <&misc>;
48 phy-id = <2>;
49 #phy-cells = <1>;
50 status = "disabled";
51 };
52
53 ahci0: ahci@b1000000 {
54 compatible = "snps,spear-ahci";
55 reg = <0xb1000000 0x10000>;
56 interrupts = <0 68 0x4>;
57 phys = <&miphy0 0>;
58 phy-names = "sata-phy";
59 status = "disabled";
60 };
61
62 ahci1: ahci@b1800000 {
63 compatible = "snps,spear-ahci";
64 reg = <0xb1800000 0x10000>;
65 interrupts = <0 69 0x4>;
66 phys = <&miphy1 0>;
67 phy-names = "sata-phy";
68 status = "disabled";
69 };
70
71 ahci2: ahci@b4000000 {
72 compatible = "snps,spear-ahci";
73 reg = <0xb4000000 0x10000>;
74 interrupts = <0 70 0x4>;
75 phys = <&miphy2 0>;
76 phy-names = "sata-phy";
77 status = "disabled";
78 };
79
80 pcie0: pcie@b1000000 {
81 compatible = "st,spear1340-pcie", "snps,dw-pcie";
82 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
83 reg-names = "dbi", "config";
84 interrupts = <0 68 0x4>;
85 interrupt-map-mask = <0 0 0 0>;
86 interrupt-map = <0x0 0 &gic 0 68 0x4>;
87 num-lanes = <1>;
88 phys = <&miphy0 1>;
89 phy-names = "pcie-phy";
90 #address-cells = <3>;
91 #size-cells = <2>;
92 device_type = "pci";
93 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
94 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
95 bus-range = <0x00 0xff>;
96 status = "disabled";
97 };
98
99 pcie1: pcie@b1800000 {
100 compatible = "st,spear1340-pcie", "snps,dw-pcie";
101 reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
102 reg-names = "dbi", "config";
103 interrupts = <0 69 0x4>;
104 interrupt-map-mask = <0 0 0 0>;
105 interrupt-map = <0x0 0 &gic 0 69 0x4>;
106 num-lanes = <1>;
107 phys = <&miphy1 1>;
108 phy-names = "pcie-phy";
109 #address-cells = <3>;
110 #size-cells = <2>;
111 device_type = "pci";
112 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
113 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
114 bus-range = <0x00 0xff>;
115 status = "disabled";
116 };
117
118 pcie2: pcie@b4000000 {
119 compatible = "st,spear1340-pcie", "snps,dw-pcie";
120 reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
121 reg-names = "dbi", "config";
122 interrupts = <0 70 0x4>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0x0 0 &gic 0 70 0x4>;
125 num-lanes = <1>;
126 phys = <&miphy2 1>;
127 phy-names = "pcie-phy";
128 #address-cells = <3>;
129 #size-cells = <2>;
130 device_type = "pci";
131 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
132 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
133 bus-range = <0x00 0xff>;
134 status = "disabled";
135 };
136
137 gmac1: eth@5c400000 {
138 compatible = "st,spear600-gmac";
139 reg = <0x5c400000 0x8000>;
140 interrupts = <0 95 0x4>;
141 interrupt-names = "macirq";
142 phy-mode = "mii";
143 status = "disabled";
144 };
145
146 gmac2: eth@5c500000 {
147 compatible = "st,spear600-gmac";
148 reg = <0x5c500000 0x8000>;
149 interrupts = <0 96 0x4>;
150 interrupt-names = "macirq";
151 phy-mode = "mii";
152 status = "disabled";
153 };
154
155 gmac3: eth@5c600000 {
156 compatible = "st,spear600-gmac";
157 reg = <0x5c600000 0x8000>;
158 interrupts = <0 97 0x4>;
159 interrupt-names = "macirq";
160 phy-mode = "rmii";
161 status = "disabled";
162 };
163
164 gmac4: eth@5c700000 {
165 compatible = "st,spear600-gmac";
166 reg = <0x5c700000 0x8000>;
167 interrupts = <0 98 0x4>;
168 interrupt-names = "macirq";
169 phy-mode = "rgmii";
170 status = "disabled";
171 };
172
173 pinmux: pinmux@e0700000 {
174 compatible = "st,spear1310-pinmux";
175 reg = <0xe0700000 0x1000>;
176 #gpio-range-cells = <3>;
177 };
178
179 apb {
180 i2c1: i2c@5cd00000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "snps,designware-i2c";
184 reg = <0x5cd00000 0x1000>;
185 interrupts = <0 87 0x4>;
186 status = "disabled";
187 };
188
189 i2c2: i2c@5ce00000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "snps,designware-i2c";
193 reg = <0x5ce00000 0x1000>;
194 interrupts = <0 88 0x4>;
195 status = "disabled";
196 };
197
198 i2c3: i2c@5cf00000 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "snps,designware-i2c";
202 reg = <0x5cf00000 0x1000>;
203 interrupts = <0 89 0x4>;
204 status = "disabled";
205 };
206
207 i2c4: i2c@5d000000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "snps,designware-i2c";
211 reg = <0x5d000000 0x1000>;
212 interrupts = <0 90 0x4>;
213 status = "disabled";
214 };
215
216 i2c5: i2c@5d100000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "snps,designware-i2c";
220 reg = <0x5d100000 0x1000>;
221 interrupts = <0 91 0x4>;
222 status = "disabled";
223 };
224
225 i2c6: i2c@5d200000 {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "snps,designware-i2c";
229 reg = <0x5d200000 0x1000>;
230 interrupts = <0 92 0x4>;
231 status = "disabled";
232 };
233
234 i2c7: i2c@5d300000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "snps,designware-i2c";
238 reg = <0x5d300000 0x1000>;
239 interrupts = <0 93 0x4>;
240 status = "disabled";
241 };
242
243 spi1: spi@5d400000 {
244 compatible = "arm,pl022", "arm,primecell";
245 reg = <0x5d400000 0x1000>;
246 interrupts = <0 99 0x4>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 status = "disabled";
250 };
251
252 serial@5c800000 {
253 compatible = "arm,pl011", "arm,primecell";
254 reg = <0x5c800000 0x1000>;
255 interrupts = <0 82 0x4>;
256 status = "disabled";
257 };
258
259 serial@5c900000 {
260 compatible = "arm,pl011", "arm,primecell";
261 reg = <0x5c900000 0x1000>;
262 interrupts = <0 83 0x4>;
263 status = "disabled";
264 };
265
266 serial@5ca00000 {
267 compatible = "arm,pl011", "arm,primecell";
268 reg = <0x5ca00000 0x1000>;
269 interrupts = <0 84 0x4>;
270 status = "disabled";
271 };
272
273 serial@5cb00000 {
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0x5cb00000 0x1000>;
276 interrupts = <0 85 0x4>;
277 status = "disabled";
278 };
279
280 serial@5cc00000 {
281 compatible = "arm,pl011", "arm,primecell";
282 reg = <0x5cc00000 0x1000>;
283 interrupts = <0 86 0x4>;
284 status = "disabled";
285 };
286
287 thermal@e07008c4 {
288 st,thermal-flags = <0x7000>;
289 };
290
291 gpiopinctrl: gpio@d8400000 {
292 compatible = "st,spear-plgpio";
293 reg = <0xd8400000 0x1000>;
294 interrupts = <0 100 0x4>;
295 #interrupt-cells = <1>;
296 interrupt-controller;
297 gpio-controller;
298 #gpio-cells = <2>;
299 gpio-ranges = <&pinmux 0 0 246>;
300 status = "disabled";
301
302 st-plgpio,ngpio = <246>;
303 st-plgpio,enb-reg = <0xd0>;
304 st-plgpio,wdata-reg = <0x90>;
305 st-plgpio,dir-reg = <0xb0>;
306 st-plgpio,ie-reg = <0x30>;
307 st-plgpio,rdata-reg = <0x70>;
308 st-plgpio,mis-reg = <0x10>;
309 st-plgpio,eit-reg = <0x50>;
310 };
311 };
312 };
313};