1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (c) 2014 MundoReader S.L.
  4 * Author: Matthias Brugger <matthias.bgg@gmail.com>
  5 *
  6*/
  7
  8#include <dt-bindings/interrupt-controller/irq.h>
  9#include <dt-bindings/interrupt-controller/arm-gic.h>
 10
 11/ {
 12	#address-cells = <1>;
 13	#size-cells = <1>;
 14	compatible = "mediatek,mt6589";
 15	interrupt-parent = <&sysirq>;
 16
 17	cpus {
 18		#address-cells = <1>;
 19		#size-cells = <0>;
 20
 21		cpu@0 {
 22			device_type = "cpu";
 23			compatible = "arm,cortex-a7";
 24			reg = <0x0>;
 25		};
 26		cpu@1 {
 27			device_type = "cpu";
 28			compatible = "arm,cortex-a7";
 29			reg = <0x1>;
 30		};
 31		cpu@2 {
 32			device_type = "cpu";
 33			compatible = "arm,cortex-a7";
 34			reg = <0x2>;
 35		};
 36		cpu@3 {
 37			device_type = "cpu";
 38			compatible = "arm,cortex-a7";
 39			reg = <0x3>;
 40		};
 41
 42	};
 43
 44	clocks {
 45		#address-cells = <1>;
 46		#size-cells = <1>;
 47		compatible = "simple-bus";
 48		ranges;
 49
 50		system_clk: dummy13m {
 51			compatible = "fixed-clock";
 52			clock-frequency = <13000000>;
 53			#clock-cells = <0>;
 54		};
 55
 56		rtc_clk: dummy32k {
 57			compatible = "fixed-clock";
 58			clock-frequency = <32000>;
 59			#clock-cells = <0>;
 60		};
 61
 62		uart_clk: dummy26m {
 63			compatible = "fixed-clock";
 64			clock-frequency = <26000000>;
 65			#clock-cells = <0>;
 66		};
 67	};
 68
 69	soc {
 70		#address-cells = <1>;
 71		#size-cells = <1>;
 72		compatible = "simple-bus";
 73		ranges;
 74
 75		timer: timer@10008000 {
 76			compatible = "mediatek,mt6577-timer";
 77			reg = <0x10008000 0x80>;
 78			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
 79			clocks = <&system_clk>, <&rtc_clk>;
 80			clock-names = "system-clk", "rtc-clk";
 81		};
 82
 83		sysirq: interrupt-controller@10200100 {
 84			compatible = "mediatek,mt6589-sysirq",
 85				     "mediatek,mt6577-sysirq";
 86			interrupt-controller;
 87			#interrupt-cells = <3>;
 88			interrupt-parent = <&gic>;
 89			reg = <0x10200100 0x1c>;
 90		};
 91
 92		gic: interrupt-controller@10211000 {
 93			compatible = "arm,cortex-a7-gic";
 94			interrupt-controller;
 95			#interrupt-cells = <3>;
 96			interrupt-parent = <&gic>;
 97			reg = <0x10211000 0x1000>,
 98			      <0x10212000 0x2000>,
 99			      <0x10214000 0x2000>,
100			      <0x10216000 0x2000>;
101		};
102
103		uart0: serial@11006000 {
104			compatible = "mediatek,mt6577-uart";
105			reg = <0x11006000 0x400>;
106			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
107			clocks = <&uart_clk>;
108			status = "disabled";
109		};
110
111		uart1: serial@11007000 {
112			compatible = "mediatek,mt6577-uart";
113			reg = <0x11007000 0x400>;
114			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
115			clocks = <&uart_clk>;
116			status = "disabled";
117		};
118
119		uart2: serial@11008000 {
120			compatible = "mediatek,mt6577-uart";
121			reg = <0x11008000 0x400>;
122			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
123			clocks = <&uart_clk>;
124			status = "disabled";
125		};
126
127		uart3: serial@11009000 {
128			compatible = "mediatek,mt6577-uart";
129			reg = <0x11009000 0x400>;
130			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
131			clocks = <&uart_clk>;
132			status = "disabled";
133		};
134
135		wdt: watchdog@10000000 {
136			compatible = "mediatek,mt6589-wdt";
137			reg = <0x10000000 0x44>;
138		};
139	};
140};