1// SPDX-License-Identifier: GPL-2.0 OR X11
  2/*
  3 * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
  4 *
  5 * Copyright (C) 2016 TQ Systems GmbH
  6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
  7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
  8 */
  9
 10/dts-v1/;
 11
 12#include "imx7d-tqma7.dtsi"
 13#include "imx7-mba7.dtsi"
 14
 15/ {
 16	model = "TQ Systems TQMa7D board on MBa7 carrier board";
 17	compatible = "tq,imx7d-mba7", "fsl,imx7d";
 18};
 19
 20&fec2 {
 21	pinctrl-names = "default";
 22	pinctrl-0 = <&pinctrl_enet2>;
 23	phy-mode = "rgmii-id";
 24	phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 25	phy-reset-duration = <1>;
 26	phy-reset-delay = <1>;
 27	phy-supply = <&reg_fec2_pwdn>;
 28	phy-handle = <&ethphy2_0>;
 29	fsl,magic-packet;
 30	status = "okay";
 31
 32	mdio {
 33		#address-cells = <1>;
 34		#size-cells = <0>;
 35
 36		ethphy2_0: ethernet-phy@0 {
 37			compatible = "ethernet-phy-ieee802.3-c22";
 38			reg = <0>;
 39			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
 40			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
 41			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 42			/* LED1: Link/Activity, LED2: error */
 43			ti,led-function = <0x0db0>;
 44			/* active low, LED1/2 driven by phy */
 45			ti,led-ctrl = <0x1001>;
 46		};
 47	};
 48};
 49
 50&iomuxc {
 51	pinctrl-names = "default";
 52	pinctrl-0 = <&pinctrl_hog_mba7_1>;
 53
 54	pinctrl_enet2: enet2grp {
 55		fsl,pins = <
 56			MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x02
 57			MX7D_PAD_SD2_WP__ENET2_MDC			0x00
 58			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x71
 59			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x71
 60			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x71
 61			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x71
 62			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x71
 63			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x71
 64			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x79
 65			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x79
 66			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79
 67			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79
 68			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79
 69			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x79
 70			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
 71			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070
 72			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
 73			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x40000078
 74		>;
 75	};
 76
 77	pinctrl_pcie: pciegrp {
 78		fsl,pins = <
 79			/* #pcie_wake */
 80			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30		0x70
 81			/* #pcie_rst */
 82			MX7D_PAD_SD2_CLK__GPIO5_IO12			0x70
 83			/* #pcie_dis */
 84			MX7D_PAD_EPDC_BDR1__GPIO2_IO29			0x70
 85		>;
 86	};
 87};
 88
 89&iomuxc_lpsr {
 90	pinctrl_usbotg2: usbotg2grp {
 91		fsl,pins = <
 92			MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC	0x5c
 93			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x59
 94		>;
 95	};
 96};
 97
 98&pcie {
 99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_pcie>;
101	/* 1.5V logically from 3.3V */
102	/* probe deferral not supported */
103	/* pcie-bus-supply = <&reg_mpcie_1v5>; */
104	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
105	disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
106	power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>;
107	status = "okay";
108};
109
110&usbotg2 {
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_usbotg2>;
113	vbus-supply = <&reg_usb_otg2_vbus>;
114	srp-disable;
115	hnp-disable;
116	adp-disable;
117	dr_mode = "host";
118	status = "okay";
119};