Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017 exceet electronics GmbH
4 * Copyright (C) 2018 Kontron Electronics GmbH
5 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8/dts-v1/;
9
10#include "imx6ul-kontron-n6310-som.dtsi"
11
12/ {
13 model = "Kontron N6310 S";
14 compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
15 "fsl,imx6ul";
16
17 gpio-leds {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
21
22 led1 {
23 label = "debug-led1";
24 gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
25 default-state = "off";
26 linux,default-trigger = "heartbeat";
27 };
28
29 led2 {
30 label = "debug-led2";
31 gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
32 default-state = "off";
33 };
34
35 led3 {
36 label = "debug-led3";
37 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
38 default-state = "off";
39 };
40 };
41
42 pwm-beeper {
43 compatible = "pwm-beeper";
44 pwms = <&pwm8 0 5000>;
45 };
46
47 reg_3v3: regulator-3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "3v3";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 };
53
54 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
55 compatible = "regulator-fixed";
56 regulator-name = "usb_otg1_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62
63 reg_vref_adc: regulator-vref-adc {
64 compatible = "regulator-fixed";
65 regulator-name = "vref-adc";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 };
69};
70
71&adc1 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_adc1>;
74 num-channels = <3>;
75 vref-supply = <®_vref_adc>;
76 status = "okay";
77};
78
79&can2 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_flexcan2>;
82 status = "okay";
83};
84
85&ecspi1 {
86 cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_ecspi1>;
89 status = "okay";
90
91 eeprom@0 {
92 compatible = "anvo,anv32e61w", "atmel,at25";
93 reg = <0>;
94 spi-max-frequency = <20000000>;
95 spi-cpha;
96 spi-cpol;
97 pagesize = <1>;
98 size = <8192>;
99 address-width = <16>;
100 };
101};
102
103&fec1 {
104 pinctrl-0 = <&pinctrl_enet1>;
105 /delete-node/ mdio;
106};
107
108&fec2 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
111 phy-mode = "rmii";
112 phy-handle = <ðphy2>;
113 status = "okay";
114
115 mdio {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 ethphy1: ethernet-phy@1 {
120 reg = <1>;
121 micrel,led-mode = <0>;
122 clocks = <&clks IMX6UL_CLK_ENET_REF>;
123 clock-names = "rmii-ref";
124 };
125
126 ethphy2: ethernet-phy@2 {
127 reg = <2>;
128 micrel,led-mode = <0>;
129 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
130 clock-names = "rmii-ref";
131 };
132 };
133};
134
135&i2c1 {
136 clock-frequency = <100000>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c1>;
139 status = "okay";
140};
141
142&i2c4 {
143 clock-frequency = <100000>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_i2c4>;
146 status = "okay";
147
148 rtc@32 {
149 compatible = "epson,rx8900";
150 reg = <0x32>;
151 };
152};
153
154&pwm8 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_pwm8>;
157 status = "okay";
158};
159
160&snvs_poweroff {
161 status = "okay";
162};
163
164&uart1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_uart1>;
167 status = "okay";
168};
169
170&uart2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_uart2>;
173 linux,rs485-enabled-at-boot-time;
174 rs485-rx-during-tx;
175 rs485-rts-active-low;
176 uart-has-rtscts;
177 status = "okay";
178};
179
180&uart3 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_uart3>;
183 fsl,uart-has-rtscts;
184 status = "okay";
185};
186
187&uart4 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_uart4>;
190 status = "okay";
191};
192
193&usbotg1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_usbotg1>;
196 dr_mode = "otg";
197 srp-disable;
198 hnp-disable;
199 adp-disable;
200 vbus-supply = <®_usb_otg1_vbus>;
201 status = "okay";
202};
203
204&usbotg2 {
205 dr_mode = "host";
206 disable-over-current;
207 status = "okay";
208};
209
210&usdhc1 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_usdhc1>;
213 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
214 keep-power-in-suspend;
215 wakeup-source;
216 vmmc-supply = <®_3v3>;
217 voltage-ranges = <3300 3300>;
218 no-1-8-v;
219 status = "okay";
220};
221
222&usdhc2 {
223 pinctrl-names = "default", "state_100mhz", "state_200mhz";
224 pinctrl-0 = <&pinctrl_usdhc2>;
225 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
226 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
227 non-removable;
228 keep-power-in-suspend;
229 wakeup-source;
230 vmmc-supply = <®_3v3>;
231 voltage-ranges = <3300 3300>;
232 no-1-8-v;
233 status = "okay";
234};
235
236&wdog1 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_wdog>;
239 fsl,ext-reset-output;
240 status = "okay";
241};
242
243&iomuxc {
244 pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
245
246 pinctrl_adc1: adc1grp {
247 fsl,pins = <
248 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
249 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
250 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
251 >;
252 };
253
254 /* FRAM */
255 pinctrl_ecspi1: ecspi1grp {
256 fsl,pins = <
257 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
258 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
259 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
260 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
261 >;
262 };
263
264 pinctrl_enet2: enet2grp {
265 fsl,pins = <
266 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
267 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
268 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
269 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
270 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
271 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
272 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
273 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
274 >;
275 };
276
277 pinctrl_enet2_mdio: enet2mdiogrp {
278 fsl,pins = <
279 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
280 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
281 >;
282 };
283
284 pinctrl_flexcan2: flexcan2grp{
285 fsl,pins = <
286 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
287 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
288 >;
289 };
290
291 pinctrl_gpio: gpiogrp {
292 fsl,pins = <
293 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
294 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
295 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
296 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
297 >;
298 };
299
300 pinctrl_gpio_leds: gpioledsgrp {
301 fsl,pins = <
302 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
303 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
304 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
305 >;
306 };
307
308 pinctrl_i2c1: i2c1grp {
309 fsl,pins = <
310 MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
311 MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
312 >;
313 };
314
315 pinctrl_i2c4: i2c4grp {
316 fsl,pins = <
317 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
318 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
319 >;
320 };
321
322 pinctrl_pwm8: pwm8grp {
323 fsl,pins = <
324 MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
325 >;
326 };
327
328 pinctrl_uart1: uart1grp {
329 fsl,pins = <
330 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
331 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
332 >;
333 };
334
335 pinctrl_uart2: uart2grp {
336 fsl,pins = <
337 MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
338 MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
339 MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
340 /*
341 * mux unused RTS to make sure it doesn't cause
342 * any interrupts when it is undefined
343 */
344 MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
345 >;
346 };
347
348 pinctrl_uart3: uart3grp {
349 fsl,pins = <
350 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
351 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
352 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
353 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
354 >;
355 };
356
357 pinctrl_uart4: uart4grp {
358 fsl,pins = <
359 MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
360 MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
361 >;
362 };
363
364 pinctrl_usbotg1: usbotg1 {
365 fsl,pins = <
366 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
367 >;
368 };
369
370 pinctrl_usdhc1: usdhc1grp {
371 fsl,pins = <
372 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
373 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
374 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
375 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
376 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
377 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
378 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
379 >;
380 };
381
382 pinctrl_usdhc2: usdhc2grp {
383 fsl,pins = <
384 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
385 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
386 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
387 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
388 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
389 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
390 >;
391 };
392
393 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
394 fsl,pins = <
395 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
396 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
397 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
398 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
399 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
400 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
401 >;
402 };
403
404 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
405 fsl,pins = <
406 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
407 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
408 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
409 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
410 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
411 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
412 >;
413 };
414
415 pinctrl_wdog: wdoggrp {
416 fsl,pins = <
417 MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
418 >;
419 };
420};