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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4 SoC series common device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
11 * SoCs from Exynos4 series can include this file and provide values for SoCs
12 * specfic bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include <dt-bindings/clock/exynos4.h>
20#include <dt-bindings/clock/exynos-audss-clk.h>
21#include <dt-bindings/interrupt-controller/arm-gic.h>
22#include <dt-bindings/interrupt-controller/irq.h>
23
24/ {
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 csis0 = &csis_0;
43 csis1 = &csis_1;
44 fimc0 = &fimc_0;
45 fimc1 = &fimc_1;
46 fimc2 = &fimc_2;
47 fimc3 = &fimc_3;
48 serial0 = &serial_0;
49 serial1 = &serial_1;
50 serial2 = &serial_2;
51 serial3 = &serial_3;
52 };
53
54 pmu: pmu {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&combiner>;
57 status = "disabled";
58 };
59
60 soc: soc {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
68 reg = <0x03810000 0x0C>;
69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
74 "sclk_pcm_in";
75 };
76
77 i2s0: i2s@3830000 {
78 compatible = "samsung,s5pv210-i2s";
79 reg = <0x03830000 0x100>;
80 clocks = <&clock_audss EXYNOS_I2S_BUS>,
81 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
82 <&clock_audss EXYNOS_SCLK_I2S>;
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
84 #clock-cells = <1>;
85 clock-output-names = "i2s_cdclk0";
86 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
87 dma-names = "tx", "rx", "tx-sec";
88 samsung,idma-addr = <0x03000000>;
89 #sound-dai-cells = <1>;
90 status = "disabled";
91 };
92
93 chipid@10000000 {
94 compatible = "samsung,exynos4210-chipid";
95 reg = <0x10000000 0x100>;
96 };
97
98 scu: snoop-control-unit@10500000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0x10500000 0x2000>;
101 };
102
103 memory-controller@12570000 {
104 compatible = "samsung,exynos4210-srom";
105 reg = <0x12570000 0x14>;
106 };
107
108 mipi_phy: video-phy {
109 compatible = "samsung,s5pv210-mipi-video-phy";
110 #phy-cells = <1>;
111 syscon = <&pmu_system_controller>;
112 };
113
114 pd_mfc: mfc-power-domain@10023c40 {
115 compatible = "samsung,exynos4210-pd";
116 reg = <0x10023C40 0x20>;
117 #power-domain-cells = <0>;
118 label = "MFC";
119 };
120
121 pd_g3d: g3d-power-domain@10023c60 {
122 compatible = "samsung,exynos4210-pd";
123 reg = <0x10023C60 0x20>;
124 #power-domain-cells = <0>;
125 label = "G3D";
126 };
127
128 pd_lcd0: lcd0-power-domain@10023c80 {
129 compatible = "samsung,exynos4210-pd";
130 reg = <0x10023C80 0x20>;
131 #power-domain-cells = <0>;
132 label = "LCD0";
133 };
134
135 pd_tv: tv-power-domain@10023c20 {
136 compatible = "samsung,exynos4210-pd";
137 reg = <0x10023C20 0x20>;
138 #power-domain-cells = <0>;
139 power-domains = <&pd_lcd0>;
140 label = "TV";
141 };
142
143 pd_cam: cam-power-domain@10023c00 {
144 compatible = "samsung,exynos4210-pd";
145 reg = <0x10023C00 0x20>;
146 #power-domain-cells = <0>;
147 label = "CAM";
148 };
149
150 pd_gps: gps-power-domain@10023ce0 {
151 compatible = "samsung,exynos4210-pd";
152 reg = <0x10023CE0 0x20>;
153 #power-domain-cells = <0>;
154 label = "GPS";
155 };
156
157 pd_gps_alive: gps-alive-power-domain@10023d00 {
158 compatible = "samsung,exynos4210-pd";
159 reg = <0x10023D00 0x20>;
160 #power-domain-cells = <0>;
161 label = "GPS alive";
162 };
163
164 gic: interrupt-controller@10490000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
169 };
170
171 combiner: interrupt-controller@10440000 {
172 compatible = "samsung,exynos4210-combiner";
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 reg = <0x10440000 0x1000>;
176 };
177
178 sys_reg: syscon@10010000 {
179 compatible = "samsung,exynos4-sysreg", "syscon";
180 reg = <0x10010000 0x400>;
181 };
182
183 pmu_system_controller: system-controller@10020000 {
184 compatible = "samsung,exynos4210-pmu", "syscon";
185 reg = <0x10020000 0x4000>;
186 interrupt-controller;
187 #interrupt-cells = <3>;
188 interrupt-parent = <&gic>;
189 };
190
191 dsi_0: dsi@11c80000 {
192 compatible = "samsung,exynos4210-mipi-dsi";
193 reg = <0x11C80000 0x10000>;
194 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
195 power-domains = <&pd_lcd0>;
196 phys = <&mipi_phy 1>;
197 phy-names = "dsim";
198 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
199 clock-names = "bus_clk", "sclk_mipi";
200 status = "disabled";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 };
204
205 camera: camera {
206 compatible = "samsung,fimc", "simple-bus";
207 status = "disabled";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 #clock-cells = <1>;
211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
212 ranges;
213
214 fimc_0: fimc@11800000 {
215 compatible = "samsung,exynos4210-fimc";
216 reg = <0x11800000 0x1000>;
217 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clock CLK_FIMC0>,
219 <&clock CLK_SCLK_FIMC0>;
220 clock-names = "fimc", "sclk_fimc";
221 power-domains = <&pd_cam>;
222 samsung,sysreg = <&sys_reg>;
223 iommus = <&sysmmu_fimc0>;
224 status = "disabled";
225 };
226
227 fimc_1: fimc@11810000 {
228 compatible = "samsung,exynos4210-fimc";
229 reg = <0x11810000 0x1000>;
230 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clock CLK_FIMC1>,
232 <&clock CLK_SCLK_FIMC1>;
233 clock-names = "fimc", "sclk_fimc";
234 power-domains = <&pd_cam>;
235 samsung,sysreg = <&sys_reg>;
236 iommus = <&sysmmu_fimc1>;
237 status = "disabled";
238 };
239
240 fimc_2: fimc@11820000 {
241 compatible = "samsung,exynos4210-fimc";
242 reg = <0x11820000 0x1000>;
243 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock CLK_FIMC2>,
245 <&clock CLK_SCLK_FIMC2>;
246 clock-names = "fimc", "sclk_fimc";
247 power-domains = <&pd_cam>;
248 samsung,sysreg = <&sys_reg>;
249 iommus = <&sysmmu_fimc2>;
250 status = "disabled";
251 };
252
253 fimc_3: fimc@11830000 {
254 compatible = "samsung,exynos4210-fimc";
255 reg = <0x11830000 0x1000>;
256 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clock CLK_FIMC3>,
258 <&clock CLK_SCLK_FIMC3>;
259 clock-names = "fimc", "sclk_fimc";
260 power-domains = <&pd_cam>;
261 samsung,sysreg = <&sys_reg>;
262 iommus = <&sysmmu_fimc3>;
263 status = "disabled";
264 };
265
266 csis_0: csis@11880000 {
267 compatible = "samsung,exynos4210-csis";
268 reg = <0x11880000 0x4000>;
269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clock CLK_CSIS0>,
271 <&clock CLK_SCLK_CSIS0>;
272 clock-names = "csis", "sclk_csis";
273 bus-width = <4>;
274 power-domains = <&pd_cam>;
275 phys = <&mipi_phy 0>;
276 phy-names = "csis";
277 status = "disabled";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 };
281
282 csis_1: csis@11890000 {
283 compatible = "samsung,exynos4210-csis";
284 reg = <0x11890000 0x4000>;
285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clock CLK_CSIS1>,
287 <&clock CLK_SCLK_CSIS1>;
288 clock-names = "csis", "sclk_csis";
289 bus-width = <2>;
290 power-domains = <&pd_cam>;
291 phys = <&mipi_phy 2>;
292 phy-names = "csis";
293 status = "disabled";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 };
297 };
298
299 rtc: rtc@10070000 {
300 compatible = "samsung,s3c6410-rtc";
301 reg = <0x10070000 0x100>;
302 interrupt-parent = <&pmu_system_controller>;
303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clock CLK_RTC>;
306 clock-names = "rtc";
307 status = "disabled";
308 };
309
310 keypad: keypad@100a0000 {
311 compatible = "samsung,s5pv210-keypad";
312 reg = <0x100A0000 0x100>;
313 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clock CLK_KEYIF>;
315 clock-names = "keypad";
316 status = "disabled";
317 };
318
319 sdhci_0: sdhci@12510000 {
320 compatible = "samsung,exynos4210-sdhci";
321 reg = <0x12510000 0x100>;
322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
324 clock-names = "hsmmc", "mmc_busclk.2";
325 status = "disabled";
326 };
327
328 sdhci_1: sdhci@12520000 {
329 compatible = "samsung,exynos4210-sdhci";
330 reg = <0x12520000 0x100>;
331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
333 clock-names = "hsmmc", "mmc_busclk.2";
334 status = "disabled";
335 };
336
337 sdhci_2: sdhci@12530000 {
338 compatible = "samsung,exynos4210-sdhci";
339 reg = <0x12530000 0x100>;
340 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
342 clock-names = "hsmmc", "mmc_busclk.2";
343 status = "disabled";
344 };
345
346 sdhci_3: sdhci@12540000 {
347 compatible = "samsung,exynos4210-sdhci";
348 reg = <0x12540000 0x100>;
349 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
351 clock-names = "hsmmc", "mmc_busclk.2";
352 status = "disabled";
353 };
354
355 exynos_usbphy: exynos-usbphy@125b0000 {
356 compatible = "samsung,exynos4210-usb2-phy";
357 reg = <0x125B0000 0x100>;
358 samsung,pmureg-phandle = <&pmu_system_controller>;
359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
360 clock-names = "phy", "ref";
361 #phy-cells = <1>;
362 status = "disabled";
363 };
364
365 hsotg: hsotg@12480000 {
366 compatible = "samsung,s3c6400-hsotg";
367 reg = <0x12480000 0x20000>;
368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clock CLK_USB_DEVICE>;
370 clock-names = "otg";
371 phys = <&exynos_usbphy 0>;
372 phy-names = "usb2-phy";
373 status = "disabled";
374 };
375
376 ehci: ehci@12580000 {
377 compatible = "samsung,exynos4210-ehci";
378 reg = <0x12580000 0x100>;
379 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clock CLK_USB_HOST>;
381 clock-names = "usbhost";
382 status = "disabled";
383 phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
384 phy-names = "host", "hsic0", "hsic1";
385 };
386
387 ohci: ohci@12590000 {
388 compatible = "samsung,exynos4210-ohci";
389 reg = <0x12590000 0x100>;
390 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clock CLK_USB_HOST>;
392 clock-names = "usbhost";
393 status = "disabled";
394 phys = <&exynos_usbphy 1>;
395 phy-names = "host";
396 };
397
398 gpu: gpu@13000000 {
399 compatible = "samsung,exynos4210-mali", "arm,mali-400";
400 reg = <0x13000000 0x10000>;
401 /*
402 * CLK_G3D is not actually bus clock but a IP-level clock.
403 * The bus clock is not described in hardware manual.
404 */
405 clocks = <&clock CLK_G3D>,
406 <&clock CLK_SCLK_G3D>;
407 clock-names = "bus", "core";
408 power-domains = <&pd_g3d>;
409 status = "disabled";
410 };
411
412 i2s1: i2s@13960000 {
413 compatible = "samsung,s3c6410-i2s";
414 reg = <0x13960000 0x100>;
415 clocks = <&clock CLK_I2S1>;
416 clock-names = "iis";
417 #clock-cells = <1>;
418 clock-output-names = "i2s_cdclk1";
419 dmas = <&pdma1 12>, <&pdma1 11>;
420 dma-names = "tx", "rx";
421 #sound-dai-cells = <1>;
422 status = "disabled";
423 };
424
425 i2s2: i2s@13970000 {
426 compatible = "samsung,s3c6410-i2s";
427 reg = <0x13970000 0x100>;
428 clocks = <&clock CLK_I2S2>;
429 clock-names = "iis";
430 #clock-cells = <1>;
431 clock-output-names = "i2s_cdclk2";
432 dmas = <&pdma0 14>, <&pdma0 13>;
433 dma-names = "tx", "rx";
434 #sound-dai-cells = <1>;
435 status = "disabled";
436 };
437
438 mfc: codec@13400000 {
439 compatible = "samsung,mfc-v5";
440 reg = <0x13400000 0x10000>;
441 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
442 power-domains = <&pd_mfc>;
443 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
444 clock-names = "mfc", "sclk_mfc";
445 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
446 iommu-names = "left", "right";
447 };
448
449 serial_0: serial@13800000 {
450 compatible = "samsung,exynos4210-uart";
451 reg = <0x13800000 0x100>;
452 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
454 clock-names = "uart", "clk_uart_baud0";
455 dmas = <&pdma0 15>, <&pdma0 16>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
459
460 serial_1: serial@13810000 {
461 compatible = "samsung,exynos4210-uart";
462 reg = <0x13810000 0x100>;
463 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
465 clock-names = "uart", "clk_uart_baud0";
466 dmas = <&pdma1 15>, <&pdma1 16>;
467 dma-names = "rx", "tx";
468 status = "disabled";
469 };
470
471 serial_2: serial@13820000 {
472 compatible = "samsung,exynos4210-uart";
473 reg = <0x13820000 0x100>;
474 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
476 clock-names = "uart", "clk_uart_baud0";
477 dmas = <&pdma0 17>, <&pdma0 18>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
482 serial_3: serial@13830000 {
483 compatible = "samsung,exynos4210-uart";
484 reg = <0x13830000 0x100>;
485 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
487 clock-names = "uart", "clk_uart_baud0";
488 dmas = <&pdma1 17>, <&pdma1 18>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
492
493 i2c_0: i2c@13860000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
497 reg = <0x13860000 0x100>;
498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clock CLK_I2C0>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_bus>;
503 status = "disabled";
504 };
505
506 i2c_1: i2c@13870000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
510 reg = <0x13870000 0x100>;
511 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clock CLK_I2C1>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c1_bus>;
516 status = "disabled";
517 };
518
519 i2c_2: i2c@13880000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "samsung,s3c2440-i2c";
523 reg = <0x13880000 0x100>;
524 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clock CLK_I2C2>;
526 clock-names = "i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_bus>;
529 status = "disabled";
530 };
531
532 i2c_3: i2c@13890000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "samsung,s3c2440-i2c";
536 reg = <0x13890000 0x100>;
537 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clock CLK_I2C3>;
539 clock-names = "i2c";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c3_bus>;
542 status = "disabled";
543 };
544
545 i2c_4: i2c@138a0000 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "samsung,s3c2440-i2c";
549 reg = <0x138A0000 0x100>;
550 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clock CLK_I2C4>;
552 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c4_bus>;
555 status = "disabled";
556 };
557
558 i2c_5: i2c@138b0000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "samsung,s3c2440-i2c";
562 reg = <0x138B0000 0x100>;
563 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clock CLK_I2C5>;
565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c5_bus>;
568 status = "disabled";
569 };
570
571 i2c_6: i2c@138c0000 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x138C0000 0x100>;
576 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clock CLK_I2C6>;
578 clock-names = "i2c";
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c6_bus>;
581 status = "disabled";
582 };
583
584 i2c_7: i2c@138d0000 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "samsung,s3c2440-i2c";
588 reg = <0x138D0000 0x100>;
589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clock CLK_I2C7>;
591 clock-names = "i2c";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c7_bus>;
594 status = "disabled";
595 };
596
597 i2c_8: i2c@138e0000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "samsung,s3c2440-hdmiphy-i2c";
601 reg = <0x138E0000 0x100>;
602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clock CLK_I2C_HDMI>;
604 clock-names = "i2c";
605 status = "disabled";
606
607 hdmi_i2c_phy: hdmiphy@38 {
608 compatible = "exynos4210-hdmiphy";
609 reg = <0x38>;
610 };
611 };
612
613 spi_0: spi@13920000 {
614 compatible = "samsung,exynos4210-spi";
615 reg = <0x13920000 0x100>;
616 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
617 dmas = <&pdma0 7>, <&pdma0 6>;
618 dma-names = "tx", "rx";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
622 clock-names = "spi", "spi_busclk0";
623 pinctrl-names = "default";
624 pinctrl-0 = <&spi0_bus>;
625 status = "disabled";
626 };
627
628 spi_1: spi@13930000 {
629 compatible = "samsung,exynos4210-spi";
630 reg = <0x13930000 0x100>;
631 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
632 dmas = <&pdma1 7>, <&pdma1 6>;
633 dma-names = "tx", "rx";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
637 clock-names = "spi", "spi_busclk0";
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi1_bus>;
640 status = "disabled";
641 };
642
643 spi_2: spi@13940000 {
644 compatible = "samsung,exynos4210-spi";
645 reg = <0x13940000 0x100>;
646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
647 dmas = <&pdma0 9>, <&pdma0 8>;
648 dma-names = "tx", "rx";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
652 clock-names = "spi", "spi_busclk0";
653 pinctrl-names = "default";
654 pinctrl-0 = <&spi2_bus>;
655 status = "disabled";
656 };
657
658 pwm: pwm@139d0000 {
659 compatible = "samsung,exynos4210-pwm";
660 reg = <0x139D0000 0x1000>;
661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clock CLK_PWM>;
667 clock-names = "timers";
668 #pwm-cells = <3>;
669 status = "disabled";
670 };
671
672 amba: amba {
673 #address-cells = <1>;
674 #size-cells = <1>;
675 compatible = "simple-bus";
676 interrupt-parent = <&gic>;
677 ranges;
678
679 pdma0: pdma@12680000 {
680 compatible = "arm,pl330", "arm,primecell";
681 reg = <0x12680000 0x1000>;
682 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clock CLK_PDMA0>;
684 clock-names = "apb_pclk";
685 #dma-cells = <1>;
686 #dma-channels = <8>;
687 #dma-requests = <32>;
688 };
689
690 pdma1: pdma@12690000 {
691 compatible = "arm,pl330", "arm,primecell";
692 reg = <0x12690000 0x1000>;
693 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clock CLK_PDMA1>;
695 clock-names = "apb_pclk";
696 #dma-cells = <1>;
697 #dma-channels = <8>;
698 #dma-requests = <32>;
699 };
700
701 mdma1: mdma@12850000 {
702 compatible = "arm,pl330", "arm,primecell";
703 reg = <0x12850000 0x1000>;
704 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&clock CLK_MDMA>;
706 clock-names = "apb_pclk";
707 #dma-cells = <1>;
708 #dma-channels = <8>;
709 #dma-requests = <1>;
710 };
711 };
712
713 fimd: fimd@11c00000 {
714 compatible = "samsung,exynos4210-fimd";
715 interrupt-parent = <&combiner>;
716 reg = <0x11c00000 0x20000>;
717 interrupt-names = "fifo", "vsync", "lcd_sys";
718 interrupts = <11 0>, <11 1>, <11 2>;
719 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
720 clock-names = "sclk_fimd", "fimd";
721 power-domains = <&pd_lcd0>;
722 iommus = <&sysmmu_fimd0>;
723 samsung,sysreg = <&sys_reg>;
724 status = "disabled";
725 };
726
727 tmu: tmu@100c0000 {
728 interrupt-parent = <&combiner>;
729 reg = <0x100C0000 0x100>;
730 interrupts = <2 4>;
731 status = "disabled";
732 #thermal-sensor-cells = <0>;
733 };
734
735 jpeg_codec: jpeg-codec@11840000 {
736 compatible = "samsung,exynos4210-jpeg";
737 reg = <0x11840000 0x1000>;
738 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&clock CLK_JPEG>;
740 clock-names = "jpeg";
741 power-domains = <&pd_cam>;
742 iommus = <&sysmmu_jpeg>;
743 };
744
745 rotator: rotator@12810000 {
746 compatible = "samsung,exynos4210-rotator";
747 reg = <0x12810000 0x64>;
748 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&clock CLK_ROTATOR>;
750 clock-names = "rotator";
751 iommus = <&sysmmu_rotator>;
752 };
753
754 hdmi: hdmi@12d00000 {
755 compatible = "samsung,exynos4210-hdmi";
756 reg = <0x12D00000 0x70000>;
757 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
758 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
759 "sclk_hdmiphy", "mout_hdmi";
760 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
761 <&clock CLK_SCLK_PIXEL>,
762 <&clock CLK_SCLK_HDMIPHY>,
763 <&clock CLK_MOUT_HDMI>;
764 phy = <&hdmi_i2c_phy>;
765 power-domains = <&pd_tv>;
766 samsung,syscon-phandle = <&pmu_system_controller>;
767 #sound-dai-cells = <0>;
768 status = "disabled";
769 };
770
771 hdmicec: cec@100b0000 {
772 compatible = "samsung,s5p-cec";
773 reg = <0x100B0000 0x200>;
774 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clock CLK_HDMI_CEC>;
776 clock-names = "hdmicec";
777 samsung,syscon-phandle = <&pmu_system_controller>;
778 hdmi-phandle = <&hdmi>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&hdmi_cec>;
781 status = "disabled";
782 };
783
784 mixer: mixer@12c10000 {
785 compatible = "samsung,exynos4210-mixer";
786 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
787 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
788 power-domains = <&pd_tv>;
789 iommus = <&sysmmu_tv>;
790 status = "disabled";
791 };
792
793 ppmu_dmc0: ppmu_dmc0@106a0000 {
794 compatible = "samsung,exynos-ppmu";
795 reg = <0x106a0000 0x2000>;
796 clocks = <&clock CLK_PPMUDMC0>;
797 clock-names = "ppmu";
798 status = "disabled";
799 };
800
801 ppmu_dmc1: ppmu_dmc1@106b0000 {
802 compatible = "samsung,exynos-ppmu";
803 reg = <0x106b0000 0x2000>;
804 clocks = <&clock CLK_PPMUDMC1>;
805 clock-names = "ppmu";
806 status = "disabled";
807 };
808
809 ppmu_cpu: ppmu_cpu@106c0000 {
810 compatible = "samsung,exynos-ppmu";
811 reg = <0x106c0000 0x2000>;
812 clocks = <&clock CLK_PPMUCPU>;
813 clock-names = "ppmu";
814 status = "disabled";
815 };
816
817 ppmu_rightbus: ppmu_rightbus@112a0000 {
818 compatible = "samsung,exynos-ppmu";
819 reg = <0x112a0000 0x2000>;
820 clocks = <&clock CLK_PPMURIGHT>;
821 clock-names = "ppmu";
822 status = "disabled";
823 };
824
825 ppmu_leftbus: ppmu_leftbus0@116a0000 {
826 compatible = "samsung,exynos-ppmu";
827 reg = <0x116a0000 0x2000>;
828 clocks = <&clock CLK_PPMULEFT>;
829 clock-names = "ppmu";
830 status = "disabled";
831 };
832
833 ppmu_camif: ppmu_camif@11ac0000 {
834 compatible = "samsung,exynos-ppmu";
835 reg = <0x11ac0000 0x2000>;
836 clocks = <&clock CLK_PPMUCAMIF>;
837 clock-names = "ppmu";
838 status = "disabled";
839 };
840
841 ppmu_lcd0: ppmu_lcd0@11e40000 {
842 compatible = "samsung,exynos-ppmu";
843 reg = <0x11e40000 0x2000>;
844 clocks = <&clock CLK_PPMULCD0>;
845 clock-names = "ppmu";
846 status = "disabled";
847 };
848
849 ppmu_fsys: ppmu_g3d@12630000 {
850 compatible = "samsung,exynos-ppmu";
851 reg = <0x12630000 0x2000>;
852 status = "disabled";
853 };
854
855 ppmu_image: ppmu_image@12aa0000 {
856 compatible = "samsung,exynos-ppmu";
857 reg = <0x12aa0000 0x2000>;
858 clocks = <&clock CLK_PPMUIMAGE>;
859 clock-names = "ppmu";
860 status = "disabled";
861 };
862
863 ppmu_tv: ppmu_tv@12e40000 {
864 compatible = "samsung,exynos-ppmu";
865 reg = <0x12e40000 0x2000>;
866 clocks = <&clock CLK_PPMUTV>;
867 clock-names = "ppmu";
868 status = "disabled";
869 };
870
871 ppmu_g3d: ppmu_g3d@13220000 {
872 compatible = "samsung,exynos-ppmu";
873 reg = <0x13220000 0x2000>;
874 clocks = <&clock CLK_PPMUG3D>;
875 clock-names = "ppmu";
876 status = "disabled";
877 };
878
879 ppmu_mfc_left: ppmu_mfc_left@13660000 {
880 compatible = "samsung,exynos-ppmu";
881 reg = <0x13660000 0x2000>;
882 clocks = <&clock CLK_PPMUMFC_L>;
883 clock-names = "ppmu";
884 status = "disabled";
885 };
886
887 ppmu_mfc_right: ppmu_mfc_right@13670000 {
888 compatible = "samsung,exynos-ppmu";
889 reg = <0x13670000 0x2000>;
890 clocks = <&clock CLK_PPMUMFC_R>;
891 clock-names = "ppmu";
892 status = "disabled";
893 };
894
895 sysmmu_mfc_l: sysmmu@13620000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x13620000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 5>;
900 clock-names = "sysmmu", "master";
901 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
902 power-domains = <&pd_mfc>;
903 #iommu-cells = <0>;
904 };
905
906 sysmmu_mfc_r: sysmmu@13630000 {
907 compatible = "samsung,exynos-sysmmu";
908 reg = <0x13630000 0x1000>;
909 interrupt-parent = <&combiner>;
910 interrupts = <5 6>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
913 power-domains = <&pd_mfc>;
914 #iommu-cells = <0>;
915 };
916
917 sysmmu_tv: sysmmu@12e20000 {
918 compatible = "samsung,exynos-sysmmu";
919 reg = <0x12E20000 0x1000>;
920 interrupt-parent = <&combiner>;
921 interrupts = <5 4>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
924 power-domains = <&pd_tv>;
925 #iommu-cells = <0>;
926 };
927
928 sysmmu_fimc0: sysmmu@11a20000 {
929 compatible = "samsung,exynos-sysmmu";
930 reg = <0x11A20000 0x1000>;
931 interrupt-parent = <&combiner>;
932 interrupts = <4 2>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
935 power-domains = <&pd_cam>;
936 #iommu-cells = <0>;
937 };
938
939 sysmmu_fimc1: sysmmu@11a30000 {
940 compatible = "samsung,exynos-sysmmu";
941 reg = <0x11A30000 0x1000>;
942 interrupt-parent = <&combiner>;
943 interrupts = <4 3>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
946 power-domains = <&pd_cam>;
947 #iommu-cells = <0>;
948 };
949
950 sysmmu_fimc2: sysmmu@11a40000 {
951 compatible = "samsung,exynos-sysmmu";
952 reg = <0x11A40000 0x1000>;
953 interrupt-parent = <&combiner>;
954 interrupts = <4 4>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
957 power-domains = <&pd_cam>;
958 #iommu-cells = <0>;
959 };
960
961 sysmmu_fimc3: sysmmu@11a50000 {
962 compatible = "samsung,exynos-sysmmu";
963 reg = <0x11A50000 0x1000>;
964 interrupt-parent = <&combiner>;
965 interrupts = <4 5>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
968 power-domains = <&pd_cam>;
969 #iommu-cells = <0>;
970 };
971
972 sysmmu_jpeg: sysmmu@11a60000 {
973 compatible = "samsung,exynos-sysmmu";
974 reg = <0x11A60000 0x1000>;
975 interrupt-parent = <&combiner>;
976 interrupts = <4 6>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
979 power-domains = <&pd_cam>;
980 #iommu-cells = <0>;
981 };
982
983 sysmmu_rotator: sysmmu@12a30000 {
984 compatible = "samsung,exynos-sysmmu";
985 reg = <0x12A30000 0x1000>;
986 interrupt-parent = <&combiner>;
987 interrupts = <5 0>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_ROTATOR>,
990 <&clock CLK_ROTATOR>;
991 #iommu-cells = <0>;
992 };
993
994 sysmmu_fimd0: sysmmu@11e20000 {
995 compatible = "samsung,exynos-sysmmu";
996 reg = <0x11E20000 0x1000>;
997 interrupt-parent = <&combiner>;
998 interrupts = <5 2>;
999 clock-names = "sysmmu", "master";
1000 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
1001 power-domains = <&pd_lcd0>;
1002 #iommu-cells = <0>;
1003 };
1004
1005 sss: sss@10830000 {
1006 compatible = "samsung,exynos4210-secss";
1007 reg = <0x10830000 0x300>;
1008 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clock CLK_SSS>;
1010 clock-names = "secss";
1011 };
1012
1013 prng: rng@10830400 {
1014 compatible = "samsung,exynos4-rng";
1015 reg = <0x10830400 0x200>;
1016 clocks = <&clock CLK_SSS>;
1017 clock-names = "secss";
1018 };
1019 };
1020};
1021
1022#include "exynos-syscon-restart.dtsi"