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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
4 */
5
6#if defined(CONFIG_SERIAL_SPRD_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7#define SUPPORT_SYSRQ
8#endif
9
10#include <linux/clk.h>
11#include <linux/console.h>
12#include <linux/delay.h>
13#include <linux/dmaengine.h>
14#include <linux/dma-mapping.h>
15#include <linux/dma/sprd-dma.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/serial.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27
28/* device name */
29#define UART_NR_MAX 8
30#define SPRD_TTY_NAME "ttyS"
31#define SPRD_FIFO_SIZE 128
32#define SPRD_DEF_RATE 26000000
33#define SPRD_BAUD_IO_LIMIT 3000000
34#define SPRD_TIMEOUT 256000
35
36/* the offset of serial registers and BITs for them */
37/* data registers */
38#define SPRD_TXD 0x0000
39#define SPRD_RXD 0x0004
40
41/* line status register and its BITs */
42#define SPRD_LSR 0x0008
43#define SPRD_LSR_OE BIT(4)
44#define SPRD_LSR_FE BIT(3)
45#define SPRD_LSR_PE BIT(2)
46#define SPRD_LSR_BI BIT(7)
47#define SPRD_LSR_TX_OVER BIT(15)
48
49/* data number in TX and RX fifo */
50#define SPRD_STS1 0x000C
51#define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
52#define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
53
54/* interrupt enable register and its BITs */
55#define SPRD_IEN 0x0010
56#define SPRD_IEN_RX_FULL BIT(0)
57#define SPRD_IEN_TX_EMPTY BIT(1)
58#define SPRD_IEN_BREAK_DETECT BIT(7)
59#define SPRD_IEN_TIMEOUT BIT(13)
60
61/* interrupt clear register */
62#define SPRD_ICLR 0x0014
63#define SPRD_ICLR_TIMEOUT BIT(13)
64
65/* line control register */
66#define SPRD_LCR 0x0018
67#define SPRD_LCR_STOP_1BIT 0x10
68#define SPRD_LCR_STOP_2BIT 0x30
69#define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
70#define SPRD_LCR_DATA_LEN5 0x0
71#define SPRD_LCR_DATA_LEN6 0x4
72#define SPRD_LCR_DATA_LEN7 0x8
73#define SPRD_LCR_DATA_LEN8 0xc
74#define SPRD_LCR_PARITY (BIT(0) | BIT(1))
75#define SPRD_LCR_PARITY_EN 0x2
76#define SPRD_LCR_EVEN_PAR 0x0
77#define SPRD_LCR_ODD_PAR 0x1
78
79/* control register 1 */
80#define SPRD_CTL1 0x001C
81#define SPRD_DMA_EN BIT(15)
82#define SPRD_LOOPBACK_EN BIT(14)
83#define RX_HW_FLOW_CTL_THLD BIT(6)
84#define RX_HW_FLOW_CTL_EN BIT(7)
85#define TX_HW_FLOW_CTL_EN BIT(8)
86#define RX_TOUT_THLD_DEF 0x3E00
87#define RX_HFC_THLD_DEF 0x40
88
89/* fifo threshold register */
90#define SPRD_CTL2 0x0020
91#define THLD_TX_EMPTY 0x40
92#define THLD_TX_EMPTY_SHIFT 8
93#define THLD_RX_FULL 0x40
94#define THLD_RX_FULL_MASK GENMASK(6, 0)
95
96/* config baud rate register */
97#define SPRD_CLKD0 0x0024
98#define SPRD_CLKD0_MASK GENMASK(15, 0)
99#define SPRD_CLKD1 0x0028
100#define SPRD_CLKD1_MASK GENMASK(20, 16)
101#define SPRD_CLKD1_SHIFT 16
102
103/* interrupt mask status register */
104#define SPRD_IMSR 0x002C
105#define SPRD_IMSR_RX_FIFO_FULL BIT(0)
106#define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
107#define SPRD_IMSR_BREAK_DETECT BIT(7)
108#define SPRD_IMSR_TIMEOUT BIT(13)
109#define SPRD_DEFAULT_SOURCE_CLK 26000000
110
111#define SPRD_RX_DMA_STEP 1
112#define SPRD_RX_FIFO_FULL 1
113#define SPRD_TX_FIFO_FULL 0x20
114#define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
115
116struct sprd_uart_dma {
117 struct dma_chan *chn;
118 unsigned char *virt;
119 dma_addr_t phys_addr;
120 dma_cookie_t cookie;
121 u32 trans_len;
122 bool enable;
123};
124
125struct sprd_uart_port {
126 struct uart_port port;
127 char name[16];
128 struct clk *clk;
129 struct sprd_uart_dma tx_dma;
130 struct sprd_uart_dma rx_dma;
131 dma_addr_t pos;
132 unsigned char *rx_buf_tail;
133};
134
135static struct sprd_uart_port *sprd_port[UART_NR_MAX];
136static int sprd_ports_num;
137
138static int sprd_start_dma_rx(struct uart_port *port);
139static int sprd_tx_dma_config(struct uart_port *port);
140
141static inline unsigned int serial_in(struct uart_port *port,
142 unsigned int offset)
143{
144 return readl_relaxed(port->membase + offset);
145}
146
147static inline void serial_out(struct uart_port *port, unsigned int offset,
148 int value)
149{
150 writel_relaxed(value, port->membase + offset);
151}
152
153static unsigned int sprd_tx_empty(struct uart_port *port)
154{
155 if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
156 return 0;
157 else
158 return TIOCSER_TEMT;
159}
160
161static unsigned int sprd_get_mctrl(struct uart_port *port)
162{
163 return TIOCM_DSR | TIOCM_CTS;
164}
165
166static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
167{
168 u32 val = serial_in(port, SPRD_CTL1);
169
170 if (mctrl & TIOCM_LOOP)
171 val |= SPRD_LOOPBACK_EN;
172 else
173 val &= ~SPRD_LOOPBACK_EN;
174
175 serial_out(port, SPRD_CTL1, val);
176}
177
178static void sprd_stop_rx(struct uart_port *port)
179{
180 struct sprd_uart_port *sp =
181 container_of(port, struct sprd_uart_port, port);
182 unsigned int ien, iclr;
183
184 if (sp->rx_dma.enable)
185 dmaengine_terminate_all(sp->rx_dma.chn);
186
187 iclr = serial_in(port, SPRD_ICLR);
188 ien = serial_in(port, SPRD_IEN);
189
190 ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
191 iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
192
193 serial_out(port, SPRD_IEN, ien);
194 serial_out(port, SPRD_ICLR, iclr);
195}
196
197static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
198{
199 u32 val = serial_in(port, SPRD_CTL1);
200
201 if (enable)
202 val |= SPRD_DMA_EN;
203 else
204 val &= ~SPRD_DMA_EN;
205
206 serial_out(port, SPRD_CTL1, val);
207}
208
209static void sprd_stop_tx_dma(struct uart_port *port)
210{
211 struct sprd_uart_port *sp =
212 container_of(port, struct sprd_uart_port, port);
213 struct circ_buf *xmit = &port->state->xmit;
214 struct dma_tx_state state;
215 u32 trans_len;
216
217 dmaengine_pause(sp->tx_dma.chn);
218
219 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
220 if (state.residue) {
221 trans_len = state.residue - sp->tx_dma.phys_addr;
222 xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1);
223 port->icount.tx += trans_len;
224 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
225 sp->tx_dma.trans_len, DMA_TO_DEVICE);
226 }
227
228 dmaengine_terminate_all(sp->tx_dma.chn);
229 sp->tx_dma.trans_len = 0;
230}
231
232static int sprd_tx_buf_remap(struct uart_port *port)
233{
234 struct sprd_uart_port *sp =
235 container_of(port, struct sprd_uart_port, port);
236 struct circ_buf *xmit = &port->state->xmit;
237
238 sp->tx_dma.trans_len =
239 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
240
241 sp->tx_dma.phys_addr = dma_map_single(port->dev,
242 (void *)&(xmit->buf[xmit->tail]),
243 sp->tx_dma.trans_len,
244 DMA_TO_DEVICE);
245 return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
246}
247
248static void sprd_complete_tx_dma(void *data)
249{
250 struct uart_port *port = (struct uart_port *)data;
251 struct sprd_uart_port *sp =
252 container_of(port, struct sprd_uart_port, port);
253 struct circ_buf *xmit = &port->state->xmit;
254 unsigned long flags;
255
256 spin_lock_irqsave(&port->lock, flags);
257 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
258 sp->tx_dma.trans_len, DMA_TO_DEVICE);
259
260 xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1);
261 port->icount.tx += sp->tx_dma.trans_len;
262
263 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
264 uart_write_wakeup(port);
265
266 if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
267 sprd_tx_dma_config(port))
268 sp->tx_dma.trans_len = 0;
269
270 spin_unlock_irqrestore(&port->lock, flags);
271}
272
273static int sprd_uart_dma_submit(struct uart_port *port,
274 struct sprd_uart_dma *ud, u32 trans_len,
275 enum dma_transfer_direction direction,
276 dma_async_tx_callback callback)
277{
278 struct dma_async_tx_descriptor *dma_des;
279 unsigned long flags;
280
281 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
282 SPRD_DMA_NO_TRG,
283 SPRD_DMA_FRAG_REQ,
284 SPRD_DMA_TRANS_INT);
285
286 dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
287 direction, flags);
288 if (!dma_des)
289 return -ENODEV;
290
291 dma_des->callback = callback;
292 dma_des->callback_param = port;
293
294 ud->cookie = dmaengine_submit(dma_des);
295 if (dma_submit_error(ud->cookie))
296 return dma_submit_error(ud->cookie);
297
298 dma_async_issue_pending(ud->chn);
299
300 return 0;
301}
302
303static int sprd_tx_dma_config(struct uart_port *port)
304{
305 struct sprd_uart_port *sp =
306 container_of(port, struct sprd_uart_port, port);
307 u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
308 SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
309 int ret;
310 struct dma_slave_config cfg = {
311 .dst_addr = port->mapbase + SPRD_TXD,
312 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
313 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
314 .src_maxburst = burst,
315 };
316
317 ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
318 if (ret < 0)
319 return ret;
320
321 return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
322 DMA_MEM_TO_DEV, sprd_complete_tx_dma);
323}
324
325static void sprd_start_tx_dma(struct uart_port *port)
326{
327 struct sprd_uart_port *sp =
328 container_of(port, struct sprd_uart_port, port);
329 struct circ_buf *xmit = &port->state->xmit;
330
331 if (port->x_char) {
332 serial_out(port, SPRD_TXD, port->x_char);
333 port->icount.tx++;
334 port->x_char = 0;
335 return;
336 }
337
338 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
339 sprd_stop_tx_dma(port);
340 return;
341 }
342
343 if (sp->tx_dma.trans_len)
344 return;
345
346 if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
347 sp->tx_dma.trans_len = 0;
348}
349
350static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
351{
352 u32 val = serial_in(port, SPRD_CTL2);
353
354 val &= ~THLD_RX_FULL_MASK;
355 val |= thld & THLD_RX_FULL_MASK;
356 serial_out(port, SPRD_CTL2, val);
357}
358
359static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
360{
361 sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
362 &sp->rx_dma.phys_addr, GFP_KERNEL);
363 if (!sp->rx_dma.virt)
364 return -ENOMEM;
365
366 return 0;
367}
368
369static void sprd_rx_free_buf(struct sprd_uart_port *sp)
370{
371 if (sp->rx_dma.virt)
372 dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
373 sp->rx_dma.virt, sp->rx_dma.phys_addr);
374
375}
376
377static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
378{
379 struct sprd_uart_port *sp =
380 container_of(port, struct sprd_uart_port, port);
381 struct dma_slave_config cfg = {
382 .src_addr = port->mapbase + SPRD_RXD,
383 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
384 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
385 .src_maxburst = burst,
386 };
387
388 return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
389}
390
391static void sprd_uart_dma_rx(struct uart_port *port)
392{
393 struct sprd_uart_port *sp =
394 container_of(port, struct sprd_uart_port, port);
395 struct tty_port *tty = &port->state->port;
396
397 port->icount.rx += sp->rx_dma.trans_len;
398 tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
399 tty_flip_buffer_push(tty);
400}
401
402static void sprd_uart_dma_irq(struct uart_port *port)
403{
404 struct sprd_uart_port *sp =
405 container_of(port, struct sprd_uart_port, port);
406 struct dma_tx_state state;
407 enum dma_status status;
408
409 status = dmaengine_tx_status(sp->rx_dma.chn,
410 sp->rx_dma.cookie, &state);
411 if (status == DMA_ERROR)
412 sprd_stop_rx(port);
413
414 if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
415 return;
416
417 if (!state.residue) {
418 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
419 sp->rx_dma.phys_addr - sp->pos;
420 sp->pos = sp->rx_dma.phys_addr;
421 } else {
422 sp->rx_dma.trans_len = state.residue - sp->pos;
423 sp->pos = state.residue;
424 }
425
426 sprd_uart_dma_rx(port);
427 sp->rx_buf_tail += sp->rx_dma.trans_len;
428}
429
430static void sprd_complete_rx_dma(void *data)
431{
432 struct uart_port *port = (struct uart_port *)data;
433 struct sprd_uart_port *sp =
434 container_of(port, struct sprd_uart_port, port);
435 struct dma_tx_state state;
436 enum dma_status status;
437 unsigned long flags;
438
439 spin_lock_irqsave(&port->lock, flags);
440
441 status = dmaengine_tx_status(sp->rx_dma.chn,
442 sp->rx_dma.cookie, &state);
443 if (status != DMA_COMPLETE) {
444 sprd_stop_rx(port);
445 spin_unlock_irqrestore(&port->lock, flags);
446 return;
447 }
448
449 if (sp->pos != sp->rx_dma.phys_addr) {
450 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
451 sp->rx_dma.phys_addr - sp->pos;
452 sprd_uart_dma_rx(port);
453 sp->rx_buf_tail += sp->rx_dma.trans_len;
454 }
455
456 if (sprd_start_dma_rx(port))
457 sprd_stop_rx(port);
458
459 spin_unlock_irqrestore(&port->lock, flags);
460}
461
462static int sprd_start_dma_rx(struct uart_port *port)
463{
464 struct sprd_uart_port *sp =
465 container_of(port, struct sprd_uart_port, port);
466 int ret;
467
468 if (!sp->rx_dma.enable)
469 return 0;
470
471 sp->pos = sp->rx_dma.phys_addr;
472 sp->rx_buf_tail = sp->rx_dma.virt;
473 sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
474 ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
475 if (ret)
476 return ret;
477
478 return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
479 DMA_DEV_TO_MEM, sprd_complete_rx_dma);
480}
481
482static void sprd_release_dma(struct uart_port *port)
483{
484 struct sprd_uart_port *sp =
485 container_of(port, struct sprd_uart_port, port);
486
487 sprd_uart_dma_enable(port, false);
488
489 if (sp->rx_dma.enable)
490 dma_release_channel(sp->rx_dma.chn);
491
492 if (sp->tx_dma.enable)
493 dma_release_channel(sp->tx_dma.chn);
494
495 sp->tx_dma.enable = false;
496 sp->rx_dma.enable = false;
497}
498
499static void sprd_request_dma(struct uart_port *port)
500{
501 struct sprd_uart_port *sp =
502 container_of(port, struct sprd_uart_port, port);
503
504 sp->tx_dma.enable = true;
505 sp->rx_dma.enable = true;
506
507 sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
508 if (IS_ERR(sp->tx_dma.chn)) {
509 dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
510 PTR_ERR(sp->tx_dma.chn));
511 sp->tx_dma.enable = false;
512 }
513
514 sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
515 if (IS_ERR(sp->rx_dma.chn)) {
516 dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
517 PTR_ERR(sp->rx_dma.chn));
518 sp->rx_dma.enable = false;
519 }
520}
521
522static void sprd_stop_tx(struct uart_port *port)
523{
524 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
525 port);
526 unsigned int ien, iclr;
527
528 if (sp->tx_dma.enable) {
529 sprd_stop_tx_dma(port);
530 return;
531 }
532
533 iclr = serial_in(port, SPRD_ICLR);
534 ien = serial_in(port, SPRD_IEN);
535
536 iclr |= SPRD_IEN_TX_EMPTY;
537 ien &= ~SPRD_IEN_TX_EMPTY;
538
539 serial_out(port, SPRD_IEN, ien);
540 serial_out(port, SPRD_ICLR, iclr);
541}
542
543static void sprd_start_tx(struct uart_port *port)
544{
545 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
546 port);
547 unsigned int ien;
548
549 if (sp->tx_dma.enable) {
550 sprd_start_tx_dma(port);
551 return;
552 }
553
554 ien = serial_in(port, SPRD_IEN);
555 if (!(ien & SPRD_IEN_TX_EMPTY)) {
556 ien |= SPRD_IEN_TX_EMPTY;
557 serial_out(port, SPRD_IEN, ien);
558 }
559}
560
561/* The Sprd serial does not support this function. */
562static void sprd_break_ctl(struct uart_port *port, int break_state)
563{
564 /* nothing to do */
565}
566
567static int handle_lsr_errors(struct uart_port *port,
568 unsigned int *flag,
569 unsigned int *lsr)
570{
571 int ret = 0;
572
573 /* statistics */
574 if (*lsr & SPRD_LSR_BI) {
575 *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
576 port->icount.brk++;
577 ret = uart_handle_break(port);
578 if (ret)
579 return ret;
580 } else if (*lsr & SPRD_LSR_PE)
581 port->icount.parity++;
582 else if (*lsr & SPRD_LSR_FE)
583 port->icount.frame++;
584 if (*lsr & SPRD_LSR_OE)
585 port->icount.overrun++;
586
587 /* mask off conditions which should be ignored */
588 *lsr &= port->read_status_mask;
589 if (*lsr & SPRD_LSR_BI)
590 *flag = TTY_BREAK;
591 else if (*lsr & SPRD_LSR_PE)
592 *flag = TTY_PARITY;
593 else if (*lsr & SPRD_LSR_FE)
594 *flag = TTY_FRAME;
595
596 return ret;
597}
598
599static inline void sprd_rx(struct uart_port *port)
600{
601 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
602 port);
603 struct tty_port *tty = &port->state->port;
604 unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
605
606 if (sp->rx_dma.enable) {
607 sprd_uart_dma_irq(port);
608 return;
609 }
610
611 while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
612 max_count--) {
613 lsr = serial_in(port, SPRD_LSR);
614 ch = serial_in(port, SPRD_RXD);
615 flag = TTY_NORMAL;
616 port->icount.rx++;
617
618 if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
619 SPRD_LSR_FE | SPRD_LSR_OE))
620 if (handle_lsr_errors(port, &flag, &lsr))
621 continue;
622 if (uart_handle_sysrq_char(port, ch))
623 continue;
624
625 uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
626 }
627
628 tty_flip_buffer_push(tty);
629}
630
631static inline void sprd_tx(struct uart_port *port)
632{
633 struct circ_buf *xmit = &port->state->xmit;
634 int count;
635
636 if (port->x_char) {
637 serial_out(port, SPRD_TXD, port->x_char);
638 port->icount.tx++;
639 port->x_char = 0;
640 return;
641 }
642
643 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
644 sprd_stop_tx(port);
645 return;
646 }
647
648 count = THLD_TX_EMPTY;
649 do {
650 serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]);
651 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
652 port->icount.tx++;
653 if (uart_circ_empty(xmit))
654 break;
655 } while (--count > 0);
656
657 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
658 uart_write_wakeup(port);
659
660 if (uart_circ_empty(xmit))
661 sprd_stop_tx(port);
662}
663
664/* this handles the interrupt from one port */
665static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
666{
667 struct uart_port *port = dev_id;
668 unsigned int ims;
669
670 spin_lock(&port->lock);
671
672 ims = serial_in(port, SPRD_IMSR);
673
674 if (!ims) {
675 spin_unlock(&port->lock);
676 return IRQ_NONE;
677 }
678
679 if (ims & SPRD_IMSR_TIMEOUT)
680 serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
681
682 if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
683 SPRD_IMSR_TIMEOUT))
684 sprd_rx(port);
685
686 if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
687 sprd_tx(port);
688
689 spin_unlock(&port->lock);
690
691 return IRQ_HANDLED;
692}
693
694static void sprd_uart_dma_startup(struct uart_port *port,
695 struct sprd_uart_port *sp)
696{
697 int ret;
698
699 sprd_request_dma(port);
700 if (!(sp->rx_dma.enable || sp->tx_dma.enable))
701 return;
702
703 ret = sprd_start_dma_rx(port);
704 if (ret) {
705 sp->rx_dma.enable = false;
706 dma_release_channel(sp->rx_dma.chn);
707 dev_warn(port->dev, "fail to start RX dma mode\n");
708 }
709
710 sprd_uart_dma_enable(port, true);
711}
712
713static int sprd_startup(struct uart_port *port)
714{
715 int ret = 0;
716 unsigned int ien, fc;
717 unsigned int timeout;
718 struct sprd_uart_port *sp;
719 unsigned long flags;
720
721 serial_out(port, SPRD_CTL2,
722 THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
723
724 /* clear rx fifo */
725 timeout = SPRD_TIMEOUT;
726 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
727 serial_in(port, SPRD_RXD);
728
729 /* clear tx fifo */
730 timeout = SPRD_TIMEOUT;
731 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
732 cpu_relax();
733
734 /* clear interrupt */
735 serial_out(port, SPRD_IEN, 0);
736 serial_out(port, SPRD_ICLR, ~0);
737
738 /* allocate irq */
739 sp = container_of(port, struct sprd_uart_port, port);
740 snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
741
742 sprd_uart_dma_startup(port, sp);
743
744 ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
745 IRQF_SHARED, sp->name, port);
746 if (ret) {
747 dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
748 port->irq, ret);
749 return ret;
750 }
751 fc = serial_in(port, SPRD_CTL1);
752 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
753 serial_out(port, SPRD_CTL1, fc);
754
755 /* enable interrupt */
756 spin_lock_irqsave(&port->lock, flags);
757 ien = serial_in(port, SPRD_IEN);
758 ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
759 if (!sp->rx_dma.enable)
760 ien |= SPRD_IEN_RX_FULL;
761 serial_out(port, SPRD_IEN, ien);
762 spin_unlock_irqrestore(&port->lock, flags);
763
764 return 0;
765}
766
767static void sprd_shutdown(struct uart_port *port)
768{
769 sprd_release_dma(port);
770 serial_out(port, SPRD_IEN, 0);
771 serial_out(port, SPRD_ICLR, ~0);
772 devm_free_irq(port->dev, port->irq, port);
773}
774
775static void sprd_set_termios(struct uart_port *port,
776 struct ktermios *termios,
777 struct ktermios *old)
778{
779 unsigned int baud, quot;
780 unsigned int lcr = 0, fc;
781 unsigned long flags;
782
783 /* ask the core to calculate the divisor for us */
784 baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
785
786 quot = port->uartclk / baud;
787
788 /* set data length */
789 switch (termios->c_cflag & CSIZE) {
790 case CS5:
791 lcr |= SPRD_LCR_DATA_LEN5;
792 break;
793 case CS6:
794 lcr |= SPRD_LCR_DATA_LEN6;
795 break;
796 case CS7:
797 lcr |= SPRD_LCR_DATA_LEN7;
798 break;
799 case CS8:
800 default:
801 lcr |= SPRD_LCR_DATA_LEN8;
802 break;
803 }
804
805 /* calculate stop bits */
806 lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
807 if (termios->c_cflag & CSTOPB)
808 lcr |= SPRD_LCR_STOP_2BIT;
809 else
810 lcr |= SPRD_LCR_STOP_1BIT;
811
812 /* calculate parity */
813 lcr &= ~SPRD_LCR_PARITY;
814 termios->c_cflag &= ~CMSPAR; /* no support mark/space */
815 if (termios->c_cflag & PARENB) {
816 lcr |= SPRD_LCR_PARITY_EN;
817 if (termios->c_cflag & PARODD)
818 lcr |= SPRD_LCR_ODD_PAR;
819 else
820 lcr |= SPRD_LCR_EVEN_PAR;
821 }
822
823 spin_lock_irqsave(&port->lock, flags);
824
825 /* update the per-port timeout */
826 uart_update_timeout(port, termios->c_cflag, baud);
827
828 port->read_status_mask = SPRD_LSR_OE;
829 if (termios->c_iflag & INPCK)
830 port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
831 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
832 port->read_status_mask |= SPRD_LSR_BI;
833
834 /* characters to ignore */
835 port->ignore_status_mask = 0;
836 if (termios->c_iflag & IGNPAR)
837 port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
838 if (termios->c_iflag & IGNBRK) {
839 port->ignore_status_mask |= SPRD_LSR_BI;
840 /*
841 * If we're ignoring parity and break indicators,
842 * ignore overruns too (for real raw support).
843 */
844 if (termios->c_iflag & IGNPAR)
845 port->ignore_status_mask |= SPRD_LSR_OE;
846 }
847
848 /* flow control */
849 fc = serial_in(port, SPRD_CTL1);
850 fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
851 if (termios->c_cflag & CRTSCTS) {
852 fc |= RX_HW_FLOW_CTL_THLD;
853 fc |= RX_HW_FLOW_CTL_EN;
854 fc |= TX_HW_FLOW_CTL_EN;
855 }
856
857 /* clock divider bit0~bit15 */
858 serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
859
860 /* clock divider bit16~bit20 */
861 serial_out(port, SPRD_CLKD1,
862 (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
863 serial_out(port, SPRD_LCR, lcr);
864 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
865 serial_out(port, SPRD_CTL1, fc);
866
867 spin_unlock_irqrestore(&port->lock, flags);
868
869 /* Don't rewrite B0 */
870 if (tty_termios_baud_rate(termios))
871 tty_termios_encode_baud_rate(termios, baud, baud);
872}
873
874static const char *sprd_type(struct uart_port *port)
875{
876 return "SPX";
877}
878
879static void sprd_release_port(struct uart_port *port)
880{
881 /* nothing to do */
882}
883
884static int sprd_request_port(struct uart_port *port)
885{
886 return 0;
887}
888
889static void sprd_config_port(struct uart_port *port, int flags)
890{
891 if (flags & UART_CONFIG_TYPE)
892 port->type = PORT_SPRD;
893}
894
895static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
896{
897 if (ser->type != PORT_SPRD)
898 return -EINVAL;
899 if (port->irq != ser->irq)
900 return -EINVAL;
901 if (port->iotype != ser->io_type)
902 return -EINVAL;
903 return 0;
904}
905
906static void sprd_pm(struct uart_port *port, unsigned int state,
907 unsigned int oldstate)
908{
909 struct sprd_uart_port *sup =
910 container_of(port, struct sprd_uart_port, port);
911
912 switch (state) {
913 case UART_PM_STATE_ON:
914 clk_prepare_enable(sup->clk);
915 break;
916 case UART_PM_STATE_OFF:
917 clk_disable_unprepare(sup->clk);
918 break;
919 }
920}
921
922static const struct uart_ops serial_sprd_ops = {
923 .tx_empty = sprd_tx_empty,
924 .get_mctrl = sprd_get_mctrl,
925 .set_mctrl = sprd_set_mctrl,
926 .stop_tx = sprd_stop_tx,
927 .start_tx = sprd_start_tx,
928 .stop_rx = sprd_stop_rx,
929 .break_ctl = sprd_break_ctl,
930 .startup = sprd_startup,
931 .shutdown = sprd_shutdown,
932 .set_termios = sprd_set_termios,
933 .type = sprd_type,
934 .release_port = sprd_release_port,
935 .request_port = sprd_request_port,
936 .config_port = sprd_config_port,
937 .verify_port = sprd_verify_port,
938 .pm = sprd_pm,
939};
940
941#ifdef CONFIG_SERIAL_SPRD_CONSOLE
942static void wait_for_xmitr(struct uart_port *port)
943{
944 unsigned int status, tmout = 10000;
945
946 /* wait up to 10ms for the character(s) to be sent */
947 do {
948 status = serial_in(port, SPRD_STS1);
949 if (--tmout == 0)
950 break;
951 udelay(1);
952 } while (status & SPRD_TX_FIFO_CNT_MASK);
953}
954
955static void sprd_console_putchar(struct uart_port *port, int ch)
956{
957 wait_for_xmitr(port);
958 serial_out(port, SPRD_TXD, ch);
959}
960
961static void sprd_console_write(struct console *co, const char *s,
962 unsigned int count)
963{
964 struct uart_port *port = &sprd_port[co->index]->port;
965 int locked = 1;
966 unsigned long flags;
967
968 if (port->sysrq)
969 locked = 0;
970 else if (oops_in_progress)
971 locked = spin_trylock_irqsave(&port->lock, flags);
972 else
973 spin_lock_irqsave(&port->lock, flags);
974
975 uart_console_write(port, s, count, sprd_console_putchar);
976
977 /* wait for transmitter to become empty */
978 wait_for_xmitr(port);
979
980 if (locked)
981 spin_unlock_irqrestore(&port->lock, flags);
982}
983
984static int __init sprd_console_setup(struct console *co, char *options)
985{
986 struct sprd_uart_port *sprd_uart_port;
987 int baud = 115200;
988 int bits = 8;
989 int parity = 'n';
990 int flow = 'n';
991
992 if (co->index >= UART_NR_MAX || co->index < 0)
993 co->index = 0;
994
995 sprd_uart_port = sprd_port[co->index];
996 if (!sprd_uart_port || !sprd_uart_port->port.membase) {
997 pr_info("serial port %d not yet initialized\n", co->index);
998 return -ENODEV;
999 }
1000
1001 if (options)
1002 uart_parse_options(options, &baud, &parity, &bits, &flow);
1003
1004 return uart_set_options(&sprd_uart_port->port, co, baud,
1005 parity, bits, flow);
1006}
1007
1008static struct uart_driver sprd_uart_driver;
1009static struct console sprd_console = {
1010 .name = SPRD_TTY_NAME,
1011 .write = sprd_console_write,
1012 .device = uart_console_device,
1013 .setup = sprd_console_setup,
1014 .flags = CON_PRINTBUFFER,
1015 .index = -1,
1016 .data = &sprd_uart_driver,
1017};
1018
1019static int __init sprd_serial_console_init(void)
1020{
1021 register_console(&sprd_console);
1022 return 0;
1023}
1024console_initcall(sprd_serial_console_init);
1025
1026#define SPRD_CONSOLE (&sprd_console)
1027
1028/* Support for earlycon */
1029static void sprd_putc(struct uart_port *port, int c)
1030{
1031 unsigned int timeout = SPRD_TIMEOUT;
1032
1033 while (timeout-- &&
1034 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
1035 cpu_relax();
1036
1037 writeb(c, port->membase + SPRD_TXD);
1038}
1039
1040static void sprd_early_write(struct console *con, const char *s, unsigned int n)
1041{
1042 struct earlycon_device *dev = con->data;
1043
1044 uart_console_write(&dev->port, s, n, sprd_putc);
1045}
1046
1047static int __init sprd_early_console_setup(struct earlycon_device *device,
1048 const char *opt)
1049{
1050 if (!device->port.membase)
1051 return -ENODEV;
1052
1053 device->con->write = sprd_early_write;
1054 return 0;
1055}
1056OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
1057 sprd_early_console_setup);
1058
1059#else /* !CONFIG_SERIAL_SPRD_CONSOLE */
1060#define SPRD_CONSOLE NULL
1061#endif
1062
1063static struct uart_driver sprd_uart_driver = {
1064 .owner = THIS_MODULE,
1065 .driver_name = "sprd_serial",
1066 .dev_name = SPRD_TTY_NAME,
1067 .major = 0,
1068 .minor = 0,
1069 .nr = UART_NR_MAX,
1070 .cons = SPRD_CONSOLE,
1071};
1072
1073static int sprd_probe_dt_alias(int index, struct device *dev)
1074{
1075 struct device_node *np;
1076 int ret = index;
1077
1078 if (!IS_ENABLED(CONFIG_OF))
1079 return ret;
1080
1081 np = dev->of_node;
1082 if (!np)
1083 return ret;
1084
1085 ret = of_alias_get_id(np, "serial");
1086 if (ret < 0)
1087 ret = index;
1088 else if (ret >= ARRAY_SIZE(sprd_port) || sprd_port[ret] != NULL) {
1089 dev_warn(dev, "requested serial port %d not available.\n", ret);
1090 ret = index;
1091 }
1092
1093 return ret;
1094}
1095
1096static int sprd_remove(struct platform_device *dev)
1097{
1098 struct sprd_uart_port *sup = platform_get_drvdata(dev);
1099
1100 if (sup) {
1101 uart_remove_one_port(&sprd_uart_driver, &sup->port);
1102 sprd_port[sup->port.line] = NULL;
1103 sprd_ports_num--;
1104 }
1105
1106 if (!sprd_ports_num)
1107 uart_unregister_driver(&sprd_uart_driver);
1108
1109 sprd_rx_free_buf(sup);
1110
1111 return 0;
1112}
1113
1114static bool sprd_uart_is_console(struct uart_port *uport)
1115{
1116 struct console *cons = sprd_uart_driver.cons;
1117
1118 if (cons && cons->index >= 0 && cons->index == uport->line)
1119 return true;
1120
1121 return false;
1122}
1123
1124static int sprd_clk_init(struct uart_port *uport)
1125{
1126 struct clk *clk_uart, *clk_parent;
1127 struct sprd_uart_port *u = sprd_port[uport->line];
1128
1129 clk_uart = devm_clk_get(uport->dev, "uart");
1130 if (IS_ERR(clk_uart)) {
1131 dev_warn(uport->dev, "uart%d can't get uart clock\n",
1132 uport->line);
1133 clk_uart = NULL;
1134 }
1135
1136 clk_parent = devm_clk_get(uport->dev, "source");
1137 if (IS_ERR(clk_parent)) {
1138 dev_warn(uport->dev, "uart%d can't get source clock\n",
1139 uport->line);
1140 clk_parent = NULL;
1141 }
1142
1143 if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
1144 uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
1145 else
1146 uport->uartclk = clk_get_rate(clk_uart);
1147
1148 u->clk = devm_clk_get(uport->dev, "enable");
1149 if (IS_ERR(u->clk)) {
1150 if (PTR_ERR(u->clk) == -EPROBE_DEFER)
1151 return -EPROBE_DEFER;
1152
1153 dev_warn(uport->dev, "uart%d can't get enable clock\n",
1154 uport->line);
1155
1156 /* To keep console alive even if the error occurred */
1157 if (!sprd_uart_is_console(uport))
1158 return PTR_ERR(u->clk);
1159
1160 u->clk = NULL;
1161 }
1162
1163 return 0;
1164}
1165
1166static int sprd_probe(struct platform_device *pdev)
1167{
1168 struct resource *res;
1169 struct uart_port *up;
1170 int irq;
1171 int index;
1172 int ret;
1173
1174 for (index = 0; index < ARRAY_SIZE(sprd_port); index++)
1175 if (sprd_port[index] == NULL)
1176 break;
1177
1178 if (index == ARRAY_SIZE(sprd_port))
1179 return -EBUSY;
1180
1181 index = sprd_probe_dt_alias(index, &pdev->dev);
1182
1183 sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]),
1184 GFP_KERNEL);
1185 if (!sprd_port[index])
1186 return -ENOMEM;
1187
1188 up = &sprd_port[index]->port;
1189 up->dev = &pdev->dev;
1190 up->line = index;
1191 up->type = PORT_SPRD;
1192 up->iotype = UPIO_MEM;
1193 up->uartclk = SPRD_DEF_RATE;
1194 up->fifosize = SPRD_FIFO_SIZE;
1195 up->ops = &serial_sprd_ops;
1196 up->flags = UPF_BOOT_AUTOCONF;
1197
1198 ret = sprd_clk_init(up);
1199 if (ret)
1200 return ret;
1201
1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 up->membase = devm_ioremap_resource(&pdev->dev, res);
1204 if (IS_ERR(up->membase))
1205 return PTR_ERR(up->membase);
1206
1207 up->mapbase = res->start;
1208
1209 irq = platform_get_irq(pdev, 0);
1210 if (irq < 0)
1211 return irq;
1212 up->irq = irq;
1213
1214 /*
1215 * Allocate one dma buffer to prepare for receive transfer, in case
1216 * memory allocation failure at runtime.
1217 */
1218 ret = sprd_rx_alloc_buf(sprd_port[index]);
1219 if (ret)
1220 return ret;
1221
1222 if (!sprd_ports_num) {
1223 ret = uart_register_driver(&sprd_uart_driver);
1224 if (ret < 0) {
1225 pr_err("Failed to register SPRD-UART driver\n");
1226 return ret;
1227 }
1228 }
1229 sprd_ports_num++;
1230
1231 ret = uart_add_one_port(&sprd_uart_driver, up);
1232 if (ret) {
1233 sprd_port[index] = NULL;
1234 sprd_remove(pdev);
1235 }
1236
1237 platform_set_drvdata(pdev, up);
1238
1239 return ret;
1240}
1241
1242#ifdef CONFIG_PM_SLEEP
1243static int sprd_suspend(struct device *dev)
1244{
1245 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1246
1247 uart_suspend_port(&sprd_uart_driver, &sup->port);
1248
1249 return 0;
1250}
1251
1252static int sprd_resume(struct device *dev)
1253{
1254 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1255
1256 uart_resume_port(&sprd_uart_driver, &sup->port);
1257
1258 return 0;
1259}
1260#endif
1261
1262static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
1263
1264static const struct of_device_id serial_ids[] = {
1265 {.compatible = "sprd,sc9836-uart",},
1266 {}
1267};
1268MODULE_DEVICE_TABLE(of, serial_ids);
1269
1270static struct platform_driver sprd_platform_driver = {
1271 .probe = sprd_probe,
1272 .remove = sprd_remove,
1273 .driver = {
1274 .name = "sprd_serial",
1275 .of_match_table = of_match_ptr(serial_ids),
1276 .pm = &sprd_pm_ops,
1277 },
1278};
1279
1280module_platform_driver(sprd_platform_driver);
1281
1282MODULE_LICENSE("GPL v2");
1283MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/console.h>
8#include <linux/delay.h>
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/dma/sprd-dma.h>
12#include <linux/io.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24/* device name */
25#define UART_NR_MAX 8
26#define SPRD_TTY_NAME "ttyS"
27#define SPRD_FIFO_SIZE 128
28#define SPRD_DEF_RATE 26000000
29#define SPRD_BAUD_IO_LIMIT 3000000
30#define SPRD_TIMEOUT 256000
31
32/* the offset of serial registers and BITs for them */
33/* data registers */
34#define SPRD_TXD 0x0000
35#define SPRD_RXD 0x0004
36
37/* line status register and its BITs */
38#define SPRD_LSR 0x0008
39#define SPRD_LSR_OE BIT(4)
40#define SPRD_LSR_FE BIT(3)
41#define SPRD_LSR_PE BIT(2)
42#define SPRD_LSR_BI BIT(7)
43#define SPRD_LSR_TX_OVER BIT(15)
44
45/* data number in TX and RX fifo */
46#define SPRD_STS1 0x000C
47#define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
48#define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
49
50/* interrupt enable register and its BITs */
51#define SPRD_IEN 0x0010
52#define SPRD_IEN_RX_FULL BIT(0)
53#define SPRD_IEN_TX_EMPTY BIT(1)
54#define SPRD_IEN_BREAK_DETECT BIT(7)
55#define SPRD_IEN_TIMEOUT BIT(13)
56#define SPRD_IEN_DATA_TIMEOUT BIT(17)
57
58/* interrupt clear register */
59#define SPRD_ICLR 0x0014
60#define SPRD_ICLR_TIMEOUT BIT(13)
61#define SPRD_ICLR_DATA_TIMEOUT BIT(17)
62
63/* line control register */
64#define SPRD_LCR 0x0018
65#define SPRD_LCR_STOP_1BIT 0x10
66#define SPRD_LCR_STOP_2BIT 0x30
67#define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
68#define SPRD_LCR_DATA_LEN5 0x0
69#define SPRD_LCR_DATA_LEN6 0x4
70#define SPRD_LCR_DATA_LEN7 0x8
71#define SPRD_LCR_DATA_LEN8 0xc
72#define SPRD_LCR_PARITY (BIT(0) | BIT(1))
73#define SPRD_LCR_PARITY_EN 0x2
74#define SPRD_LCR_EVEN_PAR 0x0
75#define SPRD_LCR_ODD_PAR 0x1
76
77/* control register 1 */
78#define SPRD_CTL1 0x001C
79#define SPRD_DMA_EN BIT(15)
80#define SPRD_LOOPBACK_EN BIT(14)
81#define RX_HW_FLOW_CTL_THLD BIT(6)
82#define RX_HW_FLOW_CTL_EN BIT(7)
83#define TX_HW_FLOW_CTL_EN BIT(8)
84#define RX_TOUT_THLD_DEF 0x3E00
85#define RX_HFC_THLD_DEF 0x40
86
87/* fifo threshold register */
88#define SPRD_CTL2 0x0020
89#define THLD_TX_EMPTY 0x40
90#define THLD_TX_EMPTY_SHIFT 8
91#define THLD_RX_FULL 0x40
92#define THLD_RX_FULL_MASK GENMASK(6, 0)
93
94/* config baud rate register */
95#define SPRD_CLKD0 0x0024
96#define SPRD_CLKD0_MASK GENMASK(15, 0)
97#define SPRD_CLKD1 0x0028
98#define SPRD_CLKD1_MASK GENMASK(20, 16)
99#define SPRD_CLKD1_SHIFT 16
100
101/* interrupt mask status register */
102#define SPRD_IMSR 0x002C
103#define SPRD_IMSR_RX_FIFO_FULL BIT(0)
104#define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
105#define SPRD_IMSR_BREAK_DETECT BIT(7)
106#define SPRD_IMSR_TIMEOUT BIT(13)
107#define SPRD_IMSR_DATA_TIMEOUT BIT(17)
108#define SPRD_DEFAULT_SOURCE_CLK 26000000
109
110#define SPRD_RX_DMA_STEP 1
111#define SPRD_RX_FIFO_FULL 1
112#define SPRD_TX_FIFO_FULL 0x20
113#define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
114
115struct sprd_uart_dma {
116 struct dma_chan *chn;
117 unsigned char *virt;
118 dma_addr_t phys_addr;
119 dma_cookie_t cookie;
120 u32 trans_len;
121 bool enable;
122};
123
124struct sprd_uart_data {
125 unsigned int timeout_ien;
126 unsigned int timeout_iclr;
127 unsigned int timeout_imsr;
128};
129
130struct sprd_uart_port {
131 struct uart_port port;
132 char name[16];
133 struct clk *clk;
134 struct sprd_uart_dma tx_dma;
135 struct sprd_uart_dma rx_dma;
136 dma_addr_t pos;
137 unsigned char *rx_buf_tail;
138 const struct sprd_uart_data *pdata;
139};
140
141static struct sprd_uart_port *sprd_port[UART_NR_MAX];
142static int sprd_ports_num;
143
144static int sprd_start_dma_rx(struct uart_port *port);
145static int sprd_tx_dma_config(struct uart_port *port);
146
147static const struct sprd_uart_data sc9836_data = {
148 .timeout_ien = SPRD_IEN_TIMEOUT,
149 .timeout_iclr = SPRD_ICLR_TIMEOUT,
150 .timeout_imsr = SPRD_IMSR_TIMEOUT,
151};
152
153static const struct sprd_uart_data sc9632_data = {
154 .timeout_ien = SPRD_IEN_DATA_TIMEOUT,
155 .timeout_iclr = SPRD_ICLR_DATA_TIMEOUT,
156 .timeout_imsr = SPRD_IMSR_DATA_TIMEOUT,
157};
158
159static inline unsigned int serial_in(struct uart_port *port,
160 unsigned int offset)
161{
162 return readl_relaxed(port->membase + offset);
163}
164
165static inline void serial_out(struct uart_port *port, unsigned int offset,
166 int value)
167{
168 writel_relaxed(value, port->membase + offset);
169}
170
171static unsigned int sprd_tx_empty(struct uart_port *port)
172{
173 if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
174 return 0;
175 else
176 return TIOCSER_TEMT;
177}
178
179static unsigned int sprd_get_mctrl(struct uart_port *port)
180{
181 return TIOCM_DSR | TIOCM_CTS;
182}
183
184static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
185{
186 u32 val = serial_in(port, SPRD_CTL1);
187
188 if (mctrl & TIOCM_LOOP)
189 val |= SPRD_LOOPBACK_EN;
190 else
191 val &= ~SPRD_LOOPBACK_EN;
192
193 serial_out(port, SPRD_CTL1, val);
194}
195
196static void sprd_stop_rx(struct uart_port *port)
197{
198 struct sprd_uart_port *sp =
199 container_of(port, struct sprd_uart_port, port);
200 unsigned int ien, iclr;
201
202 if (sp->rx_dma.enable)
203 dmaengine_terminate_all(sp->rx_dma.chn);
204
205 iclr = serial_in(port, SPRD_ICLR);
206 ien = serial_in(port, SPRD_IEN);
207
208 ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
209 iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
210
211 serial_out(port, SPRD_IEN, ien);
212 serial_out(port, SPRD_ICLR, iclr);
213}
214
215static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
216{
217 u32 val = serial_in(port, SPRD_CTL1);
218
219 if (enable)
220 val |= SPRD_DMA_EN;
221 else
222 val &= ~SPRD_DMA_EN;
223
224 serial_out(port, SPRD_CTL1, val);
225}
226
227static void sprd_stop_tx_dma(struct uart_port *port)
228{
229 struct sprd_uart_port *sp =
230 container_of(port, struct sprd_uart_port, port);
231 struct dma_tx_state state;
232 u32 trans_len;
233
234 dmaengine_pause(sp->tx_dma.chn);
235
236 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
237 if (state.residue) {
238 trans_len = state.residue - sp->tx_dma.phys_addr;
239 uart_xmit_advance(port, trans_len);
240 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
241 sp->tx_dma.trans_len, DMA_TO_DEVICE);
242 }
243
244 dmaengine_terminate_all(sp->tx_dma.chn);
245 sp->tx_dma.trans_len = 0;
246}
247
248static int sprd_tx_buf_remap(struct uart_port *port)
249{
250 struct sprd_uart_port *sp =
251 container_of(port, struct sprd_uart_port, port);
252 struct tty_port *tport = &port->state->port;
253 unsigned char *tail;
254
255 sp->tx_dma.trans_len = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
256 UART_XMIT_SIZE);
257
258 sp->tx_dma.phys_addr = dma_map_single(port->dev, tail,
259 sp->tx_dma.trans_len,
260 DMA_TO_DEVICE);
261 return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
262}
263
264static void sprd_complete_tx_dma(void *data)
265{
266 struct uart_port *port = (struct uart_port *)data;
267 struct sprd_uart_port *sp =
268 container_of(port, struct sprd_uart_port, port);
269 struct tty_port *tport = &port->state->port;
270 unsigned long flags;
271
272 uart_port_lock_irqsave(port, &flags);
273 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
274 sp->tx_dma.trans_len, DMA_TO_DEVICE);
275
276 uart_xmit_advance(port, sp->tx_dma.trans_len);
277
278 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
279 uart_write_wakeup(port);
280
281 if (kfifo_is_empty(&tport->xmit_fifo) || sprd_tx_buf_remap(port) ||
282 sprd_tx_dma_config(port))
283 sp->tx_dma.trans_len = 0;
284
285 uart_port_unlock_irqrestore(port, flags);
286}
287
288static int sprd_uart_dma_submit(struct uart_port *port,
289 struct sprd_uart_dma *ud, u32 trans_len,
290 enum dma_transfer_direction direction,
291 dma_async_tx_callback callback)
292{
293 struct dma_async_tx_descriptor *dma_des;
294 unsigned long flags;
295
296 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
297 SPRD_DMA_NO_TRG,
298 SPRD_DMA_FRAG_REQ,
299 SPRD_DMA_TRANS_INT);
300
301 dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
302 direction, flags);
303 if (!dma_des)
304 return -ENODEV;
305
306 dma_des->callback = callback;
307 dma_des->callback_param = port;
308
309 ud->cookie = dmaengine_submit(dma_des);
310 if (dma_submit_error(ud->cookie))
311 return dma_submit_error(ud->cookie);
312
313 dma_async_issue_pending(ud->chn);
314
315 return 0;
316}
317
318static int sprd_tx_dma_config(struct uart_port *port)
319{
320 struct sprd_uart_port *sp =
321 container_of(port, struct sprd_uart_port, port);
322 u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
323 SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
324 int ret;
325 struct dma_slave_config cfg = {
326 .dst_addr = port->mapbase + SPRD_TXD,
327 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
328 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
329 .src_maxburst = burst,
330 };
331
332 ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
333 if (ret < 0)
334 return ret;
335
336 return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
337 DMA_MEM_TO_DEV, sprd_complete_tx_dma);
338}
339
340static void sprd_start_tx_dma(struct uart_port *port)
341{
342 struct sprd_uart_port *sp =
343 container_of(port, struct sprd_uart_port, port);
344 struct tty_port *tport = &port->state->port;
345
346 if (port->x_char) {
347 serial_out(port, SPRD_TXD, port->x_char);
348 port->icount.tx++;
349 port->x_char = 0;
350 return;
351 }
352
353 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
354 sprd_stop_tx_dma(port);
355 return;
356 }
357
358 if (sp->tx_dma.trans_len)
359 return;
360
361 if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
362 sp->tx_dma.trans_len = 0;
363}
364
365static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
366{
367 u32 val = serial_in(port, SPRD_CTL2);
368
369 val &= ~THLD_RX_FULL_MASK;
370 val |= thld & THLD_RX_FULL_MASK;
371 serial_out(port, SPRD_CTL2, val);
372}
373
374static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
375{
376 sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
377 &sp->rx_dma.phys_addr, GFP_KERNEL);
378 if (!sp->rx_dma.virt)
379 return -ENOMEM;
380
381 return 0;
382}
383
384static void sprd_rx_free_buf(struct sprd_uart_port *sp)
385{
386 if (sp->rx_dma.virt)
387 dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
388 sp->rx_dma.virt, sp->rx_dma.phys_addr);
389 sp->rx_dma.virt = NULL;
390}
391
392static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
393{
394 struct sprd_uart_port *sp =
395 container_of(port, struct sprd_uart_port, port);
396 struct dma_slave_config cfg = {
397 .src_addr = port->mapbase + SPRD_RXD,
398 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
399 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
400 .src_maxburst = burst,
401 };
402
403 return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
404}
405
406static void sprd_uart_dma_rx(struct uart_port *port)
407{
408 struct sprd_uart_port *sp =
409 container_of(port, struct sprd_uart_port, port);
410 struct tty_port *tty = &port->state->port;
411
412 port->icount.rx += sp->rx_dma.trans_len;
413 tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
414 tty_flip_buffer_push(tty);
415}
416
417static void sprd_uart_dma_irq(struct uart_port *port)
418{
419 struct sprd_uart_port *sp =
420 container_of(port, struct sprd_uart_port, port);
421 struct dma_tx_state state;
422 enum dma_status status;
423
424 status = dmaengine_tx_status(sp->rx_dma.chn,
425 sp->rx_dma.cookie, &state);
426 if (status == DMA_ERROR)
427 sprd_stop_rx(port);
428
429 if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
430 return;
431
432 if (!state.residue) {
433 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
434 sp->rx_dma.phys_addr - sp->pos;
435 sp->pos = sp->rx_dma.phys_addr;
436 } else {
437 sp->rx_dma.trans_len = state.residue - sp->pos;
438 sp->pos = state.residue;
439 }
440
441 sprd_uart_dma_rx(port);
442 sp->rx_buf_tail += sp->rx_dma.trans_len;
443}
444
445static void sprd_complete_rx_dma(void *data)
446{
447 struct uart_port *port = (struct uart_port *)data;
448 struct sprd_uart_port *sp =
449 container_of(port, struct sprd_uart_port, port);
450 struct dma_tx_state state;
451 enum dma_status status;
452 unsigned long flags;
453
454 uart_port_lock_irqsave(port, &flags);
455
456 status = dmaengine_tx_status(sp->rx_dma.chn,
457 sp->rx_dma.cookie, &state);
458 if (status != DMA_COMPLETE) {
459 sprd_stop_rx(port);
460 uart_port_unlock_irqrestore(port, flags);
461 return;
462 }
463
464 if (sp->pos != sp->rx_dma.phys_addr) {
465 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
466 sp->rx_dma.phys_addr - sp->pos;
467 sprd_uart_dma_rx(port);
468 sp->rx_buf_tail += sp->rx_dma.trans_len;
469 }
470
471 if (sprd_start_dma_rx(port))
472 sprd_stop_rx(port);
473
474 uart_port_unlock_irqrestore(port, flags);
475}
476
477static int sprd_start_dma_rx(struct uart_port *port)
478{
479 struct sprd_uart_port *sp =
480 container_of(port, struct sprd_uart_port, port);
481 int ret;
482
483 if (!sp->rx_dma.enable)
484 return 0;
485
486 sp->pos = sp->rx_dma.phys_addr;
487 sp->rx_buf_tail = sp->rx_dma.virt;
488 sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
489 ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
490 if (ret)
491 return ret;
492
493 return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
494 DMA_DEV_TO_MEM, sprd_complete_rx_dma);
495}
496
497static void sprd_release_dma(struct uart_port *port)
498{
499 struct sprd_uart_port *sp =
500 container_of(port, struct sprd_uart_port, port);
501
502 sprd_uart_dma_enable(port, false);
503
504 if (sp->rx_dma.enable)
505 dma_release_channel(sp->rx_dma.chn);
506
507 if (sp->tx_dma.enable)
508 dma_release_channel(sp->tx_dma.chn);
509
510 sp->tx_dma.enable = false;
511 sp->rx_dma.enable = false;
512}
513
514static void sprd_request_dma(struct uart_port *port)
515{
516 struct sprd_uart_port *sp =
517 container_of(port, struct sprd_uart_port, port);
518
519 sp->tx_dma.enable = true;
520 sp->rx_dma.enable = true;
521
522 sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
523 if (IS_ERR(sp->tx_dma.chn)) {
524 dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
525 PTR_ERR(sp->tx_dma.chn));
526 sp->tx_dma.enable = false;
527 }
528
529 sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
530 if (IS_ERR(sp->rx_dma.chn)) {
531 dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
532 PTR_ERR(sp->rx_dma.chn));
533 sp->rx_dma.enable = false;
534 }
535}
536
537static void sprd_stop_tx(struct uart_port *port)
538{
539 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
540 port);
541 unsigned int ien, iclr;
542
543 if (sp->tx_dma.enable) {
544 sprd_stop_tx_dma(port);
545 return;
546 }
547
548 iclr = serial_in(port, SPRD_ICLR);
549 ien = serial_in(port, SPRD_IEN);
550
551 iclr |= SPRD_IEN_TX_EMPTY;
552 ien &= ~SPRD_IEN_TX_EMPTY;
553
554 serial_out(port, SPRD_IEN, ien);
555 serial_out(port, SPRD_ICLR, iclr);
556}
557
558static void sprd_start_tx(struct uart_port *port)
559{
560 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
561 port);
562 unsigned int ien;
563
564 if (sp->tx_dma.enable) {
565 sprd_start_tx_dma(port);
566 return;
567 }
568
569 ien = serial_in(port, SPRD_IEN);
570 if (!(ien & SPRD_IEN_TX_EMPTY)) {
571 ien |= SPRD_IEN_TX_EMPTY;
572 serial_out(port, SPRD_IEN, ien);
573 }
574}
575
576/* The Sprd serial does not support this function. */
577static void sprd_break_ctl(struct uart_port *port, int break_state)
578{
579 /* nothing to do */
580}
581
582static int handle_lsr_errors(struct uart_port *port,
583 u8 *flag,
584 unsigned int *lsr)
585{
586 int ret = 0;
587
588 /* statistics */
589 if (*lsr & SPRD_LSR_BI) {
590 *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
591 port->icount.brk++;
592 ret = uart_handle_break(port);
593 if (ret)
594 return ret;
595 } else if (*lsr & SPRD_LSR_PE)
596 port->icount.parity++;
597 else if (*lsr & SPRD_LSR_FE)
598 port->icount.frame++;
599 if (*lsr & SPRD_LSR_OE)
600 port->icount.overrun++;
601
602 /* mask off conditions which should be ignored */
603 *lsr &= port->read_status_mask;
604 if (*lsr & SPRD_LSR_BI)
605 *flag = TTY_BREAK;
606 else if (*lsr & SPRD_LSR_PE)
607 *flag = TTY_PARITY;
608 else if (*lsr & SPRD_LSR_FE)
609 *flag = TTY_FRAME;
610
611 return ret;
612}
613
614static inline void sprd_rx(struct uart_port *port)
615{
616 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
617 port);
618 struct tty_port *tty = &port->state->port;
619 unsigned int lsr, max_count = SPRD_TIMEOUT;
620 u8 ch, flag;
621
622 if (sp->rx_dma.enable) {
623 sprd_uart_dma_irq(port);
624 return;
625 }
626
627 while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
628 max_count--) {
629 lsr = serial_in(port, SPRD_LSR);
630 ch = serial_in(port, SPRD_RXD);
631 flag = TTY_NORMAL;
632 port->icount.rx++;
633
634 if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
635 SPRD_LSR_FE | SPRD_LSR_OE))
636 if (handle_lsr_errors(port, &flag, &lsr))
637 continue;
638 if (uart_handle_sysrq_char(port, ch))
639 continue;
640
641 uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
642 }
643
644 tty_flip_buffer_push(tty);
645}
646
647static inline void sprd_tx(struct uart_port *port)
648{
649 u8 ch;
650
651 uart_port_tx_limited(port, ch, THLD_TX_EMPTY,
652 true,
653 serial_out(port, SPRD_TXD, ch),
654 ({}));
655}
656
657/* this handles the interrupt from one port */
658static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
659{
660 struct uart_port *port = dev_id;
661 unsigned int ims;
662 struct sprd_uart_port *sp =
663 container_of(port, struct sprd_uart_port, port);
664
665 uart_port_lock(port);
666
667 ims = serial_in(port, SPRD_IMSR);
668
669 if (!ims) {
670 uart_port_unlock(port);
671 return IRQ_NONE;
672 }
673
674 if (ims & sp->pdata->timeout_imsr)
675 serial_out(port, SPRD_ICLR, sp->pdata->timeout_iclr);
676
677 if (ims & SPRD_IMSR_BREAK_DETECT)
678 serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
679
680 if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
681 sp->pdata->timeout_imsr))
682 sprd_rx(port);
683
684 if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
685 sprd_tx(port);
686
687 uart_port_unlock(port);
688
689 return IRQ_HANDLED;
690}
691
692static void sprd_uart_dma_startup(struct uart_port *port,
693 struct sprd_uart_port *sp)
694{
695 int ret;
696
697 sprd_request_dma(port);
698 if (!(sp->rx_dma.enable || sp->tx_dma.enable))
699 return;
700
701 ret = sprd_start_dma_rx(port);
702 if (ret) {
703 sp->rx_dma.enable = false;
704 dma_release_channel(sp->rx_dma.chn);
705 dev_warn(port->dev, "fail to start RX dma mode\n");
706 }
707
708 sprd_uart_dma_enable(port, true);
709}
710
711static int sprd_startup(struct uart_port *port)
712{
713 int ret = 0;
714 unsigned int ien, fc;
715 unsigned int timeout;
716 struct sprd_uart_port *sp;
717 unsigned long flags;
718
719 serial_out(port, SPRD_CTL2,
720 THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
721
722 /* clear rx fifo */
723 timeout = SPRD_TIMEOUT;
724 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
725 serial_in(port, SPRD_RXD);
726
727 /* clear tx fifo */
728 timeout = SPRD_TIMEOUT;
729 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
730 cpu_relax();
731
732 /* clear interrupt */
733 serial_out(port, SPRD_IEN, 0);
734 serial_out(port, SPRD_ICLR, ~0);
735
736 /* allocate irq */
737 sp = container_of(port, struct sprd_uart_port, port);
738 snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
739
740 sprd_uart_dma_startup(port, sp);
741
742 ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
743 IRQF_SHARED, sp->name, port);
744 if (ret) {
745 dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
746 port->irq, ret);
747 return ret;
748 }
749 fc = serial_in(port, SPRD_CTL1);
750 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
751 serial_out(port, SPRD_CTL1, fc);
752
753 /* enable interrupt */
754 uart_port_lock_irqsave(port, &flags);
755 ien = serial_in(port, SPRD_IEN);
756 ien |= SPRD_IEN_BREAK_DETECT | sp->pdata->timeout_ien;
757 if (!sp->rx_dma.enable)
758 ien |= SPRD_IEN_RX_FULL;
759 serial_out(port, SPRD_IEN, ien);
760 uart_port_unlock_irqrestore(port, flags);
761
762 return 0;
763}
764
765static void sprd_shutdown(struct uart_port *port)
766{
767 sprd_release_dma(port);
768 serial_out(port, SPRD_IEN, 0);
769 serial_out(port, SPRD_ICLR, ~0);
770 devm_free_irq(port->dev, port->irq, port);
771}
772
773static void sprd_set_termios(struct uart_port *port, struct ktermios *termios,
774 const struct ktermios *old)
775{
776 unsigned int baud, quot;
777 unsigned int lcr = 0, fc;
778 unsigned long flags;
779
780 /* ask the core to calculate the divisor for us */
781 baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
782
783 quot = port->uartclk / baud;
784
785 /* set data length */
786 switch (termios->c_cflag & CSIZE) {
787 case CS5:
788 lcr |= SPRD_LCR_DATA_LEN5;
789 break;
790 case CS6:
791 lcr |= SPRD_LCR_DATA_LEN6;
792 break;
793 case CS7:
794 lcr |= SPRD_LCR_DATA_LEN7;
795 break;
796 case CS8:
797 default:
798 lcr |= SPRD_LCR_DATA_LEN8;
799 break;
800 }
801
802 /* calculate stop bits */
803 lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
804 if (termios->c_cflag & CSTOPB)
805 lcr |= SPRD_LCR_STOP_2BIT;
806 else
807 lcr |= SPRD_LCR_STOP_1BIT;
808
809 /* calculate parity */
810 lcr &= ~SPRD_LCR_PARITY;
811 termios->c_cflag &= ~CMSPAR; /* no support mark/space */
812 if (termios->c_cflag & PARENB) {
813 lcr |= SPRD_LCR_PARITY_EN;
814 if (termios->c_cflag & PARODD)
815 lcr |= SPRD_LCR_ODD_PAR;
816 else
817 lcr |= SPRD_LCR_EVEN_PAR;
818 }
819
820 uart_port_lock_irqsave(port, &flags);
821
822 /* update the per-port timeout */
823 uart_update_timeout(port, termios->c_cflag, baud);
824
825 port->read_status_mask = SPRD_LSR_OE;
826 if (termios->c_iflag & INPCK)
827 port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
828 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
829 port->read_status_mask |= SPRD_LSR_BI;
830
831 /* characters to ignore */
832 port->ignore_status_mask = 0;
833 if (termios->c_iflag & IGNPAR)
834 port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
835 if (termios->c_iflag & IGNBRK) {
836 port->ignore_status_mask |= SPRD_LSR_BI;
837 /*
838 * If we're ignoring parity and break indicators,
839 * ignore overruns too (for real raw support).
840 */
841 if (termios->c_iflag & IGNPAR)
842 port->ignore_status_mask |= SPRD_LSR_OE;
843 }
844
845 /* flow control */
846 fc = serial_in(port, SPRD_CTL1);
847 fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
848 if (termios->c_cflag & CRTSCTS) {
849 fc |= RX_HW_FLOW_CTL_THLD;
850 fc |= RX_HW_FLOW_CTL_EN;
851 fc |= TX_HW_FLOW_CTL_EN;
852 }
853
854 /* clock divider bit0~bit15 */
855 serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
856
857 /* clock divider bit16~bit20 */
858 serial_out(port, SPRD_CLKD1,
859 (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
860 serial_out(port, SPRD_LCR, lcr);
861 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
862 serial_out(port, SPRD_CTL1, fc);
863
864 uart_port_unlock_irqrestore(port, flags);
865
866 /* Don't rewrite B0 */
867 if (tty_termios_baud_rate(termios))
868 tty_termios_encode_baud_rate(termios, baud, baud);
869}
870
871static const char *sprd_type(struct uart_port *port)
872{
873 return "SPX";
874}
875
876static void sprd_release_port(struct uart_port *port)
877{
878 /* nothing to do */
879}
880
881static int sprd_request_port(struct uart_port *port)
882{
883 return 0;
884}
885
886static void sprd_config_port(struct uart_port *port, int flags)
887{
888 if (flags & UART_CONFIG_TYPE)
889 port->type = PORT_SPRD;
890}
891
892static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
893{
894 if (ser->type != PORT_SPRD)
895 return -EINVAL;
896 if (port->irq != ser->irq)
897 return -EINVAL;
898 if (port->iotype != ser->io_type)
899 return -EINVAL;
900 return 0;
901}
902
903static void sprd_pm(struct uart_port *port, unsigned int state,
904 unsigned int oldstate)
905{
906 struct sprd_uart_port *sup =
907 container_of(port, struct sprd_uart_port, port);
908
909 switch (state) {
910 case UART_PM_STATE_ON:
911 clk_prepare_enable(sup->clk);
912 break;
913 case UART_PM_STATE_OFF:
914 clk_disable_unprepare(sup->clk);
915 break;
916 }
917}
918
919#ifdef CONFIG_CONSOLE_POLL
920static int sprd_poll_init(struct uart_port *port)
921{
922 if (port->state->pm_state != UART_PM_STATE_ON) {
923 sprd_pm(port, UART_PM_STATE_ON, 0);
924 port->state->pm_state = UART_PM_STATE_ON;
925 }
926
927 return 0;
928}
929
930static int sprd_poll_get_char(struct uart_port *port)
931{
932 while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
933 cpu_relax();
934
935 return serial_in(port, SPRD_RXD);
936}
937
938static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
939{
940 while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
941 cpu_relax();
942
943 serial_out(port, SPRD_TXD, ch);
944}
945#endif
946
947static const struct uart_ops serial_sprd_ops = {
948 .tx_empty = sprd_tx_empty,
949 .get_mctrl = sprd_get_mctrl,
950 .set_mctrl = sprd_set_mctrl,
951 .stop_tx = sprd_stop_tx,
952 .start_tx = sprd_start_tx,
953 .stop_rx = sprd_stop_rx,
954 .break_ctl = sprd_break_ctl,
955 .startup = sprd_startup,
956 .shutdown = sprd_shutdown,
957 .set_termios = sprd_set_termios,
958 .type = sprd_type,
959 .release_port = sprd_release_port,
960 .request_port = sprd_request_port,
961 .config_port = sprd_config_port,
962 .verify_port = sprd_verify_port,
963 .pm = sprd_pm,
964#ifdef CONFIG_CONSOLE_POLL
965 .poll_init = sprd_poll_init,
966 .poll_get_char = sprd_poll_get_char,
967 .poll_put_char = sprd_poll_put_char,
968#endif
969};
970
971#ifdef CONFIG_SERIAL_SPRD_CONSOLE
972static void wait_for_xmitr(struct uart_port *port)
973{
974 unsigned int status, tmout = 10000;
975
976 /* wait up to 10ms for the character(s) to be sent */
977 do {
978 status = serial_in(port, SPRD_STS1);
979 if (--tmout == 0)
980 break;
981 udelay(1);
982 } while (status & SPRD_TX_FIFO_CNT_MASK);
983}
984
985static void sprd_console_putchar(struct uart_port *port, unsigned char ch)
986{
987 wait_for_xmitr(port);
988 serial_out(port, SPRD_TXD, ch);
989}
990
991static void sprd_console_write(struct console *co, const char *s,
992 unsigned int count)
993{
994 struct uart_port *port = &sprd_port[co->index]->port;
995 int locked = 1;
996 unsigned long flags;
997
998 if (port->sysrq)
999 locked = 0;
1000 else if (oops_in_progress)
1001 locked = uart_port_trylock_irqsave(port, &flags);
1002 else
1003 uart_port_lock_irqsave(port, &flags);
1004
1005 uart_console_write(port, s, count, sprd_console_putchar);
1006
1007 /* wait for transmitter to become empty */
1008 wait_for_xmitr(port);
1009
1010 if (locked)
1011 uart_port_unlock_irqrestore(port, flags);
1012}
1013
1014static int sprd_console_setup(struct console *co, char *options)
1015{
1016 struct sprd_uart_port *sprd_uart_port;
1017 int baud = 115200;
1018 int bits = 8;
1019 int parity = 'n';
1020 int flow = 'n';
1021
1022 if (co->index >= UART_NR_MAX || co->index < 0)
1023 co->index = 0;
1024
1025 sprd_uart_port = sprd_port[co->index];
1026 if (!sprd_uart_port || !sprd_uart_port->port.membase) {
1027 pr_info("serial port %d not yet initialized\n", co->index);
1028 return -ENODEV;
1029 }
1030
1031 if (options)
1032 uart_parse_options(options, &baud, &parity, &bits, &flow);
1033
1034 return uart_set_options(&sprd_uart_port->port, co, baud,
1035 parity, bits, flow);
1036}
1037
1038static struct uart_driver sprd_uart_driver;
1039static struct console sprd_console = {
1040 .name = SPRD_TTY_NAME,
1041 .write = sprd_console_write,
1042 .device = uart_console_device,
1043 .setup = sprd_console_setup,
1044 .flags = CON_PRINTBUFFER,
1045 .index = -1,
1046 .data = &sprd_uart_driver,
1047};
1048
1049static int __init sprd_serial_console_init(void)
1050{
1051 register_console(&sprd_console);
1052 return 0;
1053}
1054console_initcall(sprd_serial_console_init);
1055
1056#define SPRD_CONSOLE (&sprd_console)
1057
1058/* Support for earlycon */
1059static void sprd_putc(struct uart_port *port, unsigned char c)
1060{
1061 unsigned int timeout = SPRD_TIMEOUT;
1062
1063 while (timeout-- &&
1064 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
1065 cpu_relax();
1066
1067 writeb(c, port->membase + SPRD_TXD);
1068}
1069
1070static void sprd_early_write(struct console *con, const char *s, unsigned int n)
1071{
1072 struct earlycon_device *dev = con->data;
1073
1074 uart_console_write(&dev->port, s, n, sprd_putc);
1075}
1076
1077static int __init sprd_early_console_setup(struct earlycon_device *device,
1078 const char *opt)
1079{
1080 if (!device->port.membase)
1081 return -ENODEV;
1082
1083 device->con->write = sprd_early_write;
1084 return 0;
1085}
1086OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
1087 sprd_early_console_setup);
1088
1089#else /* !CONFIG_SERIAL_SPRD_CONSOLE */
1090#define SPRD_CONSOLE NULL
1091#endif
1092
1093static struct uart_driver sprd_uart_driver = {
1094 .owner = THIS_MODULE,
1095 .driver_name = "sprd_serial",
1096 .dev_name = SPRD_TTY_NAME,
1097 .major = 0,
1098 .minor = 0,
1099 .nr = UART_NR_MAX,
1100 .cons = SPRD_CONSOLE,
1101};
1102
1103static void sprd_remove(struct platform_device *dev)
1104{
1105 struct sprd_uart_port *sup = platform_get_drvdata(dev);
1106
1107 if (sup) {
1108 uart_remove_one_port(&sprd_uart_driver, &sup->port);
1109 sprd_port[sup->port.line] = NULL;
1110 sprd_rx_free_buf(sup);
1111 sprd_ports_num--;
1112 }
1113
1114 if (!sprd_ports_num)
1115 uart_unregister_driver(&sprd_uart_driver);
1116}
1117
1118static bool sprd_uart_is_console(struct uart_port *uport)
1119{
1120 struct console *cons = sprd_uart_driver.cons;
1121
1122 if ((cons && cons->index >= 0 && cons->index == uport->line) ||
1123 of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
1124 return true;
1125
1126 return false;
1127}
1128
1129static int sprd_clk_init(struct uart_port *uport)
1130{
1131 struct clk *clk_uart, *clk_parent;
1132 struct sprd_uart_port *u = container_of(uport, struct sprd_uart_port, port);
1133
1134 clk_uart = devm_clk_get(uport->dev, "uart");
1135 if (IS_ERR(clk_uart)) {
1136 dev_warn(uport->dev, "uart%d can't get uart clock\n",
1137 uport->line);
1138 clk_uart = NULL;
1139 }
1140
1141 clk_parent = devm_clk_get(uport->dev, "source");
1142 if (IS_ERR(clk_parent)) {
1143 dev_warn(uport->dev, "uart%d can't get source clock\n",
1144 uport->line);
1145 clk_parent = NULL;
1146 }
1147
1148 if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
1149 uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
1150 else
1151 uport->uartclk = clk_get_rate(clk_uart);
1152
1153 u->clk = devm_clk_get(uport->dev, "enable");
1154 if (IS_ERR(u->clk)) {
1155 if (PTR_ERR(u->clk) == -EPROBE_DEFER)
1156 return -EPROBE_DEFER;
1157
1158 dev_warn(uport->dev, "uart%d can't get enable clock\n",
1159 uport->line);
1160
1161 /* To keep console alive even if the error occurred */
1162 if (!sprd_uart_is_console(uport))
1163 return PTR_ERR(u->clk);
1164
1165 u->clk = NULL;
1166 }
1167
1168 return 0;
1169}
1170
1171static int sprd_probe(struct platform_device *pdev)
1172{
1173 struct resource *res;
1174 struct uart_port *up;
1175 struct sprd_uart_port *sport;
1176 int irq;
1177 int index;
1178 int ret;
1179
1180 index = of_alias_get_id(pdev->dev.of_node, "serial");
1181 if (index < 0 || index >= UART_NR_MAX) {
1182 dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
1183 return -EINVAL;
1184 }
1185
1186 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1187 if (!sport)
1188 return -ENOMEM;
1189
1190 up = &sport->port;
1191 up->dev = &pdev->dev;
1192 up->line = index;
1193 up->type = PORT_SPRD;
1194 up->iotype = UPIO_MEM;
1195 up->uartclk = SPRD_DEF_RATE;
1196 up->fifosize = SPRD_FIFO_SIZE;
1197 up->ops = &serial_sprd_ops;
1198 up->flags = UPF_BOOT_AUTOCONF;
1199 up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
1200
1201 ret = sprd_clk_init(up);
1202 if (ret)
1203 return ret;
1204
1205 up->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1206 if (IS_ERR(up->membase))
1207 return PTR_ERR(up->membase);
1208
1209 up->mapbase = res->start;
1210
1211 sport->pdata = of_device_get_match_data(&pdev->dev);
1212 if (!sport->pdata) {
1213 dev_err(&pdev->dev, "get match data failed!\n");
1214 return -EINVAL;
1215 }
1216
1217 irq = platform_get_irq(pdev, 0);
1218 if (irq < 0)
1219 return irq;
1220 up->irq = irq;
1221
1222 /*
1223 * Allocate one dma buffer to prepare for receive transfer, in case
1224 * memory allocation failure at runtime.
1225 */
1226 ret = sprd_rx_alloc_buf(sport);
1227 if (ret)
1228 return ret;
1229
1230 if (!sprd_ports_num) {
1231 ret = uart_register_driver(&sprd_uart_driver);
1232 if (ret < 0) {
1233 pr_err("Failed to register SPRD-UART driver\n");
1234 goto free_rx_buf;
1235 }
1236 }
1237
1238 sprd_ports_num++;
1239 sprd_port[index] = sport;
1240
1241 ret = uart_add_one_port(&sprd_uart_driver, up);
1242 if (ret)
1243 goto clean_port;
1244
1245 platform_set_drvdata(pdev, up);
1246
1247 return 0;
1248
1249clean_port:
1250 sprd_port[index] = NULL;
1251 if (--sprd_ports_num == 0)
1252 uart_unregister_driver(&sprd_uart_driver);
1253free_rx_buf:
1254 sprd_rx_free_buf(sport);
1255 return ret;
1256}
1257
1258#ifdef CONFIG_PM_SLEEP
1259static int sprd_suspend(struct device *dev)
1260{
1261 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1262
1263 uart_suspend_port(&sprd_uart_driver, &sup->port);
1264
1265 return 0;
1266}
1267
1268static int sprd_resume(struct device *dev)
1269{
1270 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1271
1272 uart_resume_port(&sprd_uart_driver, &sup->port);
1273
1274 return 0;
1275}
1276#endif
1277
1278static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
1279
1280static const struct of_device_id serial_ids[] = {
1281 {.compatible = "sprd,sc9836-uart", .data = &sc9836_data},
1282 {.compatible = "sprd,sc9632-uart", .data = &sc9632_data},
1283 {}
1284};
1285MODULE_DEVICE_TABLE(of, serial_ids);
1286
1287static struct platform_driver sprd_platform_driver = {
1288 .probe = sprd_probe,
1289 .remove = sprd_remove,
1290 .driver = {
1291 .name = "sprd_serial",
1292 .of_match_table = serial_ids,
1293 .pm = &sprd_pm_ops,
1294 },
1295};
1296
1297module_platform_driver(sprd_platform_driver);
1298
1299MODULE_LICENSE("GPL v2");
1300MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");