1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Compaq Hot Plug Controller Driver
   4 *
   5 * Copyright (C) 1995,2001 Compaq Computer Corporation
   6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7 * Copyright (C) 2001 IBM Corp.
   8 *
   9 * All rights reserved.
  10 *
  11 * Send feedback to <greg@kroah.com>
  12 *
  13 */
  14
  15#include <linux/module.h>
  16#include <linux/kernel.h>
  17#include <linux/types.h>
  18#include <linux/slab.h>
  19#include <linux/workqueue.h>
  20#include <linux/proc_fs.h>
  21#include <linux/pci.h>
  22#include <linux/pci_hotplug.h>
  23#include "../pci.h"
  24#include "cpqphp.h"
  25#include "cpqphp_nvram.h"
  26
  27
  28u8 cpqhp_nic_irq;
  29u8 cpqhp_disk_irq;
  30
  31static u16 unused_IRQ;
  32
  33/*
  34 * detect_HRT_floating_pointer
  35 *
  36 * find the Hot Plug Resource Table in the specified region of memory.
  37 *
  38 */
  39static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
  40{
  41	void __iomem *fp;
  42	void __iomem *endp;
  43	u8 temp1, temp2, temp3, temp4;
  44	int status = 0;
  45
  46	endp = (end - sizeof(struct hrt) + 1);
  47
  48	for (fp = begin; fp <= endp; fp += 16) {
  49		temp1 = readb(fp + SIG0);
  50		temp2 = readb(fp + SIG1);
  51		temp3 = readb(fp + SIG2);
  52		temp4 = readb(fp + SIG3);
  53		if (temp1 == '$' &&
  54		    temp2 == 'H' &&
  55		    temp3 == 'R' &&
  56		    temp4 == 'T') {
  57			status = 1;
  58			break;
  59		}
  60	}
  61
  62	if (!status)
  63		fp = NULL;
  64
  65	dbg("Discovered Hotplug Resource Table at %p\n", fp);
  66	return fp;
  67}
  68
  69
  70int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
  71{
  72	struct pci_bus *child;
  73	int num;
  74
  75	pci_lock_rescan_remove();
  76
  77	if (func->pci_dev == NULL)
  78		func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
  79							PCI_DEVFN(func->device,
  80							func->function));
  81
  82	/* No pci device, we need to create it then */
  83	if (func->pci_dev == NULL) {
  84		dbg("INFO: pci_dev still null\n");
  85
  86		num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
  87		if (num)
  88			pci_bus_add_devices(ctrl->pci_dev->bus);
  89
  90		func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
  91							PCI_DEVFN(func->device,
  92							func->function));
  93		if (func->pci_dev == NULL) {
  94			dbg("ERROR: pci_dev still null\n");
  95			goto out;
  96		}
  97	}
  98
  99	if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
 100		pci_hp_add_bridge(func->pci_dev);
 101		child = func->pci_dev->subordinate;
 102		if (child)
 103			pci_bus_add_devices(child);
 104	}
 105
 106	pci_dev_put(func->pci_dev);
 107
 108 out:
 109	pci_unlock_rescan_remove();
 110	return 0;
 111}
 112
 113
 114int cpqhp_unconfigure_device(struct pci_func *func)
 115{
 116	int j;
 117
 118	dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
 119
 120	pci_lock_rescan_remove();
 121	for (j = 0; j < 8 ; j++) {
 122		struct pci_dev *temp = pci_get_domain_bus_and_slot(0,
 123							func->bus,
 124							PCI_DEVFN(func->device,
 125							j));
 126		if (temp) {
 127			pci_dev_put(temp);
 128			pci_stop_and_remove_bus_device(temp);
 129		}
 130	}
 131	pci_unlock_rescan_remove();
 132	return 0;
 133}
 134
 135static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
 136{
 137	u32 vendID = 0;
 138
 139	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
 140		return -1;
 141	if (vendID == 0xffffffff)
 142		return -1;
 143	return pci_bus_read_config_dword(bus, devfn, offset, value);
 144}
 145
 146
 147/*
 148 * cpqhp_set_irq
 149 *
 150 * @bus_num: bus number of PCI device
 151 * @dev_num: device number of PCI device
 152 * @slot: pointer to u8 where slot number will be returned
 153 */
 154int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
 155{
 156	int rc = 0;
 157
 158	if (cpqhp_legacy_mode) {
 159		struct pci_dev *fakedev;
 160		struct pci_bus *fakebus;
 161		u16 temp_word;
 162
 163		fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
 164		fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
 165		if (!fakedev || !fakebus) {
 166			kfree(fakedev);
 167			kfree(fakebus);
 168			return -ENOMEM;
 169		}
 170
 171		fakedev->devfn = dev_num << 3;
 172		fakedev->bus = fakebus;
 173		fakebus->number = bus_num;
 174		dbg("%s: dev %d, bus %d, pin %d, num %d\n",
 175		    __func__, dev_num, bus_num, int_pin, irq_num);
 176		rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
 177		kfree(fakedev);
 178		kfree(fakebus);
 179		dbg("%s: rc %d\n", __func__, rc);
 180		if (!rc)
 181			return !rc;
 182
 183		/* set the Edge Level Control Register (ELCR) */
 184		temp_word = inb(0x4d0);
 185		temp_word |= inb(0x4d1) << 8;
 186
 187		temp_word |= 0x01 << irq_num;
 188
 189		/* This should only be for x86 as it sets the Edge Level
 190		 * Control Register
 191		 */
 192		outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
 193		0xFF00) >> 8), 0x4d1); rc = 0; }
 194
 195	return rc;
 196}
 197
 198
 199static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num)
 200{
 201	u16 tdevice;
 202	u32 work;
 203	u8 tbus;
 204
 205	ctrl->pci_bus->number = bus_num;
 206
 207	for (tdevice = 0; tdevice < 0xFF; tdevice++) {
 208		/* Scan for access first */
 209		if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
 210			continue;
 211		dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
 212		/* Yep we got one. Not a bridge ? */
 213		if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
 214			*dev_num = tdevice;
 215			dbg("found it !\n");
 216			return 0;
 217		}
 218	}
 219	for (tdevice = 0; tdevice < 0xFF; tdevice++) {
 220		/* Scan for access first */
 221		if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
 222			continue;
 223		dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
 224		/* Yep we got one. bridge ? */
 225		if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
 226			pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
 227			/* XXX: no recursion, wtf? */
 228			dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
 229			return 0;
 230		}
 231	}
 232
 233	return -1;
 234}
 235
 236
 237static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
 238{
 239	int loop, len;
 240	u32 work;
 241	u8 tbus, tdevice, tslot;
 242
 243	len = cpqhp_routing_table_length();
 244	for (loop = 0; loop < len; ++loop) {
 245		tbus = cpqhp_routing_table->slots[loop].bus;
 246		tdevice = cpqhp_routing_table->slots[loop].devfn;
 247		tslot = cpqhp_routing_table->slots[loop].slot;
 248
 249		if (tslot == slot) {
 250			*bus_num = tbus;
 251			*dev_num = tdevice;
 252			ctrl->pci_bus->number = tbus;
 253			pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
 254			if (!nobridge || (work == 0xffffffff))
 255				return 0;
 256
 257			dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
 258			pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
 259			dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
 260
 261			if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
 262				pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
 263				dbg("Scan bus for Non Bridge: bus %d\n", tbus);
 264				if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
 265					*bus_num = tbus;
 266					return 0;
 267				}
 268			} else
 269				return 0;
 270		}
 271	}
 272	return -1;
 273}
 274
 275
 276int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
 277{
 278	/* plain (bridges allowed) */
 279	return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
 280}
 281
 282
 283/* More PCI configuration routines; this time centered around hotplug
 284 * controller
 285 */
 286
 287
 288/*
 289 * cpqhp_save_config
 290 *
 291 * Reads configuration for all slots in a PCI bus and saves info.
 292 *
 293 * Note:  For non-hot plug buses, the slot # saved is the device #
 294 *
 295 * returns 0 if success
 296 */
 297int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
 298{
 299	long rc;
 300	u8 class_code;
 301	u8 header_type;
 302	u32 ID;
 303	u8 secondary_bus;
 304	struct pci_func *new_slot;
 305	int sub_bus;
 306	int FirstSupported;
 307	int LastSupported;
 308	int max_functions;
 309	int function;
 310	u8 DevError;
 311	int device = 0;
 312	int cloop = 0;
 313	int stop_it;
 314	int index;
 315	u16 devfn;
 316
 317	/* Decide which slots are supported */
 318
 319	if (is_hot_plug) {
 320		/*
 321		 * is_hot_plug is the slot mask
 322		 */
 323		FirstSupported = is_hot_plug >> 4;
 324		LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
 325	} else {
 326		FirstSupported = 0;
 327		LastSupported = 0x1F;
 328	}
 329
 330	/* Save PCI configuration space for all devices in supported slots */
 331	ctrl->pci_bus->number = busnumber;
 332	for (device = FirstSupported; device <= LastSupported; device++) {
 333		ID = 0xFFFFFFFF;
 334		rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
 335
 336		if (ID == 0xFFFFFFFF) {
 337			if (is_hot_plug) {
 338				/* Setup slot structure with entry for empty
 339				 * slot
 340				 */
 341				new_slot = cpqhp_slot_create(busnumber);
 342				if (new_slot == NULL)
 343					return 1;
 344
 345				new_slot->bus = (u8) busnumber;
 346				new_slot->device = (u8) device;
 347				new_slot->function = 0;
 348				new_slot->is_a_board = 0;
 349				new_slot->presence_save = 0;
 350				new_slot->switch_save = 0;
 351			}
 352			continue;
 353		}
 354
 355		rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
 356		if (rc)
 357			return rc;
 358
 359		rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
 360		if (rc)
 361			return rc;
 362
 363		/* If multi-function device, set max_functions to 8 */
 364		if (header_type & 0x80)
 365			max_functions = 8;
 366		else
 367			max_functions = 1;
 368
 369		function = 0;
 370
 371		do {
 372			DevError = 0;
 373			if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
 374				/* Recurse the subordinate bus
 375				 * get the subordinate bus number
 376				 */
 377				rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
 378				if (rc) {
 379					return rc;
 380				} else {
 381					sub_bus = (int) secondary_bus;
 382
 383					/* Save secondary bus cfg spc
 384					 * with this recursive call.
 385					 */
 386					rc = cpqhp_save_config(ctrl, sub_bus, 0);
 387					if (rc)
 388						return rc;
 389					ctrl->pci_bus->number = busnumber;
 390				}
 391			}
 392
 393			index = 0;
 394			new_slot = cpqhp_slot_find(busnumber, device, index++);
 395			while (new_slot &&
 396			       (new_slot->function != (u8) function))
 397				new_slot = cpqhp_slot_find(busnumber, device, index++);
 398
 399			if (!new_slot) {
 400				/* Setup slot structure. */
 401				new_slot = cpqhp_slot_create(busnumber);
 402				if (new_slot == NULL)
 403					return 1;
 404			}
 405
 406			new_slot->bus = (u8) busnumber;
 407			new_slot->device = (u8) device;
 408			new_slot->function = (u8) function;
 409			new_slot->is_a_board = 1;
 410			new_slot->switch_save = 0x10;
 411			/* In case of unsupported board */
 412			new_slot->status = DevError;
 413			devfn = (new_slot->device << 3) | new_slot->function;
 414			new_slot->pci_dev = pci_get_domain_bus_and_slot(0,
 415							new_slot->bus, devfn);
 416
 417			for (cloop = 0; cloop < 0x20; cloop++) {
 418				rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
 419				if (rc)
 420					return rc;
 421			}
 422
 423			pci_dev_put(new_slot->pci_dev);
 424
 425			function++;
 426
 427			stop_it = 0;
 428
 429			/* this loop skips to the next present function
 430			 * reading in Class Code and Header type.
 431			 */
 432			while ((function < max_functions) && (!stop_it)) {
 433				rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
 434				if (ID == 0xFFFFFFFF) {
 435					function++;
 436					continue;
 437				}
 438				rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
 439				if (rc)
 440					return rc;
 441
 442				rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
 443				if (rc)
 444					return rc;
 445
 446				stop_it++;
 447			}
 448
 449		} while (function < max_functions);
 450	}			/* End of FOR loop */
 451
 452	return 0;
 453}
 454
 455
 456/*
 457 * cpqhp_save_slot_config
 458 *
 459 * Saves configuration info for all PCI devices in a given slot
 460 * including subordinate buses.
 461 *
 462 * returns 0 if success
 463 */
 464int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot)
 465{
 466	long rc;
 467	u8 class_code;
 468	u8 header_type;
 469	u32 ID;
 470	u8 secondary_bus;
 471	int sub_bus;
 472	int max_functions;
 473	int function = 0;
 474	int cloop = 0;
 475	int stop_it;
 476
 477	ID = 0xFFFFFFFF;
 478
 479	ctrl->pci_bus->number = new_slot->bus;
 480	pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
 481
 482	if (ID == 0xFFFFFFFF)
 483		return 2;
 484
 485	pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
 486	pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
 487
 488	if (header_type & 0x80)	/* Multi-function device */
 489		max_functions = 8;
 490	else
 491		max_functions = 1;
 492
 493	while (function < max_functions) {
 494		if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
 495			/*  Recurse the subordinate bus */
 496			pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
 497
 498			sub_bus = (int) secondary_bus;
 499
 500			/* Save the config headers for the secondary
 501			 * bus.
 502			 */
 503			rc = cpqhp_save_config(ctrl, sub_bus, 0);
 504			if (rc)
 505				return(rc);
 506			ctrl->pci_bus->number = new_slot->bus;
 507
 508		}
 509
 510		new_slot->status = 0;
 511
 512		for (cloop = 0; cloop < 0x20; cloop++)
 513			pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
 514
 515		function++;
 516
 517		stop_it = 0;
 518
 519		/* this loop skips to the next present function
 520		 * reading in the Class Code and the Header type.
 521		 */
 522		while ((function < max_functions) && (!stop_it)) {
 523			pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
 524
 525			if (ID == 0xFFFFFFFF)
 526				function++;
 527			else {
 528				pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
 529				pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
 530				stop_it++;
 531			}
 532		}
 533
 534	}
 535
 536	return 0;
 537}
 538
 539
 540/*
 541 * cpqhp_save_base_addr_length
 542 *
 543 * Saves the length of all base address registers for the
 544 * specified slot.  this is for hot plug REPLACE
 545 *
 546 * returns 0 if success
 547 */
 548int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func)
 549{
 550	u8 cloop;
 551	u8 header_type;
 552	u8 secondary_bus;
 553	u8 type;
 554	int sub_bus;
 555	u32 temp_register;
 556	u32 base;
 557	u32 rc;
 558	struct pci_func *next;
 559	int index = 0;
 560	struct pci_bus *pci_bus = ctrl->pci_bus;
 561	unsigned int devfn;
 562
 563	func = cpqhp_slot_find(func->bus, func->device, index++);
 564
 565	while (func != NULL) {
 566		pci_bus->number = func->bus;
 567		devfn = PCI_DEVFN(func->device, func->function);
 568
 569		/* Check for Bridge */
 570		pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
 571
 572		if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
 573			pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
 574
 575			sub_bus = (int) secondary_bus;
 576
 577			next = cpqhp_slot_list[sub_bus];
 578
 579			while (next != NULL) {
 580				rc = cpqhp_save_base_addr_length(ctrl, next);
 581				if (rc)
 582					return rc;
 583
 584				next = next->next;
 585			}
 586			pci_bus->number = func->bus;
 587
 588			/* FIXME: this loop is duplicated in the non-bridge
 589			 * case.  The two could be rolled together Figure out
 590			 * IO and memory base lengths
 591			 */
 592			for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
 593				temp_register = 0xFFFFFFFF;
 594				pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
 595				pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
 596				/* If this register is implemented */
 597				if (base) {
 598					if (base & 0x01L) {
 599						/* IO base
 600						 * set base = amount of IO space
 601						 * requested
 602						 */
 603						base = base & 0xFFFFFFFE;
 604						base = (~base) + 1;
 605
 606						type = 1;
 607					} else {
 608						/* memory base */
 609						base = base & 0xFFFFFFF0;
 610						base = (~base) + 1;
 611
 612						type = 0;
 613					}
 614				} else {
 615					base = 0x0L;
 616					type = 0;
 617				}
 618
 619				/* Save information in slot structure */
 620				func->base_length[(cloop - 0x10) >> 2] =
 621				base;
 622				func->base_type[(cloop - 0x10) >> 2] = type;
 623
 624			}	/* End of base register loop */
 625
 626		} else if ((header_type & 0x7F) == 0x00) {
 627			/* Figure out IO and memory base lengths */
 628			for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
 629				temp_register = 0xFFFFFFFF;
 630				pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
 631				pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
 632
 633				/* If this register is implemented */
 634				if (base) {
 635					if (base & 0x01L) {
 636						/* IO base
 637						 * base = amount of IO space
 638						 * requested
 639						 */
 640						base = base & 0xFFFFFFFE;
 641						base = (~base) + 1;
 642
 643						type = 1;
 644					} else {
 645						/* memory base
 646						 * base = amount of memory
 647						 * space requested
 648						 */
 649						base = base & 0xFFFFFFF0;
 650						base = (~base) + 1;
 651
 652						type = 0;
 653					}
 654				} else {
 655					base = 0x0L;
 656					type = 0;
 657				}
 658
 659				/* Save information in slot structure */
 660				func->base_length[(cloop - 0x10) >> 2] = base;
 661				func->base_type[(cloop - 0x10) >> 2] = type;
 662
 663			}	/* End of base register loop */
 664
 665		} else {	  /* Some other unknown header type */
 666		}
 667
 668		/* find the next device in this slot */
 669		func = cpqhp_slot_find(func->bus, func->device, index++);
 670	}
 671
 672	return(0);
 673}
 674
 675
 676/*
 677 * cpqhp_save_used_resources
 678 *
 679 * Stores used resource information for existing boards.  this is
 680 * for boards that were in the system when this driver was loaded.
 681 * this function is for hot plug ADD
 682 *
 683 * returns 0 if success
 684 */
 685int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func)
 686{
 687	u8 cloop;
 688	u8 header_type;
 689	u8 secondary_bus;
 690	u8 temp_byte;
 691	u8 b_base;
 692	u8 b_length;
 693	u16 command;
 694	u16 save_command;
 695	u16 w_base;
 696	u16 w_length;
 697	u32 temp_register;
 698	u32 save_base;
 699	u32 base;
 700	int index = 0;
 701	struct pci_resource *mem_node;
 702	struct pci_resource *p_mem_node;
 703	struct pci_resource *io_node;
 704	struct pci_resource *bus_node;
 705	struct pci_bus *pci_bus = ctrl->pci_bus;
 706	unsigned int devfn;
 707
 708	func = cpqhp_slot_find(func->bus, func->device, index++);
 709
 710	while ((func != NULL) && func->is_a_board) {
 711		pci_bus->number = func->bus;
 712		devfn = PCI_DEVFN(func->device, func->function);
 713
 714		/* Save the command register */
 715		pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
 716
 717		/* disable card */
 718		command = 0x00;
 719		pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
 720
 721		/* Check for Bridge */
 722		pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
 723
 724		if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
 725			/* Clear Bridge Control Register */
 726			command = 0x00;
 727			pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
 728			pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
 729			pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
 730
 731			bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
 732			if (!bus_node)
 733				return -ENOMEM;
 734
 735			bus_node->base = secondary_bus;
 736			bus_node->length = temp_byte - secondary_bus + 1;
 737
 738			bus_node->next = func->bus_head;
 739			func->bus_head = bus_node;
 740
 741			/* Save IO base and Limit registers */
 742			pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
 743			pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
 744
 745			if ((b_base <= b_length) && (save_command & 0x01)) {
 746				io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
 747				if (!io_node)
 748					return -ENOMEM;
 749
 750				io_node->base = (b_base & 0xF0) << 8;
 751				io_node->length = (b_length - b_base + 0x10) << 8;
 752
 753				io_node->next = func->io_head;
 754				func->io_head = io_node;
 755			}
 756
 757			/* Save memory base and Limit registers */
 758			pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
 759			pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
 760
 761			if ((w_base <= w_length) && (save_command & 0x02)) {
 762				mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
 763				if (!mem_node)
 764					return -ENOMEM;
 765
 766				mem_node->base = w_base << 16;
 767				mem_node->length = (w_length - w_base + 0x10) << 16;
 768
 769				mem_node->next = func->mem_head;
 770				func->mem_head = mem_node;
 771			}
 772
 773			/* Save prefetchable memory base and Limit registers */
 774			pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
 775			pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
 776
 777			if ((w_base <= w_length) && (save_command & 0x02)) {
 778				p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
 779				if (!p_mem_node)
 780					return -ENOMEM;
 781
 782				p_mem_node->base = w_base << 16;
 783				p_mem_node->length = (w_length - w_base + 0x10) << 16;
 784
 785				p_mem_node->next = func->p_mem_head;
 786				func->p_mem_head = p_mem_node;
 787			}
 788			/* Figure out IO and memory base lengths */
 789			for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
 790				pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
 791
 792				temp_register = 0xFFFFFFFF;
 793				pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
 794				pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
 795
 796				temp_register = base;
 797
 798				/* If this register is implemented */
 799				if (base) {
 800					if (((base & 0x03L) == 0x01)
 801					    && (save_command & 0x01)) {
 802						/* IO base
 803						 * set temp_register = amount
 804						 * of IO space requested
 805						 */
 806						temp_register = base & 0xFFFFFFFE;
 807						temp_register = (~temp_register) + 1;
 808
 809						io_node = kmalloc(sizeof(*io_node),
 810								GFP_KERNEL);
 811						if (!io_node)
 812							return -ENOMEM;
 813
 814						io_node->base =
 815						save_base & (~0x03L);
 816						io_node->length = temp_register;
 817
 818						io_node->next = func->io_head;
 819						func->io_head = io_node;
 820					} else
 821						if (((base & 0x0BL) == 0x08)
 822						    && (save_command & 0x02)) {
 823						/* prefetchable memory base */
 824						temp_register = base & 0xFFFFFFF0;
 825						temp_register = (~temp_register) + 1;
 826
 827						p_mem_node = kmalloc(sizeof(*p_mem_node),
 828								GFP_KERNEL);
 829						if (!p_mem_node)
 830							return -ENOMEM;
 831
 832						p_mem_node->base = save_base & (~0x0FL);
 833						p_mem_node->length = temp_register;
 834
 835						p_mem_node->next = func->p_mem_head;
 836						func->p_mem_head = p_mem_node;
 837					} else
 838						if (((base & 0x0BL) == 0x00)
 839						    && (save_command & 0x02)) {
 840						/* prefetchable memory base */
 841						temp_register = base & 0xFFFFFFF0;
 842						temp_register = (~temp_register) + 1;
 843
 844						mem_node = kmalloc(sizeof(*mem_node),
 845								GFP_KERNEL);
 846						if (!mem_node)
 847							return -ENOMEM;
 848
 849						mem_node->base = save_base & (~0x0FL);
 850						mem_node->length = temp_register;
 851
 852						mem_node->next = func->mem_head;
 853						func->mem_head = mem_node;
 854					} else
 855						return(1);
 856				}
 857			}	/* End of base register loop */
 858		/* Standard header */
 859		} else if ((header_type & 0x7F) == 0x00) {
 860			/* Figure out IO and memory base lengths */
 861			for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
 862				pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
 863
 864				temp_register = 0xFFFFFFFF;
 865				pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
 866				pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
 867
 868				temp_register = base;
 869
 870				/* If this register is implemented */
 871				if (base) {
 872					if (((base & 0x03L) == 0x01)
 873					    && (save_command & 0x01)) {
 874						/* IO base
 875						 * set temp_register = amount
 876						 * of IO space requested
 877						 */
 878						temp_register = base & 0xFFFFFFFE;
 879						temp_register = (~temp_register) + 1;
 880
 881						io_node = kmalloc(sizeof(*io_node),
 882								GFP_KERNEL);
 883						if (!io_node)
 884							return -ENOMEM;
 885
 886						io_node->base = save_base & (~0x01L);
 887						io_node->length = temp_register;
 888
 889						io_node->next = func->io_head;
 890						func->io_head = io_node;
 891					} else
 892						if (((base & 0x0BL) == 0x08)
 893						    && (save_command & 0x02)) {
 894						/* prefetchable memory base */
 895						temp_register = base & 0xFFFFFFF0;
 896						temp_register = (~temp_register) + 1;
 897
 898						p_mem_node = kmalloc(sizeof(*p_mem_node),
 899								GFP_KERNEL);
 900						if (!p_mem_node)
 901							return -ENOMEM;
 902
 903						p_mem_node->base = save_base & (~0x0FL);
 904						p_mem_node->length = temp_register;
 905
 906						p_mem_node->next = func->p_mem_head;
 907						func->p_mem_head = p_mem_node;
 908					} else
 909						if (((base & 0x0BL) == 0x00)
 910						    && (save_command & 0x02)) {
 911						/* prefetchable memory base */
 912						temp_register = base & 0xFFFFFFF0;
 913						temp_register = (~temp_register) + 1;
 914
 915						mem_node = kmalloc(sizeof(*mem_node),
 916								GFP_KERNEL);
 917						if (!mem_node)
 918							return -ENOMEM;
 919
 920						mem_node->base = save_base & (~0x0FL);
 921						mem_node->length = temp_register;
 922
 923						mem_node->next = func->mem_head;
 924						func->mem_head = mem_node;
 925					} else
 926						return(1);
 927				}
 928			}	/* End of base register loop */
 929		}
 930
 931		/* find the next device in this slot */
 932		func = cpqhp_slot_find(func->bus, func->device, index++);
 933	}
 934
 935	return 0;
 936}
 937
 938
 939/*
 940 * cpqhp_configure_board
 941 *
 942 * Copies saved configuration information to one slot.
 943 * this is called recursively for bridge devices.
 944 * this is for hot plug REPLACE!
 945 *
 946 * returns 0 if success
 947 */
 948int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func)
 949{
 950	int cloop;
 951	u8 header_type;
 952	u8 secondary_bus;
 953	int sub_bus;
 954	struct pci_func *next;
 955	u32 temp;
 956	u32 rc;
 957	int index = 0;
 958	struct pci_bus *pci_bus = ctrl->pci_bus;
 959	unsigned int devfn;
 960
 961	func = cpqhp_slot_find(func->bus, func->device, index++);
 962
 963	while (func != NULL) {
 964		pci_bus->number = func->bus;
 965		devfn = PCI_DEVFN(func->device, func->function);
 966
 967		/* Start at the top of config space so that the control
 968		 * registers are programmed last
 969		 */
 970		for (cloop = 0x3C; cloop > 0; cloop -= 4)
 971			pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
 972
 973		pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
 974
 975		/* If this is a bridge device, restore subordinate devices */
 976		if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
 977			pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
 978
 979			sub_bus = (int) secondary_bus;
 980
 981			next = cpqhp_slot_list[sub_bus];
 982
 983			while (next != NULL) {
 984				rc = cpqhp_configure_board(ctrl, next);
 985				if (rc)
 986					return rc;
 987
 988				next = next->next;
 989			}
 990		} else {
 991
 992			/* Check all the base Address Registers to make sure
 993			 * they are the same.  If not, the board is different.
 994			 */
 995
 996			for (cloop = 16; cloop < 40; cloop += 4) {
 997				pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp);
 998
 999				if (temp != func->config_space[cloop >> 2]) {
1000					dbg("Config space compare failure!!! offset = %x\n", cloop);
1001					dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
1002					dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
1003					return 1;
1004				}
1005			}
1006		}
1007
1008		func->configured = 1;
1009
1010		func = cpqhp_slot_find(func->bus, func->device, index++);
1011	}
1012
1013	return 0;
1014}
1015
1016
1017/*
1018 * cpqhp_valid_replace
1019 *
1020 * this function checks to see if a board is the same as the
1021 * one it is replacing.  this check will detect if the device's
1022 * vendor or device id's are the same
1023 *
1024 * returns 0 if the board is the same nonzero otherwise
1025 */
1026int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func)
1027{
1028	u8 cloop;
1029	u8 header_type;
1030	u8 secondary_bus;
1031	u8 type;
1032	u32 temp_register = 0;
1033	u32 base;
1034	u32 rc;
1035	struct pci_func *next;
1036	int index = 0;
1037	struct pci_bus *pci_bus = ctrl->pci_bus;
1038	unsigned int devfn;
1039
1040	if (!func->is_a_board)
1041		return(ADD_NOT_SUPPORTED);
1042
1043	func = cpqhp_slot_find(func->bus, func->device, index++);
1044
1045	while (func != NULL) {
1046		pci_bus->number = func->bus;
1047		devfn = PCI_DEVFN(func->device, func->function);
1048
1049		pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1050
1051		/* No adapter present */
1052		if (temp_register == 0xFFFFFFFF)
1053			return(NO_ADAPTER_PRESENT);
1054
1055		if (temp_register != func->config_space[0])
1056			return(ADAPTER_NOT_SAME);
1057
1058		/* Check for same revision number and class code */
1059		pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1060
1061		/* Adapter not the same */
1062		if (temp_register != func->config_space[0x08 >> 2])
1063			return(ADAPTER_NOT_SAME);
1064
1065		/* Check for Bridge */
1066		pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1067
1068		if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1069			/* In order to continue checking, we must program the
1070			 * bus registers in the bridge to respond to accesses
1071			 * for its subordinate bus(es)
1072			 */
1073
1074			temp_register = func->config_space[0x18 >> 2];
1075			pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1076
1077			secondary_bus = (temp_register >> 8) & 0xFF;
1078
1079			next = cpqhp_slot_list[secondary_bus];
1080
1081			while (next != NULL) {
1082				rc = cpqhp_valid_replace(ctrl, next);
1083				if (rc)
1084					return rc;
1085
1086				next = next->next;
1087			}
1088
1089		}
1090		/* Check to see if it is a standard config header */
1091		else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1092			/* Check subsystem vendor and ID */
1093			pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1094
1095			if (temp_register != func->config_space[0x2C >> 2]) {
1096				/* If it's a SMART-2 and the register isn't
1097				 * filled in, ignore the difference because
1098				 * they just have an old rev of the firmware
1099				 */
1100				if (!((func->config_space[0] == 0xAE100E11)
1101				      && (temp_register == 0x00L)))
1102					return(ADAPTER_NOT_SAME);
1103			}
1104			/* Figure out IO and memory base lengths */
1105			for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1106				temp_register = 0xFFFFFFFF;
1107				pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
1108				pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1109
1110				/* If this register is implemented */
1111				if (base) {
1112					if (base & 0x01L) {
1113						/* IO base
1114						 * set base = amount of IO
1115						 * space requested
1116						 */
1117						base = base & 0xFFFFFFFE;
1118						base = (~base) + 1;
1119
1120						type = 1;
1121					} else {
1122						/* memory base */
1123						base = base & 0xFFFFFFF0;
1124						base = (~base) + 1;
1125
1126						type = 0;
1127					}
1128				} else {
1129					base = 0x0L;
1130					type = 0;
1131				}
1132
1133				/* Check information in slot structure */
1134				if (func->base_length[(cloop - 0x10) >> 2] != base)
1135					return(ADAPTER_NOT_SAME);
1136
1137				if (func->base_type[(cloop - 0x10) >> 2] != type)
1138					return(ADAPTER_NOT_SAME);
1139
1140			}	/* End of base register loop */
1141
1142		}		/* End of (type 0 config space) else */
1143		else {
1144			/* this is not a type 0 or 1 config space header so
1145			 * we don't know how to do it
1146			 */
1147			return(DEVICE_TYPE_NOT_SUPPORTED);
1148		}
1149
1150		/* Get the next function */
1151		func = cpqhp_slot_find(func->bus, func->device, index++);
1152	}
1153
1154
1155	return 0;
1156}
1157
1158
1159/*
1160 * cpqhp_find_available_resources
1161 *
1162 * Finds available memory, IO, and IRQ resources for programming
1163 * devices which may be added to the system
1164 * this function is for hot plug ADD!
1165 *
1166 * returns 0 if success
1167 */
1168int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1169{
1170	u8 temp;
1171	u8 populated_slot;
1172	u8 bridged_slot;
1173	void __iomem *one_slot;
1174	void __iomem *rom_resource_table;
1175	struct pci_func *func = NULL;
1176	int i = 10, index;
1177	u32 temp_dword, rc;
1178	struct pci_resource *mem_node;
1179	struct pci_resource *p_mem_node;
1180	struct pci_resource *io_node;
1181	struct pci_resource *bus_node;
1182
1183	rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1184	dbg("rom_resource_table = %p\n", rom_resource_table);
1185
1186	if (rom_resource_table == NULL)
1187		return -ENODEV;
1188
1189	/* Sum all resources and setup resource maps */
1190	unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1191	dbg("unused_IRQ = %x\n", unused_IRQ);
1192
1193	temp = 0;
1194	while (unused_IRQ) {
1195		if (unused_IRQ & 1) {
1196			cpqhp_disk_irq = temp;
1197			break;
1198		}
1199		unused_IRQ = unused_IRQ >> 1;
1200		temp++;
1201	}
1202
1203	dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1204	unused_IRQ = unused_IRQ >> 1;
1205	temp++;
1206
1207	while (unused_IRQ) {
1208		if (unused_IRQ & 1) {
1209			cpqhp_nic_irq = temp;
1210			break;
1211		}
1212		unused_IRQ = unused_IRQ >> 1;
1213		temp++;
1214	}
1215
1216	dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1217	unused_IRQ = readl(rom_resource_table + PCIIRQ);
1218
1219	temp = 0;
1220
1221	if (!cpqhp_nic_irq)
1222		cpqhp_nic_irq = ctrl->cfgspc_irq;
1223
1224	if (!cpqhp_disk_irq)
1225		cpqhp_disk_irq = ctrl->cfgspc_irq;
1226
1227	dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1228
1229	rc = compaq_nvram_load(rom_start, ctrl);
1230	if (rc)
1231		return rc;
1232
1233	one_slot = rom_resource_table + sizeof(struct hrt);
1234
1235	i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1236	dbg("number_of_entries = %d\n", i);
1237
1238	if (!readb(one_slot + SECONDARY_BUS))
1239		return 1;
1240
1241	dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1242
1243	while (i && readb(one_slot + SECONDARY_BUS)) {
1244		u8 dev_func = readb(one_slot + DEV_FUNC);
1245		u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1246		u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1247		u8 max_bus = readb(one_slot + MAX_BUS);
1248		u16 io_base = readw(one_slot + IO_BASE);
1249		u16 io_length = readw(one_slot + IO_LENGTH);
1250		u16 mem_base = readw(one_slot + MEM_BASE);
1251		u16 mem_length = readw(one_slot + MEM_LENGTH);
1252		u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1253		u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1254
1255		dbg("%2.2x | %4.4x  | %4.4x | %4.4x   | %4.4x | %4.4x   | %4.4x |%2.2x %2.2x %2.2x\n",
1256		    dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1257		    primary_bus, secondary_bus, max_bus);
1258
1259		/* If this entry isn't for our controller's bus, ignore it */
1260		if (primary_bus != ctrl->bus) {
1261			i--;
1262			one_slot += sizeof(struct slot_rt);
1263			continue;
1264		}
1265		/* find out if this entry is for an occupied slot */
1266		ctrl->pci_bus->number = primary_bus;
1267		pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1268		dbg("temp_D_word = %x\n", temp_dword);
1269
1270		if (temp_dword != 0xFFFFFFFF) {
1271			index = 0;
1272			func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1273
1274			while (func && (func->function != (dev_func & 0x07))) {
1275				dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1276				func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1277			}
1278
1279			/* If we can't find a match, skip this table entry */
1280			if (!func) {
1281				i--;
1282				one_slot += sizeof(struct slot_rt);
1283				continue;
1284			}
1285			/* this may not work and shouldn't be used */
1286			if (secondary_bus != primary_bus)
1287				bridged_slot = 1;
1288			else
1289				bridged_slot = 0;
1290
1291			populated_slot = 1;
1292		} else {
1293			populated_slot = 0;
1294			bridged_slot = 0;
1295		}
1296
1297
1298		/* If we've got a valid IO base, use it */
1299
1300		temp_dword = io_base + io_length;
1301
1302		if ((io_base) && (temp_dword < 0x10000)) {
1303			io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1304			if (!io_node)
1305				return -ENOMEM;
1306
1307			io_node->base = io_base;
1308			io_node->length = io_length;
1309
1310			dbg("found io_node(base, length) = %x, %x\n",
1311					io_node->base, io_node->length);
1312			dbg("populated slot =%d \n", populated_slot);
1313			if (!populated_slot) {
1314				io_node->next = ctrl->io_head;
1315				ctrl->io_head = io_node;
1316			} else {
1317				io_node->next = func->io_head;
1318				func->io_head = io_node;
1319			}
1320		}
1321
1322		/* If we've got a valid memory base, use it */
1323		temp_dword = mem_base + mem_length;
1324		if ((mem_base) && (temp_dword < 0x10000)) {
1325			mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1326			if (!mem_node)
1327				return -ENOMEM;
1328
1329			mem_node->base = mem_base << 16;
1330
1331			mem_node->length = mem_length << 16;
1332
1333			dbg("found mem_node(base, length) = %x, %x\n",
1334					mem_node->base, mem_node->length);
1335			dbg("populated slot =%d \n", populated_slot);
1336			if (!populated_slot) {
1337				mem_node->next = ctrl->mem_head;
1338				ctrl->mem_head = mem_node;
1339			} else {
1340				mem_node->next = func->mem_head;
1341				func->mem_head = mem_node;
1342			}
1343		}
1344
1345		/* If we've got a valid prefetchable memory base, and
1346		 * the base + length isn't greater than 0xFFFF
1347		 */
1348		temp_dword = pre_mem_base + pre_mem_length;
1349		if ((pre_mem_base) && (temp_dword < 0x10000)) {
1350			p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1351			if (!p_mem_node)
1352				return -ENOMEM;
1353
1354			p_mem_node->base = pre_mem_base << 16;
1355
1356			p_mem_node->length = pre_mem_length << 16;
1357			dbg("found p_mem_node(base, length) = %x, %x\n",
1358					p_mem_node->base, p_mem_node->length);
1359			dbg("populated slot =%d \n", populated_slot);
1360
1361			if (!populated_slot) {
1362				p_mem_node->next = ctrl->p_mem_head;
1363				ctrl->p_mem_head = p_mem_node;
1364			} else {
1365				p_mem_node->next = func->p_mem_head;
1366				func->p_mem_head = p_mem_node;
1367			}
1368		}
1369
1370		/* If we've got a valid bus number, use it
1371		 * The second condition is to ignore bus numbers on
1372		 * populated slots that don't have PCI-PCI bridges
1373		 */
1374		if (secondary_bus && (secondary_bus != primary_bus)) {
1375			bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1376			if (!bus_node)
1377				return -ENOMEM;
1378
1379			bus_node->base = secondary_bus;
1380			bus_node->length = max_bus - secondary_bus + 1;
1381			dbg("found bus_node(base, length) = %x, %x\n",
1382					bus_node->base, bus_node->length);
1383			dbg("populated slot =%d \n", populated_slot);
1384			if (!populated_slot) {
1385				bus_node->next = ctrl->bus_head;
1386				ctrl->bus_head = bus_node;
1387			} else {
1388				bus_node->next = func->bus_head;
1389				func->bus_head = bus_node;
1390			}
1391		}
1392
1393		i--;
1394		one_slot += sizeof(struct slot_rt);
1395	}
1396
1397	/* If all of the following fail, we don't have any resources for
1398	 * hot plug add
1399	 */
1400	rc = 1;
1401	rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1402	rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1403	rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1404	rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1405
1406	return rc;
1407}
1408
1409
1410/*
1411 * cpqhp_return_board_resources
1412 *
1413 * this routine returns all resources allocated to a board to
1414 * the available pool.
1415 *
1416 * returns 0 if success
1417 */
1418int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources)
1419{
1420	int rc = 0;
1421	struct pci_resource *node;
1422	struct pci_resource *t_node;
1423	dbg("%s\n", __func__);
1424
1425	if (!func)
1426		return 1;
1427
1428	node = func->io_head;
1429	func->io_head = NULL;
1430	while (node) {
1431		t_node = node->next;
1432		return_resource(&(resources->io_head), node);
1433		node = t_node;
1434	}
1435
1436	node = func->mem_head;
1437	func->mem_head = NULL;
1438	while (node) {
1439		t_node = node->next;
1440		return_resource(&(resources->mem_head), node);
1441		node = t_node;
1442	}
1443
1444	node = func->p_mem_head;
1445	func->p_mem_head = NULL;
1446	while (node) {
1447		t_node = node->next;
1448		return_resource(&(resources->p_mem_head), node);
1449		node = t_node;
1450	}
1451
1452	node = func->bus_head;
1453	func->bus_head = NULL;
1454	while (node) {
1455		t_node = node->next;
1456		return_resource(&(resources->bus_head), node);
1457		node = t_node;
1458	}
1459
1460	rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1461	rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1462	rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1463	rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1464
1465	return rc;
1466}
1467
1468
1469/*
1470 * cpqhp_destroy_resource_list
1471 *
1472 * Puts node back in the resource list pointed to by head
1473 */
1474void cpqhp_destroy_resource_list(struct resource_lists *resources)
1475{
1476	struct pci_resource *res, *tres;
1477
1478	res = resources->io_head;
1479	resources->io_head = NULL;
1480
1481	while (res) {
1482		tres = res;
1483		res = res->next;
1484		kfree(tres);
1485	}
1486
1487	res = resources->mem_head;
1488	resources->mem_head = NULL;
1489
1490	while (res) {
1491		tres = res;
1492		res = res->next;
1493		kfree(tres);
1494	}
1495
1496	res = resources->p_mem_head;
1497	resources->p_mem_head = NULL;
1498
1499	while (res) {
1500		tres = res;
1501		res = res->next;
1502		kfree(tres);
1503	}
1504
1505	res = resources->bus_head;
1506	resources->bus_head = NULL;
1507
1508	while (res) {
1509		tres = res;
1510		res = res->next;
1511		kfree(tres);
1512	}
1513}
1514
1515
1516/*
1517 * cpqhp_destroy_board_resources
1518 *
1519 * Puts node back in the resource list pointed to by head
1520 */
1521void cpqhp_destroy_board_resources(struct pci_func *func)
1522{
1523	struct pci_resource *res, *tres;
1524
1525	res = func->io_head;
1526	func->io_head = NULL;
1527
1528	while (res) {
1529		tres = res;
1530		res = res->next;
1531		kfree(tres);
1532	}
1533
1534	res = func->mem_head;
1535	func->mem_head = NULL;
1536
1537	while (res) {
1538		tres = res;
1539		res = res->next;
1540		kfree(tres);
1541	}
1542
1543	res = func->p_mem_head;
1544	func->p_mem_head = NULL;
1545
1546	while (res) {
1547		tres = res;
1548		res = res->next;
1549		kfree(tres);
1550	}
1551
1552	res = func->bus_head;
1553	func->bus_head = NULL;
1554
1555	while (res) {
1556		tres = res;
1557		res = res->next;
1558		kfree(tres);
1559	}
1560}