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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for UniPhier SoCs
4 * Copyright 2018 Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/iopoll.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22
23#include "pcie-designware.h"
24
25#define PCL_PINCTRL0 0x002c
26#define PCL_PERST_PLDN_REGEN BIT(12)
27#define PCL_PERST_NOE_REGEN BIT(11)
28#define PCL_PERST_OUT_REGEN BIT(8)
29#define PCL_PERST_PLDN_REGVAL BIT(4)
30#define PCL_PERST_NOE_REGVAL BIT(3)
31#define PCL_PERST_OUT_REGVAL BIT(0)
32
33#define PCL_PIPEMON 0x0044
34#define PCL_PCLK_ALIVE BIT(15)
35
36#define PCL_APP_READY_CTRL 0x8008
37#define PCL_APP_LTSSM_ENABLE BIT(0)
38
39#define PCL_APP_PM0 0x8078
40#define PCL_SYS_AUX_PWR_DET BIT(8)
41
42#define PCL_RCV_INT 0x8108
43#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
44#define PCL_CFG_BW_MGT_STATUS BIT(4)
45#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
46#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
47#define PCL_CFG_PME_MSI_STATUS BIT(1)
48
49#define PCL_RCV_INTX 0x810c
50#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
51#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
52#define PCL_RCV_INTX_MASK_SHIFT 8
53#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
54#define PCL_RCV_INTX_STATUS_SHIFT 0
55
56#define PCL_STATUS_LINK 0x8140
57#define PCL_RDLH_LINK_UP BIT(1)
58#define PCL_XMLH_LINK_UP BIT(0)
59
60struct uniphier_pcie_priv {
61 void __iomem *base;
62 struct dw_pcie pci;
63 struct clk *clk;
64 struct reset_control *rst;
65 struct phy *phy;
66 struct irq_domain *legacy_irq_domain;
67};
68
69#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
70
71static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
72 bool enable)
73{
74 u32 val;
75
76 val = readl(priv->base + PCL_APP_READY_CTRL);
77 if (enable)
78 val |= PCL_APP_LTSSM_ENABLE;
79 else
80 val &= ~PCL_APP_LTSSM_ENABLE;
81 writel(val, priv->base + PCL_APP_READY_CTRL);
82}
83
84static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
85{
86 u32 val;
87
88 /* use auxiliary power detection */
89 val = readl(priv->base + PCL_APP_PM0);
90 val |= PCL_SYS_AUX_PWR_DET;
91 writel(val, priv->base + PCL_APP_PM0);
92
93 /* assert PERST# */
94 val = readl(priv->base + PCL_PINCTRL0);
95 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
96 | PCL_PERST_PLDN_REGVAL);
97 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
98 | PCL_PERST_PLDN_REGEN;
99 writel(val, priv->base + PCL_PINCTRL0);
100
101 uniphier_pcie_ltssm_enable(priv, false);
102
103 usleep_range(100000, 200000);
104
105 /* deassert PERST# */
106 val = readl(priv->base + PCL_PINCTRL0);
107 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
108 writel(val, priv->base + PCL_PINCTRL0);
109}
110
111static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
112{
113 u32 status;
114 int ret;
115
116 /* wait PIPE clock */
117 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
118 status & PCL_PCLK_ALIVE, 100000, 1000000);
119 if (ret) {
120 dev_err(priv->pci.dev,
121 "Failed to initialize controller in RC mode\n");
122 return ret;
123 }
124
125 return 0;
126}
127
128static int uniphier_pcie_link_up(struct dw_pcie *pci)
129{
130 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
131 u32 val, mask;
132
133 val = readl(priv->base + PCL_STATUS_LINK);
134 mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
135
136 return (val & mask) == mask;
137}
138
139static int uniphier_pcie_establish_link(struct dw_pcie *pci)
140{
141 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
142
143 if (dw_pcie_link_up(pci))
144 return 0;
145
146 uniphier_pcie_ltssm_enable(priv, true);
147
148 return dw_pcie_wait_for_link(pci);
149}
150
151static void uniphier_pcie_stop_link(struct dw_pcie *pci)
152{
153 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
154
155 uniphier_pcie_ltssm_enable(priv, false);
156}
157
158static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
159{
160 writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
161 writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
162}
163
164static void uniphier_pcie_irq_disable(struct uniphier_pcie_priv *priv)
165{
166 writel(0, priv->base + PCL_RCV_INT);
167 writel(0, priv->base + PCL_RCV_INTX);
168}
169
170static void uniphier_pcie_irq_ack(struct irq_data *d)
171{
172 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
173 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
174 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
175 u32 val;
176
177 val = readl(priv->base + PCL_RCV_INTX);
178 val &= ~PCL_RCV_INTX_ALL_STATUS;
179 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
180 writel(val, priv->base + PCL_RCV_INTX);
181}
182
183static void uniphier_pcie_irq_mask(struct irq_data *d)
184{
185 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
186 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
187 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
188 u32 val;
189
190 val = readl(priv->base + PCL_RCV_INTX);
191 val &= ~PCL_RCV_INTX_ALL_MASK;
192 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
193 writel(val, priv->base + PCL_RCV_INTX);
194}
195
196static void uniphier_pcie_irq_unmask(struct irq_data *d)
197{
198 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
199 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
200 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
201 u32 val;
202
203 val = readl(priv->base + PCL_RCV_INTX);
204 val &= ~PCL_RCV_INTX_ALL_MASK;
205 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
206 writel(val, priv->base + PCL_RCV_INTX);
207}
208
209static struct irq_chip uniphier_pcie_irq_chip = {
210 .name = "PCI",
211 .irq_ack = uniphier_pcie_irq_ack,
212 .irq_mask = uniphier_pcie_irq_mask,
213 .irq_unmask = uniphier_pcie_irq_unmask,
214};
215
216static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
217 irq_hw_number_t hwirq)
218{
219 irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
220 handle_level_irq);
221 irq_set_chip_data(irq, domain->host_data);
222
223 return 0;
224}
225
226static const struct irq_domain_ops uniphier_intx_domain_ops = {
227 .map = uniphier_pcie_intx_map,
228};
229
230static void uniphier_pcie_irq_handler(struct irq_desc *desc)
231{
232 struct pcie_port *pp = irq_desc_get_handler_data(desc);
233 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
234 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
235 struct irq_chip *chip = irq_desc_get_chip(desc);
236 unsigned long reg;
237 u32 val, bit, virq;
238
239 /* INT for debug */
240 val = readl(priv->base + PCL_RCV_INT);
241
242 if (val & PCL_CFG_BW_MGT_STATUS)
243 dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
244 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
245 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
246 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
247 dev_dbg(pci->dev, "Root Error\n");
248 if (val & PCL_CFG_PME_MSI_STATUS)
249 dev_dbg(pci->dev, "PME Interrupt\n");
250
251 writel(val, priv->base + PCL_RCV_INT);
252
253 /* INTx */
254 chained_irq_enter(chip, desc);
255
256 val = readl(priv->base + PCL_RCV_INTX);
257 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
258
259 for_each_set_bit(bit, ®, PCI_NUM_INTX) {
260 virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
261 generic_handle_irq(virq);
262 }
263
264 chained_irq_exit(chip, desc);
265}
266
267static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
268{
269 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
270 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
271 struct device_node *np = pci->dev->of_node;
272 struct device_node *np_intc;
273 int ret = 0;
274
275 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
276 if (!np_intc) {
277 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
278 return -EINVAL;
279 }
280
281 pp->irq = irq_of_parse_and_map(np_intc, 0);
282 if (!pp->irq) {
283 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
284 ret = -EINVAL;
285 goto out_put_node;
286 }
287
288 priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
289 &uniphier_intx_domain_ops, pp);
290 if (!priv->legacy_irq_domain) {
291 dev_err(pci->dev, "Failed to get INTx domain\n");
292 ret = -ENODEV;
293 goto out_put_node;
294 }
295
296 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
297 pp);
298
299out_put_node:
300 of_node_put(np_intc);
301 return ret;
302}
303
304static int uniphier_pcie_host_init(struct pcie_port *pp)
305{
306 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
307 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
308 int ret;
309
310 ret = uniphier_pcie_config_legacy_irq(pp);
311 if (ret)
312 return ret;
313
314 uniphier_pcie_irq_enable(priv);
315
316 dw_pcie_setup_rc(pp);
317 ret = uniphier_pcie_establish_link(pci);
318 if (ret)
319 return ret;
320
321 if (IS_ENABLED(CONFIG_PCI_MSI))
322 dw_pcie_msi_init(pp);
323
324 return 0;
325}
326
327static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
328 .host_init = uniphier_pcie_host_init,
329};
330
331static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
332 struct platform_device *pdev)
333{
334 struct dw_pcie *pci = &priv->pci;
335 struct pcie_port *pp = &pci->pp;
336 struct device *dev = &pdev->dev;
337 int ret;
338
339 pp->ops = &uniphier_pcie_host_ops;
340
341 if (IS_ENABLED(CONFIG_PCI_MSI)) {
342 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
343 if (pp->msi_irq < 0)
344 return pp->msi_irq;
345 }
346
347 ret = dw_pcie_host_init(pp);
348 if (ret) {
349 dev_err(dev, "Failed to initialize host (%d)\n", ret);
350 return ret;
351 }
352
353 return 0;
354}
355
356static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
357{
358 int ret;
359
360 ret = clk_prepare_enable(priv->clk);
361 if (ret)
362 return ret;
363
364 ret = reset_control_deassert(priv->rst);
365 if (ret)
366 goto out_clk_disable;
367
368 uniphier_pcie_init_rc(priv);
369
370 ret = phy_init(priv->phy);
371 if (ret)
372 goto out_rst_assert;
373
374 ret = uniphier_pcie_wait_rc(priv);
375 if (ret)
376 goto out_phy_exit;
377
378 return 0;
379
380out_phy_exit:
381 phy_exit(priv->phy);
382out_rst_assert:
383 reset_control_assert(priv->rst);
384out_clk_disable:
385 clk_disable_unprepare(priv->clk);
386
387 return ret;
388}
389
390static void uniphier_pcie_host_disable(struct uniphier_pcie_priv *priv)
391{
392 uniphier_pcie_irq_disable(priv);
393 phy_exit(priv->phy);
394 reset_control_assert(priv->rst);
395 clk_disable_unprepare(priv->clk);
396}
397
398static const struct dw_pcie_ops dw_pcie_ops = {
399 .start_link = uniphier_pcie_establish_link,
400 .stop_link = uniphier_pcie_stop_link,
401 .link_up = uniphier_pcie_link_up,
402};
403
404static int uniphier_pcie_probe(struct platform_device *pdev)
405{
406 struct device *dev = &pdev->dev;
407 struct uniphier_pcie_priv *priv;
408 struct resource *res;
409 int ret;
410
411 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
412 if (!priv)
413 return -ENOMEM;
414
415 priv->pci.dev = dev;
416 priv->pci.ops = &dw_pcie_ops;
417
418 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
419 priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
420 if (IS_ERR(priv->pci.dbi_base))
421 return PTR_ERR(priv->pci.dbi_base);
422
423 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link");
424 priv->base = devm_ioremap_resource(dev, res);
425 if (IS_ERR(priv->base))
426 return PTR_ERR(priv->base);
427
428 priv->clk = devm_clk_get(dev, NULL);
429 if (IS_ERR(priv->clk))
430 return PTR_ERR(priv->clk);
431
432 priv->rst = devm_reset_control_get_shared(dev, NULL);
433 if (IS_ERR(priv->rst))
434 return PTR_ERR(priv->rst);
435
436 priv->phy = devm_phy_optional_get(dev, "pcie-phy");
437 if (IS_ERR(priv->phy))
438 return PTR_ERR(priv->phy);
439
440 platform_set_drvdata(pdev, priv);
441
442 ret = uniphier_pcie_host_enable(priv);
443 if (ret)
444 return ret;
445
446 return uniphier_add_pcie_port(priv, pdev);
447}
448
449static int uniphier_pcie_remove(struct platform_device *pdev)
450{
451 struct uniphier_pcie_priv *priv = platform_get_drvdata(pdev);
452
453 uniphier_pcie_host_disable(priv);
454
455 return 0;
456}
457
458static const struct of_device_id uniphier_pcie_match[] = {
459 { .compatible = "socionext,uniphier-pcie", },
460 { /* sentinel */ },
461};
462MODULE_DEVICE_TABLE(of, uniphier_pcie_match);
463
464static struct platform_driver uniphier_pcie_driver = {
465 .probe = uniphier_pcie_probe,
466 .remove = uniphier_pcie_remove,
467 .driver = {
468 .name = "uniphier-pcie",
469 .of_match_table = uniphier_pcie_match,
470 },
471};
472builtin_platform_driver(uniphier_pcie_driver);
473
474MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
475MODULE_DESCRIPTION("UniPhier PCIe host controller driver");
476MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for UniPhier SoCs
4 * Copyright 2018 Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22
23#include "pcie-designware.h"
24
25#define PCL_PINCTRL0 0x002c
26#define PCL_PERST_PLDN_REGEN BIT(12)
27#define PCL_PERST_NOE_REGEN BIT(11)
28#define PCL_PERST_OUT_REGEN BIT(8)
29#define PCL_PERST_PLDN_REGVAL BIT(4)
30#define PCL_PERST_NOE_REGVAL BIT(3)
31#define PCL_PERST_OUT_REGVAL BIT(0)
32
33#define PCL_PIPEMON 0x0044
34#define PCL_PCLK_ALIVE BIT(15)
35
36#define PCL_MODE 0x8000
37#define PCL_MODE_REGEN BIT(8)
38#define PCL_MODE_REGVAL BIT(0)
39
40#define PCL_APP_READY_CTRL 0x8008
41#define PCL_APP_LTSSM_ENABLE BIT(0)
42
43#define PCL_APP_PM0 0x8078
44#define PCL_SYS_AUX_PWR_DET BIT(8)
45
46#define PCL_RCV_INT 0x8108
47#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
48#define PCL_CFG_BW_MGT_STATUS BIT(4)
49#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
50#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
51#define PCL_CFG_PME_MSI_STATUS BIT(1)
52
53#define PCL_RCV_INTX 0x810c
54#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
55#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
56#define PCL_RCV_INTX_MASK_SHIFT 8
57#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
58#define PCL_RCV_INTX_STATUS_SHIFT 0
59
60#define PCL_STATUS_LINK 0x8140
61#define PCL_RDLH_LINK_UP BIT(1)
62#define PCL_XMLH_LINK_UP BIT(0)
63
64struct uniphier_pcie_priv {
65 void __iomem *base;
66 struct dw_pcie pci;
67 struct clk *clk;
68 struct reset_control *rst;
69 struct phy *phy;
70 struct irq_domain *legacy_irq_domain;
71};
72
73#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
74
75static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
76 bool enable)
77{
78 u32 val;
79
80 val = readl(priv->base + PCL_APP_READY_CTRL);
81 if (enable)
82 val |= PCL_APP_LTSSM_ENABLE;
83 else
84 val &= ~PCL_APP_LTSSM_ENABLE;
85 writel(val, priv->base + PCL_APP_READY_CTRL);
86}
87
88static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
89{
90 u32 val;
91
92 /* set RC MODE */
93 val = readl(priv->base + PCL_MODE);
94 val |= PCL_MODE_REGEN;
95 val &= ~PCL_MODE_REGVAL;
96 writel(val, priv->base + PCL_MODE);
97
98 /* use auxiliary power detection */
99 val = readl(priv->base + PCL_APP_PM0);
100 val |= PCL_SYS_AUX_PWR_DET;
101 writel(val, priv->base + PCL_APP_PM0);
102
103 /* assert PERST# */
104 val = readl(priv->base + PCL_PINCTRL0);
105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
106 | PCL_PERST_PLDN_REGVAL);
107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
108 | PCL_PERST_PLDN_REGEN;
109 writel(val, priv->base + PCL_PINCTRL0);
110
111 uniphier_pcie_ltssm_enable(priv, false);
112
113 usleep_range(100000, 200000);
114
115 /* deassert PERST# */
116 val = readl(priv->base + PCL_PINCTRL0);
117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 writel(val, priv->base + PCL_PINCTRL0);
119}
120
121static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
122{
123 u32 status;
124 int ret;
125
126 /* wait PIPE clock */
127 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
128 status & PCL_PCLK_ALIVE, 100000, 1000000);
129 if (ret) {
130 dev_err(priv->pci.dev,
131 "Failed to initialize controller in RC mode\n");
132 return ret;
133 }
134
135 return 0;
136}
137
138static int uniphier_pcie_link_up(struct dw_pcie *pci)
139{
140 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
141 u32 val, mask;
142
143 val = readl(priv->base + PCL_STATUS_LINK);
144 mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
145
146 return (val & mask) == mask;
147}
148
149static int uniphier_pcie_establish_link(struct dw_pcie *pci)
150{
151 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
152
153 if (dw_pcie_link_up(pci))
154 return 0;
155
156 uniphier_pcie_ltssm_enable(priv, true);
157
158 return dw_pcie_wait_for_link(pci);
159}
160
161static void uniphier_pcie_stop_link(struct dw_pcie *pci)
162{
163 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
164
165 uniphier_pcie_ltssm_enable(priv, false);
166}
167
168static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
169{
170 writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
171 writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
172}
173
174static void uniphier_pcie_irq_ack(struct irq_data *d)
175{
176 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
177 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
178 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
179 u32 val;
180
181 val = readl(priv->base + PCL_RCV_INTX);
182 val &= ~PCL_RCV_INTX_ALL_STATUS;
183 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
184 writel(val, priv->base + PCL_RCV_INTX);
185}
186
187static void uniphier_pcie_irq_mask(struct irq_data *d)
188{
189 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
190 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
191 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
192 u32 val;
193
194 val = readl(priv->base + PCL_RCV_INTX);
195 val &= ~PCL_RCV_INTX_ALL_MASK;
196 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
197 writel(val, priv->base + PCL_RCV_INTX);
198}
199
200static void uniphier_pcie_irq_unmask(struct irq_data *d)
201{
202 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
203 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
204 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
205 u32 val;
206
207 val = readl(priv->base + PCL_RCV_INTX);
208 val &= ~PCL_RCV_INTX_ALL_MASK;
209 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
210 writel(val, priv->base + PCL_RCV_INTX);
211}
212
213static struct irq_chip uniphier_pcie_irq_chip = {
214 .name = "PCI",
215 .irq_ack = uniphier_pcie_irq_ack,
216 .irq_mask = uniphier_pcie_irq_mask,
217 .irq_unmask = uniphier_pcie_irq_unmask,
218};
219
220static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
221 irq_hw_number_t hwirq)
222{
223 irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
224 handle_level_irq);
225 irq_set_chip_data(irq, domain->host_data);
226
227 return 0;
228}
229
230static const struct irq_domain_ops uniphier_intx_domain_ops = {
231 .map = uniphier_pcie_intx_map,
232};
233
234static void uniphier_pcie_irq_handler(struct irq_desc *desc)
235{
236 struct pcie_port *pp = irq_desc_get_handler_data(desc);
237 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
238 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
239 struct irq_chip *chip = irq_desc_get_chip(desc);
240 unsigned long reg;
241 u32 val, bit, virq;
242
243 /* INT for debug */
244 val = readl(priv->base + PCL_RCV_INT);
245
246 if (val & PCL_CFG_BW_MGT_STATUS)
247 dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
248 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
249 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
250 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
251 dev_dbg(pci->dev, "Root Error\n");
252 if (val & PCL_CFG_PME_MSI_STATUS)
253 dev_dbg(pci->dev, "PME Interrupt\n");
254
255 writel(val, priv->base + PCL_RCV_INT);
256
257 /* INTx */
258 chained_irq_enter(chip, desc);
259
260 val = readl(priv->base + PCL_RCV_INTX);
261 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
262
263 for_each_set_bit(bit, ®, PCI_NUM_INTX) {
264 virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
265 generic_handle_irq(virq);
266 }
267
268 chained_irq_exit(chip, desc);
269}
270
271static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
272{
273 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
274 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
275 struct device_node *np = pci->dev->of_node;
276 struct device_node *np_intc;
277 int ret = 0;
278
279 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
280 if (!np_intc) {
281 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
282 return -EINVAL;
283 }
284
285 pp->irq = irq_of_parse_and_map(np_intc, 0);
286 if (!pp->irq) {
287 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
288 ret = -EINVAL;
289 goto out_put_node;
290 }
291
292 priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
293 &uniphier_intx_domain_ops, pp);
294 if (!priv->legacy_irq_domain) {
295 dev_err(pci->dev, "Failed to get INTx domain\n");
296 ret = -ENODEV;
297 goto out_put_node;
298 }
299
300 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
301 pp);
302
303out_put_node:
304 of_node_put(np_intc);
305 return ret;
306}
307
308static int uniphier_pcie_host_init(struct pcie_port *pp)
309{
310 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
311 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
312 int ret;
313
314 ret = uniphier_pcie_config_legacy_irq(pp);
315 if (ret)
316 return ret;
317
318 uniphier_pcie_irq_enable(priv);
319
320 dw_pcie_setup_rc(pp);
321 ret = uniphier_pcie_establish_link(pci);
322 if (ret)
323 return ret;
324
325 if (IS_ENABLED(CONFIG_PCI_MSI))
326 dw_pcie_msi_init(pp);
327
328 return 0;
329}
330
331static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
332 .host_init = uniphier_pcie_host_init,
333};
334
335static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
336 struct platform_device *pdev)
337{
338 struct dw_pcie *pci = &priv->pci;
339 struct pcie_port *pp = &pci->pp;
340 struct device *dev = &pdev->dev;
341 int ret;
342
343 pp->ops = &uniphier_pcie_host_ops;
344
345 if (IS_ENABLED(CONFIG_PCI_MSI)) {
346 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
347 if (pp->msi_irq < 0)
348 return pp->msi_irq;
349 }
350
351 ret = dw_pcie_host_init(pp);
352 if (ret) {
353 dev_err(dev, "Failed to initialize host (%d)\n", ret);
354 return ret;
355 }
356
357 return 0;
358}
359
360static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
361{
362 int ret;
363
364 ret = clk_prepare_enable(priv->clk);
365 if (ret)
366 return ret;
367
368 ret = reset_control_deassert(priv->rst);
369 if (ret)
370 goto out_clk_disable;
371
372 uniphier_pcie_init_rc(priv);
373
374 ret = phy_init(priv->phy);
375 if (ret)
376 goto out_rst_assert;
377
378 ret = uniphier_pcie_wait_rc(priv);
379 if (ret)
380 goto out_phy_exit;
381
382 return 0;
383
384out_phy_exit:
385 phy_exit(priv->phy);
386out_rst_assert:
387 reset_control_assert(priv->rst);
388out_clk_disable:
389 clk_disable_unprepare(priv->clk);
390
391 return ret;
392}
393
394static const struct dw_pcie_ops dw_pcie_ops = {
395 .start_link = uniphier_pcie_establish_link,
396 .stop_link = uniphier_pcie_stop_link,
397 .link_up = uniphier_pcie_link_up,
398};
399
400static int uniphier_pcie_probe(struct platform_device *pdev)
401{
402 struct device *dev = &pdev->dev;
403 struct uniphier_pcie_priv *priv;
404 struct resource *res;
405 int ret;
406
407 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
408 if (!priv)
409 return -ENOMEM;
410
411 priv->pci.dev = dev;
412 priv->pci.ops = &dw_pcie_ops;
413
414 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
415 priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
416 if (IS_ERR(priv->pci.dbi_base))
417 return PTR_ERR(priv->pci.dbi_base);
418
419 priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
420 if (IS_ERR(priv->base))
421 return PTR_ERR(priv->base);
422
423 priv->clk = devm_clk_get(dev, NULL);
424 if (IS_ERR(priv->clk))
425 return PTR_ERR(priv->clk);
426
427 priv->rst = devm_reset_control_get_shared(dev, NULL);
428 if (IS_ERR(priv->rst))
429 return PTR_ERR(priv->rst);
430
431 priv->phy = devm_phy_optional_get(dev, "pcie-phy");
432 if (IS_ERR(priv->phy))
433 return PTR_ERR(priv->phy);
434
435 platform_set_drvdata(pdev, priv);
436
437 ret = uniphier_pcie_host_enable(priv);
438 if (ret)
439 return ret;
440
441 return uniphier_add_pcie_port(priv, pdev);
442}
443
444static const struct of_device_id uniphier_pcie_match[] = {
445 { .compatible = "socionext,uniphier-pcie", },
446 { /* sentinel */ },
447};
448
449static struct platform_driver uniphier_pcie_driver = {
450 .probe = uniphier_pcie_probe,
451 .driver = {
452 .name = "uniphier-pcie",
453 .of_match_table = uniphier_pcie_match,
454 },
455};
456builtin_platform_driver(uniphier_pcie_driver);