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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ST SPEAr ADC driver
4 *
5 * Copyright 2012 Stefan Roese <sr@denx.de>
6 */
7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/completion.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23
24/* SPEAR registers definitions */
25#define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
26#define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
27#define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
28#define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
29
30/* Bit definitions for SPEAR_ADC_STATUS */
31#define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
32#define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
33#define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
34#define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
35#define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
36
37#define SPEAR_ADC_DATA_MASK 0x03ff
38#define SPEAR_ADC_DATA_BITS 10
39
40#define SPEAR_ADC_MOD_NAME "spear-adc"
41
42#define SPEAR_ADC_CHANNEL_NUM 8
43
44#define SPEAR_ADC_CLK_MIN 2500000
45#define SPEAR_ADC_CLK_MAX 20000000
46
47struct adc_regs_spear3xx {
48 u32 status;
49 u32 average;
50 u32 scan_rate;
51 u32 clk; /* Not avail for 1340 & 1310 */
52 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
53 u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
54};
55
56struct chan_data {
57 u32 lsb;
58 u32 msb;
59};
60
61struct adc_regs_spear6xx {
62 u32 status;
63 u32 pad[2];
64 u32 clk;
65 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
66 struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
67 u32 scan_rate_lo;
68 u32 scan_rate_hi;
69 struct chan_data average;
70};
71
72struct spear_adc_state {
73 struct device_node *np;
74 struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
75 struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
76 struct clk *clk;
77 struct completion completion;
78 u32 current_clk;
79 u32 sampling_freq;
80 u32 avg_samples;
81 u32 vref_external;
82 u32 value;
83};
84
85/*
86 * Functions to access some SPEAr ADC register. Abstracted into
87 * static inline functions, because of different register offsets
88 * on different SoC variants (SPEAr300 vs SPEAr600 etc).
89 */
90static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
91{
92 __raw_writel(val, &st->adc_base_spear6xx->status);
93}
94
95static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
96{
97 u32 clk_high, clk_low, count;
98 u32 apb_clk = clk_get_rate(st->clk);
99
100 count = DIV_ROUND_UP(apb_clk, val);
101 clk_low = count / 2;
102 clk_high = count - clk_low;
103 st->current_clk = apb_clk / count;
104
105 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
106 &st->adc_base_spear6xx->clk);
107}
108
109static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
110 u32 val)
111{
112 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
113}
114
115static u32 spear_adc_get_average(struct spear_adc_state *st)
116{
117 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
118 return __raw_readl(&st->adc_base_spear6xx->average.msb) &
119 SPEAR_ADC_DATA_MASK;
120 } else {
121 return __raw_readl(&st->adc_base_spear3xx->average) &
122 SPEAR_ADC_DATA_MASK;
123 }
124}
125
126static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
127{
128 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
129 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
130 &st->adc_base_spear6xx->scan_rate_lo);
131 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
132 &st->adc_base_spear6xx->scan_rate_hi);
133 } else {
134 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
135 }
136}
137
138static int spear_adc_read_raw(struct iio_dev *indio_dev,
139 struct iio_chan_spec const *chan,
140 int *val,
141 int *val2,
142 long mask)
143{
144 struct spear_adc_state *st = iio_priv(indio_dev);
145 u32 status;
146
147 switch (mask) {
148 case IIO_CHAN_INFO_RAW:
149 mutex_lock(&indio_dev->mlock);
150
151 status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
152 SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
153 SPEAR_ADC_STATUS_START_CONVERSION |
154 SPEAR_ADC_STATUS_ADC_ENABLE;
155 if (st->vref_external == 0)
156 status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
157
158 spear_adc_set_status(st, status);
159 wait_for_completion(&st->completion); /* set by ISR */
160 *val = st->value;
161
162 mutex_unlock(&indio_dev->mlock);
163
164 return IIO_VAL_INT;
165
166 case IIO_CHAN_INFO_SCALE:
167 *val = st->vref_external;
168 *val2 = SPEAR_ADC_DATA_BITS;
169 return IIO_VAL_FRACTIONAL_LOG2;
170 case IIO_CHAN_INFO_SAMP_FREQ:
171 *val = st->current_clk;
172 return IIO_VAL_INT;
173 }
174
175 return -EINVAL;
176}
177
178static int spear_adc_write_raw(struct iio_dev *indio_dev,
179 struct iio_chan_spec const *chan,
180 int val,
181 int val2,
182 long mask)
183{
184 struct spear_adc_state *st = iio_priv(indio_dev);
185 int ret = 0;
186
187 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
188 return -EINVAL;
189
190 mutex_lock(&indio_dev->mlock);
191
192 if ((val < SPEAR_ADC_CLK_MIN) ||
193 (val > SPEAR_ADC_CLK_MAX) ||
194 (val2 != 0)) {
195 ret = -EINVAL;
196 goto out;
197 }
198
199 spear_adc_set_clk(st, val);
200
201out:
202 mutex_unlock(&indio_dev->mlock);
203 return ret;
204}
205
206#define SPEAR_ADC_CHAN(idx) { \
207 .type = IIO_VOLTAGE, \
208 .indexed = 1, \
209 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
210 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
211 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
212 .channel = idx, \
213}
214
215static const struct iio_chan_spec spear_adc_iio_channels[] = {
216 SPEAR_ADC_CHAN(0),
217 SPEAR_ADC_CHAN(1),
218 SPEAR_ADC_CHAN(2),
219 SPEAR_ADC_CHAN(3),
220 SPEAR_ADC_CHAN(4),
221 SPEAR_ADC_CHAN(5),
222 SPEAR_ADC_CHAN(6),
223 SPEAR_ADC_CHAN(7),
224};
225
226static irqreturn_t spear_adc_isr(int irq, void *dev_id)
227{
228 struct spear_adc_state *st = dev_id;
229
230 /* Read value to clear IRQ */
231 st->value = spear_adc_get_average(st);
232 complete(&st->completion);
233
234 return IRQ_HANDLED;
235}
236
237static int spear_adc_configure(struct spear_adc_state *st)
238{
239 int i;
240
241 /* Reset ADC core */
242 spear_adc_set_status(st, 0);
243 __raw_writel(0, &st->adc_base_spear6xx->clk);
244 for (i = 0; i < 8; i++)
245 spear_adc_set_ctrl(st, i, 0);
246 spear_adc_set_scanrate(st, 0);
247
248 spear_adc_set_clk(st, st->sampling_freq);
249
250 return 0;
251}
252
253static const struct iio_info spear_adc_info = {
254 .read_raw = &spear_adc_read_raw,
255 .write_raw = &spear_adc_write_raw,
256};
257
258static int spear_adc_probe(struct platform_device *pdev)
259{
260 struct device_node *np = pdev->dev.of_node;
261 struct device *dev = &pdev->dev;
262 struct spear_adc_state *st;
263 struct resource *res;
264 struct iio_dev *indio_dev = NULL;
265 int ret = -ENODEV;
266 int irq;
267
268 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
269 if (!indio_dev) {
270 dev_err(dev, "failed allocating iio device\n");
271 return -ENOMEM;
272 }
273
274 st = iio_priv(indio_dev);
275 st->np = np;
276
277 /*
278 * SPEAr600 has a different register layout than other SPEAr SoC's
279 * (e.g. SPEAr3xx). Let's provide two register base addresses
280 * to support multi-arch kernels.
281 */
282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283 st->adc_base_spear6xx = devm_ioremap_resource(&pdev->dev, res);
284 if (IS_ERR(st->adc_base_spear6xx))
285 return PTR_ERR(st->adc_base_spear6xx);
286
287 st->adc_base_spear3xx =
288 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
289
290 st->clk = devm_clk_get(dev, NULL);
291 if (IS_ERR(st->clk)) {
292 dev_err(dev, "failed getting clock\n");
293 return PTR_ERR(st->clk);
294 }
295
296 ret = clk_prepare_enable(st->clk);
297 if (ret) {
298 dev_err(dev, "failed enabling clock\n");
299 return ret;
300 }
301
302 irq = platform_get_irq(pdev, 0);
303 if (irq <= 0) {
304 ret = -EINVAL;
305 goto errout2;
306 }
307
308 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
309 st);
310 if (ret < 0) {
311 dev_err(dev, "failed requesting interrupt\n");
312 goto errout2;
313 }
314
315 if (of_property_read_u32(np, "sampling-frequency",
316 &st->sampling_freq)) {
317 dev_err(dev, "sampling-frequency missing in DT\n");
318 ret = -EINVAL;
319 goto errout2;
320 }
321
322 /*
323 * Optional avg_samples defaults to 0, resulting in single data
324 * conversion
325 */
326 of_property_read_u32(np, "average-samples", &st->avg_samples);
327
328 /*
329 * Optional vref_external defaults to 0, resulting in internal vref
330 * selection
331 */
332 of_property_read_u32(np, "vref-external", &st->vref_external);
333
334 spear_adc_configure(st);
335
336 platform_set_drvdata(pdev, indio_dev);
337
338 init_completion(&st->completion);
339
340 indio_dev->name = SPEAR_ADC_MOD_NAME;
341 indio_dev->dev.parent = dev;
342 indio_dev->info = &spear_adc_info;
343 indio_dev->modes = INDIO_DIRECT_MODE;
344 indio_dev->channels = spear_adc_iio_channels;
345 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
346
347 ret = iio_device_register(indio_dev);
348 if (ret)
349 goto errout2;
350
351 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
352
353 return 0;
354
355errout2:
356 clk_disable_unprepare(st->clk);
357 return ret;
358}
359
360static int spear_adc_remove(struct platform_device *pdev)
361{
362 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
363 struct spear_adc_state *st = iio_priv(indio_dev);
364
365 iio_device_unregister(indio_dev);
366 clk_disable_unprepare(st->clk);
367
368 return 0;
369}
370
371#ifdef CONFIG_OF
372static const struct of_device_id spear_adc_dt_ids[] = {
373 { .compatible = "st,spear600-adc", },
374 { /* sentinel */ }
375};
376MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
377#endif
378
379static struct platform_driver spear_adc_driver = {
380 .probe = spear_adc_probe,
381 .remove = spear_adc_remove,
382 .driver = {
383 .name = SPEAR_ADC_MOD_NAME,
384 .of_match_table = of_match_ptr(spear_adc_dt_ids),
385 },
386};
387
388module_platform_driver(spear_adc_driver);
389
390MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
391MODULE_DESCRIPTION("SPEAr ADC driver");
392MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ST SPEAr ADC driver
4 *
5 * Copyright 2012 Stefan Roese <sr@denx.de>
6 */
7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/completion.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23
24/* SPEAR registers definitions */
25#define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
26#define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
27#define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
28#define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
29
30/* Bit definitions for SPEAR_ADC_STATUS */
31#define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
32#define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
33#define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
34#define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
35#define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
36
37#define SPEAR_ADC_DATA_MASK 0x03ff
38#define SPEAR_ADC_DATA_BITS 10
39
40#define SPEAR_ADC_MOD_NAME "spear-adc"
41
42#define SPEAR_ADC_CHANNEL_NUM 8
43
44#define SPEAR_ADC_CLK_MIN 2500000
45#define SPEAR_ADC_CLK_MAX 20000000
46
47struct adc_regs_spear3xx {
48 u32 status;
49 u32 average;
50 u32 scan_rate;
51 u32 clk; /* Not avail for 1340 & 1310 */
52 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
53 u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
54};
55
56struct chan_data {
57 u32 lsb;
58 u32 msb;
59};
60
61struct adc_regs_spear6xx {
62 u32 status;
63 u32 pad[2];
64 u32 clk;
65 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
66 struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
67 u32 scan_rate_lo;
68 u32 scan_rate_hi;
69 struct chan_data average;
70};
71
72struct spear_adc_state {
73 struct device_node *np;
74 struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
75 struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
76 struct clk *clk;
77 struct completion completion;
78 u32 current_clk;
79 u32 sampling_freq;
80 u32 avg_samples;
81 u32 vref_external;
82 u32 value;
83};
84
85/*
86 * Functions to access some SPEAr ADC register. Abstracted into
87 * static inline functions, because of different register offsets
88 * on different SoC variants (SPEAr300 vs SPEAr600 etc).
89 */
90static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
91{
92 __raw_writel(val, &st->adc_base_spear6xx->status);
93}
94
95static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
96{
97 u32 clk_high, clk_low, count;
98 u32 apb_clk = clk_get_rate(st->clk);
99
100 count = DIV_ROUND_UP(apb_clk, val);
101 clk_low = count / 2;
102 clk_high = count - clk_low;
103 st->current_clk = apb_clk / count;
104
105 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
106 &st->adc_base_spear6xx->clk);
107}
108
109static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
110 u32 val)
111{
112 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
113}
114
115static u32 spear_adc_get_average(struct spear_adc_state *st)
116{
117 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
118 return __raw_readl(&st->adc_base_spear6xx->average.msb) &
119 SPEAR_ADC_DATA_MASK;
120 } else {
121 return __raw_readl(&st->adc_base_spear3xx->average) &
122 SPEAR_ADC_DATA_MASK;
123 }
124}
125
126static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
127{
128 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
129 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
130 &st->adc_base_spear6xx->scan_rate_lo);
131 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
132 &st->adc_base_spear6xx->scan_rate_hi);
133 } else {
134 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
135 }
136}
137
138static int spear_adc_read_raw(struct iio_dev *indio_dev,
139 struct iio_chan_spec const *chan,
140 int *val,
141 int *val2,
142 long mask)
143{
144 struct spear_adc_state *st = iio_priv(indio_dev);
145 u32 status;
146
147 switch (mask) {
148 case IIO_CHAN_INFO_RAW:
149 mutex_lock(&indio_dev->mlock);
150
151 status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
152 SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
153 SPEAR_ADC_STATUS_START_CONVERSION |
154 SPEAR_ADC_STATUS_ADC_ENABLE;
155 if (st->vref_external == 0)
156 status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
157
158 spear_adc_set_status(st, status);
159 wait_for_completion(&st->completion); /* set by ISR */
160 *val = st->value;
161
162 mutex_unlock(&indio_dev->mlock);
163
164 return IIO_VAL_INT;
165
166 case IIO_CHAN_INFO_SCALE:
167 *val = st->vref_external;
168 *val2 = SPEAR_ADC_DATA_BITS;
169 return IIO_VAL_FRACTIONAL_LOG2;
170 case IIO_CHAN_INFO_SAMP_FREQ:
171 *val = st->current_clk;
172 return IIO_VAL_INT;
173 }
174
175 return -EINVAL;
176}
177
178static int spear_adc_write_raw(struct iio_dev *indio_dev,
179 struct iio_chan_spec const *chan,
180 int val,
181 int val2,
182 long mask)
183{
184 struct spear_adc_state *st = iio_priv(indio_dev);
185 int ret = 0;
186
187 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
188 return -EINVAL;
189
190 mutex_lock(&indio_dev->mlock);
191
192 if ((val < SPEAR_ADC_CLK_MIN) ||
193 (val > SPEAR_ADC_CLK_MAX) ||
194 (val2 != 0)) {
195 ret = -EINVAL;
196 goto out;
197 }
198
199 spear_adc_set_clk(st, val);
200
201out:
202 mutex_unlock(&indio_dev->mlock);
203 return ret;
204}
205
206#define SPEAR_ADC_CHAN(idx) { \
207 .type = IIO_VOLTAGE, \
208 .indexed = 1, \
209 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
210 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
211 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
212 .channel = idx, \
213}
214
215static const struct iio_chan_spec spear_adc_iio_channels[] = {
216 SPEAR_ADC_CHAN(0),
217 SPEAR_ADC_CHAN(1),
218 SPEAR_ADC_CHAN(2),
219 SPEAR_ADC_CHAN(3),
220 SPEAR_ADC_CHAN(4),
221 SPEAR_ADC_CHAN(5),
222 SPEAR_ADC_CHAN(6),
223 SPEAR_ADC_CHAN(7),
224};
225
226static irqreturn_t spear_adc_isr(int irq, void *dev_id)
227{
228 struct spear_adc_state *st = dev_id;
229
230 /* Read value to clear IRQ */
231 st->value = spear_adc_get_average(st);
232 complete(&st->completion);
233
234 return IRQ_HANDLED;
235}
236
237static int spear_adc_configure(struct spear_adc_state *st)
238{
239 int i;
240
241 /* Reset ADC core */
242 spear_adc_set_status(st, 0);
243 __raw_writel(0, &st->adc_base_spear6xx->clk);
244 for (i = 0; i < 8; i++)
245 spear_adc_set_ctrl(st, i, 0);
246 spear_adc_set_scanrate(st, 0);
247
248 spear_adc_set_clk(st, st->sampling_freq);
249
250 return 0;
251}
252
253static const struct iio_info spear_adc_info = {
254 .read_raw = &spear_adc_read_raw,
255 .write_raw = &spear_adc_write_raw,
256};
257
258static int spear_adc_probe(struct platform_device *pdev)
259{
260 struct device_node *np = pdev->dev.of_node;
261 struct device *dev = &pdev->dev;
262 struct spear_adc_state *st;
263 struct iio_dev *indio_dev = NULL;
264 int ret = -ENODEV;
265 int irq;
266
267 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
268 if (!indio_dev) {
269 dev_err(dev, "failed allocating iio device\n");
270 return -ENOMEM;
271 }
272
273 st = iio_priv(indio_dev);
274 st->np = np;
275
276 /*
277 * SPEAr600 has a different register layout than other SPEAr SoC's
278 * (e.g. SPEAr3xx). Let's provide two register base addresses
279 * to support multi-arch kernels.
280 */
281 st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
282 if (IS_ERR(st->adc_base_spear6xx))
283 return PTR_ERR(st->adc_base_spear6xx);
284
285 st->adc_base_spear3xx =
286 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
287
288 st->clk = devm_clk_get(dev, NULL);
289 if (IS_ERR(st->clk)) {
290 dev_err(dev, "failed getting clock\n");
291 return PTR_ERR(st->clk);
292 }
293
294 ret = clk_prepare_enable(st->clk);
295 if (ret) {
296 dev_err(dev, "failed enabling clock\n");
297 return ret;
298 }
299
300 irq = platform_get_irq(pdev, 0);
301 if (irq <= 0) {
302 ret = -EINVAL;
303 goto errout2;
304 }
305
306 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
307 st);
308 if (ret < 0) {
309 dev_err(dev, "failed requesting interrupt\n");
310 goto errout2;
311 }
312
313 if (of_property_read_u32(np, "sampling-frequency",
314 &st->sampling_freq)) {
315 dev_err(dev, "sampling-frequency missing in DT\n");
316 ret = -EINVAL;
317 goto errout2;
318 }
319
320 /*
321 * Optional avg_samples defaults to 0, resulting in single data
322 * conversion
323 */
324 of_property_read_u32(np, "average-samples", &st->avg_samples);
325
326 /*
327 * Optional vref_external defaults to 0, resulting in internal vref
328 * selection
329 */
330 of_property_read_u32(np, "vref-external", &st->vref_external);
331
332 spear_adc_configure(st);
333
334 platform_set_drvdata(pdev, indio_dev);
335
336 init_completion(&st->completion);
337
338 indio_dev->name = SPEAR_ADC_MOD_NAME;
339 indio_dev->info = &spear_adc_info;
340 indio_dev->modes = INDIO_DIRECT_MODE;
341 indio_dev->channels = spear_adc_iio_channels;
342 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
343
344 ret = iio_device_register(indio_dev);
345 if (ret)
346 goto errout2;
347
348 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
349
350 return 0;
351
352errout2:
353 clk_disable_unprepare(st->clk);
354 return ret;
355}
356
357static int spear_adc_remove(struct platform_device *pdev)
358{
359 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
360 struct spear_adc_state *st = iio_priv(indio_dev);
361
362 iio_device_unregister(indio_dev);
363 clk_disable_unprepare(st->clk);
364
365 return 0;
366}
367
368#ifdef CONFIG_OF
369static const struct of_device_id spear_adc_dt_ids[] = {
370 { .compatible = "st,spear600-adc", },
371 { /* sentinel */ }
372};
373MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
374#endif
375
376static struct platform_driver spear_adc_driver = {
377 .probe = spear_adc_probe,
378 .remove = spear_adc_remove,
379 .driver = {
380 .name = SPEAR_ADC_MOD_NAME,
381 .of_match_table = of_match_ptr(spear_adc_dt_ids),
382 },
383};
384
385module_platform_driver(spear_adc_driver);
386
387MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
388MODULE_DESCRIPTION("SPEAr ADC driver");
389MODULE_LICENSE("GPL");