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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Qualcomm PM8xxx PMIC XOADC driver
4 *
5 * These ADCs are known as HK/XO (house keeping / chrystal oscillator)
6 * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of
7 * specific-purpose and general purpose ADC converters and channels.
8 *
9 * Copyright (C) 2017 Linaro Ltd.
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 */
12
13#include <linux/iio/iio.h>
14#include <linux/iio/sysfs.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/regulator/consumer.h>
23
24#include "qcom-vadc-common.h"
25
26/*
27 * Definitions for the "user processor" registers lifted from the v3.4
28 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
29 * drivers/misc/pmic8058-xoadc.c
30 * drivers/hwmon/pm8xxx-adc.c
31 * None of them contain any complete register specification, so this is
32 * a best effort of combining the information.
33 */
34
35/* These appear to be "battery monitor" registers */
36#define ADC_ARB_BTM_CNTRL1 0x17e
37#define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
38#define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
39#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
40#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
41#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
42#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
43#define ADC_ARB_BTM_CNTRL1_EOC BIT(6)
44#define ADC_ARB_BTM_CNTRL1_REQ BIT(7)
45
46#define ADC_ARB_BTM_AMUX_CNTRL 0x17f
47#define ADC_ARB_BTM_ANA_PARAM 0x180
48#define ADC_ARB_BTM_DIG_PARAM 0x181
49#define ADC_ARB_BTM_RSV 0x182
50#define ADC_ARB_BTM_DATA1 0x183
51#define ADC_ARB_BTM_DATA0 0x184
52#define ADC_ARB_BTM_BAT_COOL_THR1 0x185
53#define ADC_ARB_BTM_BAT_COOL_THR0 0x186
54#define ADC_ARB_BTM_BAT_WARM_THR1 0x187
55#define ADC_ARB_BTM_BAT_WARM_THR0 0x188
56#define ADC_ARB_BTM_CNTRL2 0x18c
57
58/* Proper ADC registers */
59
60#define ADC_ARB_USRP_CNTRL 0x197
61#define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0)
62#define ADC_ARB_USRP_CNTRL_RSV1 BIT(1)
63#define ADC_ARB_USRP_CNTRL_RSV2 BIT(2)
64#define ADC_ARB_USRP_CNTRL_RSV3 BIT(3)
65#define ADC_ARB_USRP_CNTRL_RSV4 BIT(4)
66#define ADC_ARB_USRP_CNTRL_RSV5 BIT(5)
67#define ADC_ARB_USRP_CNTRL_EOC BIT(6)
68#define ADC_ARB_USRP_CNTRL_REQ BIT(7)
69
70#define ADC_ARB_USRP_AMUX_CNTRL 0x198
71/*
72 * The channel mask includes the bits selecting channel mux and prescaler
73 * on PM8058, or channel mux and premux on PM8921.
74 */
75#define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK 0xfc
76#define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
77#define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
78/* On PM8058 this is prescaling, on PM8921 this is premux */
79#define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2)
80#define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3)
81#define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
82#define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
83#define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
84#define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
85#define ADC_AMUX_PREMUX_SHIFT 2
86#define ADC_AMUX_SEL_SHIFT 4
87
88/* We know very little about the bits in this register */
89#define ADC_ARB_USRP_ANA_PARAM 0x199
90#define ADC_ARB_USRP_ANA_PARAM_DIS 0xFE
91#define ADC_ARB_USRP_ANA_PARAM_EN 0xFF
92
93#define ADC_ARB_USRP_DIG_PARAM 0x19A
94#define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
95#define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
96#define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
97#define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
98#define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
99/*
100 * On a later ADC the decimation factors are defined as
101 * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this
102 * holds also for this older XOADC.
103 */
104#define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
105#define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
106#define ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
107#define ADC_DIG_PARAM_DEC_SHIFT 5
108
109#define ADC_ARB_USRP_RSV 0x19B
110#define ADC_ARB_USRP_RSV_RST BIT(0)
111#define ADC_ARB_USRP_RSV_DTEST0 BIT(1)
112#define ADC_ARB_USRP_RSV_DTEST1 BIT(2)
113#define ADC_ARB_USRP_RSV_OP BIT(3)
114#define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
115#define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
116#define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
117#define ADC_ARB_USRP_RSV_TRM BIT(7)
118#define ADC_RSV_IP_SEL_SHIFT 4
119
120#define ADC_ARB_USRP_DATA0 0x19D
121#define ADC_ARB_USRP_DATA1 0x19C
122
123/**
124 * Physical channels which MUST exist on all PM variants in order to provide
125 * proper reference points for calibration.
126 *
127 * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel
128 * @PM8XXX_CHANNEL_125V: 1250mV reference channel
129 * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel
130 * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also
131 * measures XO temperature
132 */
133#define PM8XXX_CHANNEL_INTERNAL 0x0c
134#define PM8XXX_CHANNEL_125V 0x0d
135#define PM8XXX_CHANNEL_INTERNAL_2 0x0e
136#define PM8XXX_CHANNEL_MUXOFF 0x0f
137
138/*
139 * PM8058 AMUX premux scaling, two bits. This is done of the channel before
140 * reaching the AMUX.
141 */
142#define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */
143#define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */
144#define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */
145
146/* Defines reference voltage for the XOADC */
147#define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */
148#define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */
149#define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */
150#define AMUX_RSV3 0x3 /* not used */
151#define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */
152#define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */
153#define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */
154
155/**
156 * struct xoadc_channel - encodes channel properties and defaults
157 * @datasheet_name: the hardwarename of this channel
158 * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting
159 * this channel. Both this and the amux channel is needed to uniquely
160 * identify a channel. Values 0..3.
161 * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this
162 * channel, bits 4..7, selects the amux, values 0..f
163 * @prescale: the channels have hard-coded prescale ratios defined
164 * by the hardware, this tells us what it is
165 * @type: corresponding IIO channel type, usually IIO_VOLTAGE or
166 * IIO_TEMP
167 * @scale_fn_type: the liner interpolation etc to convert the
168 * ADC code to the value that IIO expects, in uV or millicelsius
169 * etc. This scale function can be pretty elaborate if different
170 * thermistors are connected or other hardware characteristics are
171 * deployed.
172 * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this
173 * selects the reference voltage for ratiometric scaling
174 */
175struct xoadc_channel {
176 const char *datasheet_name;
177 u8 pre_scale_mux:2;
178 u8 amux_channel:4;
179 const struct vadc_prescale_ratio prescale;
180 enum iio_chan_type type;
181 enum vadc_scale_fn_type scale_fn_type;
182 u8 amux_ip_rsv:3;
183};
184
185/**
186 * struct xoadc_variant - encodes the XOADC variant characteristics
187 * @name: name of this PMIC variant
188 * @channels: the hardware channels and respective settings and defaults
189 * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this
190 * is a known problem on PM8058)
191 * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058)
192 * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level
193 * mux
194 */
195struct xoadc_variant {
196 const char name[16];
197 const struct xoadc_channel *channels;
198 bool broken_ratiometric;
199 bool prescaling;
200 bool second_level_mux;
201};
202
203/*
204 * XOADC_CHAN macro parameters:
205 * _dname: the name of the channel
206 * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel
207 * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register
208 * for this channel. On some PMICs some of the bits select a prescaler, and
209 * on some PMICs some of the bits select various complex multiplex settings.
210 * _type: IIO channel type
211 * _prenum: prescaler numerator (dividend)
212 * _preden: prescaler denominator (divisor)
213 * _scale: scaling function type, this selects how the raw valued is mangled
214 * to output the actual processed measurement
215 * _amip: analog mux input parent when using ratiometric measurements
216 */
217#define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \
218 { \
219 .datasheet_name = __stringify(_dname), \
220 .pre_scale_mux = _presmux, \
221 .amux_channel = _amux, \
222 .prescale = { .num = _prenum, .den = _preden }, \
223 .type = _type, \
224 .scale_fn_type = _scale, \
225 .amux_ip_rsv = _amip, \
226 }
227
228/*
229 * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree:
230 * TODO: incomplete, needs testing.
231 */
232static const struct xoadc_channel pm8018_xoadc_channels[] = {
233 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
234 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
235 XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
236 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
237 /* Used for battery ID or battery temperature */
238 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2),
239 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
240 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
241 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
242 { }, /* Sentinel */
243};
244
245/*
246 * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree:
247 * TODO: needs testing.
248 */
249static const struct xoadc_channel pm8038_xoadc_channels[] = {
250 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
251 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
252 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
253 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
254 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
255 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
256 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
257 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
258 /* AMUX8 used for battery temperature in most cases */
259 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2),
260 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
261 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
262 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
263 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
264 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
265 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
266 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
267 { }, /* Sentinel */
268};
269
270/*
271 * This was created by cross-referencing the vendor tree
272 * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[]
273 * with the "channel types" (first field) to find the right
274 * configuration for these channels on an MSM8x60 i.e. PM8058
275 * setup.
276 */
277static const struct xoadc_channel pm8058_xoadc_channels[] = {
278 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
279 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
280 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1),
281 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
282 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
283 /*
284 * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in
285 * some code and documentation. But they are really just 5
286 * channels just like any other. They are connected to a switching
287 * matrix where they can be routed to any of the MPPs, not just
288 * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is
289 * very confusing.
290 */
291 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
292 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
293 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
294 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
295 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
296 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
297 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
298 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
299 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
300 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
301 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
302 /* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */
303 { }, /* Sentinel */
304};
305
306/*
307 * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree
308 * include/linux/mfd/pm8xxx/pm8xxx-adc.h
309 * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c
310 */
311static const struct xoadc_channel pm8921_xoadc_channels[] = {
312 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
313 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
314 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
315 /* channel "ICHG" is reserved and not used on PM8921 */
316 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
317 XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
318 /* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */
319 XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1),
320 XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
321 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
322 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
323 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
324 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
325 /* FIXME: look into the scaling of this temperature */
326 XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
327 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
328 /* The following channels have premux bit 0 set to 1 (all end in 4) */
329 XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
330 /* Set scaling to 1/2 based on the name for these two */
331 XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
332 XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
333 XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
334 XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
335 XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
336 XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
337 XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
338 XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
339 /* Internal test signals, I think */
340 XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
341 XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
342 XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
343 XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
344 XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
345 XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
346 XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
347 /* The following channels have premux bit 1 set to 1 (all end in 8) */
348 /* I guess even ATEST8 will be divided by 3 here */
349 XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
350 /* I guess div 2 div 3 becomes div 6 */
351 XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
352 XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
353 XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
354 XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
355 XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
356 XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
357 XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
358 XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
359 XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
360 XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
361 XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
362 XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
363 XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
364 XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
365 XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
366 { }, /* Sentinel */
367};
368
369/**
370 * struct pm8xxx_chan_info - ADC channel information
371 * @name: name of this channel
372 * @hwchan: pointer to hardware channel information (muxing & scaling settings)
373 * @calibration: whether to use absolute or ratiometric calibration
374 * @scale_fn_type: scaling function type
375 * @decimation: 0,1,2,3
376 * @amux_ip_rsv: ratiometric scale value if using ratiometric
377 * calibration: 0, 1, 2, 4, 5.
378 */
379struct pm8xxx_chan_info {
380 const char *name;
381 const struct xoadc_channel *hwchan;
382 enum vadc_calibration calibration;
383 u8 decimation:2;
384 u8 amux_ip_rsv:3;
385};
386
387/**
388 * struct pm8xxx_xoadc - state container for the XOADC
389 * @dev: pointer to device
390 * @map: regmap to access registers
391 * @vref: reference voltage regulator
392 * characteristics of the channels, and sensible default settings
393 * @nchans: number of channels, configured by the device tree
394 * @chans: the channel information per-channel, configured by the device tree
395 * @iio_chans: IIO channel specifiers
396 * @graph: linear calibration parameters for absolute and
397 * ratiometric measurements
398 * @complete: completion to indicate end of conversion
399 * @lock: lock to restrict access to the hardware to one client at the time
400 */
401struct pm8xxx_xoadc {
402 struct device *dev;
403 struct regmap *map;
404 const struct xoadc_variant *variant;
405 struct regulator *vref;
406 unsigned int nchans;
407 struct pm8xxx_chan_info *chans;
408 struct iio_chan_spec *iio_chans;
409 struct vadc_linear_graph graph[2];
410 struct completion complete;
411 struct mutex lock;
412};
413
414static irqreturn_t pm8xxx_eoc_irq(int irq, void *d)
415{
416 struct iio_dev *indio_dev = d;
417 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
418
419 complete(&adc->complete);
420
421 return IRQ_HANDLED;
422}
423
424static struct pm8xxx_chan_info *
425pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan)
426{
427 int i;
428
429 for (i = 0; i < adc->nchans; i++) {
430 struct pm8xxx_chan_info *ch = &adc->chans[i];
431 if (ch->hwchan->amux_channel == chan)
432 return ch;
433 }
434 return NULL;
435}
436
437static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
438 const struct pm8xxx_chan_info *ch,
439 u8 rsv, u16 *adc_code,
440 bool force_ratiometric)
441{
442 int ret;
443 unsigned int val;
444 u8 rsvmask, rsvval;
445 u8 lsb, msb;
446
447 dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
448 ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
449
450 mutex_lock(&adc->lock);
451
452 /* Mux in this channel */
453 val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
454 val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
455 ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
456 if (ret)
457 goto unlock;
458
459 /* Set up ratiometric scale value, mask off all bits except these */
460 rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
461 ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
462 if (adc->variant->broken_ratiometric && !force_ratiometric) {
463 /*
464 * Apparently the PM8058 has some kind of bug which is
465 * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
466 * which just hardcodes the RSV selector to SEL1 (0x20) for
467 * most cases and SEL0 (0x10) for the MUXOFF channel only.
468 * If we force ratiometric (currently only done when attempting
469 * to do ratiometric calibration) this doesn't seem to work
470 * very well and I suspect ratiometric conversion is simply
471 * broken or not supported on the PM8058.
472 *
473 * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
474 * the mode alone.
475 *
476 * Some PM8058 register documentation would be nice to get
477 * this right.
478 */
479 if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
480 rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
481 else
482 rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
483 } else {
484 if (rsv == 0xff)
485 rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
486 ADC_ARB_USRP_RSV_TRM;
487 else
488 rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
489 ADC_ARB_USRP_RSV_TRM;
490 }
491
492 ret = regmap_update_bits(adc->map,
493 ADC_ARB_USRP_RSV,
494 ~rsvmask,
495 rsvval);
496 if (ret)
497 goto unlock;
498
499 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
500 ADC_ARB_USRP_ANA_PARAM_DIS);
501 if (ret)
502 goto unlock;
503
504 /* Decimation factor */
505 ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
506 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
507 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
508 ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
509 if (ret)
510 goto unlock;
511
512 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
513 ADC_ARB_USRP_ANA_PARAM_EN);
514 if (ret)
515 goto unlock;
516
517 /* Enable the arbiter, the Qualcomm code does it twice like this */
518 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
519 ADC_ARB_USRP_CNTRL_EN_ARB);
520 if (ret)
521 goto unlock;
522 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
523 ADC_ARB_USRP_CNTRL_EN_ARB);
524 if (ret)
525 goto unlock;
526
527
528 /* Fire a request! */
529 reinit_completion(&adc->complete);
530 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
531 ADC_ARB_USRP_CNTRL_EN_ARB |
532 ADC_ARB_USRP_CNTRL_REQ);
533 if (ret)
534 goto unlock;
535
536 /* Next the interrupt occurs */
537 ret = wait_for_completion_timeout(&adc->complete,
538 VADC_CONV_TIME_MAX_US);
539 if (!ret) {
540 dev_err(adc->dev, "conversion timed out\n");
541 ret = -ETIMEDOUT;
542 goto unlock;
543 }
544
545 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val);
546 if (ret)
547 goto unlock;
548 lsb = val;
549 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val);
550 if (ret)
551 goto unlock;
552 msb = val;
553 *adc_code = (msb << 8) | lsb;
554
555 /* Turn off the ADC by setting the arbiter to 0 twice */
556 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
557 if (ret)
558 goto unlock;
559 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
560 if (ret)
561 goto unlock;
562
563unlock:
564 mutex_unlock(&adc->lock);
565 return ret;
566}
567
568static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc,
569 const struct pm8xxx_chan_info *ch,
570 u16 *adc_code)
571{
572 /*
573 * Normally we just use the ratiometric scale value (RSV) predefined
574 * for the channel, but during calibration we need to modify this
575 * so this wrapper is a helper hiding the more complex version.
576 */
577 return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false);
578}
579
580static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)
581{
582 const struct pm8xxx_chan_info *ch;
583 u16 read_1250v;
584 u16 read_0625v;
585 u16 read_nomux_rsv5;
586 u16 read_nomux_rsv4;
587 int ret;
588
589 adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
590 adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
591
592 /* Common reference channel calibration */
593 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
594 if (!ch)
595 return -ENODEV;
596 ret = pm8xxx_read_channel(adc, ch, &read_1250v);
597 if (ret) {
598 dev_err(adc->dev, "could not read 1.25V reference channel\n");
599 return -ENODEV;
600 }
601 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
602 if (!ch)
603 return -ENODEV;
604 ret = pm8xxx_read_channel(adc, ch, &read_0625v);
605 if (ret) {
606 dev_err(adc->dev, "could not read 0.625V reference channel\n");
607 return -ENODEV;
608 }
609 if (read_1250v == read_0625v) {
610 dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n");
611 return -ENODEV;
612 }
613
614 adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;
615 adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;
616
617 dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n",
618 VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);
619
620 /* Ratiometric calibration */
621 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
622 if (!ch)
623 return -ENODEV;
624 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,
625 &read_nomux_rsv5, true);
626 if (ret) {
627 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
628 return -ENODEV;
629 }
630 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,
631 &read_nomux_rsv4, true);
632 if (ret) {
633 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
634 return -ENODEV;
635 }
636 adc->graph[VADC_CALIB_RATIOMETRIC].dy =
637 read_nomux_rsv5 - read_nomux_rsv4;
638 adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;
639
640 dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n",
641 VADC_RATIOMETRIC_RANGE,
642 adc->graph[VADC_CALIB_RATIOMETRIC].dy);
643
644 return 0;
645}
646
647static int pm8xxx_read_raw(struct iio_dev *indio_dev,
648 struct iio_chan_spec const *chan,
649 int *val, int *val2, long mask)
650{
651 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
652 const struct pm8xxx_chan_info *ch;
653 u16 adc_code;
654 int ret;
655
656 switch (mask) {
657 case IIO_CHAN_INFO_PROCESSED:
658 ch = pm8xxx_get_channel(adc, chan->address);
659 if (!ch) {
660 dev_err(adc->dev, "no such channel %lu\n",
661 chan->address);
662 return -EINVAL;
663 }
664 ret = pm8xxx_read_channel(adc, ch, &adc_code);
665 if (ret)
666 return ret;
667
668 ret = qcom_vadc_scale(ch->hwchan->scale_fn_type,
669 &adc->graph[ch->calibration],
670 &ch->hwchan->prescale,
671 (ch->calibration == VADC_CALIB_ABSOLUTE),
672 adc_code, val);
673 if (ret)
674 return ret;
675
676 return IIO_VAL_INT;
677 case IIO_CHAN_INFO_RAW:
678 ch = pm8xxx_get_channel(adc, chan->address);
679 if (!ch) {
680 dev_err(adc->dev, "no such channel %lu\n",
681 chan->address);
682 return -EINVAL;
683 }
684 ret = pm8xxx_read_channel(adc, ch, &adc_code);
685 if (ret)
686 return ret;
687
688 *val = (int)adc_code;
689 return IIO_VAL_INT;
690 default:
691 return -EINVAL;
692 }
693}
694
695static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
696 const struct of_phandle_args *iiospec)
697{
698 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
699 u8 pre_scale_mux;
700 u8 amux_channel;
701 unsigned int i;
702
703 /*
704 * First cell is prescaler or premux, second cell is analog
705 * mux.
706 */
707 if (iiospec->args_count != 2) {
708 dev_err(&indio_dev->dev, "wrong number of arguments for %pOFn need 2 got %d\n",
709 iiospec->np,
710 iiospec->args_count);
711 return -EINVAL;
712 }
713 pre_scale_mux = (u8)iiospec->args[0];
714 amux_channel = (u8)iiospec->args[1];
715 dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n",
716 pre_scale_mux, amux_channel);
717
718 /* We need to match exactly on the prescale/premux and channel */
719 for (i = 0; i < adc->nchans; i++)
720 if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux &&
721 adc->chans[i].hwchan->amux_channel == amux_channel)
722 return i;
723
724 return -EINVAL;
725}
726
727static const struct iio_info pm8xxx_xoadc_info = {
728 .of_xlate = pm8xxx_of_xlate,
729 .read_raw = pm8xxx_read_raw,
730};
731
732static int pm8xxx_xoadc_parse_channel(struct device *dev,
733 struct device_node *np,
734 const struct xoadc_channel *hw_channels,
735 struct iio_chan_spec *iio_chan,
736 struct pm8xxx_chan_info *ch)
737{
738 const char *name = np->name;
739 const struct xoadc_channel *hwchan;
740 u32 pre_scale_mux, amux_channel;
741 u32 rsv, dec;
742 int ret;
743 int chid;
744
745 ret = of_property_read_u32_index(np, "reg", 0, &pre_scale_mux);
746 if (ret) {
747 dev_err(dev, "invalid pre scale/mux number %s\n", name);
748 return ret;
749 }
750 ret = of_property_read_u32_index(np, "reg", 1, &amux_channel);
751 if (ret) {
752 dev_err(dev, "invalid amux channel number %s\n", name);
753 return ret;
754 }
755
756 /* Find the right channel setting */
757 chid = 0;
758 hwchan = &hw_channels[0];
759 while (hwchan && hwchan->datasheet_name) {
760 if (hwchan->pre_scale_mux == pre_scale_mux &&
761 hwchan->amux_channel == amux_channel)
762 break;
763 hwchan++;
764 chid++;
765 }
766 /* The sentinel does not have a name assigned */
767 if (!hwchan->datasheet_name) {
768 dev_err(dev, "could not locate channel %02x/%02x\n",
769 pre_scale_mux, amux_channel);
770 return -EINVAL;
771 }
772 ch->name = name;
773 ch->hwchan = hwchan;
774 /* Everyone seems to use absolute calibration except in special cases */
775 ch->calibration = VADC_CALIB_ABSOLUTE;
776 /* Everyone seems to use default ("type 2") decimation */
777 ch->decimation = VADC_DEF_DECIMATION;
778
779 if (!of_property_read_u32(np, "qcom,ratiometric", &rsv)) {
780 ch->calibration = VADC_CALIB_RATIOMETRIC;
781 if (rsv > XOADC_RSV_MAX) {
782 dev_err(dev, "%s too large RSV value %d\n", name, rsv);
783 return -EINVAL;
784 }
785 if (rsv == AMUX_RSV3) {
786 dev_err(dev, "%s invalid RSV value %d\n", name, rsv);
787 return -EINVAL;
788 }
789 }
790
791 /* Optional decimation, if omitted we use the default */
792 ret = of_property_read_u32(np, "qcom,decimation", &dec);
793 if (!ret) {
794 ret = qcom_vadc_decimation_from_dt(dec);
795 if (ret < 0) {
796 dev_err(dev, "%s invalid decimation %d\n",
797 name, dec);
798 return ret;
799 }
800 ch->decimation = ret;
801 }
802
803 iio_chan->channel = chid;
804 iio_chan->address = hwchan->amux_channel;
805 iio_chan->datasheet_name = hwchan->datasheet_name;
806 iio_chan->type = hwchan->type;
807 /* All channels are raw or processed */
808 iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
809 BIT(IIO_CHAN_INFO_PROCESSED);
810 iio_chan->indexed = 1;
811
812 dev_dbg(dev, "channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" "
813 "ref voltage: %d, decimation %d "
814 "prescale %d/%d, scale function %d\n",
815 hwchan->pre_scale_mux, hwchan->amux_channel, ch->name,
816 ch->amux_ip_rsv, ch->decimation, hwchan->prescale.num,
817 hwchan->prescale.den, hwchan->scale_fn_type);
818
819 return 0;
820}
821
822static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc,
823 struct device_node *np)
824{
825 struct device_node *child;
826 struct pm8xxx_chan_info *ch;
827 int ret;
828 int i;
829
830 adc->nchans = of_get_available_child_count(np);
831 if (!adc->nchans) {
832 dev_err(adc->dev, "no channel children\n");
833 return -ENODEV;
834 }
835 dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
836
837 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
838 sizeof(*adc->iio_chans), GFP_KERNEL);
839 if (!adc->iio_chans)
840 return -ENOMEM;
841
842 adc->chans = devm_kcalloc(adc->dev, adc->nchans,
843 sizeof(*adc->chans), GFP_KERNEL);
844 if (!adc->chans)
845 return -ENOMEM;
846
847 i = 0;
848 for_each_available_child_of_node(np, child) {
849 ch = &adc->chans[i];
850 ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
851 adc->variant->channels,
852 &adc->iio_chans[i],
853 ch);
854 if (ret) {
855 of_node_put(child);
856 return ret;
857 }
858 i++;
859 }
860
861 /* Check for required channels */
862 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
863 if (!ch) {
864 dev_err(adc->dev, "missing 1.25V reference channel\n");
865 return -ENODEV;
866 }
867 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
868 if (!ch) {
869 dev_err(adc->dev, "missing 0.625V reference channel\n");
870 return -ENODEV;
871 }
872 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
873 if (!ch) {
874 dev_err(adc->dev, "missing MUXOFF reference channel\n");
875 return -ENODEV;
876 }
877
878 return 0;
879}
880
881static int pm8xxx_xoadc_probe(struct platform_device *pdev)
882{
883 const struct xoadc_variant *variant;
884 struct pm8xxx_xoadc *adc;
885 struct iio_dev *indio_dev;
886 struct device_node *np = pdev->dev.of_node;
887 struct regmap *map;
888 struct device *dev = &pdev->dev;
889 int ret;
890
891 variant = of_device_get_match_data(dev);
892 if (!variant)
893 return -ENODEV;
894
895 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
896 if (!indio_dev)
897 return -ENOMEM;
898 platform_set_drvdata(pdev, indio_dev);
899
900 adc = iio_priv(indio_dev);
901 adc->dev = dev;
902 adc->variant = variant;
903 init_completion(&adc->complete);
904 mutex_init(&adc->lock);
905
906 ret = pm8xxx_xoadc_parse_channels(adc, np);
907 if (ret)
908 return ret;
909
910 map = dev_get_regmap(dev->parent, NULL);
911 if (!map) {
912 dev_err(dev, "parent regmap unavailable.\n");
913 return -ENXIO;
914 }
915 adc->map = map;
916
917 /* Bring up regulator */
918 adc->vref = devm_regulator_get(dev, "xoadc-ref");
919 if (IS_ERR(adc->vref)) {
920 dev_err(dev, "failed to get XOADC VREF regulator\n");
921 return PTR_ERR(adc->vref);
922 }
923 ret = regulator_enable(adc->vref);
924 if (ret) {
925 dev_err(dev, "failed to enable XOADC VREF regulator\n");
926 return ret;
927 }
928
929 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
930 pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev);
931 if (ret) {
932 dev_err(dev, "unable to request IRQ\n");
933 goto out_disable_vref;
934 }
935
936 indio_dev->dev.parent = dev;
937 indio_dev->dev.of_node = np;
938 indio_dev->name = variant->name;
939 indio_dev->modes = INDIO_DIRECT_MODE;
940 indio_dev->info = &pm8xxx_xoadc_info;
941 indio_dev->channels = adc->iio_chans;
942 indio_dev->num_channels = adc->nchans;
943
944 ret = iio_device_register(indio_dev);
945 if (ret)
946 goto out_disable_vref;
947
948 ret = pm8xxx_calibrate_device(adc);
949 if (ret)
950 goto out_unreg_device;
951
952 dev_info(dev, "%s XOADC driver enabled\n", variant->name);
953
954 return 0;
955
956out_unreg_device:
957 iio_device_unregister(indio_dev);
958out_disable_vref:
959 regulator_disable(adc->vref);
960
961 return ret;
962}
963
964static int pm8xxx_xoadc_remove(struct platform_device *pdev)
965{
966 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
967 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
968
969 iio_device_unregister(indio_dev);
970
971 regulator_disable(adc->vref);
972
973 return 0;
974}
975
976static const struct xoadc_variant pm8018_variant = {
977 .name = "PM8018-XOADC",
978 .channels = pm8018_xoadc_channels,
979};
980
981static const struct xoadc_variant pm8038_variant = {
982 .name = "PM8038-XOADC",
983 .channels = pm8038_xoadc_channels,
984};
985
986static const struct xoadc_variant pm8058_variant = {
987 .name = "PM8058-XOADC",
988 .channels = pm8058_xoadc_channels,
989 .broken_ratiometric = true,
990 .prescaling = true,
991};
992
993static const struct xoadc_variant pm8921_variant = {
994 .name = "PM8921-XOADC",
995 .channels = pm8921_xoadc_channels,
996 .second_level_mux = true,
997};
998
999static const struct of_device_id pm8xxx_xoadc_id_table[] = {
1000 {
1001 .compatible = "qcom,pm8018-adc",
1002 .data = &pm8018_variant,
1003 },
1004 {
1005 .compatible = "qcom,pm8038-adc",
1006 .data = &pm8038_variant,
1007 },
1008 {
1009 .compatible = "qcom,pm8058-adc",
1010 .data = &pm8058_variant,
1011 },
1012 {
1013 .compatible = "qcom,pm8921-adc",
1014 .data = &pm8921_variant,
1015 },
1016 { },
1017};
1018MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table);
1019
1020static struct platform_driver pm8xxx_xoadc_driver = {
1021 .driver = {
1022 .name = "pm8xxx-adc",
1023 .of_match_table = pm8xxx_xoadc_id_table,
1024 },
1025 .probe = pm8xxx_xoadc_probe,
1026 .remove = pm8xxx_xoadc_remove,
1027};
1028module_platform_driver(pm8xxx_xoadc_driver);
1029
1030MODULE_DESCRIPTION("PM8xxx XOADC driver");
1031MODULE_LICENSE("GPL v2");
1032MODULE_ALIAS("platform:pm8xxx-xoadc");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Qualcomm PM8xxx PMIC XOADC driver
4 *
5 * These ADCs are known as HK/XO (house keeping / chrystal oscillator)
6 * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of
7 * specific-purpose and general purpose ADC converters and channels.
8 *
9 * Copyright (C) 2017 Linaro Ltd.
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 */
12
13#include <linux/iio/iio.h>
14#include <linux/iio/sysfs.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/regulator/consumer.h>
23
24#include "qcom-vadc-common.h"
25
26/*
27 * Definitions for the "user processor" registers lifted from the v3.4
28 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
29 * drivers/misc/pmic8058-xoadc.c
30 * drivers/hwmon/pm8xxx-adc.c
31 * None of them contain any complete register specification, so this is
32 * a best effort of combining the information.
33 */
34
35/* These appear to be "battery monitor" registers */
36#define ADC_ARB_BTM_CNTRL1 0x17e
37#define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
38#define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
39#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
40#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
41#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
42#define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
43#define ADC_ARB_BTM_CNTRL1_EOC BIT(6)
44#define ADC_ARB_BTM_CNTRL1_REQ BIT(7)
45
46#define ADC_ARB_BTM_AMUX_CNTRL 0x17f
47#define ADC_ARB_BTM_ANA_PARAM 0x180
48#define ADC_ARB_BTM_DIG_PARAM 0x181
49#define ADC_ARB_BTM_RSV 0x182
50#define ADC_ARB_BTM_DATA1 0x183
51#define ADC_ARB_BTM_DATA0 0x184
52#define ADC_ARB_BTM_BAT_COOL_THR1 0x185
53#define ADC_ARB_BTM_BAT_COOL_THR0 0x186
54#define ADC_ARB_BTM_BAT_WARM_THR1 0x187
55#define ADC_ARB_BTM_BAT_WARM_THR0 0x188
56#define ADC_ARB_BTM_CNTRL2 0x18c
57
58/* Proper ADC registers */
59
60#define ADC_ARB_USRP_CNTRL 0x197
61#define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0)
62#define ADC_ARB_USRP_CNTRL_RSV1 BIT(1)
63#define ADC_ARB_USRP_CNTRL_RSV2 BIT(2)
64#define ADC_ARB_USRP_CNTRL_RSV3 BIT(3)
65#define ADC_ARB_USRP_CNTRL_RSV4 BIT(4)
66#define ADC_ARB_USRP_CNTRL_RSV5 BIT(5)
67#define ADC_ARB_USRP_CNTRL_EOC BIT(6)
68#define ADC_ARB_USRP_CNTRL_REQ BIT(7)
69
70#define ADC_ARB_USRP_AMUX_CNTRL 0x198
71/*
72 * The channel mask includes the bits selecting channel mux and prescaler
73 * on PM8058, or channel mux and premux on PM8921.
74 */
75#define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK 0xfc
76#define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
77#define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
78/* On PM8058 this is prescaling, on PM8921 this is premux */
79#define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2)
80#define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3)
81#define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
82#define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
83#define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
84#define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
85#define ADC_AMUX_PREMUX_SHIFT 2
86#define ADC_AMUX_SEL_SHIFT 4
87
88/* We know very little about the bits in this register */
89#define ADC_ARB_USRP_ANA_PARAM 0x199
90#define ADC_ARB_USRP_ANA_PARAM_DIS 0xFE
91#define ADC_ARB_USRP_ANA_PARAM_EN 0xFF
92
93#define ADC_ARB_USRP_DIG_PARAM 0x19A
94#define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
95#define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
96#define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
97#define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
98#define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
99/*
100 * On a later ADC the decimation factors are defined as
101 * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this
102 * holds also for this older XOADC.
103 */
104#define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
105#define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
106#define ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
107#define ADC_DIG_PARAM_DEC_SHIFT 5
108
109#define ADC_ARB_USRP_RSV 0x19B
110#define ADC_ARB_USRP_RSV_RST BIT(0)
111#define ADC_ARB_USRP_RSV_DTEST0 BIT(1)
112#define ADC_ARB_USRP_RSV_DTEST1 BIT(2)
113#define ADC_ARB_USRP_RSV_OP BIT(3)
114#define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
115#define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
116#define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
117#define ADC_ARB_USRP_RSV_TRM BIT(7)
118#define ADC_RSV_IP_SEL_SHIFT 4
119
120#define ADC_ARB_USRP_DATA0 0x19D
121#define ADC_ARB_USRP_DATA1 0x19C
122
123/*
124 * Physical channels which MUST exist on all PM variants in order to provide
125 * proper reference points for calibration.
126 *
127 * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel
128 * @PM8XXX_CHANNEL_125V: 1250mV reference channel
129 * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel
130 * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also
131 * measures XO temperature
132 */
133#define PM8XXX_CHANNEL_INTERNAL 0x0c
134#define PM8XXX_CHANNEL_125V 0x0d
135#define PM8XXX_CHANNEL_INTERNAL_2 0x0e
136#define PM8XXX_CHANNEL_MUXOFF 0x0f
137
138/*
139 * PM8058 AMUX premux scaling, two bits. This is done of the channel before
140 * reaching the AMUX.
141 */
142#define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */
143#define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */
144#define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */
145
146/* Defines reference voltage for the XOADC */
147#define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */
148#define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */
149#define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */
150#define AMUX_RSV3 0x3 /* not used */
151#define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */
152#define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */
153#define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */
154
155/**
156 * struct xoadc_channel - encodes channel properties and defaults
157 * @datasheet_name: the hardwarename of this channel
158 * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting
159 * this channel. Both this and the amux channel is needed to uniquely
160 * identify a channel. Values 0..3.
161 * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this
162 * channel, bits 4..7, selects the amux, values 0..f
163 * @prescale: the channels have hard-coded prescale ratios defined
164 * by the hardware, this tells us what it is
165 * @type: corresponding IIO channel type, usually IIO_VOLTAGE or
166 * IIO_TEMP
167 * @scale_fn_type: the liner interpolation etc to convert the
168 * ADC code to the value that IIO expects, in uV or millicelsius
169 * etc. This scale function can be pretty elaborate if different
170 * thermistors are connected or other hardware characteristics are
171 * deployed.
172 * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this
173 * selects the reference voltage for ratiometric scaling
174 */
175struct xoadc_channel {
176 const char *datasheet_name;
177 u8 pre_scale_mux:2;
178 u8 amux_channel:4;
179 const struct vadc_prescale_ratio prescale;
180 enum iio_chan_type type;
181 enum vadc_scale_fn_type scale_fn_type;
182 u8 amux_ip_rsv:3;
183};
184
185/**
186 * struct xoadc_variant - encodes the XOADC variant characteristics
187 * @name: name of this PMIC variant
188 * @channels: the hardware channels and respective settings and defaults
189 * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this
190 * is a known problem on PM8058)
191 * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058)
192 * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level
193 * mux
194 */
195struct xoadc_variant {
196 const char name[16];
197 const struct xoadc_channel *channels;
198 bool broken_ratiometric;
199 bool prescaling;
200 bool second_level_mux;
201};
202
203/*
204 * XOADC_CHAN macro parameters:
205 * _dname: the name of the channel
206 * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel
207 * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register
208 * for this channel. On some PMICs some of the bits select a prescaler, and
209 * on some PMICs some of the bits select various complex multiplex settings.
210 * _type: IIO channel type
211 * _prenum: prescaler numerator (dividend)
212 * _preden: prescaler denominator (divisor)
213 * _scale: scaling function type, this selects how the raw valued is mangled
214 * to output the actual processed measurement
215 * _amip: analog mux input parent when using ratiometric measurements
216 */
217#define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \
218 { \
219 .datasheet_name = __stringify(_dname), \
220 .pre_scale_mux = _presmux, \
221 .amux_channel = _amux, \
222 .prescale = { .num = _prenum, .den = _preden }, \
223 .type = _type, \
224 .scale_fn_type = _scale, \
225 .amux_ip_rsv = _amip, \
226 }
227
228/*
229 * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree:
230 * TODO: incomplete, needs testing.
231 */
232static const struct xoadc_channel pm8018_xoadc_channels[] = {
233 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
234 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
235 XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
236 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
237 /* Used for battery ID or battery temperature */
238 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2),
239 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
240 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
241 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
242 { }, /* Sentinel */
243};
244
245/*
246 * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree:
247 * TODO: needs testing.
248 */
249static const struct xoadc_channel pm8038_xoadc_channels[] = {
250 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
251 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
252 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
253 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
254 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
255 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
256 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
257 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
258 /* AMUX8 used for battery temperature in most cases */
259 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2),
260 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
261 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
262 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
263 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
264 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
265 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
266 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
267 { }, /* Sentinel */
268};
269
270/*
271 * This was created by cross-referencing the vendor tree
272 * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[]
273 * with the "channel types" (first field) to find the right
274 * configuration for these channels on an MSM8x60 i.e. PM8058
275 * setup.
276 */
277static const struct xoadc_channel pm8058_xoadc_channels[] = {
278 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
279 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
280 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1),
281 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
282 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
283 /*
284 * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in
285 * some code and documentation. But they are really just 5
286 * channels just like any other. They are connected to a switching
287 * matrix where they can be routed to any of the MPPs, not just
288 * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is
289 * very confusing.
290 */
291 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
292 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
293 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
294 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
295 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
296 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
297 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
298 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
299 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
300 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
301 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
302 /* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */
303 { }, /* Sentinel */
304};
305
306/*
307 * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree
308 * include/linux/mfd/pm8xxx/pm8xxx-adc.h
309 * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c
310 */
311static const struct xoadc_channel pm8921_xoadc_channels[] = {
312 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
313 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
314 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
315 /* channel "ICHG" is reserved and not used on PM8921 */
316 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
317 XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
318 /* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */
319 XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1),
320 XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
321 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
322 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
323 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
324 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
325 /* FIXME: look into the scaling of this temperature */
326 XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
327 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
328 /* The following channels have premux bit 0 set to 1 (all end in 4) */
329 XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
330 /* Set scaling to 1/2 based on the name for these two */
331 XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
332 XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
333 XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
334 XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
335 XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
336 XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
337 XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
338 XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
339 /* Internal test signals, I think */
340 XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
341 XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
342 XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
343 XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
344 XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
345 XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
346 XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
347 /* The following channels have premux bit 1 set to 1 (all end in 8) */
348 /* I guess even ATEST8 will be divided by 3 here */
349 XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
350 /* I guess div 2 div 3 becomes div 6 */
351 XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
352 XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
353 XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
354 XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
355 XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
356 XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
357 XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
358 XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
359 XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
360 XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
361 XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
362 XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
363 XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
364 XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
365 XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
366 { }, /* Sentinel */
367};
368
369/**
370 * struct pm8xxx_chan_info - ADC channel information
371 * @name: name of this channel
372 * @hwchan: pointer to hardware channel information (muxing & scaling settings)
373 * @calibration: whether to use absolute or ratiometric calibration
374 * @scale_fn_type: scaling function type
375 * @decimation: 0,1,2,3
376 * @amux_ip_rsv: ratiometric scale value if using ratiometric
377 * calibration: 0, 1, 2, 4, 5.
378 */
379struct pm8xxx_chan_info {
380 const char *name;
381 const struct xoadc_channel *hwchan;
382 enum vadc_calibration calibration;
383 u8 decimation:2;
384 u8 amux_ip_rsv:3;
385};
386
387/**
388 * struct pm8xxx_xoadc - state container for the XOADC
389 * @dev: pointer to device
390 * @map: regmap to access registers
391 * @variant: XOADC variant characteristics
392 * @vref: reference voltage regulator
393 * characteristics of the channels, and sensible default settings
394 * @nchans: number of channels, configured by the device tree
395 * @chans: the channel information per-channel, configured by the device tree
396 * @iio_chans: IIO channel specifiers
397 * @graph: linear calibration parameters for absolute and
398 * ratiometric measurements
399 * @complete: completion to indicate end of conversion
400 * @lock: lock to restrict access to the hardware to one client at the time
401 */
402struct pm8xxx_xoadc {
403 struct device *dev;
404 struct regmap *map;
405 const struct xoadc_variant *variant;
406 struct regulator *vref;
407 unsigned int nchans;
408 struct pm8xxx_chan_info *chans;
409 struct iio_chan_spec *iio_chans;
410 struct vadc_linear_graph graph[2];
411 struct completion complete;
412 struct mutex lock;
413};
414
415static irqreturn_t pm8xxx_eoc_irq(int irq, void *d)
416{
417 struct iio_dev *indio_dev = d;
418 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
419
420 complete(&adc->complete);
421
422 return IRQ_HANDLED;
423}
424
425static struct pm8xxx_chan_info *
426pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan)
427{
428 int i;
429
430 for (i = 0; i < adc->nchans; i++) {
431 struct pm8xxx_chan_info *ch = &adc->chans[i];
432 if (ch->hwchan->amux_channel == chan)
433 return ch;
434 }
435 return NULL;
436}
437
438static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
439 const struct pm8xxx_chan_info *ch,
440 u8 rsv, u16 *adc_code,
441 bool force_ratiometric)
442{
443 int ret;
444 unsigned int val;
445 u8 rsvmask, rsvval;
446 u8 lsb, msb;
447
448 dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
449 ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
450
451 mutex_lock(&adc->lock);
452
453 /* Mux in this channel */
454 val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
455 val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
456 ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
457 if (ret)
458 goto unlock;
459
460 /* Set up ratiometric scale value, mask off all bits except these */
461 rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
462 ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
463 if (adc->variant->broken_ratiometric && !force_ratiometric) {
464 /*
465 * Apparently the PM8058 has some kind of bug which is
466 * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
467 * which just hardcodes the RSV selector to SEL1 (0x20) for
468 * most cases and SEL0 (0x10) for the MUXOFF channel only.
469 * If we force ratiometric (currently only done when attempting
470 * to do ratiometric calibration) this doesn't seem to work
471 * very well and I suspect ratiometric conversion is simply
472 * broken or not supported on the PM8058.
473 *
474 * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
475 * the mode alone.
476 *
477 * Some PM8058 register documentation would be nice to get
478 * this right.
479 */
480 if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
481 rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
482 else
483 rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
484 } else {
485 if (rsv == 0xff)
486 rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
487 ADC_ARB_USRP_RSV_TRM;
488 else
489 rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
490 ADC_ARB_USRP_RSV_TRM;
491 }
492
493 ret = regmap_update_bits(adc->map,
494 ADC_ARB_USRP_RSV,
495 ~rsvmask,
496 rsvval);
497 if (ret)
498 goto unlock;
499
500 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
501 ADC_ARB_USRP_ANA_PARAM_DIS);
502 if (ret)
503 goto unlock;
504
505 /* Decimation factor */
506 ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
507 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
508 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
509 ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
510 if (ret)
511 goto unlock;
512
513 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
514 ADC_ARB_USRP_ANA_PARAM_EN);
515 if (ret)
516 goto unlock;
517
518 /* Enable the arbiter, the Qualcomm code does it twice like this */
519 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
520 ADC_ARB_USRP_CNTRL_EN_ARB);
521 if (ret)
522 goto unlock;
523 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
524 ADC_ARB_USRP_CNTRL_EN_ARB);
525 if (ret)
526 goto unlock;
527
528
529 /* Fire a request! */
530 reinit_completion(&adc->complete);
531 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
532 ADC_ARB_USRP_CNTRL_EN_ARB |
533 ADC_ARB_USRP_CNTRL_REQ);
534 if (ret)
535 goto unlock;
536
537 /* Next the interrupt occurs */
538 ret = wait_for_completion_timeout(&adc->complete,
539 VADC_CONV_TIME_MAX_US);
540 if (!ret) {
541 dev_err(adc->dev, "conversion timed out\n");
542 ret = -ETIMEDOUT;
543 goto unlock;
544 }
545
546 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val);
547 if (ret)
548 goto unlock;
549 lsb = val;
550 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val);
551 if (ret)
552 goto unlock;
553 msb = val;
554 *adc_code = (msb << 8) | lsb;
555
556 /* Turn off the ADC by setting the arbiter to 0 twice */
557 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
558 if (ret)
559 goto unlock;
560 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
561 if (ret)
562 goto unlock;
563
564unlock:
565 mutex_unlock(&adc->lock);
566 return ret;
567}
568
569static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc,
570 const struct pm8xxx_chan_info *ch,
571 u16 *adc_code)
572{
573 /*
574 * Normally we just use the ratiometric scale value (RSV) predefined
575 * for the channel, but during calibration we need to modify this
576 * so this wrapper is a helper hiding the more complex version.
577 */
578 return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false);
579}
580
581static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)
582{
583 const struct pm8xxx_chan_info *ch;
584 u16 read_1250v;
585 u16 read_0625v;
586 u16 read_nomux_rsv5;
587 u16 read_nomux_rsv4;
588 int ret;
589
590 adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
591 adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
592
593 /* Common reference channel calibration */
594 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
595 if (!ch)
596 return -ENODEV;
597 ret = pm8xxx_read_channel(adc, ch, &read_1250v);
598 if (ret) {
599 dev_err(adc->dev, "could not read 1.25V reference channel\n");
600 return -ENODEV;
601 }
602 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
603 if (!ch)
604 return -ENODEV;
605 ret = pm8xxx_read_channel(adc, ch, &read_0625v);
606 if (ret) {
607 dev_err(adc->dev, "could not read 0.625V reference channel\n");
608 return -ENODEV;
609 }
610 if (read_1250v == read_0625v) {
611 dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n");
612 return -ENODEV;
613 }
614
615 adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;
616 adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;
617
618 dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n",
619 VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);
620
621 /* Ratiometric calibration */
622 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
623 if (!ch)
624 return -ENODEV;
625 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,
626 &read_nomux_rsv5, true);
627 if (ret) {
628 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
629 return -ENODEV;
630 }
631 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,
632 &read_nomux_rsv4, true);
633 if (ret) {
634 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
635 return -ENODEV;
636 }
637 adc->graph[VADC_CALIB_RATIOMETRIC].dy =
638 read_nomux_rsv5 - read_nomux_rsv4;
639 adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;
640
641 dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n",
642 VADC_RATIOMETRIC_RANGE,
643 adc->graph[VADC_CALIB_RATIOMETRIC].dy);
644
645 return 0;
646}
647
648static int pm8xxx_read_raw(struct iio_dev *indio_dev,
649 struct iio_chan_spec const *chan,
650 int *val, int *val2, long mask)
651{
652 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
653 const struct pm8xxx_chan_info *ch;
654 u16 adc_code;
655 int ret;
656
657 switch (mask) {
658 case IIO_CHAN_INFO_PROCESSED:
659 ch = pm8xxx_get_channel(adc, chan->address);
660 if (!ch) {
661 dev_err(adc->dev, "no such channel %lu\n",
662 chan->address);
663 return -EINVAL;
664 }
665 ret = pm8xxx_read_channel(adc, ch, &adc_code);
666 if (ret)
667 return ret;
668
669 ret = qcom_vadc_scale(ch->hwchan->scale_fn_type,
670 &adc->graph[ch->calibration],
671 &ch->hwchan->prescale,
672 (ch->calibration == VADC_CALIB_ABSOLUTE),
673 adc_code, val);
674 if (ret)
675 return ret;
676
677 return IIO_VAL_INT;
678 case IIO_CHAN_INFO_RAW:
679 ch = pm8xxx_get_channel(adc, chan->address);
680 if (!ch) {
681 dev_err(adc->dev, "no such channel %lu\n",
682 chan->address);
683 return -EINVAL;
684 }
685 ret = pm8xxx_read_channel(adc, ch, &adc_code);
686 if (ret)
687 return ret;
688
689 *val = (int)adc_code;
690 return IIO_VAL_INT;
691 default:
692 return -EINVAL;
693 }
694}
695
696static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
697 const struct of_phandle_args *iiospec)
698{
699 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
700 u8 pre_scale_mux;
701 u8 amux_channel;
702 unsigned int i;
703
704 /*
705 * First cell is prescaler or premux, second cell is analog
706 * mux.
707 */
708 if (iiospec->args_count != 2) {
709 dev_err(&indio_dev->dev, "wrong number of arguments for %pOFn need 2 got %d\n",
710 iiospec->np,
711 iiospec->args_count);
712 return -EINVAL;
713 }
714 pre_scale_mux = (u8)iiospec->args[0];
715 amux_channel = (u8)iiospec->args[1];
716 dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n",
717 pre_scale_mux, amux_channel);
718
719 /* We need to match exactly on the prescale/premux and channel */
720 for (i = 0; i < adc->nchans; i++)
721 if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux &&
722 adc->chans[i].hwchan->amux_channel == amux_channel)
723 return i;
724
725 return -EINVAL;
726}
727
728static const struct iio_info pm8xxx_xoadc_info = {
729 .of_xlate = pm8xxx_of_xlate,
730 .read_raw = pm8xxx_read_raw,
731};
732
733static int pm8xxx_xoadc_parse_channel(struct device *dev,
734 struct device_node *np,
735 const struct xoadc_channel *hw_channels,
736 struct iio_chan_spec *iio_chan,
737 struct pm8xxx_chan_info *ch)
738{
739 const char *name = np->name;
740 const struct xoadc_channel *hwchan;
741 u32 pre_scale_mux, amux_channel;
742 u32 rsv, dec;
743 int ret;
744 int chid;
745
746 ret = of_property_read_u32_index(np, "reg", 0, &pre_scale_mux);
747 if (ret) {
748 dev_err(dev, "invalid pre scale/mux number %s\n", name);
749 return ret;
750 }
751 ret = of_property_read_u32_index(np, "reg", 1, &amux_channel);
752 if (ret) {
753 dev_err(dev, "invalid amux channel number %s\n", name);
754 return ret;
755 }
756
757 /* Find the right channel setting */
758 chid = 0;
759 hwchan = &hw_channels[0];
760 while (hwchan && hwchan->datasheet_name) {
761 if (hwchan->pre_scale_mux == pre_scale_mux &&
762 hwchan->amux_channel == amux_channel)
763 break;
764 hwchan++;
765 chid++;
766 }
767 /* The sentinel does not have a name assigned */
768 if (!hwchan->datasheet_name) {
769 dev_err(dev, "could not locate channel %02x/%02x\n",
770 pre_scale_mux, amux_channel);
771 return -EINVAL;
772 }
773 ch->name = name;
774 ch->hwchan = hwchan;
775 /* Everyone seems to use absolute calibration except in special cases */
776 ch->calibration = VADC_CALIB_ABSOLUTE;
777 /* Everyone seems to use default ("type 2") decimation */
778 ch->decimation = VADC_DEF_DECIMATION;
779
780 if (!of_property_read_u32(np, "qcom,ratiometric", &rsv)) {
781 ch->calibration = VADC_CALIB_RATIOMETRIC;
782 if (rsv > XOADC_RSV_MAX) {
783 dev_err(dev, "%s too large RSV value %d\n", name, rsv);
784 return -EINVAL;
785 }
786 if (rsv == AMUX_RSV3) {
787 dev_err(dev, "%s invalid RSV value %d\n", name, rsv);
788 return -EINVAL;
789 }
790 }
791
792 /* Optional decimation, if omitted we use the default */
793 ret = of_property_read_u32(np, "qcom,decimation", &dec);
794 if (!ret) {
795 ret = qcom_vadc_decimation_from_dt(dec);
796 if (ret < 0) {
797 dev_err(dev, "%s invalid decimation %d\n",
798 name, dec);
799 return ret;
800 }
801 ch->decimation = ret;
802 }
803
804 iio_chan->channel = chid;
805 iio_chan->address = hwchan->amux_channel;
806 iio_chan->datasheet_name = hwchan->datasheet_name;
807 iio_chan->type = hwchan->type;
808 /* All channels are raw or processed */
809 iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
810 BIT(IIO_CHAN_INFO_PROCESSED);
811 iio_chan->indexed = 1;
812
813 dev_dbg(dev, "channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" "
814 "ref voltage: %d, decimation %d "
815 "prescale %d/%d, scale function %d\n",
816 hwchan->pre_scale_mux, hwchan->amux_channel, ch->name,
817 ch->amux_ip_rsv, ch->decimation, hwchan->prescale.num,
818 hwchan->prescale.den, hwchan->scale_fn_type);
819
820 return 0;
821}
822
823static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc,
824 struct device_node *np)
825{
826 struct device_node *child;
827 struct pm8xxx_chan_info *ch;
828 int ret;
829 int i;
830
831 adc->nchans = of_get_available_child_count(np);
832 if (!adc->nchans) {
833 dev_err(adc->dev, "no channel children\n");
834 return -ENODEV;
835 }
836 dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
837
838 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
839 sizeof(*adc->iio_chans), GFP_KERNEL);
840 if (!adc->iio_chans)
841 return -ENOMEM;
842
843 adc->chans = devm_kcalloc(adc->dev, adc->nchans,
844 sizeof(*adc->chans), GFP_KERNEL);
845 if (!adc->chans)
846 return -ENOMEM;
847
848 i = 0;
849 for_each_available_child_of_node(np, child) {
850 ch = &adc->chans[i];
851 ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
852 adc->variant->channels,
853 &adc->iio_chans[i],
854 ch);
855 if (ret) {
856 of_node_put(child);
857 return ret;
858 }
859 i++;
860 }
861
862 /* Check for required channels */
863 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
864 if (!ch) {
865 dev_err(adc->dev, "missing 1.25V reference channel\n");
866 return -ENODEV;
867 }
868 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
869 if (!ch) {
870 dev_err(adc->dev, "missing 0.625V reference channel\n");
871 return -ENODEV;
872 }
873 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
874 if (!ch) {
875 dev_err(adc->dev, "missing MUXOFF reference channel\n");
876 return -ENODEV;
877 }
878
879 return 0;
880}
881
882static int pm8xxx_xoadc_probe(struct platform_device *pdev)
883{
884 const struct xoadc_variant *variant;
885 struct pm8xxx_xoadc *adc;
886 struct iio_dev *indio_dev;
887 struct device_node *np = pdev->dev.of_node;
888 struct regmap *map;
889 struct device *dev = &pdev->dev;
890 int ret;
891
892 variant = of_device_get_match_data(dev);
893 if (!variant)
894 return -ENODEV;
895
896 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
897 if (!indio_dev)
898 return -ENOMEM;
899 platform_set_drvdata(pdev, indio_dev);
900
901 adc = iio_priv(indio_dev);
902 adc->dev = dev;
903 adc->variant = variant;
904 init_completion(&adc->complete);
905 mutex_init(&adc->lock);
906
907 ret = pm8xxx_xoadc_parse_channels(adc, np);
908 if (ret)
909 return ret;
910
911 map = dev_get_regmap(dev->parent, NULL);
912 if (!map) {
913 dev_err(dev, "parent regmap unavailable.\n");
914 return -ENXIO;
915 }
916 adc->map = map;
917
918 /* Bring up regulator */
919 adc->vref = devm_regulator_get(dev, "xoadc-ref");
920 if (IS_ERR(adc->vref)) {
921 dev_err(dev, "failed to get XOADC VREF regulator\n");
922 return PTR_ERR(adc->vref);
923 }
924 ret = regulator_enable(adc->vref);
925 if (ret) {
926 dev_err(dev, "failed to enable XOADC VREF regulator\n");
927 return ret;
928 }
929
930 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
931 pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev);
932 if (ret) {
933 dev_err(dev, "unable to request IRQ\n");
934 goto out_disable_vref;
935 }
936
937 indio_dev->name = variant->name;
938 indio_dev->modes = INDIO_DIRECT_MODE;
939 indio_dev->info = &pm8xxx_xoadc_info;
940 indio_dev->channels = adc->iio_chans;
941 indio_dev->num_channels = adc->nchans;
942
943 ret = iio_device_register(indio_dev);
944 if (ret)
945 goto out_disable_vref;
946
947 ret = pm8xxx_calibrate_device(adc);
948 if (ret)
949 goto out_unreg_device;
950
951 dev_info(dev, "%s XOADC driver enabled\n", variant->name);
952
953 return 0;
954
955out_unreg_device:
956 iio_device_unregister(indio_dev);
957out_disable_vref:
958 regulator_disable(adc->vref);
959
960 return ret;
961}
962
963static int pm8xxx_xoadc_remove(struct platform_device *pdev)
964{
965 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
966 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
967
968 iio_device_unregister(indio_dev);
969
970 regulator_disable(adc->vref);
971
972 return 0;
973}
974
975static const struct xoadc_variant pm8018_variant = {
976 .name = "PM8018-XOADC",
977 .channels = pm8018_xoadc_channels,
978};
979
980static const struct xoadc_variant pm8038_variant = {
981 .name = "PM8038-XOADC",
982 .channels = pm8038_xoadc_channels,
983};
984
985static const struct xoadc_variant pm8058_variant = {
986 .name = "PM8058-XOADC",
987 .channels = pm8058_xoadc_channels,
988 .broken_ratiometric = true,
989 .prescaling = true,
990};
991
992static const struct xoadc_variant pm8921_variant = {
993 .name = "PM8921-XOADC",
994 .channels = pm8921_xoadc_channels,
995 .second_level_mux = true,
996};
997
998static const struct of_device_id pm8xxx_xoadc_id_table[] = {
999 {
1000 .compatible = "qcom,pm8018-adc",
1001 .data = &pm8018_variant,
1002 },
1003 {
1004 .compatible = "qcom,pm8038-adc",
1005 .data = &pm8038_variant,
1006 },
1007 {
1008 .compatible = "qcom,pm8058-adc",
1009 .data = &pm8058_variant,
1010 },
1011 {
1012 .compatible = "qcom,pm8921-adc",
1013 .data = &pm8921_variant,
1014 },
1015 { },
1016};
1017MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table);
1018
1019static struct platform_driver pm8xxx_xoadc_driver = {
1020 .driver = {
1021 .name = "pm8xxx-adc",
1022 .of_match_table = pm8xxx_xoadc_id_table,
1023 },
1024 .probe = pm8xxx_xoadc_probe,
1025 .remove = pm8xxx_xoadc_remove,
1026};
1027module_platform_driver(pm8xxx_xoadc_driver);
1028
1029MODULE_DESCRIPTION("PM8xxx XOADC driver");
1030MODULE_LICENSE("GPL v2");
1031MODULE_ALIAS("platform:pm8xxx-xoadc");