1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  exynos_adc.c - Support for ADC in EXYNOS SoCs
   4 *
   5 *  8 ~ 10 channel, 10/12-bit ADC
   6 *
   7 *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
   8 */
   9
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/interrupt.h>
  13#include <linux/delay.h>
  14#include <linux/errno.h>
  15#include <linux/kernel.h>
  16#include <linux/slab.h>
  17#include <linux/io.h>
  18#include <linux/clk.h>
  19#include <linux/completion.h>
  20#include <linux/of.h>
  21#include <linux/of_irq.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/of_platform.h>
  24#include <linux/err.h>
  25#include <linux/input.h>
  26
  27#include <linux/iio/iio.h>
  28#include <linux/iio/machine.h>
  29#include <linux/iio/driver.h>
  30#include <linux/mfd/syscon.h>
  31#include <linux/regmap.h>
  32
  33#include <linux/platform_data/touchscreen-s3c2410.h>
  34
  35/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
  36#define ADC_V1_CON(x)		((x) + 0x00)
  37#define ADC_V1_TSC(x)		((x) + 0x04)
  38#define ADC_V1_DLY(x)		((x) + 0x08)
  39#define ADC_V1_DATX(x)		((x) + 0x0C)
  40#define ADC_V1_DATY(x)		((x) + 0x10)
  41#define ADC_V1_UPDN(x)		((x) + 0x14)
  42#define ADC_V1_INTCLR(x)	((x) + 0x18)
  43#define ADC_V1_MUX(x)		((x) + 0x1c)
  44#define ADC_V1_CLRINTPNDNUP(x)	((x) + 0x20)
  45
  46/* S3C2410 ADC registers definitions */
  47#define ADC_S3C2410_MUX(x)	((x) + 0x18)
  48
  49/* Future ADC_V2 registers definitions */
  50#define ADC_V2_CON1(x)		((x) + 0x00)
  51#define ADC_V2_CON2(x)		((x) + 0x04)
  52#define ADC_V2_STAT(x)		((x) + 0x08)
  53#define ADC_V2_INT_EN(x)	((x) + 0x10)
  54#define ADC_V2_INT_ST(x)	((x) + 0x14)
  55#define ADC_V2_VER(x)		((x) + 0x20)
  56
  57/* Bit definitions for ADC_V1 */
  58#define ADC_V1_CON_RES		(1u << 16)
  59#define ADC_V1_CON_PRSCEN	(1u << 14)
  60#define ADC_V1_CON_PRSCLV(x)	(((x) & 0xFF) << 6)
  61#define ADC_V1_CON_STANDBY	(1u << 2)
  62
  63/* Bit definitions for S3C2410 ADC */
  64#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
  65#define ADC_S3C2410_DATX_MASK	0x3FF
  66#define ADC_S3C2416_CON_RES_SEL	(1u << 3)
  67
  68/* touch screen always uses channel 0 */
  69#define ADC_S3C2410_MUX_TS	0
  70
  71/* ADCTSC Register Bits */
  72#define ADC_S3C2443_TSC_UD_SEN		(1u << 8)
  73#define ADC_S3C2410_TSC_YM_SEN		(1u << 7)
  74#define ADC_S3C2410_TSC_YP_SEN		(1u << 6)
  75#define ADC_S3C2410_TSC_XM_SEN		(1u << 5)
  76#define ADC_S3C2410_TSC_XP_SEN		(1u << 4)
  77#define ADC_S3C2410_TSC_PULL_UP_DISABLE	(1u << 3)
  78#define ADC_S3C2410_TSC_AUTO_PST	(1u << 2)
  79#define ADC_S3C2410_TSC_XY_PST(x)	(((x) & 0x3) << 0)
  80
  81#define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
  82			 ADC_S3C2410_TSC_YP_SEN | \
  83			 ADC_S3C2410_TSC_XP_SEN | \
  84			 ADC_S3C2410_TSC_XY_PST(3))
  85
  86#define ADC_TSC_AUTOPST	(ADC_S3C2410_TSC_YM_SEN | \
  87			 ADC_S3C2410_TSC_YP_SEN | \
  88			 ADC_S3C2410_TSC_XP_SEN | \
  89			 ADC_S3C2410_TSC_AUTO_PST | \
  90			 ADC_S3C2410_TSC_XY_PST(0))
  91
  92/* Bit definitions for ADC_V2 */
  93#define ADC_V2_CON1_SOFT_RESET	(1u << 2)
  94
  95#define ADC_V2_CON2_OSEL	(1u << 10)
  96#define ADC_V2_CON2_ESEL	(1u << 9)
  97#define ADC_V2_CON2_HIGHF	(1u << 8)
  98#define ADC_V2_CON2_C_TIME(x)	(((x) & 7) << 4)
  99#define ADC_V2_CON2_ACH_SEL(x)	(((x) & 0xF) << 0)
 100#define ADC_V2_CON2_ACH_MASK	0xF
 101
 102#define MAX_ADC_V2_CHANNELS		10
 103#define MAX_ADC_V1_CHANNELS		8
 104#define MAX_EXYNOS3250_ADC_CHANNELS	2
 105#define MAX_EXYNOS4212_ADC_CHANNELS	4
 106#define MAX_S5PV210_ADC_CHANNELS	10
 107
 108/* Bit definitions common for ADC_V1 and ADC_V2 */
 109#define ADC_CON_EN_START	(1u << 0)
 110#define ADC_CON_EN_START_MASK	(0x3 << 0)
 111#define ADC_DATX_PRESSED	(1u << 15)
 112#define ADC_DATX_MASK		0xFFF
 113#define ADC_DATY_MASK		0xFFF
 114
 115#define EXYNOS_ADC_TIMEOUT	(msecs_to_jiffies(100))
 116
 117#define EXYNOS_ADCV1_PHY_OFFSET	0x0718
 118#define EXYNOS_ADCV2_PHY_OFFSET	0x0720
 119
 120struct exynos_adc {
 121	struct exynos_adc_data	*data;
 122	struct device		*dev;
 123	struct input_dev	*input;
 124	void __iomem		*regs;
 125	struct regmap		*pmu_map;
 126	struct clk		*clk;
 127	struct clk		*sclk;
 128	unsigned int		irq;
 129	unsigned int		tsirq;
 130	unsigned int		delay;
 131	struct regulator	*vdd;
 132
 133	struct completion	completion;
 134
 135	u32			value;
 136	unsigned int            version;
 137
 138	bool			read_ts;
 139	u32			ts_x;
 140	u32			ts_y;
 141};
 142
 143struct exynos_adc_data {
 144	int num_channels;
 145	bool needs_sclk;
 146	bool needs_adc_phy;
 147	int phy_offset;
 148	u32 mask;
 149
 150	void (*init_hw)(struct exynos_adc *info);
 151	void (*exit_hw)(struct exynos_adc *info);
 152	void (*clear_irq)(struct exynos_adc *info);
 153	void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 154};
 155
 156static void exynos_adc_unprepare_clk(struct exynos_adc *info)
 157{
 158	if (info->data->needs_sclk)
 159		clk_unprepare(info->sclk);
 160	clk_unprepare(info->clk);
 161}
 162
 163static int exynos_adc_prepare_clk(struct exynos_adc *info)
 164{
 165	int ret;
 166
 167	ret = clk_prepare(info->clk);
 168	if (ret) {
 169		dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
 170		return ret;
 171	}
 172
 173	if (info->data->needs_sclk) {
 174		ret = clk_prepare(info->sclk);
 175		if (ret) {
 176			clk_unprepare(info->clk);
 177			dev_err(info->dev,
 178				"failed preparing sclk_adc clock: %d\n", ret);
 179			return ret;
 180		}
 181	}
 182
 183	return 0;
 184}
 185
 186static void exynos_adc_disable_clk(struct exynos_adc *info)
 187{
 188	if (info->data->needs_sclk)
 189		clk_disable(info->sclk);
 190	clk_disable(info->clk);
 191}
 192
 193static int exynos_adc_enable_clk(struct exynos_adc *info)
 194{
 195	int ret;
 196
 197	ret = clk_enable(info->clk);
 198	if (ret) {
 199		dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
 200		return ret;
 201	}
 202
 203	if (info->data->needs_sclk) {
 204		ret = clk_enable(info->sclk);
 205		if (ret) {
 206			clk_disable(info->clk);
 207			dev_err(info->dev,
 208				"failed enabling sclk_adc clock: %d\n", ret);
 209			return ret;
 210		}
 211	}
 212
 213	return 0;
 214}
 215
 216static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 217{
 218	u32 con1;
 219
 220	if (info->data->needs_adc_phy)
 221		regmap_write(info->pmu_map, info->data->phy_offset, 1);
 222
 223	/* set default prescaler values and Enable prescaler */
 224	con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 225
 226	/* Enable 12-bit ADC resolution */
 227	con1 |= ADC_V1_CON_RES;
 228	writel(con1, ADC_V1_CON(info->regs));
 229
 230	/* set touchscreen delay */
 231	writel(info->delay, ADC_V1_DLY(info->regs));
 232}
 233
 234static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
 235{
 236	u32 con;
 237
 238	if (info->data->needs_adc_phy)
 239		regmap_write(info->pmu_map, info->data->phy_offset, 0);
 240
 241	con = readl(ADC_V1_CON(info->regs));
 242	con |= ADC_V1_CON_STANDBY;
 243	writel(con, ADC_V1_CON(info->regs));
 244}
 245
 246static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 247{
 248	writel(1, ADC_V1_INTCLR(info->regs));
 249}
 250
 251static void exynos_adc_v1_start_conv(struct exynos_adc *info,
 252				     unsigned long addr)
 253{
 254	u32 con1;
 255
 256	writel(addr, ADC_V1_MUX(info->regs));
 257
 258	con1 = readl(ADC_V1_CON(info->regs));
 259	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 260}
 261
 262/* Exynos4212 and 4412 is like ADCv1 but with four channels only */
 263static const struct exynos_adc_data exynos4212_adc_data = {
 264	.num_channels	= MAX_EXYNOS4212_ADC_CHANNELS,
 265	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
 266	.needs_adc_phy	= true,
 267	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
 268
 269	.init_hw	= exynos_adc_v1_init_hw,
 270	.exit_hw	= exynos_adc_v1_exit_hw,
 271	.clear_irq	= exynos_adc_v1_clear_irq,
 272	.start_conv	= exynos_adc_v1_start_conv,
 273};
 274
 275static const struct exynos_adc_data exynos_adc_v1_data = {
 276	.num_channels	= MAX_ADC_V1_CHANNELS,
 277	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
 278	.needs_adc_phy	= true,
 279	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
 280
 281	.init_hw	= exynos_adc_v1_init_hw,
 282	.exit_hw	= exynos_adc_v1_exit_hw,
 283	.clear_irq	= exynos_adc_v1_clear_irq,
 284	.start_conv	= exynos_adc_v1_start_conv,
 285};
 286
 287static const struct exynos_adc_data exynos_adc_s5pv210_data = {
 288	.num_channels	= MAX_S5PV210_ADC_CHANNELS,
 289	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
 290
 291	.init_hw	= exynos_adc_v1_init_hw,
 292	.exit_hw	= exynos_adc_v1_exit_hw,
 293	.clear_irq	= exynos_adc_v1_clear_irq,
 294	.start_conv	= exynos_adc_v1_start_conv,
 295};
 296
 297static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
 298					  unsigned long addr)
 299{
 300	u32 con1;
 301
 302	/* Enable 12 bit ADC resolution */
 303	con1 = readl(ADC_V1_CON(info->regs));
 304	con1 |= ADC_S3C2416_CON_RES_SEL;
 305	writel(con1, ADC_V1_CON(info->regs));
 306
 307	/* Select channel for S3C2416 */
 308	writel(addr, ADC_S3C2410_MUX(info->regs));
 309
 310	con1 = readl(ADC_V1_CON(info->regs));
 311	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 312}
 313
 314static struct exynos_adc_data const exynos_adc_s3c2416_data = {
 315	.num_channels	= MAX_ADC_V1_CHANNELS,
 316	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
 317
 318	.init_hw	= exynos_adc_v1_init_hw,
 319	.exit_hw	= exynos_adc_v1_exit_hw,
 320	.start_conv	= exynos_adc_s3c2416_start_conv,
 321};
 322
 323static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
 324					  unsigned long addr)
 325{
 326	u32 con1;
 327
 328	/* Select channel for S3C2433 */
 329	writel(addr, ADC_S3C2410_MUX(info->regs));
 330
 331	con1 = readl(ADC_V1_CON(info->regs));
 332	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 333}
 334
 335static struct exynos_adc_data const exynos_adc_s3c2443_data = {
 336	.num_channels	= MAX_ADC_V1_CHANNELS,
 337	.mask		= ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 338
 339	.init_hw	= exynos_adc_v1_init_hw,
 340	.exit_hw	= exynos_adc_v1_exit_hw,
 341	.start_conv	= exynos_adc_s3c2443_start_conv,
 342};
 343
 344static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
 345					  unsigned long addr)
 346{
 347	u32 con1;
 348
 349	con1 = readl(ADC_V1_CON(info->regs));
 350	con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
 351	con1 |= ADC_S3C2410_CON_SELMUX(addr);
 352	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 353}
 354
 355static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
 356	.num_channels	= MAX_ADC_V1_CHANNELS,
 357	.mask		= ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 358
 359	.init_hw	= exynos_adc_v1_init_hw,
 360	.exit_hw	= exynos_adc_v1_exit_hw,
 361	.start_conv	= exynos_adc_s3c64xx_start_conv,
 362};
 363
 364static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
 365	.num_channels	= MAX_ADC_V1_CHANNELS,
 366	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
 367
 368	.init_hw	= exynos_adc_v1_init_hw,
 369	.exit_hw	= exynos_adc_v1_exit_hw,
 370	.clear_irq	= exynos_adc_v1_clear_irq,
 371	.start_conv	= exynos_adc_s3c64xx_start_conv,
 372};
 373
 374static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 375{
 376	u32 con1, con2;
 377
 378	if (info->data->needs_adc_phy)
 379		regmap_write(info->pmu_map, info->data->phy_offset, 1);
 380
 381	con1 = ADC_V2_CON1_SOFT_RESET;
 382	writel(con1, ADC_V2_CON1(info->regs));
 383
 384	con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 385		ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 386	writel(con2, ADC_V2_CON2(info->regs));
 387
 388	/* Enable interrupts */
 389	writel(1, ADC_V2_INT_EN(info->regs));
 390}
 391
 392static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
 393{
 394	u32 con;
 395
 396	if (info->data->needs_adc_phy)
 397		regmap_write(info->pmu_map, info->data->phy_offset, 0);
 398
 399	con = readl(ADC_V2_CON1(info->regs));
 400	con &= ~ADC_CON_EN_START;
 401	writel(con, ADC_V2_CON1(info->regs));
 402}
 403
 404static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 405{
 406	writel(1, ADC_V2_INT_ST(info->regs));
 407}
 408
 409static void exynos_adc_v2_start_conv(struct exynos_adc *info,
 410				     unsigned long addr)
 411{
 412	u32 con1, con2;
 413
 414	con2 = readl(ADC_V2_CON2(info->regs));
 415	con2 &= ~ADC_V2_CON2_ACH_MASK;
 416	con2 |= ADC_V2_CON2_ACH_SEL(addr);
 417	writel(con2, ADC_V2_CON2(info->regs));
 418
 419	con1 = readl(ADC_V2_CON1(info->regs));
 420	writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
 421}
 422
 423static const struct exynos_adc_data exynos_adc_v2_data = {
 424	.num_channels	= MAX_ADC_V2_CHANNELS,
 425	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
 426	.needs_adc_phy	= true,
 427	.phy_offset	= EXYNOS_ADCV2_PHY_OFFSET,
 428
 429	.init_hw	= exynos_adc_v2_init_hw,
 430	.exit_hw	= exynos_adc_v2_exit_hw,
 431	.clear_irq	= exynos_adc_v2_clear_irq,
 432	.start_conv	= exynos_adc_v2_start_conv,
 433};
 434
 435static const struct exynos_adc_data exynos3250_adc_data = {
 436	.num_channels	= MAX_EXYNOS3250_ADC_CHANNELS,
 437	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
 438	.needs_sclk	= true,
 439	.needs_adc_phy	= true,
 440	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
 441
 442	.init_hw	= exynos_adc_v2_init_hw,
 443	.exit_hw	= exynos_adc_v2_exit_hw,
 444	.clear_irq	= exynos_adc_v2_clear_irq,
 445	.start_conv	= exynos_adc_v2_start_conv,
 446};
 447
 448static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
 449{
 450	u32 con1, con2;
 451
 452	if (info->data->needs_adc_phy)
 453		regmap_write(info->pmu_map, info->data->phy_offset, 1);
 454
 455	con1 = ADC_V2_CON1_SOFT_RESET;
 456	writel(con1, ADC_V2_CON1(info->regs));
 457
 458	con2 = readl(ADC_V2_CON2(info->regs));
 459	con2 &= ~ADC_V2_CON2_C_TIME(7);
 460	con2 |= ADC_V2_CON2_C_TIME(0);
 461	writel(con2, ADC_V2_CON2(info->regs));
 462
 463	/* Enable interrupts */
 464	writel(1, ADC_V2_INT_EN(info->regs));
 465}
 466
 467static const struct exynos_adc_data exynos7_adc_data = {
 468	.num_channels	= MAX_ADC_V1_CHANNELS,
 469	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
 470
 471	.init_hw	= exynos_adc_exynos7_init_hw,
 472	.exit_hw	= exynos_adc_v2_exit_hw,
 473	.clear_irq	= exynos_adc_v2_clear_irq,
 474	.start_conv	= exynos_adc_v2_start_conv,
 475};
 476
 477static const struct of_device_id exynos_adc_match[] = {
 478	{
 479		.compatible = "samsung,s3c2410-adc",
 480		.data = &exynos_adc_s3c24xx_data,
 481	}, {
 482		.compatible = "samsung,s3c2416-adc",
 483		.data = &exynos_adc_s3c2416_data,
 484	}, {
 485		.compatible = "samsung,s3c2440-adc",
 486		.data = &exynos_adc_s3c24xx_data,
 487	}, {
 488		.compatible = "samsung,s3c2443-adc",
 489		.data = &exynos_adc_s3c2443_data,
 490	}, {
 491		.compatible = "samsung,s3c6410-adc",
 492		.data = &exynos_adc_s3c64xx_data,
 493	}, {
 494		.compatible = "samsung,s5pv210-adc",
 495		.data = &exynos_adc_s5pv210_data,
 496	}, {
 497		.compatible = "samsung,exynos4212-adc",
 498		.data = &exynos4212_adc_data,
 499	}, {
 500		.compatible = "samsung,exynos-adc-v1",
 501		.data = &exynos_adc_v1_data,
 502	}, {
 503		.compatible = "samsung,exynos-adc-v2",
 504		.data = &exynos_adc_v2_data,
 505	}, {
 506		.compatible = "samsung,exynos3250-adc",
 507		.data = &exynos3250_adc_data,
 508	}, {
 509		.compatible = "samsung,exynos7-adc",
 510		.data = &exynos7_adc_data,
 511	},
 512	{},
 513};
 514MODULE_DEVICE_TABLE(of, exynos_adc_match);
 515
 516static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
 517{
 518	const struct of_device_id *match;
 519
 520	match = of_match_node(exynos_adc_match, pdev->dev.of_node);
 521	return (struct exynos_adc_data *)match->data;
 522}
 523
 524static int exynos_read_raw(struct iio_dev *indio_dev,
 525				struct iio_chan_spec const *chan,
 526				int *val,
 527				int *val2,
 528				long mask)
 529{
 530	struct exynos_adc *info = iio_priv(indio_dev);
 531	unsigned long timeout;
 532	int ret;
 533
 534	if (mask != IIO_CHAN_INFO_RAW)
 
 
 
 
 
 
 
 
 
 
 535		return -EINVAL;
 
 536
 537	mutex_lock(&indio_dev->mlock);
 538	reinit_completion(&info->completion);
 539
 540	/* Select the channel to be used and Trigger conversion */
 541	if (info->data->start_conv)
 542		info->data->start_conv(info, chan->address);
 543
 544	timeout = wait_for_completion_timeout(&info->completion,
 545					      EXYNOS_ADC_TIMEOUT);
 546	if (timeout == 0) {
 547		dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 548		if (info->data->init_hw)
 549			info->data->init_hw(info);
 550		ret = -ETIMEDOUT;
 551	} else {
 552		*val = info->value;
 553		*val2 = 0;
 554		ret = IIO_VAL_INT;
 555	}
 556
 557	mutex_unlock(&indio_dev->mlock);
 558
 559	return ret;
 560}
 561
 562static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y)
 563{
 564	struct exynos_adc *info = iio_priv(indio_dev);
 565	unsigned long timeout;
 566	int ret;
 567
 568	mutex_lock(&indio_dev->mlock);
 569	info->read_ts = true;
 570
 571	reinit_completion(&info->completion);
 572
 573	writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST,
 574	       ADC_V1_TSC(info->regs));
 575
 576	/* Select the ts channel to be used and Trigger conversion */
 577	info->data->start_conv(info, ADC_S3C2410_MUX_TS);
 578
 579	timeout = wait_for_completion_timeout(&info->completion,
 580					      EXYNOS_ADC_TIMEOUT);
 581	if (timeout == 0) {
 582		dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 583		if (info->data->init_hw)
 584			info->data->init_hw(info);
 585		ret = -ETIMEDOUT;
 586	} else {
 587		*x = info->ts_x;
 588		*y = info->ts_y;
 589		ret = 0;
 590	}
 591
 592	info->read_ts = false;
 593	mutex_unlock(&indio_dev->mlock);
 594
 595	return ret;
 596}
 597
 598static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
 599{
 600	struct exynos_adc *info = dev_id;
 601	u32 mask = info->data->mask;
 602
 603	/* Read value */
 604	if (info->read_ts) {
 605		info->ts_x = readl(ADC_V1_DATX(info->regs));
 606		info->ts_y = readl(ADC_V1_DATY(info->regs));
 607		writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
 608	} else {
 609		info->value = readl(ADC_V1_DATX(info->regs)) & mask;
 610	}
 611
 612	/* clear irq */
 613	if (info->data->clear_irq)
 614		info->data->clear_irq(info);
 615
 616	complete(&info->completion);
 617
 618	return IRQ_HANDLED;
 619}
 620
 621/*
 622 * Here we (ab)use a threaded interrupt handler to stay running
 623 * for as long as the touchscreen remains pressed, we report
 624 * a new event with the latest data and then sleep until the
 625 * next timer tick. This mirrors the behavior of the old
 626 * driver, with much less code.
 627 */
 628static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
 629{
 630	struct exynos_adc *info = dev_id;
 631	struct iio_dev *dev = dev_get_drvdata(info->dev);
 632	u32 x, y;
 633	bool pressed;
 634	int ret;
 635
 636	while (info->input->users) {
 637		ret = exynos_read_s3c64xx_ts(dev, &x, &y);
 638		if (ret == -ETIMEDOUT)
 639			break;
 640
 641		pressed = x & y & ADC_DATX_PRESSED;
 642		if (!pressed) {
 643			input_report_key(info->input, BTN_TOUCH, 0);
 644			input_sync(info->input);
 645			break;
 646		}
 647
 648		input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
 649		input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
 650		input_report_key(info->input, BTN_TOUCH, 1);
 651		input_sync(info->input);
 652
 653		usleep_range(1000, 1100);
 654	};
 655
 656	writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
 657
 658	return IRQ_HANDLED;
 659}
 660
 661static int exynos_adc_reg_access(struct iio_dev *indio_dev,
 662			      unsigned reg, unsigned writeval,
 663			      unsigned *readval)
 664{
 665	struct exynos_adc *info = iio_priv(indio_dev);
 666
 667	if (readval == NULL)
 668		return -EINVAL;
 669
 670	*readval = readl(info->regs + reg);
 671
 672	return 0;
 673}
 674
 675static const struct iio_info exynos_adc_iio_info = {
 676	.read_raw = &exynos_read_raw,
 677	.debugfs_reg_access = &exynos_adc_reg_access,
 678};
 679
 680#define ADC_CHANNEL(_index, _id) {			\
 681	.type = IIO_VOLTAGE,				\
 682	.indexed = 1,					\
 683	.channel = _index,				\
 684	.address = _index,				\
 685	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
 
 686	.datasheet_name = _id,				\
 687}
 688
 689static const struct iio_chan_spec exynos_adc_iio_channels[] = {
 690	ADC_CHANNEL(0, "adc0"),
 691	ADC_CHANNEL(1, "adc1"),
 692	ADC_CHANNEL(2, "adc2"),
 693	ADC_CHANNEL(3, "adc3"),
 694	ADC_CHANNEL(4, "adc4"),
 695	ADC_CHANNEL(5, "adc5"),
 696	ADC_CHANNEL(6, "adc6"),
 697	ADC_CHANNEL(7, "adc7"),
 698	ADC_CHANNEL(8, "adc8"),
 699	ADC_CHANNEL(9, "adc9"),
 700};
 701
 702static int exynos_adc_remove_devices(struct device *dev, void *c)
 703{
 704	struct platform_device *pdev = to_platform_device(dev);
 705
 706	platform_device_unregister(pdev);
 707
 708	return 0;
 709}
 710
 711static int exynos_adc_ts_open(struct input_dev *dev)
 712{
 713	struct exynos_adc *info = input_get_drvdata(dev);
 714
 715	enable_irq(info->tsirq);
 716
 717	return 0;
 718}
 719
 720static void exynos_adc_ts_close(struct input_dev *dev)
 721{
 722	struct exynos_adc *info = input_get_drvdata(dev);
 723
 724	disable_irq(info->tsirq);
 725}
 726
 727static int exynos_adc_ts_init(struct exynos_adc *info)
 728{
 729	int ret;
 730
 731	if (info->tsirq <= 0)
 732		return -ENODEV;
 733
 734	info->input = input_allocate_device();
 735	if (!info->input)
 736		return -ENOMEM;
 737
 738	info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
 739	info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
 740
 741	input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
 742	input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
 743
 744	info->input->name = "S3C24xx TouchScreen";
 745	info->input->id.bustype = BUS_HOST;
 746	info->input->open = exynos_adc_ts_open;
 747	info->input->close = exynos_adc_ts_close;
 748
 749	input_set_drvdata(info->input, info);
 750
 751	ret = input_register_device(info->input);
 752	if (ret) {
 753		input_free_device(info->input);
 754		return ret;
 755	}
 756
 757	disable_irq(info->tsirq);
 758	ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
 759				   IRQF_ONESHOT, "touchscreen", info);
 760	if (ret)
 761		input_unregister_device(info->input);
 762
 763	return ret;
 764}
 765
 766static int exynos_adc_probe(struct platform_device *pdev)
 767{
 768	struct exynos_adc *info = NULL;
 769	struct device_node *np = pdev->dev.of_node;
 770	struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev);
 771	struct iio_dev *indio_dev = NULL;
 772	struct resource	*mem;
 773	bool has_ts = false;
 774	int ret = -ENODEV;
 775	int irq;
 776
 777	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
 778	if (!indio_dev) {
 779		dev_err(&pdev->dev, "failed allocating iio device\n");
 780		return -ENOMEM;
 781	}
 782
 783	info = iio_priv(indio_dev);
 784
 785	info->data = exynos_adc_get_data(pdev);
 786	if (!info->data) {
 787		dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
 788		return -EINVAL;
 789	}
 790
 791	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 792	info->regs = devm_ioremap_resource(&pdev->dev, mem);
 793	if (IS_ERR(info->regs))
 794		return PTR_ERR(info->regs);
 795
 796
 797	if (info->data->needs_adc_phy) {
 798		info->pmu_map = syscon_regmap_lookup_by_phandle(
 799					pdev->dev.of_node,
 800					"samsung,syscon-phandle");
 801		if (IS_ERR(info->pmu_map)) {
 802			dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
 803			return PTR_ERR(info->pmu_map);
 804		}
 805	}
 806
 807	irq = platform_get_irq(pdev, 0);
 808	if (irq < 0)
 809		return irq;
 810	info->irq = irq;
 811
 812	irq = platform_get_irq(pdev, 1);
 813	if (irq == -EPROBE_DEFER)
 814		return irq;
 815
 816	info->tsirq = irq;
 817
 818	info->dev = &pdev->dev;
 819
 820	init_completion(&info->completion);
 821
 822	info->clk = devm_clk_get(&pdev->dev, "adc");
 823	if (IS_ERR(info->clk)) {
 824		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 825							PTR_ERR(info->clk));
 826		return PTR_ERR(info->clk);
 827	}
 828
 829	if (info->data->needs_sclk) {
 830		info->sclk = devm_clk_get(&pdev->dev, "sclk");
 831		if (IS_ERR(info->sclk)) {
 832			dev_err(&pdev->dev,
 833				"failed getting sclk clock, err = %ld\n",
 834				PTR_ERR(info->sclk));
 835			return PTR_ERR(info->sclk);
 836		}
 837	}
 838
 839	info->vdd = devm_regulator_get(&pdev->dev, "vdd");
 840	if (IS_ERR(info->vdd)) {
 841		dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
 842							PTR_ERR(info->vdd));
 
 
 843		return PTR_ERR(info->vdd);
 844	}
 845
 846	ret = regulator_enable(info->vdd);
 847	if (ret)
 848		return ret;
 849
 850	ret = exynos_adc_prepare_clk(info);
 851	if (ret)
 852		goto err_disable_reg;
 853
 854	ret = exynos_adc_enable_clk(info);
 855	if (ret)
 856		goto err_unprepare_clk;
 857
 858	platform_set_drvdata(pdev, indio_dev);
 859
 860	indio_dev->name = dev_name(&pdev->dev);
 861	indio_dev->dev.parent = &pdev->dev;
 862	indio_dev->dev.of_node = pdev->dev.of_node;
 863	indio_dev->info = &exynos_adc_iio_info;
 864	indio_dev->modes = INDIO_DIRECT_MODE;
 865	indio_dev->channels = exynos_adc_iio_channels;
 866	indio_dev->num_channels = info->data->num_channels;
 867
 868	ret = request_irq(info->irq, exynos_adc_isr,
 869					0, dev_name(&pdev->dev), info);
 870	if (ret < 0) {
 871		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
 872							info->irq);
 873		goto err_disable_clk;
 874	}
 875
 876	ret = iio_device_register(indio_dev);
 877	if (ret)
 878		goto err_irq;
 879
 880	if (info->data->init_hw)
 881		info->data->init_hw(info);
 882
 883	/* leave out any TS related code if unreachable */
 884	if (IS_REACHABLE(CONFIG_INPUT)) {
 885		has_ts = of_property_read_bool(pdev->dev.of_node,
 886					       "has-touchscreen") || pdata;
 887	}
 888
 889	if (pdata)
 890		info->delay = pdata->delay;
 891	else
 892		info->delay = 10000;
 893
 894	if (has_ts)
 895		ret = exynos_adc_ts_init(info);
 896	if (ret)
 897		goto err_iio;
 898
 899	ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
 900	if (ret < 0) {
 901		dev_err(&pdev->dev, "failed adding child nodes\n");
 902		goto err_of_populate;
 903	}
 904
 905	return 0;
 906
 907err_of_populate:
 908	device_for_each_child(&indio_dev->dev, NULL,
 909				exynos_adc_remove_devices);
 910	if (has_ts) {
 911		input_unregister_device(info->input);
 912		free_irq(info->tsirq, info);
 913	}
 914err_iio:
 915	iio_device_unregister(indio_dev);
 916err_irq:
 917	free_irq(info->irq, info);
 918err_disable_clk:
 919	if (info->data->exit_hw)
 920		info->data->exit_hw(info);
 921	exynos_adc_disable_clk(info);
 922err_unprepare_clk:
 923	exynos_adc_unprepare_clk(info);
 924err_disable_reg:
 925	regulator_disable(info->vdd);
 926	return ret;
 927}
 928
 929static int exynos_adc_remove(struct platform_device *pdev)
 930{
 931	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 932	struct exynos_adc *info = iio_priv(indio_dev);
 933
 934	if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
 935		free_irq(info->tsirq, info);
 936		input_unregister_device(info->input);
 937	}
 938	device_for_each_child(&indio_dev->dev, NULL,
 939				exynos_adc_remove_devices);
 940	iio_device_unregister(indio_dev);
 941	free_irq(info->irq, info);
 942	if (info->data->exit_hw)
 943		info->data->exit_hw(info);
 944	exynos_adc_disable_clk(info);
 945	exynos_adc_unprepare_clk(info);
 946	regulator_disable(info->vdd);
 947
 948	return 0;
 949}
 950
 951#ifdef CONFIG_PM_SLEEP
 952static int exynos_adc_suspend(struct device *dev)
 953{
 954	struct iio_dev *indio_dev = dev_get_drvdata(dev);
 955	struct exynos_adc *info = iio_priv(indio_dev);
 956
 957	if (info->data->exit_hw)
 958		info->data->exit_hw(info);
 959	exynos_adc_disable_clk(info);
 960	regulator_disable(info->vdd);
 961
 962	return 0;
 963}
 964
 965static int exynos_adc_resume(struct device *dev)
 966{
 967	struct iio_dev *indio_dev = dev_get_drvdata(dev);
 968	struct exynos_adc *info = iio_priv(indio_dev);
 969	int ret;
 970
 971	ret = regulator_enable(info->vdd);
 972	if (ret)
 973		return ret;
 974
 975	ret = exynos_adc_enable_clk(info);
 976	if (ret)
 977		return ret;
 978
 979	if (info->data->init_hw)
 980		info->data->init_hw(info);
 981
 982	return 0;
 983}
 984#endif
 985
 986static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
 987			exynos_adc_suspend,
 988			exynos_adc_resume);
 989
 990static struct platform_driver exynos_adc_driver = {
 991	.probe		= exynos_adc_probe,
 992	.remove		= exynos_adc_remove,
 993	.driver		= {
 994		.name	= "exynos-adc",
 995		.of_match_table = exynos_adc_match,
 996		.pm	= &exynos_adc_pm_ops,
 997	},
 998};
 999
1000module_platform_driver(exynos_adc_driver);
1001
1002MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
1003MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
1004MODULE_LICENSE("GPL v2");