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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
4 *
5 * Copyright (C) 2015 Alexander Sverdlin
6 *
7 * The driver uses polling to get the conversion status. According to EP93xx
8 * datasheets, reading ADCResult register starts the conversion, but user is also
9 * responsible for ensuring that delay between adjacent conversion triggers is
10 * long enough so that maximum allowed conversion rate is not exceeded. This
11 * basically renders IRQ mode unusable.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/iio/iio.h>
19#include <linux/io.h>
20#include <linux/irqflags.h>
21#include <linux/module.h>
22#include <linux/mutex.h>
23#include <linux/platform_device.h>
24
25/*
26 * This code could benefit from real HR Timers, but jiffy granularity would
27 * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
28 * in such case.
29 *
30 * HR Timers-based version loads CPU only up to 10% during back to back ADC
31 * conversion, while busy wait-based version consumes whole CPU power.
32 */
33#ifdef CONFIG_HIGH_RES_TIMERS
34#define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
35#else
36#define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
37#endif
38
39#define EP93XX_ADC_RESULT 0x08
40#define EP93XX_ADC_SDR BIT(31)
41#define EP93XX_ADC_SWITCH 0x18
42#define EP93XX_ADC_SW_LOCK 0x20
43
44struct ep93xx_adc_priv {
45 struct clk *clk;
46 void __iomem *base;
47 int lastch;
48 struct mutex lock;
49};
50
51#define EP93XX_ADC_CH(index, dname, swcfg) { \
52 .type = IIO_VOLTAGE, \
53 .indexed = 1, \
54 .channel = index, \
55 .address = swcfg, \
56 .datasheet_name = dname, \
57 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
58 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
59 BIT(IIO_CHAN_INFO_OFFSET), \
60}
61
62/*
63 * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
64 * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
65 * not defined. So the last three are numbered randomly, let's say.
66 */
67static const struct iio_chan_spec ep93xx_adc_channels[8] = {
68 EP93XX_ADC_CH(0, "YM", 0x608),
69 EP93XX_ADC_CH(1, "SXP", 0x680),
70 EP93XX_ADC_CH(2, "SXM", 0x640),
71 EP93XX_ADC_CH(3, "SYP", 0x620),
72 EP93XX_ADC_CH(4, "SYM", 0x610),
73 EP93XX_ADC_CH(5, "XP", 0x601),
74 EP93XX_ADC_CH(6, "XM", 0x602),
75 EP93XX_ADC_CH(7, "YP", 0x604),
76};
77
78static int ep93xx_read_raw(struct iio_dev *iiodev,
79 struct iio_chan_spec const *channel, int *value,
80 int *shift, long mask)
81{
82 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
83 unsigned long timeout;
84 int ret;
85
86 switch (mask) {
87 case IIO_CHAN_INFO_RAW:
88 mutex_lock(&priv->lock);
89 if (priv->lastch != channel->channel) {
90 priv->lastch = channel->channel;
91 /*
92 * Switch register is software-locked, unlocking must be
93 * immediately followed by write
94 */
95 local_irq_disable();
96 writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
97 writel_relaxed(channel->address,
98 priv->base + EP93XX_ADC_SWITCH);
99 local_irq_enable();
100 /*
101 * Settling delay depends on module clock and could be
102 * 2ms or 500us
103 */
104 ep93xx_adc_delay(2000, 2000);
105 }
106 /* Start the conversion, eventually discarding old result */
107 readl_relaxed(priv->base + EP93XX_ADC_RESULT);
108 /* Ensure maximum conversion rate is not exceeded */
109 ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
110 DIV_ROUND_UP(1000000, 925));
111 /* At this point conversion must be completed, but anyway... */
112 ret = IIO_VAL_INT;
113 timeout = jiffies + msecs_to_jiffies(1) + 1;
114 while (1) {
115 u32 t;
116
117 t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
118 if (t & EP93XX_ADC_SDR) {
119 *value = sign_extend32(t, 15);
120 break;
121 }
122
123 if (time_after(jiffies, timeout)) {
124 dev_err(&iiodev->dev, "Conversion timeout\n");
125 ret = -ETIMEDOUT;
126 break;
127 }
128
129 cpu_relax();
130 }
131 mutex_unlock(&priv->lock);
132 return ret;
133
134 case IIO_CHAN_INFO_OFFSET:
135 /* According to datasheet, range is -25000..25000 */
136 *value = 25000;
137 return IIO_VAL_INT;
138
139 case IIO_CHAN_INFO_SCALE:
140 /* Typical supply voltage is 3.3v */
141 *value = (1ULL << 32) * 3300 / 50000;
142 *shift = 32;
143 return IIO_VAL_FRACTIONAL_LOG2;
144 }
145
146 return -EINVAL;
147}
148
149static const struct iio_info ep93xx_adc_info = {
150 .read_raw = ep93xx_read_raw,
151};
152
153static int ep93xx_adc_probe(struct platform_device *pdev)
154{
155 int ret;
156 struct iio_dev *iiodev;
157 struct ep93xx_adc_priv *priv;
158 struct clk *pclk;
159 struct resource *res;
160
161 iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
162 if (!iiodev)
163 return -ENOMEM;
164 priv = iio_priv(iiodev);
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
167 priv->base = devm_ioremap_resource(&pdev->dev, res);
168 if (IS_ERR(priv->base)) {
169 dev_err(&pdev->dev, "Cannot map memory resource\n");
170 return PTR_ERR(priv->base);
171 }
172
173 iiodev->dev.parent = &pdev->dev;
174 iiodev->name = dev_name(&pdev->dev);
175 iiodev->modes = INDIO_DIRECT_MODE;
176 iiodev->info = &ep93xx_adc_info;
177 iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
178 iiodev->channels = ep93xx_adc_channels;
179
180 priv->lastch = -1;
181 mutex_init(&priv->lock);
182
183 platform_set_drvdata(pdev, iiodev);
184
185 priv->clk = devm_clk_get(&pdev->dev, NULL);
186 if (IS_ERR(priv->clk)) {
187 dev_err(&pdev->dev, "Cannot obtain clock\n");
188 return PTR_ERR(priv->clk);
189 }
190
191 pclk = clk_get_parent(priv->clk);
192 if (!pclk) {
193 dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
194 } else {
195 /*
196 * This is actually a place for improvement:
197 * EP93xx ADC supports two clock divisors -- 4 and 16,
198 * resulting in conversion rates 3750 and 925 samples per second
199 * with 500us or 2ms settling time respectively.
200 * One might find this interesting enough to be configurable.
201 */
202 ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
203 if (ret)
204 dev_warn(&pdev->dev, "Cannot set clock rate\n");
205 /*
206 * We can tolerate rate setting failure because the module should
207 * work in any case.
208 */
209 }
210
211 ret = clk_enable(priv->clk);
212 if (ret) {
213 dev_err(&pdev->dev, "Cannot enable clock\n");
214 return ret;
215 }
216
217 ret = iio_device_register(iiodev);
218 if (ret)
219 clk_disable(priv->clk);
220
221 return ret;
222}
223
224static int ep93xx_adc_remove(struct platform_device *pdev)
225{
226 struct iio_dev *iiodev = platform_get_drvdata(pdev);
227 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
228
229 iio_device_unregister(iiodev);
230 clk_disable(priv->clk);
231
232 return 0;
233}
234
235static struct platform_driver ep93xx_adc_driver = {
236 .driver = {
237 .name = "ep93xx-adc",
238 },
239 .probe = ep93xx_adc_probe,
240 .remove = ep93xx_adc_remove,
241};
242module_platform_driver(ep93xx_adc_driver);
243
244MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
245MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
246MODULE_LICENSE("GPL");
247MODULE_ALIAS("platform:ep93xx-adc");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
4 *
5 * Copyright (C) 2015 Alexander Sverdlin
6 *
7 * The driver uses polling to get the conversion status. According to EP93xx
8 * datasheets, reading ADCResult register starts the conversion, but user is also
9 * responsible for ensuring that delay between adjacent conversion triggers is
10 * long enough so that maximum allowed conversion rate is not exceeded. This
11 * basically renders IRQ mode unusable.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/iio/iio.h>
19#include <linux/io.h>
20#include <linux/irqflags.h>
21#include <linux/module.h>
22#include <linux/mutex.h>
23#include <linux/platform_device.h>
24
25/*
26 * This code could benefit from real HR Timers, but jiffy granularity would
27 * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
28 * in such case.
29 *
30 * HR Timers-based version loads CPU only up to 10% during back to back ADC
31 * conversion, while busy wait-based version consumes whole CPU power.
32 */
33#ifdef CONFIG_HIGH_RES_TIMERS
34#define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
35#else
36#define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
37#endif
38
39#define EP93XX_ADC_RESULT 0x08
40#define EP93XX_ADC_SDR BIT(31)
41#define EP93XX_ADC_SWITCH 0x18
42#define EP93XX_ADC_SW_LOCK 0x20
43
44struct ep93xx_adc_priv {
45 struct clk *clk;
46 void __iomem *base;
47 int lastch;
48 struct mutex lock;
49};
50
51#define EP93XX_ADC_CH(index, dname, swcfg) { \
52 .type = IIO_VOLTAGE, \
53 .indexed = 1, \
54 .channel = index, \
55 .address = swcfg, \
56 .datasheet_name = dname, \
57 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
58 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
59 BIT(IIO_CHAN_INFO_OFFSET), \
60}
61
62/*
63 * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
64 * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
65 * not defined. So the last three are numbered randomly, let's say.
66 */
67static const struct iio_chan_spec ep93xx_adc_channels[8] = {
68 EP93XX_ADC_CH(0, "YM", 0x608),
69 EP93XX_ADC_CH(1, "SXP", 0x680),
70 EP93XX_ADC_CH(2, "SXM", 0x640),
71 EP93XX_ADC_CH(3, "SYP", 0x620),
72 EP93XX_ADC_CH(4, "SYM", 0x610),
73 EP93XX_ADC_CH(5, "XP", 0x601),
74 EP93XX_ADC_CH(6, "XM", 0x602),
75 EP93XX_ADC_CH(7, "YP", 0x604),
76};
77
78static int ep93xx_read_raw(struct iio_dev *iiodev,
79 struct iio_chan_spec const *channel, int *value,
80 int *shift, long mask)
81{
82 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
83 unsigned long timeout;
84 int ret;
85
86 switch (mask) {
87 case IIO_CHAN_INFO_RAW:
88 mutex_lock(&priv->lock);
89 if (priv->lastch != channel->channel) {
90 priv->lastch = channel->channel;
91 /*
92 * Switch register is software-locked, unlocking must be
93 * immediately followed by write
94 */
95 local_irq_disable();
96 writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
97 writel_relaxed(channel->address,
98 priv->base + EP93XX_ADC_SWITCH);
99 local_irq_enable();
100 /*
101 * Settling delay depends on module clock and could be
102 * 2ms or 500us
103 */
104 ep93xx_adc_delay(2000, 2000);
105 }
106 /* Start the conversion, eventually discarding old result */
107 readl_relaxed(priv->base + EP93XX_ADC_RESULT);
108 /* Ensure maximum conversion rate is not exceeded */
109 ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
110 DIV_ROUND_UP(1000000, 925));
111 /* At this point conversion must be completed, but anyway... */
112 ret = IIO_VAL_INT;
113 timeout = jiffies + msecs_to_jiffies(1) + 1;
114 while (1) {
115 u32 t;
116
117 t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
118 if (t & EP93XX_ADC_SDR) {
119 *value = sign_extend32(t, 15);
120 break;
121 }
122
123 if (time_after(jiffies, timeout)) {
124 dev_err(&iiodev->dev, "Conversion timeout\n");
125 ret = -ETIMEDOUT;
126 break;
127 }
128
129 cpu_relax();
130 }
131 mutex_unlock(&priv->lock);
132 return ret;
133
134 case IIO_CHAN_INFO_OFFSET:
135 /* According to datasheet, range is -25000..25000 */
136 *value = 25000;
137 return IIO_VAL_INT;
138
139 case IIO_CHAN_INFO_SCALE:
140 /* Typical supply voltage is 3.3v */
141 *value = (1ULL << 32) * 3300 / 50000;
142 *shift = 32;
143 return IIO_VAL_FRACTIONAL_LOG2;
144 }
145
146 return -EINVAL;
147}
148
149static const struct iio_info ep93xx_adc_info = {
150 .read_raw = ep93xx_read_raw,
151};
152
153static int ep93xx_adc_probe(struct platform_device *pdev)
154{
155 int ret;
156 struct iio_dev *iiodev;
157 struct ep93xx_adc_priv *priv;
158 struct clk *pclk;
159 struct resource *res;
160
161 iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
162 if (!iiodev)
163 return -ENOMEM;
164 priv = iio_priv(iiodev);
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
167 priv->base = devm_ioremap_resource(&pdev->dev, res);
168 if (IS_ERR(priv->base)) {
169 dev_err(&pdev->dev, "Cannot map memory resource\n");
170 return PTR_ERR(priv->base);
171 }
172
173 iiodev->name = dev_name(&pdev->dev);
174 iiodev->modes = INDIO_DIRECT_MODE;
175 iiodev->info = &ep93xx_adc_info;
176 iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
177 iiodev->channels = ep93xx_adc_channels;
178
179 priv->lastch = -1;
180 mutex_init(&priv->lock);
181
182 platform_set_drvdata(pdev, iiodev);
183
184 priv->clk = devm_clk_get(&pdev->dev, NULL);
185 if (IS_ERR(priv->clk)) {
186 dev_err(&pdev->dev, "Cannot obtain clock\n");
187 return PTR_ERR(priv->clk);
188 }
189
190 pclk = clk_get_parent(priv->clk);
191 if (!pclk) {
192 dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
193 } else {
194 /*
195 * This is actually a place for improvement:
196 * EP93xx ADC supports two clock divisors -- 4 and 16,
197 * resulting in conversion rates 3750 and 925 samples per second
198 * with 500us or 2ms settling time respectively.
199 * One might find this interesting enough to be configurable.
200 */
201 ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
202 if (ret)
203 dev_warn(&pdev->dev, "Cannot set clock rate\n");
204 /*
205 * We can tolerate rate setting failure because the module should
206 * work in any case.
207 */
208 }
209
210 ret = clk_enable(priv->clk);
211 if (ret) {
212 dev_err(&pdev->dev, "Cannot enable clock\n");
213 return ret;
214 }
215
216 ret = iio_device_register(iiodev);
217 if (ret)
218 clk_disable(priv->clk);
219
220 return ret;
221}
222
223static int ep93xx_adc_remove(struct platform_device *pdev)
224{
225 struct iio_dev *iiodev = platform_get_drvdata(pdev);
226 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
227
228 iio_device_unregister(iiodev);
229 clk_disable(priv->clk);
230
231 return 0;
232}
233
234static struct platform_driver ep93xx_adc_driver = {
235 .driver = {
236 .name = "ep93xx-adc",
237 },
238 .probe = ep93xx_adc_probe,
239 .remove = ep93xx_adc_remove,
240};
241module_platform_driver(ep93xx_adc_driver);
242
243MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
244MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
245MODULE_LICENSE("GPL");
246MODULE_ALIAS("platform:ep93xx-adc");