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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AD7904/AD7914/AD7923/AD7924 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
6 * Copyright 2012 CS Systemes d'Information
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/trigger_consumer.h>
24#include <linux/iio/triggered_buffer.h>
25
26#define AD7923_WRITE_CR BIT(11) /* write control register */
27#define AD7923_RANGE BIT(1) /* range to REFin */
28#define AD7923_CODING BIT(0) /* coding is straight binary */
29#define AD7923_PM_MODE_AS (1) /* auto shutdown */
30#define AD7923_PM_MODE_FS (2) /* full shutdown */
31#define AD7923_PM_MODE_OPS (3) /* normal operation */
32#define AD7923_CHANNEL_0 (0) /* analog input 0 */
33#define AD7923_CHANNEL_1 (1) /* analog input 1 */
34#define AD7923_CHANNEL_2 (2) /* analog input 2 */
35#define AD7923_CHANNEL_3 (3) /* analog input 3 */
36#define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
37#define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
38#define AD7923_SEQUENCE_ON (3) /* continuous sequence */
39
40#define AD7923_MAX_CHAN 4
41
42#define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
43#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
44#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
45 + (((sequence) & 2) << 9))
46 /* write sequence fonction */
47/* left shift for CR : bit 11 transmit in first */
48#define AD7923_SHIFT_REGISTER 4
49
50/* val = value, dec = left shift, bits = number of bits of the mask */
51#define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
52
53struct ad7923_state {
54 struct spi_device *spi;
55 struct spi_transfer ring_xfer[5];
56 struct spi_transfer scan_single_xfer[2];
57 struct spi_message ring_msg;
58 struct spi_message scan_single_msg;
59
60 struct regulator *reg;
61
62 unsigned int settings;
63
64 /*
65 * DMA (thus cache coherency maintenance) requires the
66 * transfer buffers to live in their own cache lines.
67 */
68 __be16 rx_buf[4] ____cacheline_aligned;
69 __be16 tx_buf[4];
70};
71
72struct ad7923_chip_info {
73 const struct iio_chan_spec *channels;
74 unsigned int num_channels;
75};
76
77enum ad7923_id {
78 AD7904,
79 AD7914,
80 AD7924,
81};
82
83#define AD7923_V_CHAN(index, bits) \
84 { \
85 .type = IIO_VOLTAGE, \
86 .indexed = 1, \
87 .channel = index, \
88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
89 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
90 .address = index, \
91 .scan_index = index, \
92 .scan_type = { \
93 .sign = 'u', \
94 .realbits = (bits), \
95 .storagebits = 16, \
96 .endianness = IIO_BE, \
97 }, \
98 }
99
100#define DECLARE_AD7923_CHANNELS(name, bits) \
101const struct iio_chan_spec name ## _channels[] = { \
102 AD7923_V_CHAN(0, bits), \
103 AD7923_V_CHAN(1, bits), \
104 AD7923_V_CHAN(2, bits), \
105 AD7923_V_CHAN(3, bits), \
106 IIO_CHAN_SOFT_TIMESTAMP(4), \
107}
108
109static DECLARE_AD7923_CHANNELS(ad7904, 8);
110static DECLARE_AD7923_CHANNELS(ad7914, 10);
111static DECLARE_AD7923_CHANNELS(ad7924, 12);
112
113static const struct ad7923_chip_info ad7923_chip_info[] = {
114 [AD7904] = {
115 .channels = ad7904_channels,
116 .num_channels = ARRAY_SIZE(ad7904_channels),
117 },
118 [AD7914] = {
119 .channels = ad7914_channels,
120 .num_channels = ARRAY_SIZE(ad7914_channels),
121 },
122 [AD7924] = {
123 .channels = ad7924_channels,
124 .num_channels = ARRAY_SIZE(ad7924_channels),
125 },
126};
127
128/**
129 * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
130 **/
131static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
132 const unsigned long *active_scan_mask)
133{
134 struct ad7923_state *st = iio_priv(indio_dev);
135 int i, cmd, len;
136
137 len = 0;
138 for_each_set_bit(i, active_scan_mask, AD7923_MAX_CHAN) {
139 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
140 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
141 st->settings;
142 cmd <<= AD7923_SHIFT_REGISTER;
143 st->tx_buf[len++] = cpu_to_be16(cmd);
144 }
145 /* build spi ring message */
146 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
147 st->ring_xfer[0].len = len;
148 st->ring_xfer[0].cs_change = 1;
149
150 spi_message_init(&st->ring_msg);
151 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
152
153 for (i = 0; i < len; i++) {
154 st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
155 st->ring_xfer[i + 1].len = 2;
156 st->ring_xfer[i + 1].cs_change = 1;
157 spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
158 }
159 /* make sure last transfer cs_change is not set */
160 st->ring_xfer[i + 1].cs_change = 0;
161
162 return 0;
163}
164
165/**
166 * ad7923_trigger_handler() bh of trigger launched polling to ring buffer
167 *
168 * Currently there is no option in this driver to disable the saving of
169 * timestamps within the ring.
170 **/
171static irqreturn_t ad7923_trigger_handler(int irq, void *p)
172{
173 struct iio_poll_func *pf = p;
174 struct iio_dev *indio_dev = pf->indio_dev;
175 struct ad7923_state *st = iio_priv(indio_dev);
176 int b_sent;
177
178 b_sent = spi_sync(st->spi, &st->ring_msg);
179 if (b_sent)
180 goto done;
181
182 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
183 iio_get_time_ns(indio_dev));
184
185done:
186 iio_trigger_notify_done(indio_dev->trig);
187
188 return IRQ_HANDLED;
189}
190
191static int ad7923_scan_direct(struct ad7923_state *st, unsigned ch)
192{
193 int ret, cmd;
194
195 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
196 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
197 st->settings;
198 cmd <<= AD7923_SHIFT_REGISTER;
199 st->tx_buf[0] = cpu_to_be16(cmd);
200
201 ret = spi_sync(st->spi, &st->scan_single_msg);
202 if (ret)
203 return ret;
204
205 return be16_to_cpu(st->rx_buf[0]);
206}
207
208static int ad7923_get_range(struct ad7923_state *st)
209{
210 int vref;
211
212 vref = regulator_get_voltage(st->reg);
213 if (vref < 0)
214 return vref;
215
216 vref /= 1000;
217
218 if (!(st->settings & AD7923_RANGE))
219 vref *= 2;
220
221 return vref;
222}
223
224static int ad7923_read_raw(struct iio_dev *indio_dev,
225 struct iio_chan_spec const *chan,
226 int *val,
227 int *val2,
228 long m)
229{
230 int ret;
231 struct ad7923_state *st = iio_priv(indio_dev);
232
233 switch (m) {
234 case IIO_CHAN_INFO_RAW:
235 ret = iio_device_claim_direct_mode(indio_dev);
236 if (ret)
237 return ret;
238 ret = ad7923_scan_direct(st, chan->address);
239 iio_device_release_direct_mode(indio_dev);
240
241 if (ret < 0)
242 return ret;
243
244 if (chan->address == EXTRACT(ret, 12, 4))
245 *val = EXTRACT(ret, 0, 12);
246 else
247 return -EIO;
248
249 return IIO_VAL_INT;
250 case IIO_CHAN_INFO_SCALE:
251 ret = ad7923_get_range(st);
252 if (ret < 0)
253 return ret;
254 *val = ret;
255 *val2 = chan->scan_type.realbits;
256 return IIO_VAL_FRACTIONAL_LOG2;
257 }
258 return -EINVAL;
259}
260
261static const struct iio_info ad7923_info = {
262 .read_raw = &ad7923_read_raw,
263 .update_scan_mode = ad7923_update_scan_mode,
264};
265
266static int ad7923_probe(struct spi_device *spi)
267{
268 struct ad7923_state *st;
269 struct iio_dev *indio_dev;
270 const struct ad7923_chip_info *info;
271 int ret;
272
273 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
274 if (!indio_dev)
275 return -ENOMEM;
276
277 st = iio_priv(indio_dev);
278
279 spi_set_drvdata(spi, indio_dev);
280
281 st->spi = spi;
282 st->settings = AD7923_CODING | AD7923_RANGE |
283 AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
284
285 info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
286
287 indio_dev->name = spi_get_device_id(spi)->name;
288 indio_dev->dev.parent = &spi->dev;
289 indio_dev->dev.of_node = spi->dev.of_node;
290 indio_dev->modes = INDIO_DIRECT_MODE;
291 indio_dev->channels = info->channels;
292 indio_dev->num_channels = info->num_channels;
293 indio_dev->info = &ad7923_info;
294
295 /* Setup default message */
296
297 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
298 st->scan_single_xfer[0].len = 2;
299 st->scan_single_xfer[0].cs_change = 1;
300 st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
301 st->scan_single_xfer[1].len = 2;
302
303 spi_message_init(&st->scan_single_msg);
304 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
305 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
306
307 st->reg = devm_regulator_get(&spi->dev, "refin");
308 if (IS_ERR(st->reg))
309 return PTR_ERR(st->reg);
310
311 ret = regulator_enable(st->reg);
312 if (ret)
313 return ret;
314
315 ret = iio_triggered_buffer_setup(indio_dev, NULL,
316 &ad7923_trigger_handler, NULL);
317 if (ret)
318 goto error_disable_reg;
319
320 ret = iio_device_register(indio_dev);
321 if (ret)
322 goto error_cleanup_ring;
323
324 return 0;
325
326error_cleanup_ring:
327 iio_triggered_buffer_cleanup(indio_dev);
328error_disable_reg:
329 regulator_disable(st->reg);
330
331 return ret;
332}
333
334static int ad7923_remove(struct spi_device *spi)
335{
336 struct iio_dev *indio_dev = spi_get_drvdata(spi);
337 struct ad7923_state *st = iio_priv(indio_dev);
338
339 iio_device_unregister(indio_dev);
340 iio_triggered_buffer_cleanup(indio_dev);
341 regulator_disable(st->reg);
342
343 return 0;
344}
345
346static const struct spi_device_id ad7923_id[] = {
347 {"ad7904", AD7904},
348 {"ad7914", AD7914},
349 {"ad7923", AD7924},
350 {"ad7924", AD7924},
351 {}
352};
353MODULE_DEVICE_TABLE(spi, ad7923_id);
354
355static struct spi_driver ad7923_driver = {
356 .driver = {
357 .name = "ad7923",
358 },
359 .probe = ad7923_probe,
360 .remove = ad7923_remove,
361 .id_table = ad7923_id,
362};
363module_spi_driver(ad7923_driver);
364
365MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
366MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
367MODULE_DESCRIPTION("Analog Devices AD7904/AD7914/AD7923/AD7924 ADC");
368MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
6 * Copyright 2012 CS Systemes d'Information
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/trigger_consumer.h>
24#include <linux/iio/triggered_buffer.h>
25
26#define AD7923_WRITE_CR BIT(11) /* write control register */
27#define AD7923_RANGE BIT(1) /* range to REFin */
28#define AD7923_CODING BIT(0) /* coding is straight binary */
29#define AD7923_PM_MODE_AS (1) /* auto shutdown */
30#define AD7923_PM_MODE_FS (2) /* full shutdown */
31#define AD7923_PM_MODE_OPS (3) /* normal operation */
32#define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
33#define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
34#define AD7923_SEQUENCE_ON (3) /* continuous sequence */
35
36
37#define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
38#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
39#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
40 + (((sequence) & 2) << 9))
41 /* write sequence fonction */
42/* left shift for CR : bit 11 transmit in first */
43#define AD7923_SHIFT_REGISTER 4
44
45/* val = value, dec = left shift, bits = number of bits of the mask */
46#define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
47
48struct ad7923_state {
49 struct spi_device *spi;
50 struct spi_transfer ring_xfer[5];
51 struct spi_transfer scan_single_xfer[2];
52 struct spi_message ring_msg;
53 struct spi_message scan_single_msg;
54
55 struct regulator *reg;
56
57 unsigned int settings;
58
59 /*
60 * DMA (thus cache coherency maintenance) requires the
61 * transfer buffers to live in their own cache lines.
62 */
63 __be16 rx_buf[4] ____cacheline_aligned;
64 __be16 tx_buf[4];
65};
66
67struct ad7923_chip_info {
68 const struct iio_chan_spec *channels;
69 unsigned int num_channels;
70};
71
72enum ad7923_id {
73 AD7904,
74 AD7914,
75 AD7924,
76 AD7908,
77 AD7918,
78 AD7928
79};
80
81#define AD7923_V_CHAN(index, bits) \
82 { \
83 .type = IIO_VOLTAGE, \
84 .indexed = 1, \
85 .channel = index, \
86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
88 .address = index, \
89 .scan_index = index, \
90 .scan_type = { \
91 .sign = 'u', \
92 .realbits = (bits), \
93 .storagebits = 16, \
94 .endianness = IIO_BE, \
95 }, \
96 }
97
98#define DECLARE_AD7923_CHANNELS(name, bits) \
99const struct iio_chan_spec name ## _channels[] = { \
100 AD7923_V_CHAN(0, bits), \
101 AD7923_V_CHAN(1, bits), \
102 AD7923_V_CHAN(2, bits), \
103 AD7923_V_CHAN(3, bits), \
104 IIO_CHAN_SOFT_TIMESTAMP(4), \
105}
106
107#define DECLARE_AD7908_CHANNELS(name, bits) \
108const struct iio_chan_spec name ## _channels[] = { \
109 AD7923_V_CHAN(0, bits), \
110 AD7923_V_CHAN(1, bits), \
111 AD7923_V_CHAN(2, bits), \
112 AD7923_V_CHAN(3, bits), \
113 AD7923_V_CHAN(4, bits), \
114 AD7923_V_CHAN(5, bits), \
115 AD7923_V_CHAN(6, bits), \
116 AD7923_V_CHAN(7, bits), \
117 IIO_CHAN_SOFT_TIMESTAMP(8), \
118}
119
120static DECLARE_AD7923_CHANNELS(ad7904, 8);
121static DECLARE_AD7923_CHANNELS(ad7914, 10);
122static DECLARE_AD7923_CHANNELS(ad7924, 12);
123static DECLARE_AD7908_CHANNELS(ad7908, 8);
124static DECLARE_AD7908_CHANNELS(ad7918, 10);
125static DECLARE_AD7908_CHANNELS(ad7928, 12);
126
127static const struct ad7923_chip_info ad7923_chip_info[] = {
128 [AD7904] = {
129 .channels = ad7904_channels,
130 .num_channels = ARRAY_SIZE(ad7904_channels),
131 },
132 [AD7914] = {
133 .channels = ad7914_channels,
134 .num_channels = ARRAY_SIZE(ad7914_channels),
135 },
136 [AD7924] = {
137 .channels = ad7924_channels,
138 .num_channels = ARRAY_SIZE(ad7924_channels),
139 },
140 [AD7908] = {
141 .channels = ad7908_channels,
142 .num_channels = ARRAY_SIZE(ad7908_channels),
143 },
144 [AD7918] = {
145 .channels = ad7918_channels,
146 .num_channels = ARRAY_SIZE(ad7918_channels),
147 },
148 [AD7928] = {
149 .channels = ad7928_channels,
150 .num_channels = ARRAY_SIZE(ad7928_channels),
151 },
152};
153
154/*
155 * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
156 */
157static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
158 const unsigned long *active_scan_mask)
159{
160 struct ad7923_state *st = iio_priv(indio_dev);
161 int i, cmd, len;
162
163 len = 0;
164 /*
165 * For this driver the last channel is always the software timestamp so
166 * skip that one.
167 */
168 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
169 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
170 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
171 st->settings;
172 cmd <<= AD7923_SHIFT_REGISTER;
173 st->tx_buf[len++] = cpu_to_be16(cmd);
174 }
175 /* build spi ring message */
176 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
177 st->ring_xfer[0].len = len;
178 st->ring_xfer[0].cs_change = 1;
179
180 spi_message_init(&st->ring_msg);
181 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
182
183 for (i = 0; i < len; i++) {
184 st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
185 st->ring_xfer[i + 1].len = 2;
186 st->ring_xfer[i + 1].cs_change = 1;
187 spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
188 }
189 /* make sure last transfer cs_change is not set */
190 st->ring_xfer[i + 1].cs_change = 0;
191
192 return 0;
193}
194
195/*
196 * ad7923_trigger_handler() bh of trigger launched polling to ring buffer
197 *
198 * Currently there is no option in this driver to disable the saving of
199 * timestamps within the ring.
200 */
201static irqreturn_t ad7923_trigger_handler(int irq, void *p)
202{
203 struct iio_poll_func *pf = p;
204 struct iio_dev *indio_dev = pf->indio_dev;
205 struct ad7923_state *st = iio_priv(indio_dev);
206 int b_sent;
207
208 b_sent = spi_sync(st->spi, &st->ring_msg);
209 if (b_sent)
210 goto done;
211
212 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
213 iio_get_time_ns(indio_dev));
214
215done:
216 iio_trigger_notify_done(indio_dev->trig);
217
218 return IRQ_HANDLED;
219}
220
221static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
222{
223 int ret, cmd;
224
225 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
226 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
227 st->settings;
228 cmd <<= AD7923_SHIFT_REGISTER;
229 st->tx_buf[0] = cpu_to_be16(cmd);
230
231 ret = spi_sync(st->spi, &st->scan_single_msg);
232 if (ret)
233 return ret;
234
235 return be16_to_cpu(st->rx_buf[0]);
236}
237
238static int ad7923_get_range(struct ad7923_state *st)
239{
240 int vref;
241
242 vref = regulator_get_voltage(st->reg);
243 if (vref < 0)
244 return vref;
245
246 vref /= 1000;
247
248 if (!(st->settings & AD7923_RANGE))
249 vref *= 2;
250
251 return vref;
252}
253
254static int ad7923_read_raw(struct iio_dev *indio_dev,
255 struct iio_chan_spec const *chan,
256 int *val,
257 int *val2,
258 long m)
259{
260 int ret;
261 struct ad7923_state *st = iio_priv(indio_dev);
262
263 switch (m) {
264 case IIO_CHAN_INFO_RAW:
265 ret = iio_device_claim_direct_mode(indio_dev);
266 if (ret)
267 return ret;
268 ret = ad7923_scan_direct(st, chan->address);
269 iio_device_release_direct_mode(indio_dev);
270
271 if (ret < 0)
272 return ret;
273
274 if (chan->address == EXTRACT(ret, 12, 4))
275 *val = EXTRACT(ret, 0, 12);
276 else
277 return -EIO;
278
279 return IIO_VAL_INT;
280 case IIO_CHAN_INFO_SCALE:
281 ret = ad7923_get_range(st);
282 if (ret < 0)
283 return ret;
284 *val = ret;
285 *val2 = chan->scan_type.realbits;
286 return IIO_VAL_FRACTIONAL_LOG2;
287 }
288 return -EINVAL;
289}
290
291static const struct iio_info ad7923_info = {
292 .read_raw = &ad7923_read_raw,
293 .update_scan_mode = ad7923_update_scan_mode,
294};
295
296static int ad7923_probe(struct spi_device *spi)
297{
298 struct ad7923_state *st;
299 struct iio_dev *indio_dev;
300 const struct ad7923_chip_info *info;
301 int ret;
302
303 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
304 if (!indio_dev)
305 return -ENOMEM;
306
307 st = iio_priv(indio_dev);
308
309 spi_set_drvdata(spi, indio_dev);
310
311 st->spi = spi;
312 st->settings = AD7923_CODING | AD7923_RANGE |
313 AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
314
315 info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
316
317 indio_dev->name = spi_get_device_id(spi)->name;
318 indio_dev->modes = INDIO_DIRECT_MODE;
319 indio_dev->channels = info->channels;
320 indio_dev->num_channels = info->num_channels;
321 indio_dev->info = &ad7923_info;
322
323 /* Setup default message */
324
325 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
326 st->scan_single_xfer[0].len = 2;
327 st->scan_single_xfer[0].cs_change = 1;
328 st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
329 st->scan_single_xfer[1].len = 2;
330
331 spi_message_init(&st->scan_single_msg);
332 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
333 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
334
335 st->reg = devm_regulator_get(&spi->dev, "refin");
336 if (IS_ERR(st->reg))
337 return PTR_ERR(st->reg);
338
339 ret = regulator_enable(st->reg);
340 if (ret)
341 return ret;
342
343 ret = iio_triggered_buffer_setup(indio_dev, NULL,
344 &ad7923_trigger_handler, NULL);
345 if (ret)
346 goto error_disable_reg;
347
348 ret = iio_device_register(indio_dev);
349 if (ret)
350 goto error_cleanup_ring;
351
352 return 0;
353
354error_cleanup_ring:
355 iio_triggered_buffer_cleanup(indio_dev);
356error_disable_reg:
357 regulator_disable(st->reg);
358
359 return ret;
360}
361
362static int ad7923_remove(struct spi_device *spi)
363{
364 struct iio_dev *indio_dev = spi_get_drvdata(spi);
365 struct ad7923_state *st = iio_priv(indio_dev);
366
367 iio_device_unregister(indio_dev);
368 iio_triggered_buffer_cleanup(indio_dev);
369 regulator_disable(st->reg);
370
371 return 0;
372}
373
374static const struct spi_device_id ad7923_id[] = {
375 {"ad7904", AD7904},
376 {"ad7914", AD7914},
377 {"ad7923", AD7924},
378 {"ad7924", AD7924},
379 {"ad7908", AD7908},
380 {"ad7918", AD7918},
381 {"ad7928", AD7928},
382 {}
383};
384MODULE_DEVICE_TABLE(spi, ad7923_id);
385
386static const struct of_device_id ad7923_of_match[] = {
387 { .compatible = "adi,ad7904", },
388 { .compatible = "adi,ad7914", },
389 { .compatible = "adi,ad7923", },
390 { .compatible = "adi,ad7924", },
391 { .compatible = "adi,ad7908", },
392 { .compatible = "adi,ad7918", },
393 { .compatible = "adi,ad7928", },
394 { },
395};
396MODULE_DEVICE_TABLE(of, ad7923_of_match);
397
398static struct spi_driver ad7923_driver = {
399 .driver = {
400 .name = "ad7923",
401 .of_match_table = ad7923_of_match,
402 },
403 .probe = ad7923_probe,
404 .remove = ad7923_remove,
405 .id_table = ad7923_id,
406};
407module_spi_driver(ad7923_driver);
408
409MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
410MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
411MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
412MODULE_LICENSE("GPL v2");