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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9
10 */
11
12#include <drm/drm_crtc_helper.h>
13#include <drm/drm_modeset_helper_vtables.h>
14#include <drm/drm_vblank.h>
15
16#include "udl_drv.h"
17
18/*
19 * All DisplayLink bulk operations start with 0xAF, followed by specific code
20 * All operations are written to buffers which then later get sent to device
21 */
22static char *udl_set_register(char *buf, u8 reg, u8 val)
23{
24 *buf++ = 0xAF;
25 *buf++ = 0x20;
26 *buf++ = reg;
27 *buf++ = val;
28 return buf;
29}
30
31static char *udl_vidreg_lock(char *buf)
32{
33 return udl_set_register(buf, 0xFF, 0x00);
34}
35
36static char *udl_vidreg_unlock(char *buf)
37{
38 return udl_set_register(buf, 0xFF, 0xFF);
39}
40
41/*
42 * On/Off for driving the DisplayLink framebuffer to the display
43 * 0x00 H and V sync on
44 * 0x01 H and V sync off (screen blank but powered)
45 * 0x07 DPMS powerdown (requires modeset to come back)
46 */
47static char *udl_set_blank(char *buf, int dpms_mode)
48{
49 u8 reg;
50 switch (dpms_mode) {
51 case DRM_MODE_DPMS_OFF:
52 reg = 0x07;
53 break;
54 case DRM_MODE_DPMS_STANDBY:
55 reg = 0x05;
56 break;
57 case DRM_MODE_DPMS_SUSPEND:
58 reg = 0x01;
59 break;
60 case DRM_MODE_DPMS_ON:
61 reg = 0x00;
62 break;
63 }
64
65 return udl_set_register(buf, 0x1f, reg);
66}
67
68static char *udl_set_color_depth(char *buf, u8 selection)
69{
70 return udl_set_register(buf, 0x00, selection);
71}
72
73static char *udl_set_base16bpp(char *wrptr, u32 base)
74{
75 /* the base pointer is 16 bits wide, 0x20 is hi byte. */
76 wrptr = udl_set_register(wrptr, 0x20, base >> 16);
77 wrptr = udl_set_register(wrptr, 0x21, base >> 8);
78 return udl_set_register(wrptr, 0x22, base);
79}
80
81/*
82 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
83 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
84 */
85static char *udl_set_base8bpp(char *wrptr, u32 base)
86{
87 wrptr = udl_set_register(wrptr, 0x26, base >> 16);
88 wrptr = udl_set_register(wrptr, 0x27, base >> 8);
89 return udl_set_register(wrptr, 0x28, base);
90}
91
92static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
93{
94 wrptr = udl_set_register(wrptr, reg, value >> 8);
95 return udl_set_register(wrptr, reg+1, value);
96}
97
98/*
99 * This is kind of weird because the controller takes some
100 * register values in a different byte order than other registers.
101 */
102static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
103{
104 wrptr = udl_set_register(wrptr, reg, value);
105 return udl_set_register(wrptr, reg+1, value >> 8);
106}
107
108/*
109 * LFSR is linear feedback shift register. The reason we have this is
110 * because the display controller needs to minimize the clock depth of
111 * various counters used in the display path. So this code reverses the
112 * provided value into the lfsr16 value by counting backwards to get
113 * the value that needs to be set in the hardware comparator to get the
114 * same actual count. This makes sense once you read above a couple of
115 * times and think about it from a hardware perspective.
116 */
117static u16 udl_lfsr16(u16 actual_count)
118{
119 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
120
121 while (actual_count--) {
122 lv = ((lv << 1) |
123 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
124 & 0xFFFF;
125 }
126
127 return (u16) lv;
128}
129
130/*
131 * This does LFSR conversion on the value that is to be written.
132 * See LFSR explanation above for more detail.
133 */
134static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
135{
136 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
137}
138
139/*
140 * This takes a standard fbdev screeninfo struct and all of its monitor mode
141 * details and converts them into the DisplayLink equivalent register commands.
142 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
143 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart));
144 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd));
145 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart));
146 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd));
147 ERR(vreg_lfsr16(dev, 0x09, xEndCount));
148 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart));
149 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd));
150 ERR(vreg_big_endian(dev, 0x0F, hPixels));
151 ERR(vreg_lfsr16(dev, 0x11, yEndCount));
152 ERR(vreg_lfsr16(dev, 0x13, vSyncStart));
153 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd));
154 ERR(vreg_big_endian(dev, 0x17, vPixels));
155 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
156
157 ERR(vreg(dev, 0x1F, 0));
158
159 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
160 */
161static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
162{
163 u16 xds, yds;
164 u16 xde, yde;
165 u16 yec;
166
167 /* x display start */
168 xds = mode->crtc_htotal - mode->crtc_hsync_start;
169 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
170 /* x display end */
171 xde = xds + mode->crtc_hdisplay;
172 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
173
174 /* y display start */
175 yds = mode->crtc_vtotal - mode->crtc_vsync_start;
176 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
177 /* y display end */
178 yde = yds + mode->crtc_vdisplay;
179 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
180
181 /* x end count is active + blanking - 1 */
182 wrptr = udl_set_register_lfsr16(wrptr, 0x09,
183 mode->crtc_htotal - 1);
184
185 /* libdlo hardcodes hsync start to 1 */
186 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
187
188 /* hsync end is width of sync pulse + 1 */
189 wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
190 mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
191
192 /* hpixels is active pixels */
193 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
194
195 /* yendcount is vertical active + vertical blanking */
196 yec = mode->crtc_vtotal;
197 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
198
199 /* libdlo hardcodes vsync start to 0 */
200 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
201
202 /* vsync end is width of vsync pulse */
203 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
204
205 /* vpixels is active pixels */
206 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
207
208 wrptr = udl_set_register_16be(wrptr, 0x1B,
209 mode->clock / 5);
210
211 return wrptr;
212}
213
214static char *udl_dummy_render(char *wrptr)
215{
216 *wrptr++ = 0xAF;
217 *wrptr++ = 0x6A; /* copy */
218 *wrptr++ = 0x00; /* from addr */
219 *wrptr++ = 0x00;
220 *wrptr++ = 0x00;
221 *wrptr++ = 0x01; /* one pixel */
222 *wrptr++ = 0x00; /* to address */
223 *wrptr++ = 0x00;
224 *wrptr++ = 0x00;
225 return wrptr;
226}
227
228static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
229{
230 struct drm_device *dev = crtc->dev;
231 struct udl_device *udl = dev->dev_private;
232 struct urb *urb;
233 char *buf;
234 int retval;
235
236 urb = udl_get_urb(dev);
237 if (!urb)
238 return -ENOMEM;
239
240 buf = (char *)urb->transfer_buffer;
241
242 memcpy(buf, udl->mode_buf, udl->mode_buf_len);
243 retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
244 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
245 return retval;
246}
247
248
249static void udl_crtc_dpms(struct drm_crtc *crtc, int mode)
250{
251 struct drm_device *dev = crtc->dev;
252 struct udl_device *udl = dev->dev_private;
253 int retval;
254
255 if (mode == DRM_MODE_DPMS_OFF) {
256 char *buf;
257 struct urb *urb;
258 urb = udl_get_urb(dev);
259 if (!urb)
260 return;
261
262 buf = (char *)urb->transfer_buffer;
263 buf = udl_vidreg_lock(buf);
264 buf = udl_set_blank(buf, mode);
265 buf = udl_vidreg_unlock(buf);
266
267 buf = udl_dummy_render(buf);
268 retval = udl_submit_urb(dev, urb, buf - (char *)
269 urb->transfer_buffer);
270 } else {
271 if (udl->mode_buf_len == 0) {
272 DRM_ERROR("Trying to enable DPMS with no mode\n");
273 return;
274 }
275 udl_crtc_write_mode_to_hw(crtc);
276 }
277
278}
279
280#if 0
281static int
282udl_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
283 int x, int y, enum mode_set_atomic state)
284{
285 return 0;
286}
287
288static int
289udl_pipe_set_base(struct drm_crtc *crtc, int x, int y,
290 struct drm_framebuffer *old_fb)
291{
292 return 0;
293}
294#endif
295
296static int udl_crtc_mode_set(struct drm_crtc *crtc,
297 struct drm_display_mode *mode,
298 struct drm_display_mode *adjusted_mode,
299 int x, int y,
300 struct drm_framebuffer *old_fb)
301
302{
303 struct drm_device *dev = crtc->dev;
304 struct udl_framebuffer *ufb = to_udl_fb(crtc->primary->fb);
305 struct udl_device *udl = dev->dev_private;
306 char *buf;
307 char *wrptr;
308 int color_depth = 0;
309
310 udl->crtc = crtc;
311
312 buf = (char *)udl->mode_buf;
313
314 /* for now we just clip 24 -> 16 - if we fix that fix this */
315 /*if (crtc->fb->bits_per_pixel != 16)
316 color_depth = 1; */
317
318 /* This first section has to do with setting the base address on the
319 * controller * associated with the display. There are 2 base
320 * pointers, currently, we only * use the 16 bpp segment.
321 */
322 wrptr = udl_vidreg_lock(buf);
323 wrptr = udl_set_color_depth(wrptr, color_depth);
324 /* set base for 16bpp segment to 0 */
325 wrptr = udl_set_base16bpp(wrptr, 0);
326 /* set base for 8bpp segment to end of fb */
327 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
328
329 wrptr = udl_set_vid_cmds(wrptr, adjusted_mode);
330 wrptr = udl_set_blank(wrptr, DRM_MODE_DPMS_ON);
331 wrptr = udl_vidreg_unlock(wrptr);
332
333 wrptr = udl_dummy_render(wrptr);
334
335 if (old_fb) {
336 struct udl_framebuffer *uold_fb = to_udl_fb(old_fb);
337 uold_fb->active_16 = false;
338 }
339 ufb->active_16 = true;
340 udl->mode_buf_len = wrptr - buf;
341
342 /* damage all of it */
343 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height);
344 return 0;
345}
346
347
348static void udl_crtc_disable(struct drm_crtc *crtc)
349{
350 udl_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
351}
352
353static void udl_crtc_destroy(struct drm_crtc *crtc)
354{
355 drm_crtc_cleanup(crtc);
356 kfree(crtc);
357}
358
359static int udl_crtc_page_flip(struct drm_crtc *crtc,
360 struct drm_framebuffer *fb,
361 struct drm_pending_vblank_event *event,
362 uint32_t page_flip_flags,
363 struct drm_modeset_acquire_ctx *ctx)
364{
365 struct udl_framebuffer *ufb = to_udl_fb(fb);
366 struct drm_device *dev = crtc->dev;
367
368 struct drm_framebuffer *old_fb = crtc->primary->fb;
369 if (old_fb) {
370 struct udl_framebuffer *uold_fb = to_udl_fb(old_fb);
371 uold_fb->active_16 = false;
372 }
373 ufb->active_16 = true;
374
375 udl_handle_damage(ufb, 0, 0, fb->width, fb->height);
376
377 spin_lock_irq(&dev->event_lock);
378 if (event)
379 drm_crtc_send_vblank_event(crtc, event);
380 spin_unlock_irq(&dev->event_lock);
381 crtc->primary->fb = fb;
382
383 return 0;
384}
385
386static void udl_crtc_prepare(struct drm_crtc *crtc)
387{
388}
389
390static void udl_crtc_commit(struct drm_crtc *crtc)
391{
392 udl_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
393}
394
395static const struct drm_crtc_helper_funcs udl_helper_funcs = {
396 .dpms = udl_crtc_dpms,
397 .mode_set = udl_crtc_mode_set,
398 .prepare = udl_crtc_prepare,
399 .commit = udl_crtc_commit,
400 .disable = udl_crtc_disable,
401};
402
403static const struct drm_crtc_funcs udl_crtc_funcs = {
404 .set_config = drm_crtc_helper_set_config,
405 .destroy = udl_crtc_destroy,
406 .page_flip = udl_crtc_page_flip,
407};
408
409static int udl_crtc_init(struct drm_device *dev)
410{
411 struct drm_crtc *crtc;
412
413 crtc = kzalloc(sizeof(struct drm_crtc) + sizeof(struct drm_connector *), GFP_KERNEL);
414 if (crtc == NULL)
415 return -ENOMEM;
416
417 drm_crtc_init(dev, crtc, &udl_crtc_funcs);
418 drm_crtc_helper_add(crtc, &udl_helper_funcs);
419
420 return 0;
421}
422
423static const struct drm_mode_config_funcs udl_mode_funcs = {
424 .fb_create = udl_fb_user_fb_create,
425 .output_poll_changed = NULL,
426};
427
428int udl_modeset_init(struct drm_device *dev)
429{
430 struct drm_encoder *encoder;
431 drm_mode_config_init(dev);
432
433 dev->mode_config.min_width = 640;
434 dev->mode_config.min_height = 480;
435
436 dev->mode_config.max_width = 2048;
437 dev->mode_config.max_height = 2048;
438
439 dev->mode_config.prefer_shadow = 0;
440 dev->mode_config.preferred_depth = 24;
441
442 dev->mode_config.funcs = &udl_mode_funcs;
443
444 udl_crtc_init(dev);
445
446 encoder = udl_encoder_init(dev);
447
448 udl_connector_init(dev, encoder);
449
450 return 0;
451}
452
453void udl_modeset_restore(struct drm_device *dev)
454{
455 struct udl_device *udl = dev->dev_private;
456 struct udl_framebuffer *ufb;
457
458 if (!udl->crtc || !udl->crtc->primary->fb)
459 return;
460 udl_crtc_commit(udl->crtc);
461 ufb = to_udl_fb(udl->crtc->primary->fb);
462 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height);
463}
464
465void udl_modeset_cleanup(struct drm_device *dev)
466{
467 drm_mode_config_cleanup(dev);
468}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9
10 */
11
12#include <linux/dma-buf.h>
13
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc_helper.h>
16#include <drm/drm_damage_helper.h>
17#include <drm/drm_fourcc.h>
18#include <drm/drm_gem_framebuffer_helper.h>
19#include <drm/drm_gem_shmem_helper.h>
20#include <drm/drm_modeset_helper_vtables.h>
21#include <drm/drm_vblank.h>
22
23#include "udl_drv.h"
24
25#define UDL_COLOR_DEPTH_16BPP 0
26
27/*
28 * All DisplayLink bulk operations start with 0xAF, followed by specific code
29 * All operations are written to buffers which then later get sent to device
30 */
31static char *udl_set_register(char *buf, u8 reg, u8 val)
32{
33 *buf++ = 0xAF;
34 *buf++ = 0x20;
35 *buf++ = reg;
36 *buf++ = val;
37 return buf;
38}
39
40static char *udl_vidreg_lock(char *buf)
41{
42 return udl_set_register(buf, 0xFF, 0x00);
43}
44
45static char *udl_vidreg_unlock(char *buf)
46{
47 return udl_set_register(buf, 0xFF, 0xFF);
48}
49
50static char *udl_set_blank_mode(char *buf, u8 mode)
51{
52 return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
53}
54
55static char *udl_set_color_depth(char *buf, u8 selection)
56{
57 return udl_set_register(buf, 0x00, selection);
58}
59
60static char *udl_set_base16bpp(char *wrptr, u32 base)
61{
62 /* the base pointer is 16 bits wide, 0x20 is hi byte. */
63 wrptr = udl_set_register(wrptr, 0x20, base >> 16);
64 wrptr = udl_set_register(wrptr, 0x21, base >> 8);
65 return udl_set_register(wrptr, 0x22, base);
66}
67
68/*
69 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
70 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
71 */
72static char *udl_set_base8bpp(char *wrptr, u32 base)
73{
74 wrptr = udl_set_register(wrptr, 0x26, base >> 16);
75 wrptr = udl_set_register(wrptr, 0x27, base >> 8);
76 return udl_set_register(wrptr, 0x28, base);
77}
78
79static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
80{
81 wrptr = udl_set_register(wrptr, reg, value >> 8);
82 return udl_set_register(wrptr, reg+1, value);
83}
84
85/*
86 * This is kind of weird because the controller takes some
87 * register values in a different byte order than other registers.
88 */
89static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
90{
91 wrptr = udl_set_register(wrptr, reg, value);
92 return udl_set_register(wrptr, reg+1, value >> 8);
93}
94
95/*
96 * LFSR is linear feedback shift register. The reason we have this is
97 * because the display controller needs to minimize the clock depth of
98 * various counters used in the display path. So this code reverses the
99 * provided value into the lfsr16 value by counting backwards to get
100 * the value that needs to be set in the hardware comparator to get the
101 * same actual count. This makes sense once you read above a couple of
102 * times and think about it from a hardware perspective.
103 */
104static u16 udl_lfsr16(u16 actual_count)
105{
106 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
107
108 while (actual_count--) {
109 lv = ((lv << 1) |
110 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
111 & 0xFFFF;
112 }
113
114 return (u16) lv;
115}
116
117/*
118 * This does LFSR conversion on the value that is to be written.
119 * See LFSR explanation above for more detail.
120 */
121static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
122{
123 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
124}
125
126/*
127 * This takes a standard fbdev screeninfo struct and all of its monitor mode
128 * details and converts them into the DisplayLink equivalent register commands.
129 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
130 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart));
131 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd));
132 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart));
133 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd));
134 ERR(vreg_lfsr16(dev, 0x09, xEndCount));
135 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart));
136 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd));
137 ERR(vreg_big_endian(dev, 0x0F, hPixels));
138 ERR(vreg_lfsr16(dev, 0x11, yEndCount));
139 ERR(vreg_lfsr16(dev, 0x13, vSyncStart));
140 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd));
141 ERR(vreg_big_endian(dev, 0x17, vPixels));
142 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
143
144 ERR(vreg(dev, 0x1F, 0));
145
146 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
147 */
148static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
149{
150 u16 xds, yds;
151 u16 xde, yde;
152 u16 yec;
153
154 /* x display start */
155 xds = mode->crtc_htotal - mode->crtc_hsync_start;
156 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
157 /* x display end */
158 xde = xds + mode->crtc_hdisplay;
159 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
160
161 /* y display start */
162 yds = mode->crtc_vtotal - mode->crtc_vsync_start;
163 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
164 /* y display end */
165 yde = yds + mode->crtc_vdisplay;
166 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
167
168 /* x end count is active + blanking - 1 */
169 wrptr = udl_set_register_lfsr16(wrptr, 0x09,
170 mode->crtc_htotal - 1);
171
172 /* libdlo hardcodes hsync start to 1 */
173 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
174
175 /* hsync end is width of sync pulse + 1 */
176 wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
177 mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
178
179 /* hpixels is active pixels */
180 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
181
182 /* yendcount is vertical active + vertical blanking */
183 yec = mode->crtc_vtotal;
184 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
185
186 /* libdlo hardcodes vsync start to 0 */
187 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
188
189 /* vsync end is width of vsync pulse */
190 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
191
192 /* vpixels is active pixels */
193 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
194
195 wrptr = udl_set_register_16be(wrptr, 0x1B,
196 mode->clock / 5);
197
198 return wrptr;
199}
200
201static char *udl_dummy_render(char *wrptr)
202{
203 *wrptr++ = 0xAF;
204 *wrptr++ = 0x6A; /* copy */
205 *wrptr++ = 0x00; /* from addr */
206 *wrptr++ = 0x00;
207 *wrptr++ = 0x00;
208 *wrptr++ = 0x01; /* one pixel */
209 *wrptr++ = 0x00; /* to address */
210 *wrptr++ = 0x00;
211 *wrptr++ = 0x00;
212 return wrptr;
213}
214
215static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
216{
217 struct drm_device *dev = crtc->dev;
218 struct udl_device *udl = to_udl(dev);
219 struct urb *urb;
220 char *buf;
221 int retval;
222
223 if (udl->mode_buf_len == 0) {
224 DRM_ERROR("No mode set\n");
225 return -EINVAL;
226 }
227
228 urb = udl_get_urb(dev);
229 if (!urb)
230 return -ENOMEM;
231
232 buf = (char *)urb->transfer_buffer;
233
234 memcpy(buf, udl->mode_buf, udl->mode_buf_len);
235 retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
236 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
237 return retval;
238}
239
240static long udl_log_cpp(unsigned int cpp)
241{
242 if (WARN_ON(!is_power_of_2(cpp)))
243 return -EINVAL;
244 return __ffs(cpp);
245}
246
247static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y,
248 int width, int height)
249{
250 int x1, x2;
251
252 if (WARN_ON_ONCE(x < 0) ||
253 WARN_ON_ONCE(y < 0) ||
254 WARN_ON_ONCE(width < 0) ||
255 WARN_ON_ONCE(height < 0))
256 return -EINVAL;
257
258 x1 = ALIGN_DOWN(x, sizeof(unsigned long));
259 x2 = ALIGN(width + (x - x1), sizeof(unsigned long)) + x1;
260
261 clip->x1 = x1;
262 clip->y1 = y;
263 clip->x2 = x2;
264 clip->y2 = y + height;
265
266 return 0;
267}
268
269static int udl_handle_damage(struct drm_framebuffer *fb, int x, int y,
270 int width, int height)
271{
272 struct drm_device *dev = fb->dev;
273 struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
274 int i, ret, tmp_ret;
275 char *cmd;
276 struct urb *urb;
277 struct drm_rect clip;
278 int log_bpp;
279 void *vaddr;
280
281 ret = udl_log_cpp(fb->format->cpp[0]);
282 if (ret < 0)
283 return ret;
284 log_bpp = ret;
285
286 ret = udl_aligned_damage_clip(&clip, x, y, width, height);
287 if (ret)
288 return ret;
289 else if ((clip.x2 > fb->width) || (clip.y2 > fb->height))
290 return -EINVAL;
291
292 if (import_attach) {
293 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
294 DMA_FROM_DEVICE);
295 if (ret)
296 return ret;
297 }
298
299 vaddr = drm_gem_shmem_vmap(fb->obj[0]);
300 if (IS_ERR(vaddr)) {
301 DRM_ERROR("failed to vmap fb\n");
302 goto out_dma_buf_end_cpu_access;
303 }
304
305 urb = udl_get_urb(dev);
306 if (!urb)
307 goto out_drm_gem_shmem_vunmap;
308 cmd = urb->transfer_buffer;
309
310 for (i = clip.y1; i < clip.y2; i++) {
311 const int line_offset = fb->pitches[0] * i;
312 const int byte_offset = line_offset + (clip.x1 << log_bpp);
313 const int dev_byte_offset = (fb->width * i + clip.x1) << log_bpp;
314 const int byte_width = (clip.x2 - clip.x1) << log_bpp;
315 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
316 &cmd, byte_offset, dev_byte_offset,
317 byte_width);
318 if (ret)
319 goto out_drm_gem_shmem_vunmap;
320 }
321
322 if (cmd > (char *)urb->transfer_buffer) {
323 /* Send partial buffer remaining before exiting */
324 int len;
325 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
326 *cmd++ = 0xAF;
327 len = cmd - (char *)urb->transfer_buffer;
328 ret = udl_submit_urb(dev, urb, len);
329 } else {
330 udl_urb_completion(urb);
331 }
332
333 ret = 0;
334
335out_drm_gem_shmem_vunmap:
336 drm_gem_shmem_vunmap(fb->obj[0], vaddr);
337out_dma_buf_end_cpu_access:
338 if (import_attach) {
339 tmp_ret = dma_buf_end_cpu_access(import_attach->dmabuf,
340 DMA_FROM_DEVICE);
341 if (tmp_ret && !ret)
342 ret = tmp_ret; /* only update ret if not set yet */
343 }
344
345 return ret;
346}
347
348/*
349 * Simple display pipeline
350 */
351
352static const uint32_t udl_simple_display_pipe_formats[] = {
353 DRM_FORMAT_RGB565,
354 DRM_FORMAT_XRGB8888,
355};
356
357static enum drm_mode_status
358udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
359 const struct drm_display_mode *mode)
360{
361 return MODE_OK;
362}
363
364static void
365udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
366 struct drm_crtc_state *crtc_state,
367 struct drm_plane_state *plane_state)
368{
369 struct drm_crtc *crtc = &pipe->crtc;
370 struct drm_device *dev = crtc->dev;
371 struct drm_framebuffer *fb = plane_state->fb;
372 struct udl_device *udl = to_udl(dev);
373 struct drm_display_mode *mode = &crtc_state->mode;
374 char *buf;
375 char *wrptr;
376 int color_depth = UDL_COLOR_DEPTH_16BPP;
377
378 buf = (char *)udl->mode_buf;
379
380 /* This first section has to do with setting the base address on the
381 * controller associated with the display. There are 2 base
382 * pointers, currently, we only use the 16 bpp segment.
383 */
384 wrptr = udl_vidreg_lock(buf);
385 wrptr = udl_set_color_depth(wrptr, color_depth);
386 /* set base for 16bpp segment to 0 */
387 wrptr = udl_set_base16bpp(wrptr, 0);
388 /* set base for 8bpp segment to end of fb */
389 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
390
391 wrptr = udl_set_vid_cmds(wrptr, mode);
392 wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
393 wrptr = udl_vidreg_unlock(wrptr);
394
395 wrptr = udl_dummy_render(wrptr);
396
397 udl->mode_buf_len = wrptr - buf;
398
399 udl_handle_damage(fb, 0, 0, fb->width, fb->height);
400
401 if (!crtc_state->mode_changed)
402 return;
403
404 /* enable display */
405 udl_crtc_write_mode_to_hw(crtc);
406}
407
408static void
409udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
410{
411 struct drm_crtc *crtc = &pipe->crtc;
412 struct drm_device *dev = crtc->dev;
413 struct urb *urb;
414 char *buf;
415
416 urb = udl_get_urb(dev);
417 if (!urb)
418 return;
419
420 buf = (char *)urb->transfer_buffer;
421 buf = udl_vidreg_lock(buf);
422 buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
423 buf = udl_vidreg_unlock(buf);
424 buf = udl_dummy_render(buf);
425
426 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
427}
428
429static void
430udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
431 struct drm_plane_state *old_plane_state)
432{
433 struct drm_plane_state *state = pipe->plane.state;
434 struct drm_framebuffer *fb = state->fb;
435 struct drm_rect rect;
436
437 if (!fb)
438 return;
439
440 if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
441 udl_handle_damage(fb, rect.x1, rect.y1, rect.x2 - rect.x1,
442 rect.y2 - rect.y1);
443}
444
445static const
446struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
447 .mode_valid = udl_simple_display_pipe_mode_valid,
448 .enable = udl_simple_display_pipe_enable,
449 .disable = udl_simple_display_pipe_disable,
450 .update = udl_simple_display_pipe_update,
451 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
452};
453
454/*
455 * Modesetting
456 */
457
458static const struct drm_mode_config_funcs udl_mode_funcs = {
459 .fb_create = drm_gem_fb_create_with_dirty,
460 .atomic_check = drm_atomic_helper_check,
461 .atomic_commit = drm_atomic_helper_commit,
462};
463
464int udl_modeset_init(struct drm_device *dev)
465{
466 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
467 struct udl_device *udl = to_udl(dev);
468 struct drm_connector *connector;
469 int ret;
470
471 ret = drmm_mode_config_init(dev);
472 if (ret)
473 return ret;
474
475 dev->mode_config.min_width = 640;
476 dev->mode_config.min_height = 480;
477
478 dev->mode_config.max_width = 2048;
479 dev->mode_config.max_height = 2048;
480
481 dev->mode_config.prefer_shadow = 0;
482 dev->mode_config.preferred_depth = 16;
483
484 dev->mode_config.funcs = &udl_mode_funcs;
485
486 connector = udl_connector_init(dev);
487 if (IS_ERR(connector))
488 return PTR_ERR(connector);
489
490 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
491
492 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
493 &udl_simple_display_pipe_funcs,
494 udl_simple_display_pipe_formats,
495 format_count, NULL, connector);
496 if (ret)
497 return ret;
498
499 drm_mode_config_reset(dev);
500
501 return 0;
502}