Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/phy/phy.h>
14
15#define MIPITX_DSI_CON 0x00
16#define RG_DSI_LDOCORE_EN BIT(0)
17#define RG_DSI_CKG_LDOOUT_EN BIT(1)
18#define RG_DSI_BCLK_SEL (3 << 2)
19#define RG_DSI_LD_IDX_SEL (7 << 4)
20#define RG_DSI_PHYCLK_SEL (2 << 8)
21#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
22#define RG_DSI_LPTX_CLMP_EN BIT(11)
23
24#define MIPITX_DSI_CLOCK_LANE 0x04
25#define MIPITX_DSI_DATA_LANE0 0x08
26#define MIPITX_DSI_DATA_LANE1 0x0c
27#define MIPITX_DSI_DATA_LANE2 0x10
28#define MIPITX_DSI_DATA_LANE3 0x14
29#define RG_DSI_LNTx_LDOOUT_EN BIT(0)
30#define RG_DSI_LNTx_CKLANE_EN BIT(1)
31#define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
32#define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
33#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
34#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
35#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
36#define RG_DSI_LNTx_RT_CODE (0xf << 8)
37
38#define MIPITX_DSI_TOP_CON 0x40
39#define RG_DSI_LNT_INTR_EN BIT(0)
40#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
41#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
42#define RG_DSI_LNT_TESTMODE_EN BIT(3)
43#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
44#define RG_DSI_LNT_AIO_SEL (7 << 8)
45#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
46#define RG_DSI_DEBUG_INPUT_EN BIT(12)
47#define RG_DSI_PRESERVE (7 << 13)
48
49#define MIPITX_DSI_BG_CON 0x44
50#define RG_DSI_BG_CORE_EN BIT(0)
51#define RG_DSI_BG_CKEN BIT(1)
52#define RG_DSI_BG_DIV (0x3 << 2)
53#define RG_DSI_BG_FAST_CHARGE BIT(4)
54#define RG_DSI_VOUT_MSK (0x3ffff << 5)
55#define RG_DSI_V12_SEL (7 << 5)
56#define RG_DSI_V10_SEL (7 << 8)
57#define RG_DSI_V072_SEL (7 << 11)
58#define RG_DSI_V04_SEL (7 << 14)
59#define RG_DSI_V032_SEL (7 << 17)
60#define RG_DSI_V02_SEL (7 << 20)
61#define RG_DSI_BG_R1_TRIM (0xf << 24)
62#define RG_DSI_BG_R2_TRIM (0xf << 28)
63
64#define MIPITX_DSI_PLL_CON0 0x50
65#define RG_DSI_MPPLL_PLL_EN BIT(0)
66#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
67#define RG_DSI_MPPLL_PREDIV (3 << 1)
68#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
69#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
70#define RG_DSI_MPPLL_POSDIV (7 << 7)
71#define RG_DSI_MPPLL_MONVC_EN BIT(10)
72#define RG_DSI_MPPLL_MONREF_EN BIT(11)
73#define RG_DSI_MPPLL_VOD_EN BIT(12)
74
75#define MIPITX_DSI_PLL_CON1 0x54
76#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
77#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
78#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
79#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
80
81#define MIPITX_DSI_PLL_CON2 0x58
82
83#define MIPITX_DSI_PLL_TOP 0x64
84#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
85
86#define MIPITX_DSI_PLL_PWR 0x68
87#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
88#define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
89#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
90
91#define MIPITX_DSI_SW_CTRL 0x80
92#define SW_CTRL_EN BIT(0)
93
94#define MIPITX_DSI_SW_CTRL_CON0 0x84
95#define SW_LNTC_LPTX_PRE_OE BIT(0)
96#define SW_LNTC_LPTX_OE BIT(1)
97#define SW_LNTC_LPTX_P BIT(2)
98#define SW_LNTC_LPTX_N BIT(3)
99#define SW_LNTC_HSTX_PRE_OE BIT(4)
100#define SW_LNTC_HSTX_OE BIT(5)
101#define SW_LNTC_HSTX_ZEROCLK BIT(6)
102#define SW_LNT0_LPTX_PRE_OE BIT(7)
103#define SW_LNT0_LPTX_OE BIT(8)
104#define SW_LNT0_LPTX_P BIT(9)
105#define SW_LNT0_LPTX_N BIT(10)
106#define SW_LNT0_HSTX_PRE_OE BIT(11)
107#define SW_LNT0_HSTX_OE BIT(12)
108#define SW_LNT0_LPRX_EN BIT(13)
109#define SW_LNT1_LPTX_PRE_OE BIT(14)
110#define SW_LNT1_LPTX_OE BIT(15)
111#define SW_LNT1_LPTX_P BIT(16)
112#define SW_LNT1_LPTX_N BIT(17)
113#define SW_LNT1_HSTX_PRE_OE BIT(18)
114#define SW_LNT1_HSTX_OE BIT(19)
115#define SW_LNT2_LPTX_PRE_OE BIT(20)
116#define SW_LNT2_LPTX_OE BIT(21)
117#define SW_LNT2_LPTX_P BIT(22)
118#define SW_LNT2_LPTX_N BIT(23)
119#define SW_LNT2_HSTX_PRE_OE BIT(24)
120#define SW_LNT2_HSTX_OE BIT(25)
121
122struct mtk_mipitx_data {
123 const u32 mppll_preserve;
124};
125
126struct mtk_mipi_tx {
127 struct device *dev;
128 void __iomem *regs;
129 u32 data_rate;
130 const struct mtk_mipitx_data *driver_data;
131 struct clk_hw pll_hw;
132 struct clk *pll;
133};
134
135static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
136{
137 return container_of(hw, struct mtk_mipi_tx, pll_hw);
138}
139
140static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
141 u32 bits)
142{
143 u32 temp = readl(mipi_tx->regs + offset);
144
145 writel(temp & ~bits, mipi_tx->regs + offset);
146}
147
148static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
149 u32 bits)
150{
151 u32 temp = readl(mipi_tx->regs + offset);
152
153 writel(temp | bits, mipi_tx->regs + offset);
154}
155
156static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
157 u32 mask, u32 data)
158{
159 u32 temp = readl(mipi_tx->regs + offset);
160
161 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
162}
163
164static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
165{
166 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
167 u8 txdiv, txdiv0, txdiv1;
168 u64 pcw;
169
170 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
171
172 if (mipi_tx->data_rate >= 500000000) {
173 txdiv = 1;
174 txdiv0 = 0;
175 txdiv1 = 0;
176 } else if (mipi_tx->data_rate >= 250000000) {
177 txdiv = 2;
178 txdiv0 = 1;
179 txdiv1 = 0;
180 } else if (mipi_tx->data_rate >= 125000000) {
181 txdiv = 4;
182 txdiv0 = 2;
183 txdiv1 = 0;
184 } else if (mipi_tx->data_rate > 62000000) {
185 txdiv = 8;
186 txdiv0 = 2;
187 txdiv1 = 1;
188 } else if (mipi_tx->data_rate >= 50000000) {
189 txdiv = 16;
190 txdiv0 = 2;
191 txdiv1 = 2;
192 } else {
193 return -EINVAL;
194 }
195
196 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
197 RG_DSI_VOUT_MSK |
198 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
199 (4 << 20) | (4 << 17) | (4 << 14) |
200 (4 << 11) | (4 << 8) | (4 << 5) |
201 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
202
203 usleep_range(30, 100);
204
205 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
206 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
207 (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
208
209 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
210 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
211
212 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
213 RG_DSI_MPPLL_SDM_PWR_ON |
214 RG_DSI_MPPLL_SDM_ISO_EN,
215 RG_DSI_MPPLL_SDM_PWR_ON);
216
217 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
218 RG_DSI_MPPLL_PLL_EN);
219
220 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
221 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
222 RG_DSI_MPPLL_PREDIV,
223 (txdiv0 << 3) | (txdiv1 << 5));
224
225 /*
226 * PLL PCW config
227 * PCW bit 24~30 = integer part of pcw
228 * PCW bit 0~23 = fractional part of pcw
229 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
230 * Post DIV =4, so need data_Rate*4
231 * Ref_clk is 26MHz
232 */
233 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
234 26000000);
235 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
236
237 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
238 RG_DSI_MPPLL_SDM_FRA_EN);
239
240 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
241
242 usleep_range(20, 100);
243
244 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
245 RG_DSI_MPPLL_SDM_SSC_EN);
246
247 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
248 RG_DSI_MPPLL_PRESERVE,
249 mipi_tx->driver_data->mppll_preserve);
250
251 return 0;
252}
253
254static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
255{
256 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
257
258 dev_dbg(mipi_tx->dev, "unprepare\n");
259
260 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
261 RG_DSI_MPPLL_PLL_EN);
262
263 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
264 RG_DSI_MPPLL_PRESERVE, 0);
265
266 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
267 RG_DSI_MPPLL_SDM_ISO_EN |
268 RG_DSI_MPPLL_SDM_PWR_ON,
269 RG_DSI_MPPLL_SDM_ISO_EN);
270
271 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
272 RG_DSI_LNT_HS_BIAS_EN);
273
274 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
275 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
276
277 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
278 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
279
280 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
281 RG_DSI_MPPLL_DIV_MSK);
282}
283
284static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
285 unsigned long *prate)
286{
287 return clamp_val(rate, 50000000, 1250000000);
288}
289
290static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
291 unsigned long parent_rate)
292{
293 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
294
295 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
296
297 mipi_tx->data_rate = rate;
298
299 return 0;
300}
301
302static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
303 unsigned long parent_rate)
304{
305 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
306
307 return mipi_tx->data_rate;
308}
309
310static const struct clk_ops mtk_mipi_tx_pll_ops = {
311 .prepare = mtk_mipi_tx_pll_prepare,
312 .unprepare = mtk_mipi_tx_pll_unprepare,
313 .round_rate = mtk_mipi_tx_pll_round_rate,
314 .set_rate = mtk_mipi_tx_pll_set_rate,
315 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
316};
317
318static int mtk_mipi_tx_power_on_signal(struct phy *phy)
319{
320 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
321 u32 reg;
322
323 for (reg = MIPITX_DSI_CLOCK_LANE;
324 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
325 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
326
327 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
328 RG_DSI_PAD_TIE_LOW_EN);
329
330 return 0;
331}
332
333static int mtk_mipi_tx_power_on(struct phy *phy)
334{
335 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
336 int ret;
337
338 /* Power up core and enable PLL */
339 ret = clk_prepare_enable(mipi_tx->pll);
340 if (ret < 0)
341 return ret;
342
343 /* Enable DSI Lane LDO outputs, disable pad tie low */
344 mtk_mipi_tx_power_on_signal(phy);
345
346 return 0;
347}
348
349static void mtk_mipi_tx_power_off_signal(struct phy *phy)
350{
351 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
352 u32 reg;
353
354 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
355 RG_DSI_PAD_TIE_LOW_EN);
356
357 for (reg = MIPITX_DSI_CLOCK_LANE;
358 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
359 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
360}
361
362static int mtk_mipi_tx_power_off(struct phy *phy)
363{
364 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
365
366 /* Enable pad tie low, disable DSI Lane LDO outputs */
367 mtk_mipi_tx_power_off_signal(phy);
368
369 /* Disable PLL and power down core */
370 clk_disable_unprepare(mipi_tx->pll);
371
372 return 0;
373}
374
375static const struct phy_ops mtk_mipi_tx_ops = {
376 .power_on = mtk_mipi_tx_power_on,
377 .power_off = mtk_mipi_tx_power_off,
378 .owner = THIS_MODULE,
379};
380
381static int mtk_mipi_tx_probe(struct platform_device *pdev)
382{
383 struct device *dev = &pdev->dev;
384 struct mtk_mipi_tx *mipi_tx;
385 struct resource *mem;
386 struct clk *ref_clk;
387 const char *ref_clk_name;
388 struct clk_init_data clk_init = {
389 .ops = &mtk_mipi_tx_pll_ops,
390 .num_parents = 1,
391 .parent_names = (const char * const *)&ref_clk_name,
392 .flags = CLK_SET_RATE_GATE,
393 };
394 struct phy *phy;
395 struct phy_provider *phy_provider;
396 int ret;
397
398 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
399 if (!mipi_tx)
400 return -ENOMEM;
401
402 mipi_tx->driver_data = of_device_get_match_data(dev);
403 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
404 mipi_tx->regs = devm_ioremap_resource(dev, mem);
405 if (IS_ERR(mipi_tx->regs)) {
406 ret = PTR_ERR(mipi_tx->regs);
407 dev_err(dev, "Failed to get memory resource: %d\n", ret);
408 return ret;
409 }
410
411 ref_clk = devm_clk_get(dev, NULL);
412 if (IS_ERR(ref_clk)) {
413 ret = PTR_ERR(ref_clk);
414 dev_err(dev, "Failed to get reference clock: %d\n", ret);
415 return ret;
416 }
417 ref_clk_name = __clk_get_name(ref_clk);
418
419 ret = of_property_read_string(dev->of_node, "clock-output-names",
420 &clk_init.name);
421 if (ret < 0) {
422 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
423 return ret;
424 }
425
426 mipi_tx->pll_hw.init = &clk_init;
427 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
428 if (IS_ERR(mipi_tx->pll)) {
429 ret = PTR_ERR(mipi_tx->pll);
430 dev_err(dev, "Failed to register PLL: %d\n", ret);
431 return ret;
432 }
433
434 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
435 if (IS_ERR(phy)) {
436 ret = PTR_ERR(phy);
437 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
438 return ret;
439 }
440 phy_set_drvdata(phy, mipi_tx);
441
442 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
443 if (IS_ERR(phy_provider)) {
444 ret = PTR_ERR(phy_provider);
445 return ret;
446 }
447
448 mipi_tx->dev = dev;
449
450 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
451 mipi_tx->pll);
452}
453
454static int mtk_mipi_tx_remove(struct platform_device *pdev)
455{
456 of_clk_del_provider(pdev->dev.of_node);
457 return 0;
458}
459
460static const struct mtk_mipitx_data mt2701_mipitx_data = {
461 .mppll_preserve = (3 << 8)
462};
463
464static const struct mtk_mipitx_data mt8173_mipitx_data = {
465 .mppll_preserve = (0 << 8)
466};
467
468static const struct of_device_id mtk_mipi_tx_match[] = {
469 { .compatible = "mediatek,mt2701-mipi-tx",
470 .data = &mt2701_mipitx_data },
471 { .compatible = "mediatek,mt8173-mipi-tx",
472 .data = &mt8173_mipitx_data },
473 {},
474};
475
476struct platform_driver mtk_mipi_tx_driver = {
477 .probe = mtk_mipi_tx_probe,
478 .remove = mtk_mipi_tx_remove,
479 .driver = {
480 .name = "mediatek-mipi-tx",
481 .of_match_table = mtk_mipi_tx_match,
482 },
483};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include "mtk_mipi_tx.h"
7
8inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
9{
10 return container_of(hw, struct mtk_mipi_tx, pll_hw);
11}
12
13void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
14 u32 bits)
15{
16 u32 temp = readl(mipi_tx->regs + offset);
17
18 writel(temp & ~bits, mipi_tx->regs + offset);
19}
20
21void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
22 u32 bits)
23{
24 u32 temp = readl(mipi_tx->regs + offset);
25
26 writel(temp | bits, mipi_tx->regs + offset);
27}
28
29void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
30 u32 mask, u32 data)
31{
32 u32 temp = readl(mipi_tx->regs + offset);
33
34 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
35}
36
37int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
38 unsigned long parent_rate)
39{
40 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
41
42 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
43
44 mipi_tx->data_rate = rate;
45
46 return 0;
47}
48
49unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
50 unsigned long parent_rate)
51{
52 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
53
54 return mipi_tx->data_rate;
55}
56
57static int mtk_mipi_tx_power_on(struct phy *phy)
58{
59 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
60 int ret;
61
62 /* Power up core and enable PLL */
63 ret = clk_prepare_enable(mipi_tx->pll);
64 if (ret < 0)
65 return ret;
66
67 /* Enable DSI Lane LDO outputs, disable pad tie low */
68 mipi_tx->driver_data->mipi_tx_enable_signal(phy);
69 return 0;
70}
71
72static int mtk_mipi_tx_power_off(struct phy *phy)
73{
74 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
75
76 /* Enable pad tie low, disable DSI Lane LDO outputs */
77 mipi_tx->driver_data->mipi_tx_disable_signal(phy);
78
79 /* Disable PLL and power down core */
80 clk_disable_unprepare(mipi_tx->pll);
81
82 return 0;
83}
84
85static const struct phy_ops mtk_mipi_tx_ops = {
86 .power_on = mtk_mipi_tx_power_on,
87 .power_off = mtk_mipi_tx_power_off,
88 .owner = THIS_MODULE,
89};
90
91static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
92{
93 struct nvmem_cell *cell;
94 size_t len;
95 u32 *buf;
96
97 cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
98 if (IS_ERR(cell)) {
99 dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
100 return;
101 }
102 buf = (u32 *)nvmem_cell_read(cell, &len);
103 nvmem_cell_put(cell);
104
105 if (IS_ERR(buf)) {
106 dev_info(mipi_tx->dev, "can't get data, ignore it\n");
107 return;
108 }
109
110 if (len < 3 * sizeof(u32)) {
111 dev_info(mipi_tx->dev, "invalid calibration data\n");
112 kfree(buf);
113 return;
114 }
115
116 mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
117 (buf[0] >> 11 & 0x1f);
118 mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
119 (buf[0] >> 1 & 0x1f);
120 mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
121 (buf[1] >> 22 & 0x1f);
122 mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
123 (buf[1] >> 12 & 0x1f);
124 mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
125 (buf[1] >> 2 & 0x1f);
126 kfree(buf);
127}
128
129static int mtk_mipi_tx_probe(struct platform_device *pdev)
130{
131 struct device *dev = &pdev->dev;
132 struct mtk_mipi_tx *mipi_tx;
133 struct resource *mem;
134 const char *ref_clk_name;
135 struct clk *ref_clk;
136 struct clk_init_data clk_init = {
137 .num_parents = 1,
138 .parent_names = (const char * const *)&ref_clk_name,
139 .flags = CLK_SET_RATE_GATE,
140 };
141 struct phy *phy;
142 struct phy_provider *phy_provider;
143 int ret;
144
145 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
146 if (!mipi_tx)
147 return -ENOMEM;
148
149 mipi_tx->driver_data = of_device_get_match_data(dev);
150
151 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
152 mipi_tx->regs = devm_ioremap_resource(dev, mem);
153 if (IS_ERR(mipi_tx->regs)) {
154 ret = PTR_ERR(mipi_tx->regs);
155 dev_err(dev, "Failed to get memory resource: %d\n", ret);
156 return ret;
157 }
158
159 ref_clk = devm_clk_get(dev, NULL);
160 if (IS_ERR(ref_clk)) {
161 ret = PTR_ERR(ref_clk);
162 dev_err(dev, "Failed to get reference clock: %d\n", ret);
163 return ret;
164 }
165
166 ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
167 &mipi_tx->mipitx_drive);
168 /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
169 if (ret < 0)
170 mipi_tx->mipitx_drive = 4600;
171
172 /* check the mipitx_drive valid */
173 if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
174 dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
175 mipi_tx->mipitx_drive);
176 mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
177 6000);
178 }
179
180 ref_clk_name = __clk_get_name(ref_clk);
181
182 ret = of_property_read_string(dev->of_node, "clock-output-names",
183 &clk_init.name);
184 if (ret < 0) {
185 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
186 return ret;
187 }
188
189 clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
190
191 mipi_tx->pll_hw.init = &clk_init;
192 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
193 if (IS_ERR(mipi_tx->pll)) {
194 ret = PTR_ERR(mipi_tx->pll);
195 dev_err(dev, "Failed to register PLL: %d\n", ret);
196 return ret;
197 }
198
199 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
200 if (IS_ERR(phy)) {
201 ret = PTR_ERR(phy);
202 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
203 return ret;
204 }
205 phy_set_drvdata(phy, mipi_tx);
206
207 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
208 if (IS_ERR(phy_provider)) {
209 ret = PTR_ERR(phy_provider);
210 return ret;
211 }
212
213 mipi_tx->dev = dev;
214
215 mtk_mipi_tx_get_calibration_datal(mipi_tx);
216
217 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
218 mipi_tx->pll);
219}
220
221static int mtk_mipi_tx_remove(struct platform_device *pdev)
222{
223 of_clk_del_provider(pdev->dev.of_node);
224 return 0;
225}
226
227static const struct of_device_id mtk_mipi_tx_match[] = {
228 { .compatible = "mediatek,mt2701-mipi-tx",
229 .data = &mt2701_mipitx_data },
230 { .compatible = "mediatek,mt8173-mipi-tx",
231 .data = &mt8173_mipitx_data },
232 { .compatible = "mediatek,mt8183-mipi-tx",
233 .data = &mt8183_mipitx_data },
234 { },
235};
236
237struct platform_driver mtk_mipi_tx_driver = {
238 .probe = mtk_mipi_tx_probe,
239 .remove = mtk_mipi_tx_remove,
240 .driver = {
241 .name = "mediatek-mipi-tx",
242 .of_match_table = mtk_mipi_tx_match,
243 },
244};
245