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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9#include <asm/fpu/internal.h>
10#include <asm/fpu/regset.h>
11#include <asm/fpu/signal.h>
12#include <asm/fpu/types.h>
13#include <asm/traps.h>
14#include <asm/irq_regs.h>
15
16#include <linux/hardirq.h>
17#include <linux/pkeys.h>
18
19#define CREATE_TRACE_POINTS
20#include <asm/trace/fpu.h>
21
22/*
23 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
24 * depending on the FPU hardware format:
25 */
26union fpregs_state init_fpstate __read_mostly;
27
28/*
29 * Track whether the kernel is using the FPU state
30 * currently.
31 *
32 * This flag is used:
33 *
34 * - by IRQ context code to potentially use the FPU
35 * if it's unused.
36 *
37 * - to debug kernel_fpu_begin()/end() correctness
38 */
39static DEFINE_PER_CPU(bool, in_kernel_fpu);
40
41/*
42 * Track which context is using the FPU on the CPU:
43 */
44DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
45
46static bool kernel_fpu_disabled(void)
47{
48 return this_cpu_read(in_kernel_fpu);
49}
50
51static bool interrupted_kernel_fpu_idle(void)
52{
53 return !kernel_fpu_disabled();
54}
55
56/*
57 * Were we in user mode (or vm86 mode) when we were
58 * interrupted?
59 *
60 * Doing kernel_fpu_begin/end() is ok if we are running
61 * in an interrupt context from user mode - we'll just
62 * save the FPU state as required.
63 */
64static bool interrupted_user_mode(void)
65{
66 struct pt_regs *regs = get_irq_regs();
67 return regs && user_mode(regs);
68}
69
70/*
71 * Can we use the FPU in kernel mode with the
72 * whole "kernel_fpu_begin/end()" sequence?
73 *
74 * It's always ok in process context (ie "not interrupt")
75 * but it is sometimes ok even from an irq.
76 */
77bool irq_fpu_usable(void)
78{
79 return !in_interrupt() ||
80 interrupted_user_mode() ||
81 interrupted_kernel_fpu_idle();
82}
83EXPORT_SYMBOL(irq_fpu_usable);
84
85void kernel_fpu_begin(void)
86{
87 preempt_disable();
88
89 WARN_ON_FPU(!irq_fpu_usable());
90 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
91
92 this_cpu_write(in_kernel_fpu, true);
93
94 if (!(current->flags & PF_KTHREAD) &&
95 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
96 set_thread_flag(TIF_NEED_FPU_LOAD);
97 /*
98 * Ignore return value -- we don't care if reg state
99 * is clobbered.
100 */
101 copy_fpregs_to_fpstate(¤t->thread.fpu);
102 }
103 __cpu_invalidate_fpregs_state();
104}
105EXPORT_SYMBOL_GPL(kernel_fpu_begin);
106
107void kernel_fpu_end(void)
108{
109 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
110
111 this_cpu_write(in_kernel_fpu, false);
112 preempt_enable();
113}
114EXPORT_SYMBOL_GPL(kernel_fpu_end);
115
116/*
117 * Save the FPU state (mark it for reload if necessary):
118 *
119 * This only ever gets called for the current task.
120 */
121void fpu__save(struct fpu *fpu)
122{
123 WARN_ON_FPU(fpu != ¤t->thread.fpu);
124
125 fpregs_lock();
126 trace_x86_fpu_before_save(fpu);
127
128 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
129 if (!copy_fpregs_to_fpstate(fpu)) {
130 copy_kernel_to_fpregs(&fpu->state);
131 }
132 }
133
134 trace_x86_fpu_after_save(fpu);
135 fpregs_unlock();
136}
137
138/*
139 * Legacy x87 fpstate state init:
140 */
141static inline void fpstate_init_fstate(struct fregs_state *fp)
142{
143 fp->cwd = 0xffff037fu;
144 fp->swd = 0xffff0000u;
145 fp->twd = 0xffffffffu;
146 fp->fos = 0xffff0000u;
147}
148
149void fpstate_init(union fpregs_state *state)
150{
151 if (!static_cpu_has(X86_FEATURE_FPU)) {
152 fpstate_init_soft(&state->soft);
153 return;
154 }
155
156 memset(state, 0, fpu_kernel_xstate_size);
157
158 if (static_cpu_has(X86_FEATURE_XSAVES))
159 fpstate_init_xstate(&state->xsave);
160 if (static_cpu_has(X86_FEATURE_FXSR))
161 fpstate_init_fxstate(&state->fxsave);
162 else
163 fpstate_init_fstate(&state->fsave);
164}
165EXPORT_SYMBOL_GPL(fpstate_init);
166
167int fpu__copy(struct task_struct *dst, struct task_struct *src)
168{
169 struct fpu *dst_fpu = &dst->thread.fpu;
170 struct fpu *src_fpu = &src->thread.fpu;
171
172 dst_fpu->last_cpu = -1;
173
174 if (!static_cpu_has(X86_FEATURE_FPU))
175 return 0;
176
177 WARN_ON_FPU(src_fpu != ¤t->thread.fpu);
178
179 /*
180 * Don't let 'init optimized' areas of the XSAVE area
181 * leak into the child task:
182 */
183 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);
184
185 /*
186 * If the FPU registers are not current just memcpy() the state.
187 * Otherwise save current FPU registers directly into the child's FPU
188 * context, without any memory-to-memory copying.
189 *
190 * ( The function 'fails' in the FNSAVE case, which destroys
191 * register contents so we have to load them back. )
192 */
193 fpregs_lock();
194 if (test_thread_flag(TIF_NEED_FPU_LOAD))
195 memcpy(&dst_fpu->state, &src_fpu->state, fpu_kernel_xstate_size);
196
197 else if (!copy_fpregs_to_fpstate(dst_fpu))
198 copy_kernel_to_fpregs(&dst_fpu->state);
199
200 fpregs_unlock();
201
202 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
203
204 trace_x86_fpu_copy_src(src_fpu);
205 trace_x86_fpu_copy_dst(dst_fpu);
206
207 return 0;
208}
209
210/*
211 * Activate the current task's in-memory FPU context,
212 * if it has not been used before:
213 */
214static void fpu__initialize(struct fpu *fpu)
215{
216 WARN_ON_FPU(fpu != ¤t->thread.fpu);
217
218 set_thread_flag(TIF_NEED_FPU_LOAD);
219 fpstate_init(&fpu->state);
220 trace_x86_fpu_init_state(fpu);
221}
222
223/*
224 * This function must be called before we read a task's fpstate.
225 *
226 * There's two cases where this gets called:
227 *
228 * - for the current task (when coredumping), in which case we have
229 * to save the latest FPU registers into the fpstate,
230 *
231 * - or it's called for stopped tasks (ptrace), in which case the
232 * registers were already saved by the context-switch code when
233 * the task scheduled out.
234 *
235 * If the task has used the FPU before then save it.
236 */
237void fpu__prepare_read(struct fpu *fpu)
238{
239 if (fpu == ¤t->thread.fpu)
240 fpu__save(fpu);
241}
242
243/*
244 * This function must be called before we write a task's fpstate.
245 *
246 * Invalidate any cached FPU registers.
247 *
248 * After this function call, after registers in the fpstate are
249 * modified and the child task has woken up, the child task will
250 * restore the modified FPU state from the modified context. If we
251 * didn't clear its cached status here then the cached in-registers
252 * state pending on its former CPU could be restored, corrupting
253 * the modifications.
254 */
255void fpu__prepare_write(struct fpu *fpu)
256{
257 /*
258 * Only stopped child tasks can be used to modify the FPU
259 * state in the fpstate buffer:
260 */
261 WARN_ON_FPU(fpu == ¤t->thread.fpu);
262
263 /* Invalidate any cached state: */
264 __fpu_invalidate_fpregs_state(fpu);
265}
266
267/*
268 * Drops current FPU state: deactivates the fpregs and
269 * the fpstate. NOTE: it still leaves previous contents
270 * in the fpregs in the eager-FPU case.
271 *
272 * This function can be used in cases where we know that
273 * a state-restore is coming: either an explicit one,
274 * or a reschedule.
275 */
276void fpu__drop(struct fpu *fpu)
277{
278 preempt_disable();
279
280 if (fpu == ¤t->thread.fpu) {
281 /* Ignore delayed exceptions from user space */
282 asm volatile("1: fwait\n"
283 "2:\n"
284 _ASM_EXTABLE(1b, 2b));
285 fpregs_deactivate(fpu);
286 }
287
288 trace_x86_fpu_dropped(fpu);
289
290 preempt_enable();
291}
292
293/*
294 * Clear FPU registers by setting them up from
295 * the init fpstate:
296 */
297static inline void copy_init_fpstate_to_fpregs(void)
298{
299 fpregs_lock();
300
301 if (use_xsave())
302 copy_kernel_to_xregs(&init_fpstate.xsave, -1);
303 else if (static_cpu_has(X86_FEATURE_FXSR))
304 copy_kernel_to_fxregs(&init_fpstate.fxsave);
305 else
306 copy_kernel_to_fregs(&init_fpstate.fsave);
307
308 if (boot_cpu_has(X86_FEATURE_OSPKE))
309 copy_init_pkru_to_fpregs();
310
311 fpregs_mark_activate();
312 fpregs_unlock();
313}
314
315/*
316 * Clear the FPU state back to init state.
317 *
318 * Called by sys_execve(), by the signal handler code and by various
319 * error paths.
320 */
321void fpu__clear(struct fpu *fpu)
322{
323 WARN_ON_FPU(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
324
325 fpu__drop(fpu);
326
327 /*
328 * Make sure fpstate is cleared and initialized.
329 */
330 fpu__initialize(fpu);
331 if (static_cpu_has(X86_FEATURE_FPU))
332 copy_init_fpstate_to_fpregs();
333}
334
335/*
336 * Load FPU context before returning to userspace.
337 */
338void switch_fpu_return(void)
339{
340 if (!static_cpu_has(X86_FEATURE_FPU))
341 return;
342
343 __fpregs_load_activate();
344}
345EXPORT_SYMBOL_GPL(switch_fpu_return);
346
347#ifdef CONFIG_X86_DEBUG_FPU
348/*
349 * If current FPU state according to its tracking (loaded FPU context on this
350 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
351 * loaded on return to userland.
352 */
353void fpregs_assert_state_consistent(void)
354{
355 struct fpu *fpu = ¤t->thread.fpu;
356
357 if (test_thread_flag(TIF_NEED_FPU_LOAD))
358 return;
359
360 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
361}
362EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
363#endif
364
365void fpregs_mark_activate(void)
366{
367 struct fpu *fpu = ¤t->thread.fpu;
368
369 fpregs_activate(fpu);
370 fpu->last_cpu = smp_processor_id();
371 clear_thread_flag(TIF_NEED_FPU_LOAD);
372}
373EXPORT_SYMBOL_GPL(fpregs_mark_activate);
374
375/*
376 * x87 math exception handling:
377 */
378
379int fpu__exception_code(struct fpu *fpu, int trap_nr)
380{
381 int err;
382
383 if (trap_nr == X86_TRAP_MF) {
384 unsigned short cwd, swd;
385 /*
386 * (~cwd & swd) will mask out exceptions that are not set to unmasked
387 * status. 0x3f is the exception bits in these regs, 0x200 is the
388 * C1 reg you need in case of a stack fault, 0x040 is the stack
389 * fault bit. We should only be taking one exception at a time,
390 * so if this combination doesn't produce any single exception,
391 * then we have a bad program that isn't synchronizing its FPU usage
392 * and it will suffer the consequences since we won't be able to
393 * fully reproduce the context of the exception.
394 */
395 if (boot_cpu_has(X86_FEATURE_FXSR)) {
396 cwd = fpu->state.fxsave.cwd;
397 swd = fpu->state.fxsave.swd;
398 } else {
399 cwd = (unsigned short)fpu->state.fsave.cwd;
400 swd = (unsigned short)fpu->state.fsave.swd;
401 }
402
403 err = swd & ~cwd;
404 } else {
405 /*
406 * The SIMD FPU exceptions are handled a little differently, as there
407 * is only a single status/control register. Thus, to determine which
408 * unmasked exception was caught we must mask the exception mask bits
409 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
410 */
411 unsigned short mxcsr = MXCSR_DEFAULT;
412
413 if (boot_cpu_has(X86_FEATURE_XMM))
414 mxcsr = fpu->state.fxsave.mxcsr;
415
416 err = ~(mxcsr >> 7) & mxcsr;
417 }
418
419 if (err & 0x001) { /* Invalid op */
420 /*
421 * swd & 0x240 == 0x040: Stack Underflow
422 * swd & 0x240 == 0x240: Stack Overflow
423 * User must clear the SF bit (0x40) if set
424 */
425 return FPE_FLTINV;
426 } else if (err & 0x004) { /* Divide by Zero */
427 return FPE_FLTDIV;
428 } else if (err & 0x008) { /* Overflow */
429 return FPE_FLTOVF;
430 } else if (err & 0x012) { /* Denormal, Underflow */
431 return FPE_FLTUND;
432 } else if (err & 0x020) { /* Precision */
433 return FPE_FLTRES;
434 }
435
436 /*
437 * If we're using IRQ 13, or supposedly even some trap
438 * X86_TRAP_MF implementations, it's possible
439 * we get a spurious trap, which is not an error.
440 */
441 return 0;
442}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9#include <asm/fpu/internal.h>
10#include <asm/fpu/regset.h>
11#include <asm/fpu/signal.h>
12#include <asm/fpu/types.h>
13#include <asm/traps.h>
14#include <asm/irq_regs.h>
15
16#include <linux/hardirq.h>
17#include <linux/pkeys.h>
18
19#define CREATE_TRACE_POINTS
20#include <asm/trace/fpu.h>
21
22/*
23 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
24 * depending on the FPU hardware format:
25 */
26union fpregs_state init_fpstate __read_mostly;
27
28/*
29 * Track whether the kernel is using the FPU state
30 * currently.
31 *
32 * This flag is used:
33 *
34 * - by IRQ context code to potentially use the FPU
35 * if it's unused.
36 *
37 * - to debug kernel_fpu_begin()/end() correctness
38 */
39static DEFINE_PER_CPU(bool, in_kernel_fpu);
40
41/*
42 * Track which context is using the FPU on the CPU:
43 */
44DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
45
46static bool kernel_fpu_disabled(void)
47{
48 return this_cpu_read(in_kernel_fpu);
49}
50
51static bool interrupted_kernel_fpu_idle(void)
52{
53 return !kernel_fpu_disabled();
54}
55
56/*
57 * Were we in user mode (or vm86 mode) when we were
58 * interrupted?
59 *
60 * Doing kernel_fpu_begin/end() is ok if we are running
61 * in an interrupt context from user mode - we'll just
62 * save the FPU state as required.
63 */
64static bool interrupted_user_mode(void)
65{
66 struct pt_regs *regs = get_irq_regs();
67 return regs && user_mode(regs);
68}
69
70/*
71 * Can we use the FPU in kernel mode with the
72 * whole "kernel_fpu_begin/end()" sequence?
73 *
74 * It's always ok in process context (ie "not interrupt")
75 * but it is sometimes ok even from an irq.
76 */
77bool irq_fpu_usable(void)
78{
79 return !in_interrupt() ||
80 interrupted_user_mode() ||
81 interrupted_kernel_fpu_idle();
82}
83EXPORT_SYMBOL(irq_fpu_usable);
84
85/*
86 * These must be called with preempt disabled. Returns
87 * 'true' if the FPU state is still intact and we can
88 * keep registers active.
89 *
90 * The legacy FNSAVE instruction cleared all FPU state
91 * unconditionally, so registers are essentially destroyed.
92 * Modern FPU state can be kept in registers, if there are
93 * no pending FP exceptions.
94 */
95int copy_fpregs_to_fpstate(struct fpu *fpu)
96{
97 if (likely(use_xsave())) {
98 copy_xregs_to_kernel(&fpu->state.xsave);
99
100 /*
101 * AVX512 state is tracked here because its use is
102 * known to slow the max clock speed of the core.
103 */
104 if (fpu->state.xsave.header.xfeatures & XFEATURE_MASK_AVX512)
105 fpu->avx512_timestamp = jiffies;
106 return 1;
107 }
108
109 if (likely(use_fxsr())) {
110 copy_fxregs_to_kernel(fpu);
111 return 1;
112 }
113
114 /*
115 * Legacy FPU register saving, FNSAVE always clears FPU registers,
116 * so we have to mark them inactive:
117 */
118 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave));
119
120 return 0;
121}
122EXPORT_SYMBOL(copy_fpregs_to_fpstate);
123
124void kernel_fpu_begin(void)
125{
126 preempt_disable();
127
128 WARN_ON_FPU(!irq_fpu_usable());
129 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
130
131 this_cpu_write(in_kernel_fpu, true);
132
133 if (!(current->flags & PF_KTHREAD) &&
134 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
135 set_thread_flag(TIF_NEED_FPU_LOAD);
136 /*
137 * Ignore return value -- we don't care if reg state
138 * is clobbered.
139 */
140 copy_fpregs_to_fpstate(¤t->thread.fpu);
141 }
142 __cpu_invalidate_fpregs_state();
143
144 if (boot_cpu_has(X86_FEATURE_XMM))
145 ldmxcsr(MXCSR_DEFAULT);
146
147 if (boot_cpu_has(X86_FEATURE_FPU))
148 asm volatile ("fninit");
149}
150EXPORT_SYMBOL_GPL(kernel_fpu_begin);
151
152void kernel_fpu_end(void)
153{
154 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
155
156 this_cpu_write(in_kernel_fpu, false);
157 preempt_enable();
158}
159EXPORT_SYMBOL_GPL(kernel_fpu_end);
160
161/*
162 * Save the FPU state (mark it for reload if necessary):
163 *
164 * This only ever gets called for the current task.
165 */
166void fpu__save(struct fpu *fpu)
167{
168 WARN_ON_FPU(fpu != ¤t->thread.fpu);
169
170 fpregs_lock();
171 trace_x86_fpu_before_save(fpu);
172
173 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
174 if (!copy_fpregs_to_fpstate(fpu)) {
175 copy_kernel_to_fpregs(&fpu->state);
176 }
177 }
178
179 trace_x86_fpu_after_save(fpu);
180 fpregs_unlock();
181}
182
183/*
184 * Legacy x87 fpstate state init:
185 */
186static inline void fpstate_init_fstate(struct fregs_state *fp)
187{
188 fp->cwd = 0xffff037fu;
189 fp->swd = 0xffff0000u;
190 fp->twd = 0xffffffffu;
191 fp->fos = 0xffff0000u;
192}
193
194void fpstate_init(union fpregs_state *state)
195{
196 if (!static_cpu_has(X86_FEATURE_FPU)) {
197 fpstate_init_soft(&state->soft);
198 return;
199 }
200
201 memset(state, 0, fpu_kernel_xstate_size);
202
203 if (static_cpu_has(X86_FEATURE_XSAVES))
204 fpstate_init_xstate(&state->xsave);
205 if (static_cpu_has(X86_FEATURE_FXSR))
206 fpstate_init_fxstate(&state->fxsave);
207 else
208 fpstate_init_fstate(&state->fsave);
209}
210EXPORT_SYMBOL_GPL(fpstate_init);
211
212int fpu__copy(struct task_struct *dst, struct task_struct *src)
213{
214 struct fpu *dst_fpu = &dst->thread.fpu;
215 struct fpu *src_fpu = &src->thread.fpu;
216
217 dst_fpu->last_cpu = -1;
218
219 if (!static_cpu_has(X86_FEATURE_FPU))
220 return 0;
221
222 WARN_ON_FPU(src_fpu != ¤t->thread.fpu);
223
224 /*
225 * Don't let 'init optimized' areas of the XSAVE area
226 * leak into the child task:
227 */
228 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);
229
230 /*
231 * If the FPU registers are not current just memcpy() the state.
232 * Otherwise save current FPU registers directly into the child's FPU
233 * context, without any memory-to-memory copying.
234 *
235 * ( The function 'fails' in the FNSAVE case, which destroys
236 * register contents so we have to load them back. )
237 */
238 fpregs_lock();
239 if (test_thread_flag(TIF_NEED_FPU_LOAD))
240 memcpy(&dst_fpu->state, &src_fpu->state, fpu_kernel_xstate_size);
241
242 else if (!copy_fpregs_to_fpstate(dst_fpu))
243 copy_kernel_to_fpregs(&dst_fpu->state);
244
245 fpregs_unlock();
246
247 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
248
249 trace_x86_fpu_copy_src(src_fpu);
250 trace_x86_fpu_copy_dst(dst_fpu);
251
252 return 0;
253}
254
255/*
256 * Activate the current task's in-memory FPU context,
257 * if it has not been used before:
258 */
259static void fpu__initialize(struct fpu *fpu)
260{
261 WARN_ON_FPU(fpu != ¤t->thread.fpu);
262
263 set_thread_flag(TIF_NEED_FPU_LOAD);
264 fpstate_init(&fpu->state);
265 trace_x86_fpu_init_state(fpu);
266}
267
268/*
269 * This function must be called before we read a task's fpstate.
270 *
271 * There's two cases where this gets called:
272 *
273 * - for the current task (when coredumping), in which case we have
274 * to save the latest FPU registers into the fpstate,
275 *
276 * - or it's called for stopped tasks (ptrace), in which case the
277 * registers were already saved by the context-switch code when
278 * the task scheduled out.
279 *
280 * If the task has used the FPU before then save it.
281 */
282void fpu__prepare_read(struct fpu *fpu)
283{
284 if (fpu == ¤t->thread.fpu)
285 fpu__save(fpu);
286}
287
288/*
289 * This function must be called before we write a task's fpstate.
290 *
291 * Invalidate any cached FPU registers.
292 *
293 * After this function call, after registers in the fpstate are
294 * modified and the child task has woken up, the child task will
295 * restore the modified FPU state from the modified context. If we
296 * didn't clear its cached status here then the cached in-registers
297 * state pending on its former CPU could be restored, corrupting
298 * the modifications.
299 */
300void fpu__prepare_write(struct fpu *fpu)
301{
302 /*
303 * Only stopped child tasks can be used to modify the FPU
304 * state in the fpstate buffer:
305 */
306 WARN_ON_FPU(fpu == ¤t->thread.fpu);
307
308 /* Invalidate any cached state: */
309 __fpu_invalidate_fpregs_state(fpu);
310}
311
312/*
313 * Drops current FPU state: deactivates the fpregs and
314 * the fpstate. NOTE: it still leaves previous contents
315 * in the fpregs in the eager-FPU case.
316 *
317 * This function can be used in cases where we know that
318 * a state-restore is coming: either an explicit one,
319 * or a reschedule.
320 */
321void fpu__drop(struct fpu *fpu)
322{
323 preempt_disable();
324
325 if (fpu == ¤t->thread.fpu) {
326 /* Ignore delayed exceptions from user space */
327 asm volatile("1: fwait\n"
328 "2:\n"
329 _ASM_EXTABLE(1b, 2b));
330 fpregs_deactivate(fpu);
331 }
332
333 trace_x86_fpu_dropped(fpu);
334
335 preempt_enable();
336}
337
338/*
339 * Clear FPU registers by setting them up from the init fpstate.
340 * Caller must do fpregs_[un]lock() around it.
341 */
342static inline void copy_init_fpstate_to_fpregs(u64 features_mask)
343{
344 if (use_xsave())
345 copy_kernel_to_xregs(&init_fpstate.xsave, features_mask);
346 else if (static_cpu_has(X86_FEATURE_FXSR))
347 copy_kernel_to_fxregs(&init_fpstate.fxsave);
348 else
349 copy_kernel_to_fregs(&init_fpstate.fsave);
350
351 if (boot_cpu_has(X86_FEATURE_OSPKE))
352 copy_init_pkru_to_fpregs();
353}
354
355/*
356 * Clear the FPU state back to init state.
357 *
358 * Called by sys_execve(), by the signal handler code and by various
359 * error paths.
360 */
361static void fpu__clear(struct fpu *fpu, bool user_only)
362{
363 WARN_ON_FPU(fpu != ¤t->thread.fpu);
364
365 if (!static_cpu_has(X86_FEATURE_FPU)) {
366 fpu__drop(fpu);
367 fpu__initialize(fpu);
368 return;
369 }
370
371 fpregs_lock();
372
373 if (user_only) {
374 if (!fpregs_state_valid(fpu, smp_processor_id()) &&
375 xfeatures_mask_supervisor())
376 copy_kernel_to_xregs(&fpu->state.xsave,
377 xfeatures_mask_supervisor());
378 copy_init_fpstate_to_fpregs(xfeatures_mask_user());
379 } else {
380 copy_init_fpstate_to_fpregs(xfeatures_mask_all);
381 }
382
383 fpregs_mark_activate();
384 fpregs_unlock();
385}
386
387void fpu__clear_user_states(struct fpu *fpu)
388{
389 fpu__clear(fpu, true);
390}
391
392void fpu__clear_all(struct fpu *fpu)
393{
394 fpu__clear(fpu, false);
395}
396
397/*
398 * Load FPU context before returning to userspace.
399 */
400void switch_fpu_return(void)
401{
402 if (!static_cpu_has(X86_FEATURE_FPU))
403 return;
404
405 __fpregs_load_activate();
406}
407EXPORT_SYMBOL_GPL(switch_fpu_return);
408
409#ifdef CONFIG_X86_DEBUG_FPU
410/*
411 * If current FPU state according to its tracking (loaded FPU context on this
412 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
413 * loaded on return to userland.
414 */
415void fpregs_assert_state_consistent(void)
416{
417 struct fpu *fpu = ¤t->thread.fpu;
418
419 if (test_thread_flag(TIF_NEED_FPU_LOAD))
420 return;
421
422 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
423}
424EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
425#endif
426
427void fpregs_mark_activate(void)
428{
429 struct fpu *fpu = ¤t->thread.fpu;
430
431 fpregs_activate(fpu);
432 fpu->last_cpu = smp_processor_id();
433 clear_thread_flag(TIF_NEED_FPU_LOAD);
434}
435EXPORT_SYMBOL_GPL(fpregs_mark_activate);
436
437/*
438 * x87 math exception handling:
439 */
440
441int fpu__exception_code(struct fpu *fpu, int trap_nr)
442{
443 int err;
444
445 if (trap_nr == X86_TRAP_MF) {
446 unsigned short cwd, swd;
447 /*
448 * (~cwd & swd) will mask out exceptions that are not set to unmasked
449 * status. 0x3f is the exception bits in these regs, 0x200 is the
450 * C1 reg you need in case of a stack fault, 0x040 is the stack
451 * fault bit. We should only be taking one exception at a time,
452 * so if this combination doesn't produce any single exception,
453 * then we have a bad program that isn't synchronizing its FPU usage
454 * and it will suffer the consequences since we won't be able to
455 * fully reproduce the context of the exception.
456 */
457 if (boot_cpu_has(X86_FEATURE_FXSR)) {
458 cwd = fpu->state.fxsave.cwd;
459 swd = fpu->state.fxsave.swd;
460 } else {
461 cwd = (unsigned short)fpu->state.fsave.cwd;
462 swd = (unsigned short)fpu->state.fsave.swd;
463 }
464
465 err = swd & ~cwd;
466 } else {
467 /*
468 * The SIMD FPU exceptions are handled a little differently, as there
469 * is only a single status/control register. Thus, to determine which
470 * unmasked exception was caught we must mask the exception mask bits
471 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
472 */
473 unsigned short mxcsr = MXCSR_DEFAULT;
474
475 if (boot_cpu_has(X86_FEATURE_XMM))
476 mxcsr = fpu->state.fxsave.mxcsr;
477
478 err = ~(mxcsr >> 7) & mxcsr;
479 }
480
481 if (err & 0x001) { /* Invalid op */
482 /*
483 * swd & 0x240 == 0x040: Stack Underflow
484 * swd & 0x240 == 0x240: Stack Overflow
485 * User must clear the SF bit (0x40) if set
486 */
487 return FPE_FLTINV;
488 } else if (err & 0x004) { /* Divide by Zero */
489 return FPE_FLTDIV;
490 } else if (err & 0x008) { /* Overflow */
491 return FPE_FLTOVF;
492 } else if (err & 0x012) { /* Denormal, Underflow */
493 return FPE_FLTUND;
494 } else if (err & 0x020) { /* Precision */
495 return FPE_FLTRES;
496 }
497
498 /*
499 * If we're using IRQ 13, or supposedly even some trap
500 * X86_TRAP_MF implementations, it's possible
501 * we get a spurious trap, which is not an error.
502 */
503 return 0;
504}