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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Octeon CIU definitions
3 *
4 * Copyright (C) 2003-2018 Cavium, Inc.
5 */
6
7#ifndef __CVMX_CIU_DEFS_H__
8#define __CVMX_CIU_DEFS_H__
9
10#include <asm/bitfield.h>
11
12#define CVMX_CIU_ADDR(addr, coreid, coremask, offset) \
13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
14 (((coreid) & (coremask)) * offset))
15
16#define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17#define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18#define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19#define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20#define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21#define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22#define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23#define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24#define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
25#define CVMX_CIU_INTX_EN1_W1C(c) CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
26#define CVMX_CIU_INTX_EN1_W1S(c) CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
27#define CVMX_CIU_INTX_SUM0(c) CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
28#define CVMX_CIU_NMI CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
29#define CVMX_CIU_PCI_INTA CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
30#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
31#define CVMX_CIU_PP_DBG CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
32#define CVMX_CIU_PP_RST CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
33#define CVMX_CIU_QLM0 CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
34#define CVMX_CIU_QLM1 CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
35#define CVMX_CIU_QLM_JTGC CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
36#define CVMX_CIU_QLM_JTGD CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
37#define CVMX_CIU_SOFT_BIST CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
38#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
39#define CVMX_CIU_SOFT_PRST CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
40#define CVMX_CIU_SOFT_RST CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
41#define CVMX_CIU_SUM2_PPX_IP4(c) CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
42#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
43#define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
44
45static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned int coreid)
46{
47 if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
48 return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8);
49 else
50 return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8);
51}
52
53static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned int coreid)
54{
55 if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
56 return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8);
57 else
58 return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8);
59}
60
61static inline uint64_t CVMX_CIU_PP_POKEX(unsigned int coreid)
62{
63 switch (cvmx_get_octeon_family()) {
64 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
65 return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8);
66 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
69 return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) -
70 0x60000000000ull;
71 default:
72 return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8);
73 }
74}
75
76static inline uint64_t CVMX_CIU_WDOGX(unsigned int coreid)
77{
78 switch (cvmx_get_octeon_family()) {
79 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
80 return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8);
81 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
83 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
84 return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) -
85 0x60000000000ull;
86 default:
87 return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8);
88 }
89}
90
91
92union cvmx_ciu_qlm {
93 uint64_t u64;
94 struct cvmx_ciu_qlm_s {
95 __BITFIELD_FIELD(uint64_t g2bypass:1,
96 __BITFIELD_FIELD(uint64_t reserved_53_62:10,
97 __BITFIELD_FIELD(uint64_t g2deemph:5,
98 __BITFIELD_FIELD(uint64_t reserved_45_47:3,
99 __BITFIELD_FIELD(uint64_t g2margin:5,
100 __BITFIELD_FIELD(uint64_t reserved_32_39:8,
101 __BITFIELD_FIELD(uint64_t txbypass:1,
102 __BITFIELD_FIELD(uint64_t reserved_21_30:10,
103 __BITFIELD_FIELD(uint64_t txdeemph:5,
104 __BITFIELD_FIELD(uint64_t reserved_13_15:3,
105 __BITFIELD_FIELD(uint64_t txmargin:5,
106 __BITFIELD_FIELD(uint64_t reserved_4_7:4,
107 __BITFIELD_FIELD(uint64_t lane_en:4,
108 ;)))))))))))))
109 } s;
110};
111
112union cvmx_ciu_qlm_jtgc {
113 uint64_t u64;
114 struct cvmx_ciu_qlm_jtgc_s {
115 __BITFIELD_FIELD(uint64_t reserved_17_63:47,
116 __BITFIELD_FIELD(uint64_t bypass_ext:1,
117 __BITFIELD_FIELD(uint64_t reserved_11_15:5,
118 __BITFIELD_FIELD(uint64_t clk_div:3,
119 __BITFIELD_FIELD(uint64_t reserved_7_7:1,
120 __BITFIELD_FIELD(uint64_t mux_sel:3,
121 __BITFIELD_FIELD(uint64_t bypass:4,
122 ;)))))))
123 } s;
124};
125
126union cvmx_ciu_qlm_jtgd {
127 uint64_t u64;
128 struct cvmx_ciu_qlm_jtgd_s {
129 __BITFIELD_FIELD(uint64_t capture:1,
130 __BITFIELD_FIELD(uint64_t shift:1,
131 __BITFIELD_FIELD(uint64_t update:1,
132 __BITFIELD_FIELD(uint64_t reserved_45_60:16,
133 __BITFIELD_FIELD(uint64_t select:5,
134 __BITFIELD_FIELD(uint64_t reserved_37_39:3,
135 __BITFIELD_FIELD(uint64_t shft_cnt:5,
136 __BITFIELD_FIELD(uint64_t shft_reg:32,
137 ;))))))))
138 } s;
139};
140
141union cvmx_ciu_soft_prst {
142 uint64_t u64;
143 struct cvmx_ciu_soft_prst_s {
144 __BITFIELD_FIELD(uint64_t reserved_3_63:61,
145 __BITFIELD_FIELD(uint64_t host64:1,
146 __BITFIELD_FIELD(uint64_t npi:1,
147 __BITFIELD_FIELD(uint64_t soft_prst:1,
148 ;))))
149 } s;
150};
151
152union cvmx_ciu_timx {
153 uint64_t u64;
154 struct cvmx_ciu_timx_s {
155 __BITFIELD_FIELD(uint64_t reserved_37_63:27,
156 __BITFIELD_FIELD(uint64_t one_shot:1,
157 __BITFIELD_FIELD(uint64_t len:36,
158 ;)))
159 } s;
160};
161
162union cvmx_ciu_wdogx {
163 uint64_t u64;
164 struct cvmx_ciu_wdogx_s {
165 __BITFIELD_FIELD(uint64_t reserved_46_63:18,
166 __BITFIELD_FIELD(uint64_t gstopen:1,
167 __BITFIELD_FIELD(uint64_t dstop:1,
168 __BITFIELD_FIELD(uint64_t cnt:24,
169 __BITFIELD_FIELD(uint64_t len:16,
170 __BITFIELD_FIELD(uint64_t state:2,
171 __BITFIELD_FIELD(uint64_t mode:2,
172 ;)))))))
173 } s;
174};
175
176#endif /* __CVMX_CIU_DEFS_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Octeon CIU definitions
3 *
4 * Copyright (C) 2003-2018 Cavium, Inc.
5 */
6
7#ifndef __CVMX_CIU_DEFS_H__
8#define __CVMX_CIU_DEFS_H__
9
10#include <asm/bitfield.h>
11
12#define CVMX_CIU_ADDR(addr, coreid, coremask, offset) \
13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
14 (((coreid) & (coremask)) * offset))
15
16#define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17#define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18#define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19#define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20#define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21#define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22#define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23#define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24#define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
25#define CVMX_CIU_INTX_EN1_W1C(c) CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
26#define CVMX_CIU_INTX_EN1_W1S(c) CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
27#define CVMX_CIU_INTX_SUM0(c) CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
28#define CVMX_CIU_NMI CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
29#define CVMX_CIU_PCI_INTA CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
30#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
31#define CVMX_CIU_PP_DBG CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
32#define CVMX_CIU_PP_RST CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
33#define CVMX_CIU_QLM0 CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
34#define CVMX_CIU_QLM1 CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
35#define CVMX_CIU_QLM_JTGC CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
36#define CVMX_CIU_QLM_JTGD CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
37#define CVMX_CIU_SOFT_BIST CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
38#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
39#define CVMX_CIU_SOFT_PRST CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
40#define CVMX_CIU_SOFT_RST CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
41#define CVMX_CIU_SUM2_PPX_IP4(c) CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
42#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
43#define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
44
45static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned int coreid)
46{
47 if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
48 return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8);
49 else
50 return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8);
51}
52
53static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned int coreid)
54{
55 if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
56 return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8);
57 else
58 return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8);
59}
60
61static inline uint64_t CVMX_CIU_PP_POKEX(unsigned int coreid)
62{
63 switch (cvmx_get_octeon_family()) {
64 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
65 return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8);
66 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
69 return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) -
70 0x60000000000ull;
71 default:
72 return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8);
73 }
74}
75
76static inline uint64_t CVMX_CIU_WDOGX(unsigned int coreid)
77{
78 switch (cvmx_get_octeon_family()) {
79 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
80 return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8);
81 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
83 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
84 return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) -
85 0x60000000000ull;
86 default:
87 return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8);
88 }
89}
90
91
92union cvmx_ciu_qlm {
93 uint64_t u64;
94 struct cvmx_ciu_qlm_s {
95 __BITFIELD_FIELD(uint64_t g2bypass:1,
96 __BITFIELD_FIELD(uint64_t reserved_53_62:10,
97 __BITFIELD_FIELD(uint64_t g2deemph:5,
98 __BITFIELD_FIELD(uint64_t reserved_45_47:3,
99 __BITFIELD_FIELD(uint64_t g2margin:5,
100 __BITFIELD_FIELD(uint64_t reserved_32_39:8,
101 __BITFIELD_FIELD(uint64_t txbypass:1,
102 __BITFIELD_FIELD(uint64_t reserved_21_30:10,
103 __BITFIELD_FIELD(uint64_t txdeemph:5,
104 __BITFIELD_FIELD(uint64_t reserved_13_15:3,
105 __BITFIELD_FIELD(uint64_t txmargin:5,
106 __BITFIELD_FIELD(uint64_t reserved_4_7:4,
107 __BITFIELD_FIELD(uint64_t lane_en:4,
108 ;)))))))))))))
109 } s;
110};
111
112union cvmx_ciu_qlm_jtgc {
113 uint64_t u64;
114 struct cvmx_ciu_qlm_jtgc_s {
115 __BITFIELD_FIELD(uint64_t reserved_17_63:47,
116 __BITFIELD_FIELD(uint64_t bypass_ext:1,
117 __BITFIELD_FIELD(uint64_t reserved_11_15:5,
118 __BITFIELD_FIELD(uint64_t clk_div:3,
119 __BITFIELD_FIELD(uint64_t reserved_7_7:1,
120 __BITFIELD_FIELD(uint64_t mux_sel:3,
121 __BITFIELD_FIELD(uint64_t bypass:4,
122 ;)))))))
123 } s;
124};
125
126union cvmx_ciu_qlm_jtgd {
127 uint64_t u64;
128 struct cvmx_ciu_qlm_jtgd_s {
129 __BITFIELD_FIELD(uint64_t capture:1,
130 __BITFIELD_FIELD(uint64_t shift:1,
131 __BITFIELD_FIELD(uint64_t update:1,
132 __BITFIELD_FIELD(uint64_t reserved_45_60:16,
133 __BITFIELD_FIELD(uint64_t select:5,
134 __BITFIELD_FIELD(uint64_t reserved_37_39:3,
135 __BITFIELD_FIELD(uint64_t shft_cnt:5,
136 __BITFIELD_FIELD(uint64_t shft_reg:32,
137 ;))))))))
138 } s;
139};
140
141union cvmx_ciu_soft_prst {
142 uint64_t u64;
143 struct cvmx_ciu_soft_prst_s {
144 __BITFIELD_FIELD(uint64_t reserved_3_63:61,
145 __BITFIELD_FIELD(uint64_t host64:1,
146 __BITFIELD_FIELD(uint64_t npi:1,
147 __BITFIELD_FIELD(uint64_t soft_prst:1,
148 ;))))
149 } s;
150};
151
152union cvmx_ciu_timx {
153 uint64_t u64;
154 struct cvmx_ciu_timx_s {
155 __BITFIELD_FIELD(uint64_t reserved_37_63:27,
156 __BITFIELD_FIELD(uint64_t one_shot:1,
157 __BITFIELD_FIELD(uint64_t len:36,
158 ;)))
159 } s;
160};
161
162union cvmx_ciu_wdogx {
163 uint64_t u64;
164 struct cvmx_ciu_wdogx_s {
165 __BITFIELD_FIELD(uint64_t reserved_46_63:18,
166 __BITFIELD_FIELD(uint64_t gstopen:1,
167 __BITFIELD_FIELD(uint64_t dstop:1,
168 __BITFIELD_FIELD(uint64_t cnt:24,
169 __BITFIELD_FIELD(uint64_t len:16,
170 __BITFIELD_FIELD(uint64_t state:2,
171 __BITFIELD_FIELD(uint64_t mode:2,
172 ;)))))))
173 } s;
174};
175
176#endif /* __CVMX_CIU_DEFS_H__ */