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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) NEC Electronics Corporation 2005-2006
4 *
5 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
6 * Copyright 2001 MontaVista Software Inc.
7 */
8#ifndef __ASM_EMMA_EMMA2RH_H
9#define __ASM_EMMA_EMMA2RH_H
10
11#include <irq.h>
12
13/*
14 * EMMA2RH registers
15 */
16#define REGBASE 0x10000000
17
18#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
19#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
20#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
21#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
22#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
23#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
24#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
25#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
26#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
27#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
28#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
29#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
30#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
31#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
32#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
33#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
34#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
35#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
36#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
37#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
38#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
39#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
40#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
41#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
42#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
43#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
44#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
45#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
46#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
47#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
48#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
49#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
50#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
51#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
52#define EMMA2RH_PCI_INT (0x200020+REGBASE)
53#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
54#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
55#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
56#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
57#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
58
59/*
60 * Memory map (physical address)
61 *
62 * Note most of the following address must be properly aligned by the
63 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
64 * PCI_IO_BASE must be aligned along 16MB boundary.
65 */
66
67/* the actual ram size is detected at run-time */
68#define EMMA2RH_RAM_BASE 0x00000000
69#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
70
71#define EMMA2RH_IO_BASE 0x10000000
72#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
73
74#define EMMA2RH_GENERALIO_BASE 0x11000000
75#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
76
77#define EMMA2RH_PCI_IO_BASE 0x12000000
78#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
79
80#define EMMA2RH_PCI_MEM_BASE 0x14000000
81#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
82
83#define EMMA2RH_ROM_BASE 0x1c000000
84#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
85
86#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
87#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
88
89#define NUM_EMMA2RH_IRQ 96
90
91#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
92
93/*
94 * emma2rh irq defs
95 */
96
97#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
98
99#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
100#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
101#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
102#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
103#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
104#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
105
106/*
107 * EMMA2RH Register Access
108 */
109
110#define EMMA2RH_BASE (0xa0000000)
111
112static inline void emma2rh_sync(void)
113{
114 volatile u32 *p = (volatile u32 *)0xbfc00000;
115 (void)(*p);
116}
117
118static inline void emma2rh_out32(u32 offset, u32 val)
119{
120 *(volatile u32 *)(EMMA2RH_BASE | offset) = val;
121 emma2rh_sync();
122}
123
124static inline u32 emma2rh_in32(u32 offset)
125{
126 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
127 return val;
128}
129
130static inline void emma2rh_out16(u32 offset, u16 val)
131{
132 *(volatile u16 *)(EMMA2RH_BASE | offset) = val;
133 emma2rh_sync();
134}
135
136static inline u16 emma2rh_in16(u32 offset)
137{
138 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
139 return val;
140}
141
142static inline void emma2rh_out8(u32 offset, u8 val)
143{
144 *(volatile u8 *)(EMMA2RH_BASE | offset) = val;
145 emma2rh_sync();
146}
147
148static inline u8 emma2rh_in8(u32 offset)
149{
150 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
151 return val;
152}
153
154/**
155 * IIC registers map
156 **/
157
158/*---------------------------------------------------------------------------*/
159/* CNT - Control register (00H R/W) */
160/*---------------------------------------------------------------------------*/
161#define SPT 0x00000001
162#define STT 0x00000002
163#define ACKE 0x00000004
164#define WTIM 0x00000008
165#define SPIE 0x00000010
166#define WREL 0x00000020
167#define LREL 0x00000040
168#define IICE 0x00000080
169#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
170
171#define I2C_EMMA_START (IICE | STT)
172#define I2C_EMMA_STOP (IICE | SPT)
173#define I2C_EMMA_REPSTART I2C_EMMA_START
174
175/*---------------------------------------------------------------------------*/
176/* STA - Status register (10H Read) */
177/*---------------------------------------------------------------------------*/
178#define MSTS 0x00000080
179#define ALD 0x00000040
180#define EXC 0x00000020
181#define COI 0x00000010
182#define TRC 0x00000008
183#define ACKD 0x00000004
184#define STD 0x00000002
185#define SPD 0x00000001
186
187/*---------------------------------------------------------------------------*/
188/* CSEL - Clock select register (20H R/W) */
189/*---------------------------------------------------------------------------*/
190#define FCL 0x00000080
191#define ND50 0x00000040
192#define CLD 0x00000020
193#define DAD 0x00000010
194#define SMC 0x00000008
195#define DFC 0x00000004
196#define CL 0x00000003
197#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
198
199#define FAST397 0x0000008b
200#define FAST297 0x0000008a
201#define FAST347 0x0000000b
202#define FAST260 0x0000000a
203#define FAST130 0x00000008
204#define STANDARD108 0x00000083
205#define STANDARD83 0x00000082
206#define STANDARD95 0x00000003
207#define STANDARD73 0x00000002
208#define STANDARD36 0x00000001
209#define STANDARD71 0x00000000
210
211/*---------------------------------------------------------------------------*/
212/* SVA - Slave address register (30H R/W) */
213/*---------------------------------------------------------------------------*/
214#define SVA 0x000000fe
215
216/*---------------------------------------------------------------------------*/
217/* SHR - Shift register (40H R/W) */
218/*---------------------------------------------------------------------------*/
219#define SR 0x000000ff
220
221/*---------------------------------------------------------------------------*/
222/* INT - Interrupt register (50H R/W) */
223/* INTM - Interrupt mask register (60H R/W) */
224/*---------------------------------------------------------------------------*/
225#define INTE0 0x00000001
226
227/***********************************************************************
228 * I2C registers
229 ***********************************************************************
230 */
231#define I2C_EMMA_CNT 0x00
232#define I2C_EMMA_STA 0x10
233#define I2C_EMMA_CSEL 0x20
234#define I2C_EMMA_SVA 0x30
235#define I2C_EMMA_SHR 0x40
236#define I2C_EMMA_INT 0x50
237#define I2C_EMMA_INTM 0x60
238
239/*
240 * include the board dependent part
241 */
242#ifdef CONFIG_NEC_MARKEINS
243#include <asm/emma/markeins.h>
244#else
245#error "Unknown EMMA2RH board!"
246#endif
247
248#endif /* __ASM_EMMA_EMMA2RH_H */