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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/serial_reg.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/platform_device.h>
32#include <linux/io.h>
33#include <linux/clk.h>
34#include <linux/serial_core.h>
35#include <linux/irq.h>
36#include <linux/pm_runtime.h>
37#include <linux/pm_wakeirq.h>
38#include <linux/of.h>
39#include <linux/of_irq.h>
40#include <linux/gpio.h>
41#include <linux/of_gpio.h>
42#include <linux/platform_data/serial-omap.h>
43
44#include <dt-bindings/gpio/gpio.h>
45
46#define OMAP_MAX_HSUART_PORTS 10
47
48#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
49
50#define OMAP_UART_REV_42 0x0402
51#define OMAP_UART_REV_46 0x0406
52#define OMAP_UART_REV_52 0x0502
53#define OMAP_UART_REV_63 0x0603
54
55#define OMAP_UART_TX_WAKEUP_EN BIT(7)
56
57/* Feature flags */
58#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
59
60#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
61#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
62
63#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
64
65/* SCR register bitmasks */
66#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
67#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
68#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
69
70/* FCR register bitmasks */
71#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
72#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
73
74/* MVR register bitmasks */
75#define OMAP_UART_MVR_SCHEME_SHIFT 30
76
77#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
78#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
79#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
80
81#define OMAP_UART_MVR_MAJ_MASK 0x700
82#define OMAP_UART_MVR_MAJ_SHIFT 8
83#define OMAP_UART_MVR_MIN_MASK 0x3f
84
85#define OMAP_UART_DMA_CH_FREE -1
86
87#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
88#define OMAP_MODE13X_SPEED 230400
89
90/* WER = 0x7F
91 * Enable module level wakeup in WER reg
92 */
93#define OMAP_UART_WER_MOD_WKUP 0x7F
94
95/* Enable XON/XOFF flow control on output */
96#define OMAP_UART_SW_TX 0x08
97
98/* Enable XON/XOFF flow control on input */
99#define OMAP_UART_SW_RX 0x02
100
101#define OMAP_UART_SW_CLR 0xF0
102
103#define OMAP_UART_TCR_TRIG 0x0F
104
105struct uart_omap_dma {
106 u8 uart_dma_tx;
107 u8 uart_dma_rx;
108 int rx_dma_channel;
109 int tx_dma_channel;
110 dma_addr_t rx_buf_dma_phys;
111 dma_addr_t tx_buf_dma_phys;
112 unsigned int uart_base;
113 /*
114 * Buffer for rx dma. It is not required for tx because the buffer
115 * comes from port structure.
116 */
117 unsigned char *rx_buf;
118 unsigned int prev_rx_dma_pos;
119 int tx_buf_size;
120 int tx_dma_used;
121 int rx_dma_used;
122 spinlock_t tx_lock;
123 spinlock_t rx_lock;
124 /* timer to poll activity on rx dma */
125 struct timer_list rx_timer;
126 unsigned int rx_buf_size;
127 unsigned int rx_poll_rate;
128 unsigned int rx_timeout;
129};
130
131struct uart_omap_port {
132 struct uart_port port;
133 struct uart_omap_dma uart_dma;
134 struct device *dev;
135 int wakeirq;
136
137 unsigned char ier;
138 unsigned char lcr;
139 unsigned char mcr;
140 unsigned char fcr;
141 unsigned char efr;
142 unsigned char dll;
143 unsigned char dlh;
144 unsigned char mdr1;
145 unsigned char scr;
146 unsigned char wer;
147
148 int use_dma;
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read, but the bits will not
152 * be immediately processed.
153 */
154 unsigned int lsr_break_flag;
155 unsigned char msr_saved_flags;
156 char name[20];
157 unsigned long port_activity;
158 int context_loss_cnt;
159 u32 errata;
160 u32 features;
161
162 int rts_gpio;
163
164 struct pm_qos_request pm_qos_request;
165 u32 latency;
166 u32 calc_latency;
167 struct work_struct qos_work;
168 bool is_suspending;
169};
170
171#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
172
173static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
174
175/* Forward declaration of functions */
176static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
177
178static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
179{
180 offset <<= up->port.regshift;
181 return readw(up->port.membase + offset);
182}
183
184static inline void serial_out(struct uart_omap_port *up, int offset, int value)
185{
186 offset <<= up->port.regshift;
187 writew(value, up->port.membase + offset);
188}
189
190static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
191{
192 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
193 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
194 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
195 serial_out(up, UART_FCR, 0);
196}
197
198#ifdef CONFIG_PM
199static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
200{
201 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
202
203 if (!pdata || !pdata->get_context_loss_count)
204 return -EINVAL;
205
206 return pdata->get_context_loss_count(up->dev);
207}
208
209/* REVISIT: Remove this when omap3 boots in device tree only mode */
210static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
211{
212 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
213
214 if (!pdata || !pdata->enable_wakeup)
215 return;
216
217 pdata->enable_wakeup(up->dev, enable);
218}
219#endif /* CONFIG_PM */
220
221/*
222 * Calculate the absolute difference between the desired and actual baud
223 * rate for the given mode.
224 */
225static inline int calculate_baud_abs_diff(struct uart_port *port,
226 unsigned int baud, unsigned int mode)
227{
228 unsigned int n = port->uartclk / (mode * baud);
229 int abs_diff;
230
231 if (n == 0)
232 n = 1;
233
234 abs_diff = baud - (port->uartclk / (mode * n));
235 if (abs_diff < 0)
236 abs_diff = -abs_diff;
237
238 return abs_diff;
239}
240
241/*
242 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
243 * @port: uart port info
244 * @baud: baudrate for which mode needs to be determined
245 *
246 * Returns true if baud rate is MODE16X and false if MODE13X
247 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
248 * and Error Rates" determines modes not for all common baud rates.
249 * E.g. for 1000000 baud rate mode must be 16x, but according to that
250 * table it's determined as 13x.
251 */
252static bool
253serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
254{
255 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
256 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
257
258 return (abs_diff_13 >= abs_diff_16);
259}
260
261/*
262 * serial_omap_get_divisor - calculate divisor value
263 * @port: uart port info
264 * @baud: baudrate for which divisor needs to be calculated.
265 */
266static unsigned int
267serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
268{
269 unsigned int mode;
270
271 if (!serial_omap_baud_is_mode16(port, baud))
272 mode = 13;
273 else
274 mode = 16;
275 return port->uartclk/(mode * baud);
276}
277
278static void serial_omap_enable_ms(struct uart_port *port)
279{
280 struct uart_omap_port *up = to_uart_omap_port(port);
281
282 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
283
284 pm_runtime_get_sync(up->dev);
285 up->ier |= UART_IER_MSI;
286 serial_out(up, UART_IER, up->ier);
287 pm_runtime_mark_last_busy(up->dev);
288 pm_runtime_put_autosuspend(up->dev);
289}
290
291static void serial_omap_stop_tx(struct uart_port *port)
292{
293 struct uart_omap_port *up = to_uart_omap_port(port);
294 int res;
295
296 pm_runtime_get_sync(up->dev);
297
298 /* Handle RS-485 */
299 if (port->rs485.flags & SER_RS485_ENABLED) {
300 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
301 /* THR interrupt is fired when both TX FIFO and TX
302 * shift register are empty. This means there's nothing
303 * left to transmit now, so make sure the THR interrupt
304 * is fired when TX FIFO is below the trigger level,
305 * disable THR interrupts and toggle the RS-485 GPIO
306 * data direction pin if needed.
307 */
308 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
309 serial_out(up, UART_OMAP_SCR, up->scr);
310 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
311 1 : 0;
312 if (gpio_get_value(up->rts_gpio) != res) {
313 if (port->rs485.delay_rts_after_send > 0)
314 mdelay(
315 port->rs485.delay_rts_after_send);
316 gpio_set_value(up->rts_gpio, res);
317 }
318 } else {
319 /* We're asked to stop, but there's still stuff in the
320 * UART FIFO, so make sure the THR interrupt is fired
321 * when both TX FIFO and TX shift register are empty.
322 * The next THR interrupt (if no transmission is started
323 * in the meantime) will indicate the end of a
324 * transmission. Therefore we _don't_ disable THR
325 * interrupts in this situation.
326 */
327 up->scr |= OMAP_UART_SCR_TX_EMPTY;
328 serial_out(up, UART_OMAP_SCR, up->scr);
329 return;
330 }
331 }
332
333 if (up->ier & UART_IER_THRI) {
334 up->ier &= ~UART_IER_THRI;
335 serial_out(up, UART_IER, up->ier);
336 }
337
338 if ((port->rs485.flags & SER_RS485_ENABLED) &&
339 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
340 /*
341 * Empty the RX FIFO, we are not interested in anything
342 * received during the half-duplex transmission.
343 */
344 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
345 /* Re-enable RX interrupts */
346 up->ier |= UART_IER_RLSI | UART_IER_RDI;
347 up->port.read_status_mask |= UART_LSR_DR;
348 serial_out(up, UART_IER, up->ier);
349 }
350
351 pm_runtime_mark_last_busy(up->dev);
352 pm_runtime_put_autosuspend(up->dev);
353}
354
355static void serial_omap_stop_rx(struct uart_port *port)
356{
357 struct uart_omap_port *up = to_uart_omap_port(port);
358
359 pm_runtime_get_sync(up->dev);
360 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
361 up->port.read_status_mask &= ~UART_LSR_DR;
362 serial_out(up, UART_IER, up->ier);
363 pm_runtime_mark_last_busy(up->dev);
364 pm_runtime_put_autosuspend(up->dev);
365}
366
367static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
368{
369 struct circ_buf *xmit = &up->port.state->xmit;
370 int count;
371
372 if (up->port.x_char) {
373 serial_out(up, UART_TX, up->port.x_char);
374 up->port.icount.tx++;
375 up->port.x_char = 0;
376 return;
377 }
378 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
379 serial_omap_stop_tx(&up->port);
380 return;
381 }
382 count = up->port.fifosize / 4;
383 do {
384 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
385 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
386 up->port.icount.tx++;
387 if (uart_circ_empty(xmit))
388 break;
389 } while (--count > 0);
390
391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 uart_write_wakeup(&up->port);
393
394 if (uart_circ_empty(xmit))
395 serial_omap_stop_tx(&up->port);
396}
397
398static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
399{
400 if (!(up->ier & UART_IER_THRI)) {
401 up->ier |= UART_IER_THRI;
402 serial_out(up, UART_IER, up->ier);
403 }
404}
405
406static void serial_omap_start_tx(struct uart_port *port)
407{
408 struct uart_omap_port *up = to_uart_omap_port(port);
409 int res;
410
411 pm_runtime_get_sync(up->dev);
412
413 /* Handle RS-485 */
414 if (port->rs485.flags & SER_RS485_ENABLED) {
415 /* Fire THR interrupts when FIFO is below trigger level */
416 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
417 serial_out(up, UART_OMAP_SCR, up->scr);
418
419 /* if rts not already enabled */
420 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
421 if (gpio_get_value(up->rts_gpio) != res) {
422 gpio_set_value(up->rts_gpio, res);
423 if (port->rs485.delay_rts_before_send > 0)
424 mdelay(port->rs485.delay_rts_before_send);
425 }
426 }
427
428 if ((port->rs485.flags & SER_RS485_ENABLED) &&
429 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
430 serial_omap_stop_rx(port);
431
432 serial_omap_enable_ier_thri(up);
433 pm_runtime_mark_last_busy(up->dev);
434 pm_runtime_put_autosuspend(up->dev);
435}
436
437static void serial_omap_throttle(struct uart_port *port)
438{
439 struct uart_omap_port *up = to_uart_omap_port(port);
440 unsigned long flags;
441
442 pm_runtime_get_sync(up->dev);
443 spin_lock_irqsave(&up->port.lock, flags);
444 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
445 serial_out(up, UART_IER, up->ier);
446 spin_unlock_irqrestore(&up->port.lock, flags);
447 pm_runtime_mark_last_busy(up->dev);
448 pm_runtime_put_autosuspend(up->dev);
449}
450
451static void serial_omap_unthrottle(struct uart_port *port)
452{
453 struct uart_omap_port *up = to_uart_omap_port(port);
454 unsigned long flags;
455
456 pm_runtime_get_sync(up->dev);
457 spin_lock_irqsave(&up->port.lock, flags);
458 up->ier |= UART_IER_RLSI | UART_IER_RDI;
459 serial_out(up, UART_IER, up->ier);
460 spin_unlock_irqrestore(&up->port.lock, flags);
461 pm_runtime_mark_last_busy(up->dev);
462 pm_runtime_put_autosuspend(up->dev);
463}
464
465static unsigned int check_modem_status(struct uart_omap_port *up)
466{
467 unsigned int status;
468
469 status = serial_in(up, UART_MSR);
470 status |= up->msr_saved_flags;
471 up->msr_saved_flags = 0;
472 if ((status & UART_MSR_ANY_DELTA) == 0)
473 return status;
474
475 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
476 up->port.state != NULL) {
477 if (status & UART_MSR_TERI)
478 up->port.icount.rng++;
479 if (status & UART_MSR_DDSR)
480 up->port.icount.dsr++;
481 if (status & UART_MSR_DDCD)
482 uart_handle_dcd_change
483 (&up->port, status & UART_MSR_DCD);
484 if (status & UART_MSR_DCTS)
485 uart_handle_cts_change
486 (&up->port, status & UART_MSR_CTS);
487 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
488 }
489
490 return status;
491}
492
493static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
494{
495 unsigned int flag;
496 unsigned char ch = 0;
497
498 if (likely(lsr & UART_LSR_DR))
499 ch = serial_in(up, UART_RX);
500
501 up->port.icount.rx++;
502 flag = TTY_NORMAL;
503
504 if (lsr & UART_LSR_BI) {
505 flag = TTY_BREAK;
506 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
507 up->port.icount.brk++;
508 /*
509 * We do the SysRQ and SAK checking
510 * here because otherwise the break
511 * may get masked by ignore_status_mask
512 * or read_status_mask.
513 */
514 if (uart_handle_break(&up->port))
515 return;
516
517 }
518
519 if (lsr & UART_LSR_PE) {
520 flag = TTY_PARITY;
521 up->port.icount.parity++;
522 }
523
524 if (lsr & UART_LSR_FE) {
525 flag = TTY_FRAME;
526 up->port.icount.frame++;
527 }
528
529 if (lsr & UART_LSR_OE)
530 up->port.icount.overrun++;
531
532#ifdef CONFIG_SERIAL_OMAP_CONSOLE
533 if (up->port.line == up->port.cons->index) {
534 /* Recover the break flag from console xmit */
535 lsr |= up->lsr_break_flag;
536 }
537#endif
538 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
539}
540
541static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
542{
543 unsigned char ch = 0;
544 unsigned int flag;
545
546 if (!(lsr & UART_LSR_DR))
547 return;
548
549 ch = serial_in(up, UART_RX);
550 flag = TTY_NORMAL;
551 up->port.icount.rx++;
552
553 if (uart_handle_sysrq_char(&up->port, ch))
554 return;
555
556 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
557}
558
559/**
560 * serial_omap_irq() - This handles the interrupt from one port
561 * @irq: uart port irq number
562 * @dev_id: uart port info
563 */
564static irqreturn_t serial_omap_irq(int irq, void *dev_id)
565{
566 struct uart_omap_port *up = dev_id;
567 unsigned int iir, lsr;
568 unsigned int type;
569 irqreturn_t ret = IRQ_NONE;
570 int max_count = 256;
571
572 spin_lock(&up->port.lock);
573 pm_runtime_get_sync(up->dev);
574
575 do {
576 iir = serial_in(up, UART_IIR);
577 if (iir & UART_IIR_NO_INT)
578 break;
579
580 ret = IRQ_HANDLED;
581 lsr = serial_in(up, UART_LSR);
582
583 /* extract IRQ type from IIR register */
584 type = iir & 0x3e;
585
586 switch (type) {
587 case UART_IIR_MSI:
588 check_modem_status(up);
589 break;
590 case UART_IIR_THRI:
591 transmit_chars(up, lsr);
592 break;
593 case UART_IIR_RX_TIMEOUT:
594 /* FALLTHROUGH */
595 case UART_IIR_RDI:
596 serial_omap_rdi(up, lsr);
597 break;
598 case UART_IIR_RLSI:
599 serial_omap_rlsi(up, lsr);
600 break;
601 case UART_IIR_CTS_RTS_DSR:
602 /* simply try again */
603 break;
604 case UART_IIR_XOFF:
605 /* FALLTHROUGH */
606 default:
607 break;
608 }
609 } while (max_count--);
610
611 spin_unlock(&up->port.lock);
612
613 tty_flip_buffer_push(&up->port.state->port);
614
615 pm_runtime_mark_last_busy(up->dev);
616 pm_runtime_put_autosuspend(up->dev);
617 up->port_activity = jiffies;
618
619 return ret;
620}
621
622static unsigned int serial_omap_tx_empty(struct uart_port *port)
623{
624 struct uart_omap_port *up = to_uart_omap_port(port);
625 unsigned long flags = 0;
626 unsigned int ret = 0;
627
628 pm_runtime_get_sync(up->dev);
629 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
630 spin_lock_irqsave(&up->port.lock, flags);
631 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
632 spin_unlock_irqrestore(&up->port.lock, flags);
633 pm_runtime_mark_last_busy(up->dev);
634 pm_runtime_put_autosuspend(up->dev);
635 return ret;
636}
637
638static unsigned int serial_omap_get_mctrl(struct uart_port *port)
639{
640 struct uart_omap_port *up = to_uart_omap_port(port);
641 unsigned int status;
642 unsigned int ret = 0;
643
644 pm_runtime_get_sync(up->dev);
645 status = check_modem_status(up);
646 pm_runtime_mark_last_busy(up->dev);
647 pm_runtime_put_autosuspend(up->dev);
648
649 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
650
651 if (status & UART_MSR_DCD)
652 ret |= TIOCM_CAR;
653 if (status & UART_MSR_RI)
654 ret |= TIOCM_RNG;
655 if (status & UART_MSR_DSR)
656 ret |= TIOCM_DSR;
657 if (status & UART_MSR_CTS)
658 ret |= TIOCM_CTS;
659 return ret;
660}
661
662static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
663{
664 struct uart_omap_port *up = to_uart_omap_port(port);
665 unsigned char mcr = 0, old_mcr, lcr;
666
667 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
668 if (mctrl & TIOCM_RTS)
669 mcr |= UART_MCR_RTS;
670 if (mctrl & TIOCM_DTR)
671 mcr |= UART_MCR_DTR;
672 if (mctrl & TIOCM_OUT1)
673 mcr |= UART_MCR_OUT1;
674 if (mctrl & TIOCM_OUT2)
675 mcr |= UART_MCR_OUT2;
676 if (mctrl & TIOCM_LOOP)
677 mcr |= UART_MCR_LOOP;
678
679 pm_runtime_get_sync(up->dev);
680 old_mcr = serial_in(up, UART_MCR);
681 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
682 UART_MCR_DTR | UART_MCR_RTS);
683 up->mcr = old_mcr | mcr;
684 serial_out(up, UART_MCR, up->mcr);
685
686 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
687 lcr = serial_in(up, UART_LCR);
688 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
689 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
690 up->efr |= UART_EFR_RTS;
691 else
692 up->efr &= ~UART_EFR_RTS;
693 serial_out(up, UART_EFR, up->efr);
694 serial_out(up, UART_LCR, lcr);
695
696 pm_runtime_mark_last_busy(up->dev);
697 pm_runtime_put_autosuspend(up->dev);
698}
699
700static void serial_omap_break_ctl(struct uart_port *port, int break_state)
701{
702 struct uart_omap_port *up = to_uart_omap_port(port);
703 unsigned long flags = 0;
704
705 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
706 pm_runtime_get_sync(up->dev);
707 spin_lock_irqsave(&up->port.lock, flags);
708 if (break_state == -1)
709 up->lcr |= UART_LCR_SBC;
710 else
711 up->lcr &= ~UART_LCR_SBC;
712 serial_out(up, UART_LCR, up->lcr);
713 spin_unlock_irqrestore(&up->port.lock, flags);
714 pm_runtime_mark_last_busy(up->dev);
715 pm_runtime_put_autosuspend(up->dev);
716}
717
718static int serial_omap_startup(struct uart_port *port)
719{
720 struct uart_omap_port *up = to_uart_omap_port(port);
721 unsigned long flags = 0;
722 int retval;
723
724 /*
725 * Allocate the IRQ
726 */
727 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
728 up->name, up);
729 if (retval)
730 return retval;
731
732 /* Optional wake-up IRQ */
733 if (up->wakeirq) {
734 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
735 if (retval) {
736 free_irq(up->port.irq, up);
737 return retval;
738 }
739 }
740
741 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
742
743 pm_runtime_get_sync(up->dev);
744 /*
745 * Clear the FIFO buffers and disable them.
746 * (they will be reenabled in set_termios())
747 */
748 serial_omap_clear_fifos(up);
749
750 /*
751 * Clear the interrupt registers.
752 */
753 (void) serial_in(up, UART_LSR);
754 if (serial_in(up, UART_LSR) & UART_LSR_DR)
755 (void) serial_in(up, UART_RX);
756 (void) serial_in(up, UART_IIR);
757 (void) serial_in(up, UART_MSR);
758
759 /*
760 * Now, initialize the UART
761 */
762 serial_out(up, UART_LCR, UART_LCR_WLEN8);
763 spin_lock_irqsave(&up->port.lock, flags);
764 /*
765 * Most PC uarts need OUT2 raised to enable interrupts.
766 */
767 up->port.mctrl |= TIOCM_OUT2;
768 serial_omap_set_mctrl(&up->port, up->port.mctrl);
769 spin_unlock_irqrestore(&up->port.lock, flags);
770
771 up->msr_saved_flags = 0;
772 /*
773 * Finally, enable interrupts. Note: Modem status interrupts
774 * are set via set_termios(), which will be occurring imminently
775 * anyway, so we don't enable them here.
776 */
777 up->ier = UART_IER_RLSI | UART_IER_RDI;
778 serial_out(up, UART_IER, up->ier);
779
780 /* Enable module level wake up */
781 up->wer = OMAP_UART_WER_MOD_WKUP;
782 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
783 up->wer |= OMAP_UART_TX_WAKEUP_EN;
784
785 serial_out(up, UART_OMAP_WER, up->wer);
786
787 pm_runtime_mark_last_busy(up->dev);
788 pm_runtime_put_autosuspend(up->dev);
789 up->port_activity = jiffies;
790 return 0;
791}
792
793static void serial_omap_shutdown(struct uart_port *port)
794{
795 struct uart_omap_port *up = to_uart_omap_port(port);
796 unsigned long flags = 0;
797
798 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
799
800 pm_runtime_get_sync(up->dev);
801 /*
802 * Disable interrupts from this port
803 */
804 up->ier = 0;
805 serial_out(up, UART_IER, 0);
806
807 spin_lock_irqsave(&up->port.lock, flags);
808 up->port.mctrl &= ~TIOCM_OUT2;
809 serial_omap_set_mctrl(&up->port, up->port.mctrl);
810 spin_unlock_irqrestore(&up->port.lock, flags);
811
812 /*
813 * Disable break condition and FIFOs
814 */
815 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
816 serial_omap_clear_fifos(up);
817
818 /*
819 * Read data port to reset things, and then free the irq
820 */
821 if (serial_in(up, UART_LSR) & UART_LSR_DR)
822 (void) serial_in(up, UART_RX);
823
824 pm_runtime_mark_last_busy(up->dev);
825 pm_runtime_put_autosuspend(up->dev);
826 free_irq(up->port.irq, up);
827 dev_pm_clear_wake_irq(up->dev);
828}
829
830static void serial_omap_uart_qos_work(struct work_struct *work)
831{
832 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
833 qos_work);
834
835 pm_qos_update_request(&up->pm_qos_request, up->latency);
836}
837
838static void
839serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
840 struct ktermios *old)
841{
842 struct uart_omap_port *up = to_uart_omap_port(port);
843 unsigned char cval = 0;
844 unsigned long flags = 0;
845 unsigned int baud, quot;
846
847 switch (termios->c_cflag & CSIZE) {
848 case CS5:
849 cval = UART_LCR_WLEN5;
850 break;
851 case CS6:
852 cval = UART_LCR_WLEN6;
853 break;
854 case CS7:
855 cval = UART_LCR_WLEN7;
856 break;
857 default:
858 case CS8:
859 cval = UART_LCR_WLEN8;
860 break;
861 }
862
863 if (termios->c_cflag & CSTOPB)
864 cval |= UART_LCR_STOP;
865 if (termios->c_cflag & PARENB)
866 cval |= UART_LCR_PARITY;
867 if (!(termios->c_cflag & PARODD))
868 cval |= UART_LCR_EPAR;
869 if (termios->c_cflag & CMSPAR)
870 cval |= UART_LCR_SPAR;
871
872 /*
873 * Ask the core to calculate the divisor for us.
874 */
875
876 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
877 quot = serial_omap_get_divisor(port, baud);
878
879 /* calculate wakeup latency constraint */
880 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
881 up->latency = up->calc_latency;
882 schedule_work(&up->qos_work);
883
884 up->dll = quot & 0xff;
885 up->dlh = quot >> 8;
886 up->mdr1 = UART_OMAP_MDR1_DISABLE;
887
888 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
889 UART_FCR_ENABLE_FIFO;
890
891 /*
892 * Ok, we're now changing the port state. Do it with
893 * interrupts disabled.
894 */
895 pm_runtime_get_sync(up->dev);
896 spin_lock_irqsave(&up->port.lock, flags);
897
898 /*
899 * Update the per-port timeout.
900 */
901 uart_update_timeout(port, termios->c_cflag, baud);
902
903 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
904 if (termios->c_iflag & INPCK)
905 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
906 if (termios->c_iflag & (BRKINT | PARMRK))
907 up->port.read_status_mask |= UART_LSR_BI;
908
909 /*
910 * Characters to ignore
911 */
912 up->port.ignore_status_mask = 0;
913 if (termios->c_iflag & IGNPAR)
914 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
915 if (termios->c_iflag & IGNBRK) {
916 up->port.ignore_status_mask |= UART_LSR_BI;
917 /*
918 * If we're ignoring parity and break indicators,
919 * ignore overruns too (for real raw support).
920 */
921 if (termios->c_iflag & IGNPAR)
922 up->port.ignore_status_mask |= UART_LSR_OE;
923 }
924
925 /*
926 * ignore all characters if CREAD is not set
927 */
928 if ((termios->c_cflag & CREAD) == 0)
929 up->port.ignore_status_mask |= UART_LSR_DR;
930
931 /*
932 * Modem status interrupts
933 */
934 up->ier &= ~UART_IER_MSI;
935 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
936 up->ier |= UART_IER_MSI;
937 serial_out(up, UART_IER, up->ier);
938 serial_out(up, UART_LCR, cval); /* reset DLAB */
939 up->lcr = cval;
940 up->scr = 0;
941
942 /* FIFOs and DMA Settings */
943
944 /* FCR can be changed only when the
945 * baud clock is not running
946 * DLL_REG and DLH_REG set to 0.
947 */
948 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
949 serial_out(up, UART_DLL, 0);
950 serial_out(up, UART_DLM, 0);
951 serial_out(up, UART_LCR, 0);
952
953 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
954
955 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
956 up->efr &= ~UART_EFR_SCD;
957 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
958
959 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
960 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
961 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
962 /* FIFO ENABLE, DMA MODE */
963
964 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
965 /*
966 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
967 * sets Enables the granularity of 1 for TRIGGER RX
968 * level. Along with setting RX FIFO trigger level
969 * to 1 (as noted below, 16 characters) and TLR[3:0]
970 * to zero this will result RX FIFO threshold level
971 * to 1 character, instead of 16 as noted in comment
972 * below.
973 */
974
975 /* Set receive FIFO threshold to 16 characters and
976 * transmit FIFO threshold to 32 spaces
977 */
978 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
979 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
980 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
981 UART_FCR_ENABLE_FIFO;
982
983 serial_out(up, UART_FCR, up->fcr);
984 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
985
986 serial_out(up, UART_OMAP_SCR, up->scr);
987
988 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
990 serial_out(up, UART_MCR, up->mcr);
991 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
992 serial_out(up, UART_EFR, up->efr);
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
994
995 /* Protocol, Baud Rate, and Interrupt Settings */
996
997 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
998 serial_omap_mdr1_errataset(up, up->mdr1);
999 else
1000 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1001
1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1003 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1004
1005 serial_out(up, UART_LCR, 0);
1006 serial_out(up, UART_IER, 0);
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1008
1009 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1010 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1011
1012 serial_out(up, UART_LCR, 0);
1013 serial_out(up, UART_IER, up->ier);
1014 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1015
1016 serial_out(up, UART_EFR, up->efr);
1017 serial_out(up, UART_LCR, cval);
1018
1019 if (!serial_omap_baud_is_mode16(port, baud))
1020 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1021 else
1022 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1023
1024 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1025 serial_omap_mdr1_errataset(up, up->mdr1);
1026 else
1027 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1028
1029 /* Configure flow control */
1030 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1031
1032 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1033 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1034 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1035
1036 /* Enable access to TCR/TLR */
1037 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1038 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1039 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1040
1041 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1042
1043 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1044
1045 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1046 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1047 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1048 up->efr |= UART_EFR_CTS;
1049 } else {
1050 /* Disable AUTORTS and AUTOCTS */
1051 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1052 }
1053
1054 if (up->port.flags & UPF_SOFT_FLOW) {
1055 /* clear SW control mode bits */
1056 up->efr &= OMAP_UART_SW_CLR;
1057
1058 /*
1059 * IXON Flag:
1060 * Enable XON/XOFF flow control on input.
1061 * Receiver compares XON1, XOFF1.
1062 */
1063 if (termios->c_iflag & IXON)
1064 up->efr |= OMAP_UART_SW_RX;
1065
1066 /*
1067 * IXOFF Flag:
1068 * Enable XON/XOFF flow control on output.
1069 * Transmit XON1, XOFF1
1070 */
1071 if (termios->c_iflag & IXOFF) {
1072 up->port.status |= UPSTAT_AUTOXOFF;
1073 up->efr |= OMAP_UART_SW_TX;
1074 }
1075
1076 /*
1077 * IXANY Flag:
1078 * Enable any character to restart output.
1079 * Operation resumes after receiving any
1080 * character after recognition of the XOFF character
1081 */
1082 if (termios->c_iflag & IXANY)
1083 up->mcr |= UART_MCR_XONANY;
1084 else
1085 up->mcr &= ~UART_MCR_XONANY;
1086 }
1087 serial_out(up, UART_MCR, up->mcr);
1088 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1089 serial_out(up, UART_EFR, up->efr);
1090 serial_out(up, UART_LCR, up->lcr);
1091
1092 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1093
1094 spin_unlock_irqrestore(&up->port.lock, flags);
1095 pm_runtime_mark_last_busy(up->dev);
1096 pm_runtime_put_autosuspend(up->dev);
1097 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1098}
1099
1100static void
1101serial_omap_pm(struct uart_port *port, unsigned int state,
1102 unsigned int oldstate)
1103{
1104 struct uart_omap_port *up = to_uart_omap_port(port);
1105 unsigned char efr;
1106
1107 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1108
1109 pm_runtime_get_sync(up->dev);
1110 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111 efr = serial_in(up, UART_EFR);
1112 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1113 serial_out(up, UART_LCR, 0);
1114
1115 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1116 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1117 serial_out(up, UART_EFR, efr);
1118 serial_out(up, UART_LCR, 0);
1119
1120 pm_runtime_mark_last_busy(up->dev);
1121 pm_runtime_put_autosuspend(up->dev);
1122}
1123
1124static void serial_omap_release_port(struct uart_port *port)
1125{
1126 dev_dbg(port->dev, "serial_omap_release_port+\n");
1127}
1128
1129static int serial_omap_request_port(struct uart_port *port)
1130{
1131 dev_dbg(port->dev, "serial_omap_request_port+\n");
1132 return 0;
1133}
1134
1135static void serial_omap_config_port(struct uart_port *port, int flags)
1136{
1137 struct uart_omap_port *up = to_uart_omap_port(port);
1138
1139 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1140 up->port.line);
1141 up->port.type = PORT_OMAP;
1142 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1143}
1144
1145static int
1146serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1147{
1148 /* we don't want the core code to modify any port params */
1149 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1150 return -EINVAL;
1151}
1152
1153static const char *
1154serial_omap_type(struct uart_port *port)
1155{
1156 struct uart_omap_port *up = to_uart_omap_port(port);
1157
1158 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1159 return up->name;
1160}
1161
1162#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1163
1164static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1165{
1166 unsigned int status, tmout = 10000;
1167
1168 /* Wait up to 10ms for the character(s) to be sent. */
1169 do {
1170 status = serial_in(up, UART_LSR);
1171
1172 if (status & UART_LSR_BI)
1173 up->lsr_break_flag = UART_LSR_BI;
1174
1175 if (--tmout == 0)
1176 break;
1177 udelay(1);
1178 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1179
1180 /* Wait up to 1s for flow control if necessary */
1181 if (up->port.flags & UPF_CONS_FLOW) {
1182 tmout = 1000000;
1183 for (tmout = 1000000; tmout; tmout--) {
1184 unsigned int msr = serial_in(up, UART_MSR);
1185
1186 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1187 if (msr & UART_MSR_CTS)
1188 break;
1189
1190 udelay(1);
1191 }
1192 }
1193}
1194
1195#ifdef CONFIG_CONSOLE_POLL
1196
1197static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1198{
1199 struct uart_omap_port *up = to_uart_omap_port(port);
1200
1201 pm_runtime_get_sync(up->dev);
1202 wait_for_xmitr(up);
1203 serial_out(up, UART_TX, ch);
1204 pm_runtime_mark_last_busy(up->dev);
1205 pm_runtime_put_autosuspend(up->dev);
1206}
1207
1208static int serial_omap_poll_get_char(struct uart_port *port)
1209{
1210 struct uart_omap_port *up = to_uart_omap_port(port);
1211 unsigned int status;
1212
1213 pm_runtime_get_sync(up->dev);
1214 status = serial_in(up, UART_LSR);
1215 if (!(status & UART_LSR_DR)) {
1216 status = NO_POLL_CHAR;
1217 goto out;
1218 }
1219
1220 status = serial_in(up, UART_RX);
1221
1222out:
1223 pm_runtime_mark_last_busy(up->dev);
1224 pm_runtime_put_autosuspend(up->dev);
1225
1226 return status;
1227}
1228
1229#endif /* CONFIG_CONSOLE_POLL */
1230
1231#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1232
1233#ifdef CONFIG_SERIAL_EARLYCON
1234static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1235{
1236 offset <<= port->regshift;
1237 return readw(port->membase + offset);
1238}
1239
1240static void omap_serial_early_out(struct uart_port *port, int offset,
1241 int value)
1242{
1243 offset <<= port->regshift;
1244 writew(value, port->membase + offset);
1245}
1246
1247static void omap_serial_early_putc(struct uart_port *port, int c)
1248{
1249 unsigned int status;
1250
1251 for (;;) {
1252 status = omap_serial_early_in(port, UART_LSR);
1253 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1254 break;
1255 cpu_relax();
1256 }
1257 omap_serial_early_out(port, UART_TX, c);
1258}
1259
1260static void early_omap_serial_write(struct console *console, const char *s,
1261 unsigned int count)
1262{
1263 struct earlycon_device *device = console->data;
1264 struct uart_port *port = &device->port;
1265
1266 uart_console_write(port, s, count, omap_serial_early_putc);
1267}
1268
1269static int __init early_omap_serial_setup(struct earlycon_device *device,
1270 const char *options)
1271{
1272 struct uart_port *port = &device->port;
1273
1274 if (!(device->port.membase || device->port.iobase))
1275 return -ENODEV;
1276
1277 port->regshift = 2;
1278 device->con->write = early_omap_serial_write;
1279 return 0;
1280}
1281
1282OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1283OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1284OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1285#endif /* CONFIG_SERIAL_EARLYCON */
1286
1287static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1288
1289static struct uart_driver serial_omap_reg;
1290
1291static void serial_omap_console_putchar(struct uart_port *port, int ch)
1292{
1293 struct uart_omap_port *up = to_uart_omap_port(port);
1294
1295 wait_for_xmitr(up);
1296 serial_out(up, UART_TX, ch);
1297}
1298
1299static void
1300serial_omap_console_write(struct console *co, const char *s,
1301 unsigned int count)
1302{
1303 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1304 unsigned long flags;
1305 unsigned int ier;
1306 int locked = 1;
1307
1308 pm_runtime_get_sync(up->dev);
1309
1310 local_irq_save(flags);
1311 if (up->port.sysrq)
1312 locked = 0;
1313 else if (oops_in_progress)
1314 locked = spin_trylock(&up->port.lock);
1315 else
1316 spin_lock(&up->port.lock);
1317
1318 /*
1319 * First save the IER then disable the interrupts
1320 */
1321 ier = serial_in(up, UART_IER);
1322 serial_out(up, UART_IER, 0);
1323
1324 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1325
1326 /*
1327 * Finally, wait for transmitter to become empty
1328 * and restore the IER
1329 */
1330 wait_for_xmitr(up);
1331 serial_out(up, UART_IER, ier);
1332 /*
1333 * The receive handling will happen properly because the
1334 * receive ready bit will still be set; it is not cleared
1335 * on read. However, modem control will not, we must
1336 * call it if we have saved something in the saved flags
1337 * while processing with interrupts off.
1338 */
1339 if (up->msr_saved_flags)
1340 check_modem_status(up);
1341
1342 pm_runtime_mark_last_busy(up->dev);
1343 pm_runtime_put_autosuspend(up->dev);
1344 if (locked)
1345 spin_unlock(&up->port.lock);
1346 local_irq_restore(flags);
1347}
1348
1349static int __init
1350serial_omap_console_setup(struct console *co, char *options)
1351{
1352 struct uart_omap_port *up;
1353 int baud = 115200;
1354 int bits = 8;
1355 int parity = 'n';
1356 int flow = 'n';
1357
1358 if (serial_omap_console_ports[co->index] == NULL)
1359 return -ENODEV;
1360 up = serial_omap_console_ports[co->index];
1361
1362 if (options)
1363 uart_parse_options(options, &baud, &parity, &bits, &flow);
1364
1365 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1366}
1367
1368static struct console serial_omap_console = {
1369 .name = OMAP_SERIAL_NAME,
1370 .write = serial_omap_console_write,
1371 .device = uart_console_device,
1372 .setup = serial_omap_console_setup,
1373 .flags = CON_PRINTBUFFER,
1374 .index = -1,
1375 .data = &serial_omap_reg,
1376};
1377
1378static void serial_omap_add_console_port(struct uart_omap_port *up)
1379{
1380 serial_omap_console_ports[up->port.line] = up;
1381}
1382
1383#define OMAP_CONSOLE (&serial_omap_console)
1384
1385#else
1386
1387#define OMAP_CONSOLE NULL
1388
1389static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1390{}
1391
1392#endif
1393
1394/* Enable or disable the rs485 support */
1395static int
1396serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1397{
1398 struct uart_omap_port *up = to_uart_omap_port(port);
1399 unsigned int mode;
1400 int val;
1401
1402 pm_runtime_get_sync(up->dev);
1403
1404 /* Disable interrupts from this port */
1405 mode = up->ier;
1406 up->ier = 0;
1407 serial_out(up, UART_IER, 0);
1408
1409 /* Clamp the delays to [0, 100ms] */
1410 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1411 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1412
1413 /* store new config */
1414 port->rs485 = *rs485;
1415
1416 /*
1417 * Just as a precaution, only allow rs485
1418 * to be enabled if the gpio pin is valid
1419 */
1420 if (gpio_is_valid(up->rts_gpio)) {
1421 /* enable / disable rts */
1422 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1423 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1424 val = (port->rs485.flags & val) ? 1 : 0;
1425 gpio_set_value(up->rts_gpio, val);
1426 } else
1427 port->rs485.flags &= ~SER_RS485_ENABLED;
1428
1429 /* Enable interrupts */
1430 up->ier = mode;
1431 serial_out(up, UART_IER, up->ier);
1432
1433 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1434 * TX FIFO is below the trigger level.
1435 */
1436 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1437 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1438 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1439 serial_out(up, UART_OMAP_SCR, up->scr);
1440 }
1441
1442 pm_runtime_mark_last_busy(up->dev);
1443 pm_runtime_put_autosuspend(up->dev);
1444
1445 return 0;
1446}
1447
1448static const struct uart_ops serial_omap_pops = {
1449 .tx_empty = serial_omap_tx_empty,
1450 .set_mctrl = serial_omap_set_mctrl,
1451 .get_mctrl = serial_omap_get_mctrl,
1452 .stop_tx = serial_omap_stop_tx,
1453 .start_tx = serial_omap_start_tx,
1454 .throttle = serial_omap_throttle,
1455 .unthrottle = serial_omap_unthrottle,
1456 .stop_rx = serial_omap_stop_rx,
1457 .enable_ms = serial_omap_enable_ms,
1458 .break_ctl = serial_omap_break_ctl,
1459 .startup = serial_omap_startup,
1460 .shutdown = serial_omap_shutdown,
1461 .set_termios = serial_omap_set_termios,
1462 .pm = serial_omap_pm,
1463 .type = serial_omap_type,
1464 .release_port = serial_omap_release_port,
1465 .request_port = serial_omap_request_port,
1466 .config_port = serial_omap_config_port,
1467 .verify_port = serial_omap_verify_port,
1468#ifdef CONFIG_CONSOLE_POLL
1469 .poll_put_char = serial_omap_poll_put_char,
1470 .poll_get_char = serial_omap_poll_get_char,
1471#endif
1472};
1473
1474static struct uart_driver serial_omap_reg = {
1475 .owner = THIS_MODULE,
1476 .driver_name = "OMAP-SERIAL",
1477 .dev_name = OMAP_SERIAL_NAME,
1478 .nr = OMAP_MAX_HSUART_PORTS,
1479 .cons = OMAP_CONSOLE,
1480};
1481
1482#ifdef CONFIG_PM_SLEEP
1483static int serial_omap_prepare(struct device *dev)
1484{
1485 struct uart_omap_port *up = dev_get_drvdata(dev);
1486
1487 up->is_suspending = true;
1488
1489 return 0;
1490}
1491
1492static void serial_omap_complete(struct device *dev)
1493{
1494 struct uart_omap_port *up = dev_get_drvdata(dev);
1495
1496 up->is_suspending = false;
1497}
1498
1499static int serial_omap_suspend(struct device *dev)
1500{
1501 struct uart_omap_port *up = dev_get_drvdata(dev);
1502
1503 uart_suspend_port(&serial_omap_reg, &up->port);
1504 flush_work(&up->qos_work);
1505
1506 if (device_may_wakeup(dev))
1507 serial_omap_enable_wakeup(up, true);
1508 else
1509 serial_omap_enable_wakeup(up, false);
1510
1511 return 0;
1512}
1513
1514static int serial_omap_resume(struct device *dev)
1515{
1516 struct uart_omap_port *up = dev_get_drvdata(dev);
1517
1518 if (device_may_wakeup(dev))
1519 serial_omap_enable_wakeup(up, false);
1520
1521 uart_resume_port(&serial_omap_reg, &up->port);
1522
1523 return 0;
1524}
1525#else
1526#define serial_omap_prepare NULL
1527#define serial_omap_complete NULL
1528#endif /* CONFIG_PM_SLEEP */
1529
1530static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1531{
1532 u32 mvr, scheme;
1533 u16 revision, major, minor;
1534
1535 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1536
1537 /* Check revision register scheme */
1538 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1539
1540 switch (scheme) {
1541 case 0: /* Legacy Scheme: OMAP2/3 */
1542 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1543 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1544 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1545 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1546 break;
1547 case 1:
1548 /* New Scheme: OMAP4+ */
1549 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1550 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1551 OMAP_UART_MVR_MAJ_SHIFT;
1552 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1553 break;
1554 default:
1555 dev_warn(up->dev,
1556 "Unknown %s revision, defaulting to highest\n",
1557 up->name);
1558 /* highest possible revision */
1559 major = 0xff;
1560 minor = 0xff;
1561 }
1562
1563 /* normalize revision for the driver */
1564 revision = UART_BUILD_REVISION(major, minor);
1565
1566 switch (revision) {
1567 case OMAP_UART_REV_46:
1568 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1569 UART_ERRATA_i291_DMA_FORCEIDLE);
1570 break;
1571 case OMAP_UART_REV_52:
1572 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1573 UART_ERRATA_i291_DMA_FORCEIDLE);
1574 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1575 break;
1576 case OMAP_UART_REV_63:
1577 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1578 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1579 break;
1580 default:
1581 break;
1582 }
1583}
1584
1585static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1586{
1587 struct omap_uart_port_info *omap_up_info;
1588
1589 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1590 if (!omap_up_info)
1591 return NULL; /* out of memory */
1592
1593 of_property_read_u32(dev->of_node, "clock-frequency",
1594 &omap_up_info->uartclk);
1595
1596 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1597
1598 return omap_up_info;
1599}
1600
1601static int serial_omap_probe_rs485(struct uart_omap_port *up,
1602 struct device_node *np)
1603{
1604 struct serial_rs485 *rs485conf = &up->port.rs485;
1605 int ret;
1606
1607 rs485conf->flags = 0;
1608 up->rts_gpio = -EINVAL;
1609
1610 if (!np)
1611 return 0;
1612
1613 uart_get_rs485_mode(up->dev, rs485conf);
1614
1615 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1616 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1617 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1618 } else {
1619 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1620 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1621 }
1622
1623 /* check for tx enable gpio */
1624 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
1625 if (gpio_is_valid(up->rts_gpio)) {
1626 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1627 if (ret < 0)
1628 return ret;
1629 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
1630 ret = gpio_direction_output(up->rts_gpio, ret);
1631 if (ret < 0)
1632 return ret;
1633 } else if (up->rts_gpio == -EPROBE_DEFER) {
1634 return -EPROBE_DEFER;
1635 } else {
1636 up->rts_gpio = -EINVAL;
1637 }
1638
1639 return 0;
1640}
1641
1642static int serial_omap_probe(struct platform_device *pdev)
1643{
1644 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1645 struct uart_omap_port *up;
1646 struct resource *mem;
1647 void __iomem *base;
1648 int uartirq = 0;
1649 int wakeirq = 0;
1650 int ret;
1651
1652 /* The optional wakeirq may be specified in the board dts file */
1653 if (pdev->dev.of_node) {
1654 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1655 if (!uartirq)
1656 return -EPROBE_DEFER;
1657 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1658 omap_up_info = of_get_uart_port_info(&pdev->dev);
1659 pdev->dev.platform_data = omap_up_info;
1660 } else {
1661 uartirq = platform_get_irq(pdev, 0);
1662 if (uartirq < 0)
1663 return -EPROBE_DEFER;
1664 }
1665
1666 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1667 if (!up)
1668 return -ENOMEM;
1669
1670 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1671 base = devm_ioremap_resource(&pdev->dev, mem);
1672 if (IS_ERR(base))
1673 return PTR_ERR(base);
1674
1675 up->dev = &pdev->dev;
1676 up->port.dev = &pdev->dev;
1677 up->port.type = PORT_OMAP;
1678 up->port.iotype = UPIO_MEM;
1679 up->port.irq = uartirq;
1680 up->port.regshift = 2;
1681 up->port.fifosize = 64;
1682 up->port.ops = &serial_omap_pops;
1683
1684 if (pdev->dev.of_node)
1685 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1686 else
1687 ret = pdev->id;
1688
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691 ret);
1692 goto err_port_line;
1693 }
1694 up->port.line = ret;
1695
1696 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1697 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1698 OMAP_MAX_HSUART_PORTS);
1699 ret = -ENXIO;
1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1708 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1725 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1727 pm_qos_add_request(&up->pm_qos_request,
1728 PM_QOS_CPU_DMA_LATENCY, up->latency);
1729 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1730
1731 platform_set_drvdata(pdev, up);
1732 if (omap_up_info->autosuspend_timeout == 0)
1733 omap_up_info->autosuspend_timeout = -1;
1734
1735 device_init_wakeup(up->dev, true);
1736 pm_runtime_use_autosuspend(&pdev->dev);
1737 pm_runtime_set_autosuspend_delay(&pdev->dev,
1738 omap_up_info->autosuspend_timeout);
1739
1740 pm_runtime_irq_safe(&pdev->dev);
1741 pm_runtime_enable(&pdev->dev);
1742
1743 pm_runtime_get_sync(&pdev->dev);
1744
1745 omap_serial_fill_features_erratas(up);
1746
1747 ui[up->port.line] = up;
1748 serial_omap_add_console_port(up);
1749
1750 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1751 if (ret != 0)
1752 goto err_add_port;
1753
1754 pm_runtime_mark_last_busy(up->dev);
1755 pm_runtime_put_autosuspend(up->dev);
1756 return 0;
1757
1758err_add_port:
1759 pm_runtime_dont_use_autosuspend(&pdev->dev);
1760 pm_runtime_put_sync(&pdev->dev);
1761 pm_runtime_disable(&pdev->dev);
1762 pm_qos_remove_request(&up->pm_qos_request);
1763 device_init_wakeup(up->dev, false);
1764err_rs485:
1765err_port_line:
1766 return ret;
1767}
1768
1769static int serial_omap_remove(struct platform_device *dev)
1770{
1771 struct uart_omap_port *up = platform_get_drvdata(dev);
1772
1773 pm_runtime_get_sync(up->dev);
1774
1775 uart_remove_one_port(&serial_omap_reg, &up->port);
1776
1777 pm_runtime_dont_use_autosuspend(up->dev);
1778 pm_runtime_put_sync(up->dev);
1779 pm_runtime_disable(up->dev);
1780 pm_qos_remove_request(&up->pm_qos_request);
1781 device_init_wakeup(&dev->dev, false);
1782
1783 return 0;
1784}
1785
1786/*
1787 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1788 * The access to uart register after MDR1 Access
1789 * causes UART to corrupt data.
1790 *
1791 * Need a delay =
1792 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1793 * give 10 times as much
1794 */
1795static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1796{
1797 u8 timeout = 255;
1798
1799 serial_out(up, UART_OMAP_MDR1, mdr1);
1800 udelay(2);
1801 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1802 UART_FCR_CLEAR_RCVR);
1803 /*
1804 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1805 * TX_FIFO_E bit is 1.
1806 */
1807 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1808 (UART_LSR_THRE | UART_LSR_DR))) {
1809 timeout--;
1810 if (!timeout) {
1811 /* Should *never* happen. we warn and carry on */
1812 dev_crit(up->dev, "Errata i202: timedout %x\n",
1813 serial_in(up, UART_LSR));
1814 break;
1815 }
1816 udelay(1);
1817 }
1818}
1819
1820#ifdef CONFIG_PM
1821static void serial_omap_restore_context(struct uart_omap_port *up)
1822{
1823 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1824 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1825 else
1826 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1827
1828 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1829 serial_out(up, UART_EFR, UART_EFR_ECB);
1830 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1831 serial_out(up, UART_IER, 0x0);
1832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833 serial_out(up, UART_DLL, up->dll);
1834 serial_out(up, UART_DLM, up->dlh);
1835 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1836 serial_out(up, UART_IER, up->ier);
1837 serial_out(up, UART_FCR, up->fcr);
1838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1839 serial_out(up, UART_MCR, up->mcr);
1840 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1841 serial_out(up, UART_OMAP_SCR, up->scr);
1842 serial_out(up, UART_EFR, up->efr);
1843 serial_out(up, UART_LCR, up->lcr);
1844 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1845 serial_omap_mdr1_errataset(up, up->mdr1);
1846 else
1847 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1848 serial_out(up, UART_OMAP_WER, up->wer);
1849}
1850
1851static int serial_omap_runtime_suspend(struct device *dev)
1852{
1853 struct uart_omap_port *up = dev_get_drvdata(dev);
1854
1855 if (!up)
1856 return -EINVAL;
1857
1858 /*
1859 * When using 'no_console_suspend', the console UART must not be
1860 * suspended. Since driver suspend is managed by runtime suspend,
1861 * preventing runtime suspend (by returning error) will keep device
1862 * active during suspend.
1863 */
1864 if (up->is_suspending && !console_suspend_enabled &&
1865 uart_console(&up->port))
1866 return -EBUSY;
1867
1868 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1869
1870 serial_omap_enable_wakeup(up, true);
1871
1872 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1873 schedule_work(&up->qos_work);
1874
1875 return 0;
1876}
1877
1878static int serial_omap_runtime_resume(struct device *dev)
1879{
1880 struct uart_omap_port *up = dev_get_drvdata(dev);
1881
1882 int loss_cnt = serial_omap_get_context_loss_count(up);
1883
1884 serial_omap_enable_wakeup(up, false);
1885
1886 if (loss_cnt < 0) {
1887 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1888 loss_cnt);
1889 serial_omap_restore_context(up);
1890 } else if (up->context_loss_cnt != loss_cnt) {
1891 serial_omap_restore_context(up);
1892 }
1893 up->latency = up->calc_latency;
1894 schedule_work(&up->qos_work);
1895
1896 return 0;
1897}
1898#endif
1899
1900static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1901 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1902 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1903 serial_omap_runtime_resume, NULL)
1904 .prepare = serial_omap_prepare,
1905 .complete = serial_omap_complete,
1906};
1907
1908#if defined(CONFIG_OF)
1909static const struct of_device_id omap_serial_of_match[] = {
1910 { .compatible = "ti,omap2-uart" },
1911 { .compatible = "ti,omap3-uart" },
1912 { .compatible = "ti,omap4-uart" },
1913 {},
1914};
1915MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1916#endif
1917
1918static struct platform_driver serial_omap_driver = {
1919 .probe = serial_omap_probe,
1920 .remove = serial_omap_remove,
1921 .driver = {
1922 .name = OMAP_SERIAL_DRIVER_NAME,
1923 .pm = &serial_omap_dev_pm_ops,
1924 .of_match_table = of_match_ptr(omap_serial_of_match),
1925 },
1926};
1927
1928static int __init serial_omap_init(void)
1929{
1930 int ret;
1931
1932 ret = uart_register_driver(&serial_omap_reg);
1933 if (ret != 0)
1934 return ret;
1935 ret = platform_driver_register(&serial_omap_driver);
1936 if (ret != 0)
1937 uart_unregister_driver(&serial_omap_reg);
1938 return ret;
1939}
1940
1941static void __exit serial_omap_exit(void)
1942{
1943 platform_driver_unregister(&serial_omap_driver);
1944 uart_unregister_driver(&serial_omap_reg);
1945}
1946
1947module_init(serial_omap_init);
1948module_exit(serial_omap_exit);
1949
1950MODULE_DESCRIPTION("OMAP High Speed UART driver");
1951MODULE_LICENSE("GPL");
1952MODULE_AUTHOR("Texas Instruments Inc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/console.h>
22#include <linux/serial_reg.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/gpio/consumer.h>
37#include <linux/platform_data/serial-omap.h>
38
39#define OMAP_MAX_HSUART_PORTS 10
40
41#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
42
43#define OMAP_UART_REV_42 0x0402
44#define OMAP_UART_REV_46 0x0406
45#define OMAP_UART_REV_52 0x0502
46#define OMAP_UART_REV_63 0x0603
47
48#define OMAP_UART_TX_WAKEUP_EN BIT(7)
49
50/* Feature flags */
51#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
52
53#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
54#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
55
56#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
57
58/* SCR register bitmasks */
59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
61#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
62
63/* FCR register bitmasks */
64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
66
67/* MVR register bitmasks */
68#define OMAP_UART_MVR_SCHEME_SHIFT 30
69
70#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
72#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
73
74#define OMAP_UART_MVR_MAJ_MASK 0x700
75#define OMAP_UART_MVR_MAJ_SHIFT 8
76#define OMAP_UART_MVR_MIN_MASK 0x3f
77
78#define OMAP_UART_DMA_CH_FREE -1
79
80#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
81#define OMAP_MODE13X_SPEED 230400
82
83/* WER = 0x7F
84 * Enable module level wakeup in WER reg
85 */
86#define OMAP_UART_WER_MOD_WKUP 0x7F
87
88/* Enable XON/XOFF flow control on output */
89#define OMAP_UART_SW_TX 0x08
90
91/* Enable XON/XOFF flow control on input */
92#define OMAP_UART_SW_RX 0x02
93
94#define OMAP_UART_SW_CLR 0xF0
95
96#define OMAP_UART_TCR_TRIG 0x0F
97
98struct uart_omap_dma {
99 u8 uart_dma_tx;
100 u8 uart_dma_rx;
101 int rx_dma_channel;
102 int tx_dma_channel;
103 dma_addr_t rx_buf_dma_phys;
104 dma_addr_t tx_buf_dma_phys;
105 unsigned int uart_base;
106 /*
107 * Buffer for rx dma. It is not required for tx because the buffer
108 * comes from port structure.
109 */
110 unsigned char *rx_buf;
111 unsigned int prev_rx_dma_pos;
112 int tx_buf_size;
113 int tx_dma_used;
114 int rx_dma_used;
115 spinlock_t tx_lock;
116 spinlock_t rx_lock;
117 /* timer to poll activity on rx dma */
118 struct timer_list rx_timer;
119 unsigned int rx_buf_size;
120 unsigned int rx_poll_rate;
121 unsigned int rx_timeout;
122};
123
124struct uart_omap_port {
125 struct uart_port port;
126 struct uart_omap_dma uart_dma;
127 struct device *dev;
128 int wakeirq;
129
130 unsigned char ier;
131 unsigned char lcr;
132 unsigned char mcr;
133 unsigned char fcr;
134 unsigned char efr;
135 unsigned char dll;
136 unsigned char dlh;
137 unsigned char mdr1;
138 unsigned char scr;
139 unsigned char wer;
140
141 int use_dma;
142 /*
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read, but the bits will not
145 * be immediately processed.
146 */
147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
149 char name[20];
150 unsigned long port_activity;
151 int context_loss_cnt;
152 u32 errata;
153 u32 features;
154
155 struct gpio_desc *rts_gpiod;
156
157 struct pm_qos_request pm_qos_request;
158 u32 latency;
159 u32 calc_latency;
160 struct work_struct qos_work;
161 bool is_suspending;
162};
163
164#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
165
166static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
167
168/* Forward declaration of functions */
169static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
170
171static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
172{
173 offset <<= up->port.regshift;
174 return readw(up->port.membase + offset);
175}
176
177static inline void serial_out(struct uart_omap_port *up, int offset, int value)
178{
179 offset <<= up->port.regshift;
180 writew(value, up->port.membase + offset);
181}
182
183static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
184{
185 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
186 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
187 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
188 serial_out(up, UART_FCR, 0);
189}
190
191#ifdef CONFIG_PM
192static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
193{
194 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
195
196 if (!pdata || !pdata->get_context_loss_count)
197 return -EINVAL;
198
199 return pdata->get_context_loss_count(up->dev);
200}
201
202/* REVISIT: Remove this when omap3 boots in device tree only mode */
203static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
204{
205 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
206
207 if (!pdata || !pdata->enable_wakeup)
208 return;
209
210 pdata->enable_wakeup(up->dev, enable);
211}
212#endif /* CONFIG_PM */
213
214/*
215 * Calculate the absolute difference between the desired and actual baud
216 * rate for the given mode.
217 */
218static inline int calculate_baud_abs_diff(struct uart_port *port,
219 unsigned int baud, unsigned int mode)
220{
221 unsigned int n = port->uartclk / (mode * baud);
222 int abs_diff;
223
224 if (n == 0)
225 n = 1;
226
227 abs_diff = baud - (port->uartclk / (mode * n));
228 if (abs_diff < 0)
229 abs_diff = -abs_diff;
230
231 return abs_diff;
232}
233
234/*
235 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
236 * @port: uart port info
237 * @baud: baudrate for which mode needs to be determined
238 *
239 * Returns true if baud rate is MODE16X and false if MODE13X
240 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
241 * and Error Rates" determines modes not for all common baud rates.
242 * E.g. for 1000000 baud rate mode must be 16x, but according to that
243 * table it's determined as 13x.
244 */
245static bool
246serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
247{
248 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
249 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
250
251 return (abs_diff_13 >= abs_diff_16);
252}
253
254/*
255 * serial_omap_get_divisor - calculate divisor value
256 * @port: uart port info
257 * @baud: baudrate for which divisor needs to be calculated.
258 */
259static unsigned int
260serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
261{
262 unsigned int mode;
263
264 if (!serial_omap_baud_is_mode16(port, baud))
265 mode = 13;
266 else
267 mode = 16;
268 return port->uartclk/(mode * baud);
269}
270
271static void serial_omap_enable_ms(struct uart_port *port)
272{
273 struct uart_omap_port *up = to_uart_omap_port(port);
274
275 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
276
277 pm_runtime_get_sync(up->dev);
278 up->ier |= UART_IER_MSI;
279 serial_out(up, UART_IER, up->ier);
280 pm_runtime_mark_last_busy(up->dev);
281 pm_runtime_put_autosuspend(up->dev);
282}
283
284static void serial_omap_stop_tx(struct uart_port *port)
285{
286 struct uart_omap_port *up = to_uart_omap_port(port);
287 int res;
288
289 pm_runtime_get_sync(up->dev);
290
291 /* Handle RS-485 */
292 if (port->rs485.flags & SER_RS485_ENABLED) {
293 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
294 /* THR interrupt is fired when both TX FIFO and TX
295 * shift register are empty. This means there's nothing
296 * left to transmit now, so make sure the THR interrupt
297 * is fired when TX FIFO is below the trigger level,
298 * disable THR interrupts and toggle the RS-485 GPIO
299 * data direction pin if needed.
300 */
301 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
302 serial_out(up, UART_OMAP_SCR, up->scr);
303 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
304 1 : 0;
305 if (gpiod_get_value(up->rts_gpiod) != res) {
306 if (port->rs485.delay_rts_after_send > 0)
307 mdelay(
308 port->rs485.delay_rts_after_send);
309 gpiod_set_value(up->rts_gpiod, res);
310 }
311 } else {
312 /* We're asked to stop, but there's still stuff in the
313 * UART FIFO, so make sure the THR interrupt is fired
314 * when both TX FIFO and TX shift register are empty.
315 * The next THR interrupt (if no transmission is started
316 * in the meantime) will indicate the end of a
317 * transmission. Therefore we _don't_ disable THR
318 * interrupts in this situation.
319 */
320 up->scr |= OMAP_UART_SCR_TX_EMPTY;
321 serial_out(up, UART_OMAP_SCR, up->scr);
322 return;
323 }
324 }
325
326 if (up->ier & UART_IER_THRI) {
327 up->ier &= ~UART_IER_THRI;
328 serial_out(up, UART_IER, up->ier);
329 }
330
331 if ((port->rs485.flags & SER_RS485_ENABLED) &&
332 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
333 /*
334 * Empty the RX FIFO, we are not interested in anything
335 * received during the half-duplex transmission.
336 */
337 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
338 /* Re-enable RX interrupts */
339 up->ier |= UART_IER_RLSI | UART_IER_RDI;
340 up->port.read_status_mask |= UART_LSR_DR;
341 serial_out(up, UART_IER, up->ier);
342 }
343
344 pm_runtime_mark_last_busy(up->dev);
345 pm_runtime_put_autosuspend(up->dev);
346}
347
348static void serial_omap_stop_rx(struct uart_port *port)
349{
350 struct uart_omap_port *up = to_uart_omap_port(port);
351
352 pm_runtime_get_sync(up->dev);
353 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
354 up->port.read_status_mask &= ~UART_LSR_DR;
355 serial_out(up, UART_IER, up->ier);
356 pm_runtime_mark_last_busy(up->dev);
357 pm_runtime_put_autosuspend(up->dev);
358}
359
360static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
361{
362 struct circ_buf *xmit = &up->port.state->xmit;
363 int count;
364
365 if (up->port.x_char) {
366 serial_out(up, UART_TX, up->port.x_char);
367 up->port.icount.tx++;
368 up->port.x_char = 0;
369 return;
370 }
371 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
372 serial_omap_stop_tx(&up->port);
373 return;
374 }
375 count = up->port.fifosize / 4;
376 do {
377 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
379 up->port.icount.tx++;
380 if (uart_circ_empty(xmit))
381 break;
382 } while (--count > 0);
383
384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
385 uart_write_wakeup(&up->port);
386
387 if (uart_circ_empty(xmit))
388 serial_omap_stop_tx(&up->port);
389}
390
391static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
392{
393 if (!(up->ier & UART_IER_THRI)) {
394 up->ier |= UART_IER_THRI;
395 serial_out(up, UART_IER, up->ier);
396 }
397}
398
399static void serial_omap_start_tx(struct uart_port *port)
400{
401 struct uart_omap_port *up = to_uart_omap_port(port);
402 int res;
403
404 pm_runtime_get_sync(up->dev);
405
406 /* Handle RS-485 */
407 if (port->rs485.flags & SER_RS485_ENABLED) {
408 /* Fire THR interrupts when FIFO is below trigger level */
409 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
410 serial_out(up, UART_OMAP_SCR, up->scr);
411
412 /* if rts not already enabled */
413 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
414 if (gpiod_get_value(up->rts_gpiod) != res) {
415 gpiod_set_value(up->rts_gpiod, res);
416 if (port->rs485.delay_rts_before_send > 0)
417 mdelay(port->rs485.delay_rts_before_send);
418 }
419 }
420
421 if ((port->rs485.flags & SER_RS485_ENABLED) &&
422 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
423 serial_omap_stop_rx(port);
424
425 serial_omap_enable_ier_thri(up);
426 pm_runtime_mark_last_busy(up->dev);
427 pm_runtime_put_autosuspend(up->dev);
428}
429
430static void serial_omap_throttle(struct uart_port *port)
431{
432 struct uart_omap_port *up = to_uart_omap_port(port);
433 unsigned long flags;
434
435 pm_runtime_get_sync(up->dev);
436 spin_lock_irqsave(&up->port.lock, flags);
437 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
438 serial_out(up, UART_IER, up->ier);
439 spin_unlock_irqrestore(&up->port.lock, flags);
440 pm_runtime_mark_last_busy(up->dev);
441 pm_runtime_put_autosuspend(up->dev);
442}
443
444static void serial_omap_unthrottle(struct uart_port *port)
445{
446 struct uart_omap_port *up = to_uart_omap_port(port);
447 unsigned long flags;
448
449 pm_runtime_get_sync(up->dev);
450 spin_lock_irqsave(&up->port.lock, flags);
451 up->ier |= UART_IER_RLSI | UART_IER_RDI;
452 serial_out(up, UART_IER, up->ier);
453 spin_unlock_irqrestore(&up->port.lock, flags);
454 pm_runtime_mark_last_busy(up->dev);
455 pm_runtime_put_autosuspend(up->dev);
456}
457
458static unsigned int check_modem_status(struct uart_omap_port *up)
459{
460 unsigned int status;
461
462 status = serial_in(up, UART_MSR);
463 status |= up->msr_saved_flags;
464 up->msr_saved_flags = 0;
465 if ((status & UART_MSR_ANY_DELTA) == 0)
466 return status;
467
468 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
469 up->port.state != NULL) {
470 if (status & UART_MSR_TERI)
471 up->port.icount.rng++;
472 if (status & UART_MSR_DDSR)
473 up->port.icount.dsr++;
474 if (status & UART_MSR_DDCD)
475 uart_handle_dcd_change
476 (&up->port, status & UART_MSR_DCD);
477 if (status & UART_MSR_DCTS)
478 uart_handle_cts_change
479 (&up->port, status & UART_MSR_CTS);
480 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
481 }
482
483 return status;
484}
485
486static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
487{
488 unsigned int flag;
489
490 /*
491 * Read one data character out to avoid stalling the receiver according
492 * to the table 23-246 of the omap4 TRM.
493 */
494 if (likely(lsr & UART_LSR_DR))
495 serial_in(up, UART_RX);
496
497 up->port.icount.rx++;
498 flag = TTY_NORMAL;
499
500 if (lsr & UART_LSR_BI) {
501 flag = TTY_BREAK;
502 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
503 up->port.icount.brk++;
504 /*
505 * We do the SysRQ and SAK checking
506 * here because otherwise the break
507 * may get masked by ignore_status_mask
508 * or read_status_mask.
509 */
510 if (uart_handle_break(&up->port))
511 return;
512
513 }
514
515 if (lsr & UART_LSR_PE) {
516 flag = TTY_PARITY;
517 up->port.icount.parity++;
518 }
519
520 if (lsr & UART_LSR_FE) {
521 flag = TTY_FRAME;
522 up->port.icount.frame++;
523 }
524
525 if (lsr & UART_LSR_OE)
526 up->port.icount.overrun++;
527
528#ifdef CONFIG_SERIAL_OMAP_CONSOLE
529 if (up->port.line == up->port.cons->index) {
530 /* Recover the break flag from console xmit */
531 lsr |= up->lsr_break_flag;
532 }
533#endif
534 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
535}
536
537static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
538{
539 unsigned char ch = 0;
540 unsigned int flag;
541
542 if (!(lsr & UART_LSR_DR))
543 return;
544
545 ch = serial_in(up, UART_RX);
546 flag = TTY_NORMAL;
547 up->port.icount.rx++;
548
549 if (uart_handle_sysrq_char(&up->port, ch))
550 return;
551
552 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
553}
554
555/**
556 * serial_omap_irq() - This handles the interrupt from one port
557 * @irq: uart port irq number
558 * @dev_id: uart port info
559 */
560static irqreturn_t serial_omap_irq(int irq, void *dev_id)
561{
562 struct uart_omap_port *up = dev_id;
563 unsigned int iir, lsr;
564 unsigned int type;
565 irqreturn_t ret = IRQ_NONE;
566 int max_count = 256;
567
568 spin_lock(&up->port.lock);
569 pm_runtime_get_sync(up->dev);
570
571 do {
572 iir = serial_in(up, UART_IIR);
573 if (iir & UART_IIR_NO_INT)
574 break;
575
576 ret = IRQ_HANDLED;
577 lsr = serial_in(up, UART_LSR);
578
579 /* extract IRQ type from IIR register */
580 type = iir & 0x3e;
581
582 switch (type) {
583 case UART_IIR_MSI:
584 check_modem_status(up);
585 break;
586 case UART_IIR_THRI:
587 transmit_chars(up, lsr);
588 break;
589 case UART_IIR_RX_TIMEOUT:
590 case UART_IIR_RDI:
591 serial_omap_rdi(up, lsr);
592 break;
593 case UART_IIR_RLSI:
594 serial_omap_rlsi(up, lsr);
595 break;
596 case UART_IIR_CTS_RTS_DSR:
597 /* simply try again */
598 break;
599 case UART_IIR_XOFF:
600 default:
601 break;
602 }
603 } while (max_count--);
604
605 spin_unlock(&up->port.lock);
606
607 tty_flip_buffer_push(&up->port.state->port);
608
609 pm_runtime_mark_last_busy(up->dev);
610 pm_runtime_put_autosuspend(up->dev);
611 up->port_activity = jiffies;
612
613 return ret;
614}
615
616static unsigned int serial_omap_tx_empty(struct uart_port *port)
617{
618 struct uart_omap_port *up = to_uart_omap_port(port);
619 unsigned long flags = 0;
620 unsigned int ret = 0;
621
622 pm_runtime_get_sync(up->dev);
623 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
624 spin_lock_irqsave(&up->port.lock, flags);
625 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
626 spin_unlock_irqrestore(&up->port.lock, flags);
627 pm_runtime_mark_last_busy(up->dev);
628 pm_runtime_put_autosuspend(up->dev);
629 return ret;
630}
631
632static unsigned int serial_omap_get_mctrl(struct uart_port *port)
633{
634 struct uart_omap_port *up = to_uart_omap_port(port);
635 unsigned int status;
636 unsigned int ret = 0;
637
638 pm_runtime_get_sync(up->dev);
639 status = check_modem_status(up);
640 pm_runtime_mark_last_busy(up->dev);
641 pm_runtime_put_autosuspend(up->dev);
642
643 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
644
645 if (status & UART_MSR_DCD)
646 ret |= TIOCM_CAR;
647 if (status & UART_MSR_RI)
648 ret |= TIOCM_RNG;
649 if (status & UART_MSR_DSR)
650 ret |= TIOCM_DSR;
651 if (status & UART_MSR_CTS)
652 ret |= TIOCM_CTS;
653 return ret;
654}
655
656static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
657{
658 struct uart_omap_port *up = to_uart_omap_port(port);
659 unsigned char mcr = 0, old_mcr, lcr;
660
661 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
662 if (mctrl & TIOCM_RTS)
663 mcr |= UART_MCR_RTS;
664 if (mctrl & TIOCM_DTR)
665 mcr |= UART_MCR_DTR;
666 if (mctrl & TIOCM_OUT1)
667 mcr |= UART_MCR_OUT1;
668 if (mctrl & TIOCM_OUT2)
669 mcr |= UART_MCR_OUT2;
670 if (mctrl & TIOCM_LOOP)
671 mcr |= UART_MCR_LOOP;
672
673 pm_runtime_get_sync(up->dev);
674 old_mcr = serial_in(up, UART_MCR);
675 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
676 UART_MCR_DTR | UART_MCR_RTS);
677 up->mcr = old_mcr | mcr;
678 serial_out(up, UART_MCR, up->mcr);
679
680 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
681 lcr = serial_in(up, UART_LCR);
682 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
683 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
684 up->efr |= UART_EFR_RTS;
685 else
686 up->efr &= ~UART_EFR_RTS;
687 serial_out(up, UART_EFR, up->efr);
688 serial_out(up, UART_LCR, lcr);
689
690 pm_runtime_mark_last_busy(up->dev);
691 pm_runtime_put_autosuspend(up->dev);
692}
693
694static void serial_omap_break_ctl(struct uart_port *port, int break_state)
695{
696 struct uart_omap_port *up = to_uart_omap_port(port);
697 unsigned long flags = 0;
698
699 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
700 pm_runtime_get_sync(up->dev);
701 spin_lock_irqsave(&up->port.lock, flags);
702 if (break_state == -1)
703 up->lcr |= UART_LCR_SBC;
704 else
705 up->lcr &= ~UART_LCR_SBC;
706 serial_out(up, UART_LCR, up->lcr);
707 spin_unlock_irqrestore(&up->port.lock, flags);
708 pm_runtime_mark_last_busy(up->dev);
709 pm_runtime_put_autosuspend(up->dev);
710}
711
712static int serial_omap_startup(struct uart_port *port)
713{
714 struct uart_omap_port *up = to_uart_omap_port(port);
715 unsigned long flags = 0;
716 int retval;
717
718 /*
719 * Allocate the IRQ
720 */
721 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
722 up->name, up);
723 if (retval)
724 return retval;
725
726 /* Optional wake-up IRQ */
727 if (up->wakeirq) {
728 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
729 if (retval) {
730 free_irq(up->port.irq, up);
731 return retval;
732 }
733 }
734
735 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
736
737 pm_runtime_get_sync(up->dev);
738 /*
739 * Clear the FIFO buffers and disable them.
740 * (they will be reenabled in set_termios())
741 */
742 serial_omap_clear_fifos(up);
743
744 /*
745 * Clear the interrupt registers.
746 */
747 (void) serial_in(up, UART_LSR);
748 if (serial_in(up, UART_LSR) & UART_LSR_DR)
749 (void) serial_in(up, UART_RX);
750 (void) serial_in(up, UART_IIR);
751 (void) serial_in(up, UART_MSR);
752
753 /*
754 * Now, initialize the UART
755 */
756 serial_out(up, UART_LCR, UART_LCR_WLEN8);
757 spin_lock_irqsave(&up->port.lock, flags);
758 /*
759 * Most PC uarts need OUT2 raised to enable interrupts.
760 */
761 up->port.mctrl |= TIOCM_OUT2;
762 serial_omap_set_mctrl(&up->port, up->port.mctrl);
763 spin_unlock_irqrestore(&up->port.lock, flags);
764
765 up->msr_saved_flags = 0;
766 /*
767 * Finally, enable interrupts. Note: Modem status interrupts
768 * are set via set_termios(), which will be occurring imminently
769 * anyway, so we don't enable them here.
770 */
771 up->ier = UART_IER_RLSI | UART_IER_RDI;
772 serial_out(up, UART_IER, up->ier);
773
774 /* Enable module level wake up */
775 up->wer = OMAP_UART_WER_MOD_WKUP;
776 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
777 up->wer |= OMAP_UART_TX_WAKEUP_EN;
778
779 serial_out(up, UART_OMAP_WER, up->wer);
780
781 pm_runtime_mark_last_busy(up->dev);
782 pm_runtime_put_autosuspend(up->dev);
783 up->port_activity = jiffies;
784 return 0;
785}
786
787static void serial_omap_shutdown(struct uart_port *port)
788{
789 struct uart_omap_port *up = to_uart_omap_port(port);
790 unsigned long flags = 0;
791
792 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
793
794 pm_runtime_get_sync(up->dev);
795 /*
796 * Disable interrupts from this port
797 */
798 up->ier = 0;
799 serial_out(up, UART_IER, 0);
800
801 spin_lock_irqsave(&up->port.lock, flags);
802 up->port.mctrl &= ~TIOCM_OUT2;
803 serial_omap_set_mctrl(&up->port, up->port.mctrl);
804 spin_unlock_irqrestore(&up->port.lock, flags);
805
806 /*
807 * Disable break condition and FIFOs
808 */
809 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
810 serial_omap_clear_fifos(up);
811
812 /*
813 * Read data port to reset things, and then free the irq
814 */
815 if (serial_in(up, UART_LSR) & UART_LSR_DR)
816 (void) serial_in(up, UART_RX);
817
818 pm_runtime_mark_last_busy(up->dev);
819 pm_runtime_put_autosuspend(up->dev);
820 free_irq(up->port.irq, up);
821 dev_pm_clear_wake_irq(up->dev);
822}
823
824static void serial_omap_uart_qos_work(struct work_struct *work)
825{
826 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
827 qos_work);
828
829 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
830}
831
832static void
833serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
834 struct ktermios *old)
835{
836 struct uart_omap_port *up = to_uart_omap_port(port);
837 unsigned char cval = 0;
838 unsigned long flags = 0;
839 unsigned int baud, quot;
840
841 switch (termios->c_cflag & CSIZE) {
842 case CS5:
843 cval = UART_LCR_WLEN5;
844 break;
845 case CS6:
846 cval = UART_LCR_WLEN6;
847 break;
848 case CS7:
849 cval = UART_LCR_WLEN7;
850 break;
851 default:
852 case CS8:
853 cval = UART_LCR_WLEN8;
854 break;
855 }
856
857 if (termios->c_cflag & CSTOPB)
858 cval |= UART_LCR_STOP;
859 if (termios->c_cflag & PARENB)
860 cval |= UART_LCR_PARITY;
861 if (!(termios->c_cflag & PARODD))
862 cval |= UART_LCR_EPAR;
863 if (termios->c_cflag & CMSPAR)
864 cval |= UART_LCR_SPAR;
865
866 /*
867 * Ask the core to calculate the divisor for us.
868 */
869
870 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
871 quot = serial_omap_get_divisor(port, baud);
872
873 /* calculate wakeup latency constraint */
874 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
875 up->latency = up->calc_latency;
876 schedule_work(&up->qos_work);
877
878 up->dll = quot & 0xff;
879 up->dlh = quot >> 8;
880 up->mdr1 = UART_OMAP_MDR1_DISABLE;
881
882 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
883 UART_FCR_ENABLE_FIFO;
884
885 /*
886 * Ok, we're now changing the port state. Do it with
887 * interrupts disabled.
888 */
889 pm_runtime_get_sync(up->dev);
890 spin_lock_irqsave(&up->port.lock, flags);
891
892 /*
893 * Update the per-port timeout.
894 */
895 uart_update_timeout(port, termios->c_cflag, baud);
896
897 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
898 if (termios->c_iflag & INPCK)
899 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
900 if (termios->c_iflag & (BRKINT | PARMRK))
901 up->port.read_status_mask |= UART_LSR_BI;
902
903 /*
904 * Characters to ignore
905 */
906 up->port.ignore_status_mask = 0;
907 if (termios->c_iflag & IGNPAR)
908 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
909 if (termios->c_iflag & IGNBRK) {
910 up->port.ignore_status_mask |= UART_LSR_BI;
911 /*
912 * If we're ignoring parity and break indicators,
913 * ignore overruns too (for real raw support).
914 */
915 if (termios->c_iflag & IGNPAR)
916 up->port.ignore_status_mask |= UART_LSR_OE;
917 }
918
919 /*
920 * ignore all characters if CREAD is not set
921 */
922 if ((termios->c_cflag & CREAD) == 0)
923 up->port.ignore_status_mask |= UART_LSR_DR;
924
925 /*
926 * Modem status interrupts
927 */
928 up->ier &= ~UART_IER_MSI;
929 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
930 up->ier |= UART_IER_MSI;
931 serial_out(up, UART_IER, up->ier);
932 serial_out(up, UART_LCR, cval); /* reset DLAB */
933 up->lcr = cval;
934 up->scr = 0;
935
936 /* FIFOs and DMA Settings */
937
938 /* FCR can be changed only when the
939 * baud clock is not running
940 * DLL_REG and DLH_REG set to 0.
941 */
942 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
943 serial_out(up, UART_DLL, 0);
944 serial_out(up, UART_DLM, 0);
945 serial_out(up, UART_LCR, 0);
946
947 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
948
949 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
950 up->efr &= ~UART_EFR_SCD;
951 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
952
953 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
954 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
955 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
956 /* FIFO ENABLE, DMA MODE */
957
958 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
959 /*
960 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
961 * sets Enables the granularity of 1 for TRIGGER RX
962 * level. Along with setting RX FIFO trigger level
963 * to 1 (as noted below, 16 characters) and TLR[3:0]
964 * to zero this will result RX FIFO threshold level
965 * to 1 character, instead of 16 as noted in comment
966 * below.
967 */
968
969 /* Set receive FIFO threshold to 16 characters and
970 * transmit FIFO threshold to 32 spaces
971 */
972 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
973 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
974 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
975 UART_FCR_ENABLE_FIFO;
976
977 serial_out(up, UART_FCR, up->fcr);
978 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
979
980 serial_out(up, UART_OMAP_SCR, up->scr);
981
982 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
983 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
984 serial_out(up, UART_MCR, up->mcr);
985 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
986 serial_out(up, UART_EFR, up->efr);
987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
988
989 /* Protocol, Baud Rate, and Interrupt Settings */
990
991 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
992 serial_omap_mdr1_errataset(up, up->mdr1);
993 else
994 serial_out(up, UART_OMAP_MDR1, up->mdr1);
995
996 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
997 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
998
999 serial_out(up, UART_LCR, 0);
1000 serial_out(up, UART_IER, 0);
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1002
1003 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1004 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1005
1006 serial_out(up, UART_LCR, 0);
1007 serial_out(up, UART_IER, up->ier);
1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1009
1010 serial_out(up, UART_EFR, up->efr);
1011 serial_out(up, UART_LCR, cval);
1012
1013 if (!serial_omap_baud_is_mode16(port, baud))
1014 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1015 else
1016 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1017
1018 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1019 serial_omap_mdr1_errataset(up, up->mdr1);
1020 else
1021 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1022
1023 /* Configure flow control */
1024 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1025
1026 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1027 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1028 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1029
1030 /* Enable access to TCR/TLR */
1031 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1032 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1033 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1034
1035 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1036
1037 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1038
1039 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1040 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1041 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1042 up->efr |= UART_EFR_CTS;
1043 } else {
1044 /* Disable AUTORTS and AUTOCTS */
1045 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1046 }
1047
1048 if (up->port.flags & UPF_SOFT_FLOW) {
1049 /* clear SW control mode bits */
1050 up->efr &= OMAP_UART_SW_CLR;
1051
1052 /*
1053 * IXON Flag:
1054 * Enable XON/XOFF flow control on input.
1055 * Receiver compares XON1, XOFF1.
1056 */
1057 if (termios->c_iflag & IXON)
1058 up->efr |= OMAP_UART_SW_RX;
1059
1060 /*
1061 * IXOFF Flag:
1062 * Enable XON/XOFF flow control on output.
1063 * Transmit XON1, XOFF1
1064 */
1065 if (termios->c_iflag & IXOFF) {
1066 up->port.status |= UPSTAT_AUTOXOFF;
1067 up->efr |= OMAP_UART_SW_TX;
1068 }
1069
1070 /*
1071 * IXANY Flag:
1072 * Enable any character to restart output.
1073 * Operation resumes after receiving any
1074 * character after recognition of the XOFF character
1075 */
1076 if (termios->c_iflag & IXANY)
1077 up->mcr |= UART_MCR_XONANY;
1078 else
1079 up->mcr &= ~UART_MCR_XONANY;
1080 }
1081 serial_out(up, UART_MCR, up->mcr);
1082 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1083 serial_out(up, UART_EFR, up->efr);
1084 serial_out(up, UART_LCR, up->lcr);
1085
1086 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1087
1088 spin_unlock_irqrestore(&up->port.lock, flags);
1089 pm_runtime_mark_last_busy(up->dev);
1090 pm_runtime_put_autosuspend(up->dev);
1091 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1092}
1093
1094static void
1095serial_omap_pm(struct uart_port *port, unsigned int state,
1096 unsigned int oldstate)
1097{
1098 struct uart_omap_port *up = to_uart_omap_port(port);
1099 unsigned char efr;
1100
1101 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1102
1103 pm_runtime_get_sync(up->dev);
1104 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1105 efr = serial_in(up, UART_EFR);
1106 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1107 serial_out(up, UART_LCR, 0);
1108
1109 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1110 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111 serial_out(up, UART_EFR, efr);
1112 serial_out(up, UART_LCR, 0);
1113
1114 pm_runtime_mark_last_busy(up->dev);
1115 pm_runtime_put_autosuspend(up->dev);
1116}
1117
1118static void serial_omap_release_port(struct uart_port *port)
1119{
1120 dev_dbg(port->dev, "serial_omap_release_port+\n");
1121}
1122
1123static int serial_omap_request_port(struct uart_port *port)
1124{
1125 dev_dbg(port->dev, "serial_omap_request_port+\n");
1126 return 0;
1127}
1128
1129static void serial_omap_config_port(struct uart_port *port, int flags)
1130{
1131 struct uart_omap_port *up = to_uart_omap_port(port);
1132
1133 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1134 up->port.line);
1135 up->port.type = PORT_OMAP;
1136 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1137}
1138
1139static int
1140serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1141{
1142 /* we don't want the core code to modify any port params */
1143 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1144 return -EINVAL;
1145}
1146
1147static const char *
1148serial_omap_type(struct uart_port *port)
1149{
1150 struct uart_omap_port *up = to_uart_omap_port(port);
1151
1152 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1153 return up->name;
1154}
1155
1156#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1157
1158static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1159{
1160 unsigned int status, tmout = 10000;
1161
1162 /* Wait up to 10ms for the character(s) to be sent. */
1163 do {
1164 status = serial_in(up, UART_LSR);
1165
1166 if (status & UART_LSR_BI)
1167 up->lsr_break_flag = UART_LSR_BI;
1168
1169 if (--tmout == 0)
1170 break;
1171 udelay(1);
1172 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1173
1174 /* Wait up to 1s for flow control if necessary */
1175 if (up->port.flags & UPF_CONS_FLOW) {
1176 tmout = 1000000;
1177 for (tmout = 1000000; tmout; tmout--) {
1178 unsigned int msr = serial_in(up, UART_MSR);
1179
1180 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1181 if (msr & UART_MSR_CTS)
1182 break;
1183
1184 udelay(1);
1185 }
1186 }
1187}
1188
1189#ifdef CONFIG_CONSOLE_POLL
1190
1191static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1192{
1193 struct uart_omap_port *up = to_uart_omap_port(port);
1194
1195 pm_runtime_get_sync(up->dev);
1196 wait_for_xmitr(up);
1197 serial_out(up, UART_TX, ch);
1198 pm_runtime_mark_last_busy(up->dev);
1199 pm_runtime_put_autosuspend(up->dev);
1200}
1201
1202static int serial_omap_poll_get_char(struct uart_port *port)
1203{
1204 struct uart_omap_port *up = to_uart_omap_port(port);
1205 unsigned int status;
1206
1207 pm_runtime_get_sync(up->dev);
1208 status = serial_in(up, UART_LSR);
1209 if (!(status & UART_LSR_DR)) {
1210 status = NO_POLL_CHAR;
1211 goto out;
1212 }
1213
1214 status = serial_in(up, UART_RX);
1215
1216out:
1217 pm_runtime_mark_last_busy(up->dev);
1218 pm_runtime_put_autosuspend(up->dev);
1219
1220 return status;
1221}
1222
1223#endif /* CONFIG_CONSOLE_POLL */
1224
1225#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1226
1227#ifdef CONFIG_SERIAL_EARLYCON
1228static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1229{
1230 offset <<= port->regshift;
1231 return readw(port->membase + offset);
1232}
1233
1234static void omap_serial_early_out(struct uart_port *port, int offset,
1235 int value)
1236{
1237 offset <<= port->regshift;
1238 writew(value, port->membase + offset);
1239}
1240
1241static void omap_serial_early_putc(struct uart_port *port, int c)
1242{
1243 unsigned int status;
1244
1245 for (;;) {
1246 status = omap_serial_early_in(port, UART_LSR);
1247 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1248 break;
1249 cpu_relax();
1250 }
1251 omap_serial_early_out(port, UART_TX, c);
1252}
1253
1254static void early_omap_serial_write(struct console *console, const char *s,
1255 unsigned int count)
1256{
1257 struct earlycon_device *device = console->data;
1258 struct uart_port *port = &device->port;
1259
1260 uart_console_write(port, s, count, omap_serial_early_putc);
1261}
1262
1263static int __init early_omap_serial_setup(struct earlycon_device *device,
1264 const char *options)
1265{
1266 struct uart_port *port = &device->port;
1267
1268 if (!(device->port.membase || device->port.iobase))
1269 return -ENODEV;
1270
1271 port->regshift = 2;
1272 device->con->write = early_omap_serial_write;
1273 return 0;
1274}
1275
1276OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1277OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1278OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1279#endif /* CONFIG_SERIAL_EARLYCON */
1280
1281static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1282
1283static struct uart_driver serial_omap_reg;
1284
1285static void serial_omap_console_putchar(struct uart_port *port, int ch)
1286{
1287 struct uart_omap_port *up = to_uart_omap_port(port);
1288
1289 wait_for_xmitr(up);
1290 serial_out(up, UART_TX, ch);
1291}
1292
1293static void
1294serial_omap_console_write(struct console *co, const char *s,
1295 unsigned int count)
1296{
1297 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1298 unsigned long flags;
1299 unsigned int ier;
1300 int locked = 1;
1301
1302 pm_runtime_get_sync(up->dev);
1303
1304 local_irq_save(flags);
1305 if (up->port.sysrq)
1306 locked = 0;
1307 else if (oops_in_progress)
1308 locked = spin_trylock(&up->port.lock);
1309 else
1310 spin_lock(&up->port.lock);
1311
1312 /*
1313 * First save the IER then disable the interrupts
1314 */
1315 ier = serial_in(up, UART_IER);
1316 serial_out(up, UART_IER, 0);
1317
1318 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1319
1320 /*
1321 * Finally, wait for transmitter to become empty
1322 * and restore the IER
1323 */
1324 wait_for_xmitr(up);
1325 serial_out(up, UART_IER, ier);
1326 /*
1327 * The receive handling will happen properly because the
1328 * receive ready bit will still be set; it is not cleared
1329 * on read. However, modem control will not, we must
1330 * call it if we have saved something in the saved flags
1331 * while processing with interrupts off.
1332 */
1333 if (up->msr_saved_flags)
1334 check_modem_status(up);
1335
1336 pm_runtime_mark_last_busy(up->dev);
1337 pm_runtime_put_autosuspend(up->dev);
1338 if (locked)
1339 spin_unlock(&up->port.lock);
1340 local_irq_restore(flags);
1341}
1342
1343static int __init
1344serial_omap_console_setup(struct console *co, char *options)
1345{
1346 struct uart_omap_port *up;
1347 int baud = 115200;
1348 int bits = 8;
1349 int parity = 'n';
1350 int flow = 'n';
1351
1352 if (serial_omap_console_ports[co->index] == NULL)
1353 return -ENODEV;
1354 up = serial_omap_console_ports[co->index];
1355
1356 if (options)
1357 uart_parse_options(options, &baud, &parity, &bits, &flow);
1358
1359 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1360}
1361
1362static struct console serial_omap_console = {
1363 .name = OMAP_SERIAL_NAME,
1364 .write = serial_omap_console_write,
1365 .device = uart_console_device,
1366 .setup = serial_omap_console_setup,
1367 .flags = CON_PRINTBUFFER,
1368 .index = -1,
1369 .data = &serial_omap_reg,
1370};
1371
1372static void serial_omap_add_console_port(struct uart_omap_port *up)
1373{
1374 serial_omap_console_ports[up->port.line] = up;
1375}
1376
1377#define OMAP_CONSOLE (&serial_omap_console)
1378
1379#else
1380
1381#define OMAP_CONSOLE NULL
1382
1383static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1384{}
1385
1386#endif
1387
1388/* Enable or disable the rs485 support */
1389static int
1390serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1391{
1392 struct uart_omap_port *up = to_uart_omap_port(port);
1393 unsigned int mode;
1394 int val;
1395
1396 pm_runtime_get_sync(up->dev);
1397
1398 /* Disable interrupts from this port */
1399 mode = up->ier;
1400 up->ier = 0;
1401 serial_out(up, UART_IER, 0);
1402
1403 /* Clamp the delays to [0, 100ms] */
1404 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1405 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1406
1407 /* store new config */
1408 port->rs485 = *rs485;
1409
1410 /*
1411 * Just as a precaution, only allow rs485
1412 * to be enabled if the gpio pin is valid
1413 */
1414 if (up->rts_gpiod) {
1415 /* enable / disable rts */
1416 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1417 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1418 val = (port->rs485.flags & val) ? 1 : 0;
1419 gpiod_set_value(up->rts_gpiod, val);
1420 } else
1421 port->rs485.flags &= ~SER_RS485_ENABLED;
1422
1423 /* Enable interrupts */
1424 up->ier = mode;
1425 serial_out(up, UART_IER, up->ier);
1426
1427 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1428 * TX FIFO is below the trigger level.
1429 */
1430 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1431 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1432 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1433 serial_out(up, UART_OMAP_SCR, up->scr);
1434 }
1435
1436 pm_runtime_mark_last_busy(up->dev);
1437 pm_runtime_put_autosuspend(up->dev);
1438
1439 return 0;
1440}
1441
1442static const struct uart_ops serial_omap_pops = {
1443 .tx_empty = serial_omap_tx_empty,
1444 .set_mctrl = serial_omap_set_mctrl,
1445 .get_mctrl = serial_omap_get_mctrl,
1446 .stop_tx = serial_omap_stop_tx,
1447 .start_tx = serial_omap_start_tx,
1448 .throttle = serial_omap_throttle,
1449 .unthrottle = serial_omap_unthrottle,
1450 .stop_rx = serial_omap_stop_rx,
1451 .enable_ms = serial_omap_enable_ms,
1452 .break_ctl = serial_omap_break_ctl,
1453 .startup = serial_omap_startup,
1454 .shutdown = serial_omap_shutdown,
1455 .set_termios = serial_omap_set_termios,
1456 .pm = serial_omap_pm,
1457 .type = serial_omap_type,
1458 .release_port = serial_omap_release_port,
1459 .request_port = serial_omap_request_port,
1460 .config_port = serial_omap_config_port,
1461 .verify_port = serial_omap_verify_port,
1462#ifdef CONFIG_CONSOLE_POLL
1463 .poll_put_char = serial_omap_poll_put_char,
1464 .poll_get_char = serial_omap_poll_get_char,
1465#endif
1466};
1467
1468static struct uart_driver serial_omap_reg = {
1469 .owner = THIS_MODULE,
1470 .driver_name = "OMAP-SERIAL",
1471 .dev_name = OMAP_SERIAL_NAME,
1472 .nr = OMAP_MAX_HSUART_PORTS,
1473 .cons = OMAP_CONSOLE,
1474};
1475
1476#ifdef CONFIG_PM_SLEEP
1477static int serial_omap_prepare(struct device *dev)
1478{
1479 struct uart_omap_port *up = dev_get_drvdata(dev);
1480
1481 up->is_suspending = true;
1482
1483 return 0;
1484}
1485
1486static void serial_omap_complete(struct device *dev)
1487{
1488 struct uart_omap_port *up = dev_get_drvdata(dev);
1489
1490 up->is_suspending = false;
1491}
1492
1493static int serial_omap_suspend(struct device *dev)
1494{
1495 struct uart_omap_port *up = dev_get_drvdata(dev);
1496
1497 uart_suspend_port(&serial_omap_reg, &up->port);
1498 flush_work(&up->qos_work);
1499
1500 if (device_may_wakeup(dev))
1501 serial_omap_enable_wakeup(up, true);
1502 else
1503 serial_omap_enable_wakeup(up, false);
1504
1505 return 0;
1506}
1507
1508static int serial_omap_resume(struct device *dev)
1509{
1510 struct uart_omap_port *up = dev_get_drvdata(dev);
1511
1512 if (device_may_wakeup(dev))
1513 serial_omap_enable_wakeup(up, false);
1514
1515 uart_resume_port(&serial_omap_reg, &up->port);
1516
1517 return 0;
1518}
1519#else
1520#define serial_omap_prepare NULL
1521#define serial_omap_complete NULL
1522#endif /* CONFIG_PM_SLEEP */
1523
1524static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1525{
1526 u32 mvr, scheme;
1527 u16 revision, major, minor;
1528
1529 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1530
1531 /* Check revision register scheme */
1532 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1533
1534 switch (scheme) {
1535 case 0: /* Legacy Scheme: OMAP2/3 */
1536 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1537 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1538 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1539 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1540 break;
1541 case 1:
1542 /* New Scheme: OMAP4+ */
1543 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1544 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1545 OMAP_UART_MVR_MAJ_SHIFT;
1546 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1547 break;
1548 default:
1549 dev_warn(up->dev,
1550 "Unknown %s revision, defaulting to highest\n",
1551 up->name);
1552 /* highest possible revision */
1553 major = 0xff;
1554 minor = 0xff;
1555 }
1556
1557 /* normalize revision for the driver */
1558 revision = UART_BUILD_REVISION(major, minor);
1559
1560 switch (revision) {
1561 case OMAP_UART_REV_46:
1562 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1563 UART_ERRATA_i291_DMA_FORCEIDLE);
1564 break;
1565 case OMAP_UART_REV_52:
1566 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1567 UART_ERRATA_i291_DMA_FORCEIDLE);
1568 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1569 break;
1570 case OMAP_UART_REV_63:
1571 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1572 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1573 break;
1574 default:
1575 break;
1576 }
1577}
1578
1579static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1580{
1581 struct omap_uart_port_info *omap_up_info;
1582
1583 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1584 if (!omap_up_info)
1585 return NULL; /* out of memory */
1586
1587 of_property_read_u32(dev->of_node, "clock-frequency",
1588 &omap_up_info->uartclk);
1589
1590 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1591
1592 return omap_up_info;
1593}
1594
1595static int serial_omap_probe_rs485(struct uart_omap_port *up,
1596 struct device *dev)
1597{
1598 struct serial_rs485 *rs485conf = &up->port.rs485;
1599 struct device_node *np = dev->of_node;
1600 enum gpiod_flags gflags;
1601 int ret;
1602
1603 rs485conf->flags = 0;
1604 up->rts_gpiod = NULL;
1605
1606 if (!np)
1607 return 0;
1608
1609 ret = uart_get_rs485_mode(&up->port);
1610 if (ret)
1611 return ret;
1612
1613 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1614 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1615 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1616 } else {
1617 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1618 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1619 }
1620
1621 /* check for tx enable gpio */
1622 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1623 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1624 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1625 if (IS_ERR(up->rts_gpiod)) {
1626 ret = PTR_ERR(up->rts_gpiod);
1627 if (ret == -EPROBE_DEFER)
1628 return ret;
1629 /*
1630 * FIXME: the code historically ignored any other error than
1631 * -EPROBE_DEFER and just went on without GPIO.
1632 */
1633 up->rts_gpiod = NULL;
1634 } else {
1635 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1636 }
1637
1638 return 0;
1639}
1640
1641static int serial_omap_probe(struct platform_device *pdev)
1642{
1643 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1644 struct uart_omap_port *up;
1645 struct resource *mem;
1646 void __iomem *base;
1647 int uartirq = 0;
1648 int wakeirq = 0;
1649 int ret;
1650
1651 /* The optional wakeirq may be specified in the board dts file */
1652 if (pdev->dev.of_node) {
1653 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1654 if (!uartirq)
1655 return -EPROBE_DEFER;
1656 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1657 omap_up_info = of_get_uart_port_info(&pdev->dev);
1658 pdev->dev.platform_data = omap_up_info;
1659 } else {
1660 uartirq = platform_get_irq(pdev, 0);
1661 if (uartirq < 0)
1662 return -EPROBE_DEFER;
1663 }
1664
1665 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1666 if (!up)
1667 return -ENOMEM;
1668
1669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 base = devm_ioremap_resource(&pdev->dev, mem);
1671 if (IS_ERR(base))
1672 return PTR_ERR(base);
1673
1674 up->dev = &pdev->dev;
1675 up->port.dev = &pdev->dev;
1676 up->port.type = PORT_OMAP;
1677 up->port.iotype = UPIO_MEM;
1678 up->port.irq = uartirq;
1679 up->port.regshift = 2;
1680 up->port.fifosize = 64;
1681 up->port.ops = &serial_omap_pops;
1682 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1683
1684 if (pdev->dev.of_node)
1685 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1686 else
1687 ret = pdev->id;
1688
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691 ret);
1692 goto err_port_line;
1693 }
1694 up->port.line = ret;
1695
1696 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1697 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1698 OMAP_MAX_HSUART_PORTS);
1699 ret = -ENXIO;
1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1708 ret = serial_omap_probe_rs485(up, &pdev->dev);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1725 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1727 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1728 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1729
1730 platform_set_drvdata(pdev, up);
1731 if (omap_up_info->autosuspend_timeout == 0)
1732 omap_up_info->autosuspend_timeout = -1;
1733
1734 device_init_wakeup(up->dev, true);
1735 pm_runtime_use_autosuspend(&pdev->dev);
1736 pm_runtime_set_autosuspend_delay(&pdev->dev,
1737 omap_up_info->autosuspend_timeout);
1738
1739 pm_runtime_irq_safe(&pdev->dev);
1740 pm_runtime_enable(&pdev->dev);
1741
1742 pm_runtime_get_sync(&pdev->dev);
1743
1744 omap_serial_fill_features_erratas(up);
1745
1746 ui[up->port.line] = up;
1747 serial_omap_add_console_port(up);
1748
1749 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1750 if (ret != 0)
1751 goto err_add_port;
1752
1753 pm_runtime_mark_last_busy(up->dev);
1754 pm_runtime_put_autosuspend(up->dev);
1755 return 0;
1756
1757err_add_port:
1758 pm_runtime_dont_use_autosuspend(&pdev->dev);
1759 pm_runtime_put_sync(&pdev->dev);
1760 pm_runtime_disable(&pdev->dev);
1761 cpu_latency_qos_remove_request(&up->pm_qos_request);
1762 device_init_wakeup(up->dev, false);
1763err_rs485:
1764err_port_line:
1765 return ret;
1766}
1767
1768static int serial_omap_remove(struct platform_device *dev)
1769{
1770 struct uart_omap_port *up = platform_get_drvdata(dev);
1771
1772 pm_runtime_get_sync(up->dev);
1773
1774 uart_remove_one_port(&serial_omap_reg, &up->port);
1775
1776 pm_runtime_dont_use_autosuspend(up->dev);
1777 pm_runtime_put_sync(up->dev);
1778 pm_runtime_disable(up->dev);
1779 cpu_latency_qos_remove_request(&up->pm_qos_request);
1780 device_init_wakeup(&dev->dev, false);
1781
1782 return 0;
1783}
1784
1785/*
1786 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1787 * The access to uart register after MDR1 Access
1788 * causes UART to corrupt data.
1789 *
1790 * Need a delay =
1791 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1792 * give 10 times as much
1793 */
1794static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1795{
1796 u8 timeout = 255;
1797
1798 serial_out(up, UART_OMAP_MDR1, mdr1);
1799 udelay(2);
1800 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1801 UART_FCR_CLEAR_RCVR);
1802 /*
1803 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1804 * TX_FIFO_E bit is 1.
1805 */
1806 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1807 (UART_LSR_THRE | UART_LSR_DR))) {
1808 timeout--;
1809 if (!timeout) {
1810 /* Should *never* happen. we warn and carry on */
1811 dev_crit(up->dev, "Errata i202: timedout %x\n",
1812 serial_in(up, UART_LSR));
1813 break;
1814 }
1815 udelay(1);
1816 }
1817}
1818
1819#ifdef CONFIG_PM
1820static void serial_omap_restore_context(struct uart_omap_port *up)
1821{
1822 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1823 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1824 else
1825 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1826
1827 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1828 serial_out(up, UART_EFR, UART_EFR_ECB);
1829 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1830 serial_out(up, UART_IER, 0x0);
1831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1832 serial_out(up, UART_DLL, up->dll);
1833 serial_out(up, UART_DLM, up->dlh);
1834 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1835 serial_out(up, UART_IER, up->ier);
1836 serial_out(up, UART_FCR, up->fcr);
1837 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1838 serial_out(up, UART_MCR, up->mcr);
1839 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1840 serial_out(up, UART_OMAP_SCR, up->scr);
1841 serial_out(up, UART_EFR, up->efr);
1842 serial_out(up, UART_LCR, up->lcr);
1843 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1844 serial_omap_mdr1_errataset(up, up->mdr1);
1845 else
1846 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1847 serial_out(up, UART_OMAP_WER, up->wer);
1848}
1849
1850static int serial_omap_runtime_suspend(struct device *dev)
1851{
1852 struct uart_omap_port *up = dev_get_drvdata(dev);
1853
1854 if (!up)
1855 return -EINVAL;
1856
1857 /*
1858 * When using 'no_console_suspend', the console UART must not be
1859 * suspended. Since driver suspend is managed by runtime suspend,
1860 * preventing runtime suspend (by returning error) will keep device
1861 * active during suspend.
1862 */
1863 if (up->is_suspending && !console_suspend_enabled &&
1864 uart_console(&up->port))
1865 return -EBUSY;
1866
1867 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1868
1869 serial_omap_enable_wakeup(up, true);
1870
1871 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1872 schedule_work(&up->qos_work);
1873
1874 return 0;
1875}
1876
1877static int serial_omap_runtime_resume(struct device *dev)
1878{
1879 struct uart_omap_port *up = dev_get_drvdata(dev);
1880
1881 int loss_cnt = serial_omap_get_context_loss_count(up);
1882
1883 serial_omap_enable_wakeup(up, false);
1884
1885 if (loss_cnt < 0) {
1886 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1887 loss_cnt);
1888 serial_omap_restore_context(up);
1889 } else if (up->context_loss_cnt != loss_cnt) {
1890 serial_omap_restore_context(up);
1891 }
1892 up->latency = up->calc_latency;
1893 schedule_work(&up->qos_work);
1894
1895 return 0;
1896}
1897#endif
1898
1899static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1900 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1901 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1902 serial_omap_runtime_resume, NULL)
1903 .prepare = serial_omap_prepare,
1904 .complete = serial_omap_complete,
1905};
1906
1907#if defined(CONFIG_OF)
1908static const struct of_device_id omap_serial_of_match[] = {
1909 { .compatible = "ti,omap2-uart" },
1910 { .compatible = "ti,omap3-uart" },
1911 { .compatible = "ti,omap4-uart" },
1912 {},
1913};
1914MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1915#endif
1916
1917static struct platform_driver serial_omap_driver = {
1918 .probe = serial_omap_probe,
1919 .remove = serial_omap_remove,
1920 .driver = {
1921 .name = OMAP_SERIAL_DRIVER_NAME,
1922 .pm = &serial_omap_dev_pm_ops,
1923 .of_match_table = of_match_ptr(omap_serial_of_match),
1924 },
1925};
1926
1927static int __init serial_omap_init(void)
1928{
1929 int ret;
1930
1931 ret = uart_register_driver(&serial_omap_reg);
1932 if (ret != 0)
1933 return ret;
1934 ret = platform_driver_register(&serial_omap_driver);
1935 if (ret != 0)
1936 uart_unregister_driver(&serial_omap_reg);
1937 return ret;
1938}
1939
1940static void __exit serial_omap_exit(void)
1941{
1942 platform_driver_unregister(&serial_omap_driver);
1943 uart_unregister_driver(&serial_omap_reg);
1944}
1945
1946module_init(serial_omap_init);
1947module_exit(serial_omap_exit);
1948
1949MODULE_DESCRIPTION("OMAP High Speed UART driver");
1950MODULE_LICENSE("GPL");
1951MODULE_AUTHOR("Texas Instruments Inc");