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1// SPDX-License-Identifier: GPL-2.0
2/**
3 * Synopsys DesignWare PCIe Endpoint controller driver
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/of.h>
10
11#include "pcie-designware.h"
12#include <linux/pci-epc.h>
13#include <linux/pci-epf.h>
14
15void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
16{
17 struct pci_epc *epc = ep->epc;
18
19 pci_epc_linkup(epc);
20}
21
22static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
23 int flags)
24{
25 u32 reg;
26
27 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
28 dw_pcie_dbi_ro_wr_en(pci);
29 dw_pcie_writel_dbi2(pci, reg, 0x0);
30 dw_pcie_writel_dbi(pci, reg, 0x0);
31 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
32 dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
33 dw_pcie_writel_dbi(pci, reg + 4, 0x0);
34 }
35 dw_pcie_dbi_ro_wr_dis(pci);
36}
37
38void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
39{
40 __dw_pcie_ep_reset_bar(pci, bar, 0);
41}
42
43static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
44 struct pci_epf_header *hdr)
45{
46 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
47 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
48
49 dw_pcie_dbi_ro_wr_en(pci);
50 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
51 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
52 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
53 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
54 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
55 hdr->subclass_code | hdr->baseclass_code << 8);
56 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
57 hdr->cache_line_size);
58 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
59 hdr->subsys_vendor_id);
60 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
61 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
62 hdr->interrupt_pin);
63 dw_pcie_dbi_ro_wr_dis(pci);
64
65 return 0;
66}
67
68static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
69 dma_addr_t cpu_addr,
70 enum dw_pcie_as_type as_type)
71{
72 int ret;
73 u32 free_win;
74 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
75
76 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
77 if (free_win >= ep->num_ib_windows) {
78 dev_err(pci->dev, "No free inbound window\n");
79 return -EINVAL;
80 }
81
82 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
83 as_type);
84 if (ret < 0) {
85 dev_err(pci->dev, "Failed to program IB window\n");
86 return ret;
87 }
88
89 ep->bar_to_atu[bar] = free_win;
90 set_bit(free_win, ep->ib_window_map);
91
92 return 0;
93}
94
95static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
96 u64 pci_addr, size_t size)
97{
98 u32 free_win;
99 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
100
101 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
102 if (free_win >= ep->num_ob_windows) {
103 dev_err(pci->dev, "No free outbound window\n");
104 return -EINVAL;
105 }
106
107 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
108 phys_addr, pci_addr, size);
109
110 set_bit(free_win, ep->ob_window_map);
111 ep->outbound_addr[free_win] = phys_addr;
112
113 return 0;
114}
115
116static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
117 struct pci_epf_bar *epf_bar)
118{
119 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
120 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
121 enum pci_barno bar = epf_bar->barno;
122 u32 atu_index = ep->bar_to_atu[bar];
123
124 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
125
126 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
127 clear_bit(atu_index, ep->ib_window_map);
128}
129
130static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
131 struct pci_epf_bar *epf_bar)
132{
133 int ret;
134 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
135 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
136 enum pci_barno bar = epf_bar->barno;
137 size_t size = epf_bar->size;
138 int flags = epf_bar->flags;
139 enum dw_pcie_as_type as_type;
140 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
141
142 if (!(flags & PCI_BASE_ADDRESS_SPACE))
143 as_type = DW_PCIE_AS_MEM;
144 else
145 as_type = DW_PCIE_AS_IO;
146
147 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
148 if (ret)
149 return ret;
150
151 dw_pcie_dbi_ro_wr_en(pci);
152
153 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
154 dw_pcie_writel_dbi(pci, reg, flags);
155
156 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
157 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
158 dw_pcie_writel_dbi(pci, reg + 4, 0);
159 }
160
161 dw_pcie_dbi_ro_wr_dis(pci);
162
163 return 0;
164}
165
166static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
167 u32 *atu_index)
168{
169 u32 index;
170
171 for (index = 0; index < ep->num_ob_windows; index++) {
172 if (ep->outbound_addr[index] != addr)
173 continue;
174 *atu_index = index;
175 return 0;
176 }
177
178 return -EINVAL;
179}
180
181static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
182 phys_addr_t addr)
183{
184 int ret;
185 u32 atu_index;
186 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
187 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
188
189 ret = dw_pcie_find_index(ep, addr, &atu_index);
190 if (ret < 0)
191 return;
192
193 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
194 clear_bit(atu_index, ep->ob_window_map);
195}
196
197static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
198 phys_addr_t addr,
199 u64 pci_addr, size_t size)
200{
201 int ret;
202 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
203 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
204
205 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
206 if (ret) {
207 dev_err(pci->dev, "Failed to enable address\n");
208 return ret;
209 }
210
211 return 0;
212}
213
214static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
215{
216 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
217 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
218 u32 val, reg;
219
220 if (!ep->msi_cap)
221 return -EINVAL;
222
223 reg = ep->msi_cap + PCI_MSI_FLAGS;
224 val = dw_pcie_readw_dbi(pci, reg);
225 if (!(val & PCI_MSI_FLAGS_ENABLE))
226 return -EINVAL;
227
228 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
229
230 return val;
231}
232
233static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
234{
235 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
236 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
237 u32 val, reg;
238
239 if (!ep->msi_cap)
240 return -EINVAL;
241
242 reg = ep->msi_cap + PCI_MSI_FLAGS;
243 val = dw_pcie_readw_dbi(pci, reg);
244 val &= ~PCI_MSI_FLAGS_QMASK;
245 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
246 dw_pcie_dbi_ro_wr_en(pci);
247 dw_pcie_writew_dbi(pci, reg, val);
248 dw_pcie_dbi_ro_wr_dis(pci);
249
250 return 0;
251}
252
253static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
254{
255 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
256 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
257 u32 val, reg;
258
259 if (!ep->msix_cap)
260 return -EINVAL;
261
262 reg = ep->msix_cap + PCI_MSIX_FLAGS;
263 val = dw_pcie_readw_dbi(pci, reg);
264 if (!(val & PCI_MSIX_FLAGS_ENABLE))
265 return -EINVAL;
266
267 val &= PCI_MSIX_FLAGS_QSIZE;
268
269 return val;
270}
271
272static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
273{
274 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
275 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
276 u32 val, reg;
277
278 if (!ep->msix_cap)
279 return -EINVAL;
280
281 reg = ep->msix_cap + PCI_MSIX_FLAGS;
282 val = dw_pcie_readw_dbi(pci, reg);
283 val &= ~PCI_MSIX_FLAGS_QSIZE;
284 val |= interrupts;
285 dw_pcie_dbi_ro_wr_en(pci);
286 dw_pcie_writew_dbi(pci, reg, val);
287 dw_pcie_dbi_ro_wr_dis(pci);
288
289 return 0;
290}
291
292static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
293 enum pci_epc_irq_type type, u16 interrupt_num)
294{
295 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
296
297 if (!ep->ops->raise_irq)
298 return -EINVAL;
299
300 return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
301}
302
303static void dw_pcie_ep_stop(struct pci_epc *epc)
304{
305 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
306 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
307
308 if (!pci->ops->stop_link)
309 return;
310
311 pci->ops->stop_link(pci);
312}
313
314static int dw_pcie_ep_start(struct pci_epc *epc)
315{
316 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
317 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
318
319 if (!pci->ops->start_link)
320 return -EINVAL;
321
322 return pci->ops->start_link(pci);
323}
324
325static const struct pci_epc_features*
326dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
327{
328 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
329
330 if (!ep->ops->get_features)
331 return NULL;
332
333 return ep->ops->get_features(ep);
334}
335
336static const struct pci_epc_ops epc_ops = {
337 .write_header = dw_pcie_ep_write_header,
338 .set_bar = dw_pcie_ep_set_bar,
339 .clear_bar = dw_pcie_ep_clear_bar,
340 .map_addr = dw_pcie_ep_map_addr,
341 .unmap_addr = dw_pcie_ep_unmap_addr,
342 .set_msi = dw_pcie_ep_set_msi,
343 .get_msi = dw_pcie_ep_get_msi,
344 .set_msix = dw_pcie_ep_set_msix,
345 .get_msix = dw_pcie_ep_get_msix,
346 .raise_irq = dw_pcie_ep_raise_irq,
347 .start = dw_pcie_ep_start,
348 .stop = dw_pcie_ep_stop,
349 .get_features = dw_pcie_ep_get_features,
350};
351
352int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
353{
354 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
355 struct device *dev = pci->dev;
356
357 dev_err(dev, "EP cannot trigger legacy IRQs\n");
358
359 return -EINVAL;
360}
361
362int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
363 u8 interrupt_num)
364{
365 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
366 struct pci_epc *epc = ep->epc;
367 unsigned int aligned_offset;
368 u16 msg_ctrl, msg_data;
369 u32 msg_addr_lower, msg_addr_upper, reg;
370 u64 msg_addr;
371 bool has_upper;
372 int ret;
373
374 if (!ep->msi_cap)
375 return -EINVAL;
376
377 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
378 reg = ep->msi_cap + PCI_MSI_FLAGS;
379 msg_ctrl = dw_pcie_readw_dbi(pci, reg);
380 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
381 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
382 msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
383 if (has_upper) {
384 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
385 msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
386 reg = ep->msi_cap + PCI_MSI_DATA_64;
387 msg_data = dw_pcie_readw_dbi(pci, reg);
388 } else {
389 msg_addr_upper = 0;
390 reg = ep->msi_cap + PCI_MSI_DATA_32;
391 msg_data = dw_pcie_readw_dbi(pci, reg);
392 }
393 aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
394 msg_addr = ((u64)msg_addr_upper) << 32 |
395 (msg_addr_lower & ~aligned_offset);
396 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
397 epc->mem->page_size);
398 if (ret)
399 return ret;
400
401 writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
402
403 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
404
405 return 0;
406}
407
408int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
409 u16 interrupt_num)
410{
411 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
412 struct pci_epc *epc = ep->epc;
413 u16 tbl_offset, bir;
414 u32 bar_addr_upper, bar_addr_lower;
415 u32 msg_addr_upper, msg_addr_lower;
416 u32 reg, msg_data, vec_ctrl;
417 u64 tbl_addr, msg_addr, reg_u64;
418 void __iomem *msix_tbl;
419 int ret;
420
421 reg = ep->msix_cap + PCI_MSIX_TABLE;
422 tbl_offset = dw_pcie_readl_dbi(pci, reg);
423 bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
424 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
425
426 reg = PCI_BASE_ADDRESS_0 + (4 * bir);
427 bar_addr_upper = 0;
428 bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
429 reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
430 if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
431 bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
432
433 tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
434 tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
435 tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
436
437 msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
438 PCI_MSIX_ENTRY_SIZE);
439 if (!msix_tbl)
440 return -EINVAL;
441
442 msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
443 msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
444 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
445 msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
446 vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
447
448 iounmap(msix_tbl);
449
450 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
451 dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
452 return -EPERM;
453 }
454
455 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
456 epc->mem->page_size);
457 if (ret)
458 return ret;
459
460 writel(msg_data, ep->msi_mem);
461
462 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
463
464 return 0;
465}
466
467void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
468{
469 struct pci_epc *epc = ep->epc;
470
471 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
472 epc->mem->page_size);
473
474 pci_epc_mem_exit(epc);
475}
476
477static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
478{
479 u32 header;
480 int pos = PCI_CFG_SPACE_SIZE;
481
482 while (pos) {
483 header = dw_pcie_readl_dbi(pci, pos);
484 if (PCI_EXT_CAP_ID(header) == cap)
485 return pos;
486
487 pos = PCI_EXT_CAP_NEXT(header);
488 if (!pos)
489 break;
490 }
491
492 return 0;
493}
494
495int dw_pcie_ep_init(struct dw_pcie_ep *ep)
496{
497 int i;
498 int ret;
499 u32 reg;
500 void *addr;
501 u8 hdr_type;
502 unsigned int nbars;
503 unsigned int offset;
504 struct pci_epc *epc;
505 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
506 struct device *dev = pci->dev;
507 struct device_node *np = dev->of_node;
508
509 if (!pci->dbi_base || !pci->dbi_base2) {
510 dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
511 return -EINVAL;
512 }
513
514 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
515 if (ret < 0) {
516 dev_err(dev, "Unable to read *num-ib-windows* property\n");
517 return ret;
518 }
519 if (ep->num_ib_windows > MAX_IATU_IN) {
520 dev_err(dev, "Invalid *num-ib-windows*\n");
521 return -EINVAL;
522 }
523
524 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
525 if (ret < 0) {
526 dev_err(dev, "Unable to read *num-ob-windows* property\n");
527 return ret;
528 }
529 if (ep->num_ob_windows > MAX_IATU_OUT) {
530 dev_err(dev, "Invalid *num-ob-windows*\n");
531 return -EINVAL;
532 }
533
534 ep->ib_window_map = devm_kcalloc(dev,
535 BITS_TO_LONGS(ep->num_ib_windows),
536 sizeof(long),
537 GFP_KERNEL);
538 if (!ep->ib_window_map)
539 return -ENOMEM;
540
541 ep->ob_window_map = devm_kcalloc(dev,
542 BITS_TO_LONGS(ep->num_ob_windows),
543 sizeof(long),
544 GFP_KERNEL);
545 if (!ep->ob_window_map)
546 return -ENOMEM;
547
548 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
549 GFP_KERNEL);
550 if (!addr)
551 return -ENOMEM;
552 ep->outbound_addr = addr;
553
554 epc = devm_pci_epc_create(dev, &epc_ops);
555 if (IS_ERR(epc)) {
556 dev_err(dev, "Failed to create epc device\n");
557 return PTR_ERR(epc);
558 }
559
560 ep->epc = epc;
561 epc_set_drvdata(epc, ep);
562
563 if (ep->ops->ep_init)
564 ep->ops->ep_init(ep);
565
566 hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
567 if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
568 dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
569 hdr_type);
570 return -EIO;
571 }
572
573 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
574 if (ret < 0)
575 epc->max_functions = 1;
576
577 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
578 ep->page_size);
579 if (ret < 0) {
580 dev_err(dev, "Failed to initialize address space\n");
581 return ret;
582 }
583
584 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
585 epc->mem->page_size);
586 if (!ep->msi_mem) {
587 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
588 return -ENOMEM;
589 }
590 ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
591
592 ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
593
594 offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
595 if (offset) {
596 reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
597 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
598 PCI_REBAR_CTRL_NBAR_SHIFT;
599
600 dw_pcie_dbi_ro_wr_en(pci);
601 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
602 dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
603 dw_pcie_dbi_ro_wr_dis(pci);
604 }
605
606 dw_pcie_setup(pci);
607
608 return 0;
609}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe Endpoint controller driver
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/of.h>
10
11#include "pcie-designware.h"
12#include <linux/pci-epc.h>
13#include <linux/pci-epf.h>
14
15void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
16{
17 struct pci_epc *epc = ep->epc;
18
19 pci_epc_linkup(epc);
20}
21EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);
22
23void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
24{
25 struct pci_epc *epc = ep->epc;
26
27 pci_epc_init_notify(epc);
28}
29EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
30
31static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
32 int flags)
33{
34 u32 reg;
35
36 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
37 dw_pcie_dbi_ro_wr_en(pci);
38 dw_pcie_writel_dbi2(pci, reg, 0x0);
39 dw_pcie_writel_dbi(pci, reg, 0x0);
40 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
41 dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
42 dw_pcie_writel_dbi(pci, reg + 4, 0x0);
43 }
44 dw_pcie_dbi_ro_wr_dis(pci);
45}
46
47void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
48{
49 __dw_pcie_ep_reset_bar(pci, bar, 0);
50}
51
52static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
53 struct pci_epf_header *hdr)
54{
55 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
56 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
57
58 dw_pcie_dbi_ro_wr_en(pci);
59 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
60 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
61 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
62 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
63 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
64 hdr->subclass_code | hdr->baseclass_code << 8);
65 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
66 hdr->cache_line_size);
67 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
68 hdr->subsys_vendor_id);
69 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
70 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
71 hdr->interrupt_pin);
72 dw_pcie_dbi_ro_wr_dis(pci);
73
74 return 0;
75}
76
77static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
78 dma_addr_t cpu_addr,
79 enum dw_pcie_as_type as_type)
80{
81 int ret;
82 u32 free_win;
83 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
84
85 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
86 if (free_win >= ep->num_ib_windows) {
87 dev_err(pci->dev, "No free inbound window\n");
88 return -EINVAL;
89 }
90
91 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
92 as_type);
93 if (ret < 0) {
94 dev_err(pci->dev, "Failed to program IB window\n");
95 return ret;
96 }
97
98 ep->bar_to_atu[bar] = free_win;
99 set_bit(free_win, ep->ib_window_map);
100
101 return 0;
102}
103
104static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
105 u64 pci_addr, size_t size)
106{
107 u32 free_win;
108 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
109
110 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
111 if (free_win >= ep->num_ob_windows) {
112 dev_err(pci->dev, "No free outbound window\n");
113 return -EINVAL;
114 }
115
116 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
117 phys_addr, pci_addr, size);
118
119 set_bit(free_win, ep->ob_window_map);
120 ep->outbound_addr[free_win] = phys_addr;
121
122 return 0;
123}
124
125static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
126 struct pci_epf_bar *epf_bar)
127{
128 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
129 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
130 enum pci_barno bar = epf_bar->barno;
131 u32 atu_index = ep->bar_to_atu[bar];
132
133 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
134
135 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
136 clear_bit(atu_index, ep->ib_window_map);
137 ep->epf_bar[bar] = NULL;
138}
139
140static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
141 struct pci_epf_bar *epf_bar)
142{
143 int ret;
144 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
145 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
146 enum pci_barno bar = epf_bar->barno;
147 size_t size = epf_bar->size;
148 int flags = epf_bar->flags;
149 enum dw_pcie_as_type as_type;
150 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
151
152 if (!(flags & PCI_BASE_ADDRESS_SPACE))
153 as_type = DW_PCIE_AS_MEM;
154 else
155 as_type = DW_PCIE_AS_IO;
156
157 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
158 if (ret)
159 return ret;
160
161 dw_pcie_dbi_ro_wr_en(pci);
162
163 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
164 dw_pcie_writel_dbi(pci, reg, flags);
165
166 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
167 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
168 dw_pcie_writel_dbi(pci, reg + 4, 0);
169 }
170
171 ep->epf_bar[bar] = epf_bar;
172 dw_pcie_dbi_ro_wr_dis(pci);
173
174 return 0;
175}
176
177static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
178 u32 *atu_index)
179{
180 u32 index;
181
182 for (index = 0; index < ep->num_ob_windows; index++) {
183 if (ep->outbound_addr[index] != addr)
184 continue;
185 *atu_index = index;
186 return 0;
187 }
188
189 return -EINVAL;
190}
191
192static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
193 phys_addr_t addr)
194{
195 int ret;
196 u32 atu_index;
197 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
198 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
199
200 ret = dw_pcie_find_index(ep, addr, &atu_index);
201 if (ret < 0)
202 return;
203
204 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
205 clear_bit(atu_index, ep->ob_window_map);
206}
207
208static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
209 phys_addr_t addr,
210 u64 pci_addr, size_t size)
211{
212 int ret;
213 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
214 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
215
216 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
217 if (ret) {
218 dev_err(pci->dev, "Failed to enable address\n");
219 return ret;
220 }
221
222 return 0;
223}
224
225static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
226{
227 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
228 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
229 u32 val, reg;
230
231 if (!ep->msi_cap)
232 return -EINVAL;
233
234 reg = ep->msi_cap + PCI_MSI_FLAGS;
235 val = dw_pcie_readw_dbi(pci, reg);
236 if (!(val & PCI_MSI_FLAGS_ENABLE))
237 return -EINVAL;
238
239 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
240
241 return val;
242}
243
244static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
245{
246 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
247 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
248 u32 val, reg;
249
250 if (!ep->msi_cap)
251 return -EINVAL;
252
253 reg = ep->msi_cap + PCI_MSI_FLAGS;
254 val = dw_pcie_readw_dbi(pci, reg);
255 val &= ~PCI_MSI_FLAGS_QMASK;
256 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
257 dw_pcie_dbi_ro_wr_en(pci);
258 dw_pcie_writew_dbi(pci, reg, val);
259 dw_pcie_dbi_ro_wr_dis(pci);
260
261 return 0;
262}
263
264static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
265{
266 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
267 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
268 u32 val, reg;
269
270 if (!ep->msix_cap)
271 return -EINVAL;
272
273 reg = ep->msix_cap + PCI_MSIX_FLAGS;
274 val = dw_pcie_readw_dbi(pci, reg);
275 if (!(val & PCI_MSIX_FLAGS_ENABLE))
276 return -EINVAL;
277
278 val &= PCI_MSIX_FLAGS_QSIZE;
279
280 return val;
281}
282
283static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
284 enum pci_barno bir, u32 offset)
285{
286 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
287 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
288 u32 val, reg;
289
290 if (!ep->msix_cap)
291 return -EINVAL;
292
293 dw_pcie_dbi_ro_wr_en(pci);
294
295 reg = ep->msix_cap + PCI_MSIX_FLAGS;
296 val = dw_pcie_readw_dbi(pci, reg);
297 val &= ~PCI_MSIX_FLAGS_QSIZE;
298 val |= interrupts;
299 dw_pcie_writew_dbi(pci, reg, val);
300
301 reg = ep->msix_cap + PCI_MSIX_TABLE;
302 val = offset | bir;
303 dw_pcie_writel_dbi(pci, reg, val);
304
305 reg = ep->msix_cap + PCI_MSIX_PBA;
306 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
307 dw_pcie_writel_dbi(pci, reg, val);
308
309 dw_pcie_dbi_ro_wr_dis(pci);
310
311 return 0;
312}
313
314static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
315 enum pci_epc_irq_type type, u16 interrupt_num)
316{
317 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
318
319 if (!ep->ops->raise_irq)
320 return -EINVAL;
321
322 return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
323}
324
325static void dw_pcie_ep_stop(struct pci_epc *epc)
326{
327 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
328 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
329
330 if (!pci->ops->stop_link)
331 return;
332
333 pci->ops->stop_link(pci);
334}
335
336static int dw_pcie_ep_start(struct pci_epc *epc)
337{
338 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
339 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
340
341 if (!pci->ops->start_link)
342 return -EINVAL;
343
344 return pci->ops->start_link(pci);
345}
346
347static const struct pci_epc_features*
348dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
349{
350 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
351
352 if (!ep->ops->get_features)
353 return NULL;
354
355 return ep->ops->get_features(ep);
356}
357
358static const struct pci_epc_ops epc_ops = {
359 .write_header = dw_pcie_ep_write_header,
360 .set_bar = dw_pcie_ep_set_bar,
361 .clear_bar = dw_pcie_ep_clear_bar,
362 .map_addr = dw_pcie_ep_map_addr,
363 .unmap_addr = dw_pcie_ep_unmap_addr,
364 .set_msi = dw_pcie_ep_set_msi,
365 .get_msi = dw_pcie_ep_get_msi,
366 .set_msix = dw_pcie_ep_set_msix,
367 .get_msix = dw_pcie_ep_get_msix,
368 .raise_irq = dw_pcie_ep_raise_irq,
369 .start = dw_pcie_ep_start,
370 .stop = dw_pcie_ep_stop,
371 .get_features = dw_pcie_ep_get_features,
372};
373
374int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
375{
376 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
377 struct device *dev = pci->dev;
378
379 dev_err(dev, "EP cannot trigger legacy IRQs\n");
380
381 return -EINVAL;
382}
383
384int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
385 u8 interrupt_num)
386{
387 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
388 struct pci_epc *epc = ep->epc;
389 unsigned int aligned_offset;
390 u16 msg_ctrl, msg_data;
391 u32 msg_addr_lower, msg_addr_upper, reg;
392 u64 msg_addr;
393 bool has_upper;
394 int ret;
395
396 if (!ep->msi_cap)
397 return -EINVAL;
398
399 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
400 reg = ep->msi_cap + PCI_MSI_FLAGS;
401 msg_ctrl = dw_pcie_readw_dbi(pci, reg);
402 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
403 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
404 msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
405 if (has_upper) {
406 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
407 msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
408 reg = ep->msi_cap + PCI_MSI_DATA_64;
409 msg_data = dw_pcie_readw_dbi(pci, reg);
410 } else {
411 msg_addr_upper = 0;
412 reg = ep->msi_cap + PCI_MSI_DATA_32;
413 msg_data = dw_pcie_readw_dbi(pci, reg);
414 }
415 aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
416 msg_addr = ((u64)msg_addr_upper) << 32 |
417 (msg_addr_lower & ~aligned_offset);
418 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
419 epc->mem->window.page_size);
420 if (ret)
421 return ret;
422
423 writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
424
425 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
426
427 return 0;
428}
429
430int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
431 u16 interrupt_num)
432{
433 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
434 struct pci_epf_msix_tbl *msix_tbl;
435 struct pci_epc *epc = ep->epc;
436 u32 reg, msg_data, vec_ctrl;
437 unsigned int aligned_offset;
438 u32 tbl_offset;
439 u64 msg_addr;
440 int ret;
441 u8 bir;
442
443 reg = ep->msix_cap + PCI_MSIX_TABLE;
444 tbl_offset = dw_pcie_readl_dbi(pci, reg);
445 bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
446 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
447
448 msix_tbl = ep->epf_bar[bir]->addr + tbl_offset;
449 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
450 msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
451 vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl;
452
453 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
454 dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
455 return -EPERM;
456 }
457
458 aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
459 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
460 epc->mem->window.page_size);
461 if (ret)
462 return ret;
463
464 writel(msg_data, ep->msi_mem + aligned_offset);
465
466 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
467
468 return 0;
469}
470
471void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
472{
473 struct pci_epc *epc = ep->epc;
474
475 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
476 epc->mem->window.page_size);
477
478 pci_epc_mem_exit(epc);
479}
480
481static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
482{
483 u32 header;
484 int pos = PCI_CFG_SPACE_SIZE;
485
486 while (pos) {
487 header = dw_pcie_readl_dbi(pci, pos);
488 if (PCI_EXT_CAP_ID(header) == cap)
489 return pos;
490
491 pos = PCI_EXT_CAP_NEXT(header);
492 if (!pos)
493 break;
494 }
495
496 return 0;
497}
498
499int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
500{
501 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
502 unsigned int offset;
503 unsigned int nbars;
504 u8 hdr_type;
505 u32 reg;
506 int i;
507
508 hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
509 if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
510 dev_err(pci->dev,
511 "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
512 hdr_type);
513 return -EIO;
514 }
515
516 ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
517
518 ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
519
520 offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
521 if (offset) {
522 reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
523 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
524 PCI_REBAR_CTRL_NBAR_SHIFT;
525
526 dw_pcie_dbi_ro_wr_en(pci);
527 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
528 dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
529 dw_pcie_dbi_ro_wr_dis(pci);
530 }
531
532 dw_pcie_setup(pci);
533
534 return 0;
535}
536EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
537
538int dw_pcie_ep_init(struct dw_pcie_ep *ep)
539{
540 int ret;
541 void *addr;
542 struct pci_epc *epc;
543 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
544 struct device *dev = pci->dev;
545 struct device_node *np = dev->of_node;
546 const struct pci_epc_features *epc_features;
547
548 if (!pci->dbi_base || !pci->dbi_base2) {
549 dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
550 return -EINVAL;
551 }
552
553 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
554 if (ret < 0) {
555 dev_err(dev, "Unable to read *num-ib-windows* property\n");
556 return ret;
557 }
558 if (ep->num_ib_windows > MAX_IATU_IN) {
559 dev_err(dev, "Invalid *num-ib-windows*\n");
560 return -EINVAL;
561 }
562
563 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
564 if (ret < 0) {
565 dev_err(dev, "Unable to read *num-ob-windows* property\n");
566 return ret;
567 }
568 if (ep->num_ob_windows > MAX_IATU_OUT) {
569 dev_err(dev, "Invalid *num-ob-windows*\n");
570 return -EINVAL;
571 }
572
573 ep->ib_window_map = devm_kcalloc(dev,
574 BITS_TO_LONGS(ep->num_ib_windows),
575 sizeof(long),
576 GFP_KERNEL);
577 if (!ep->ib_window_map)
578 return -ENOMEM;
579
580 ep->ob_window_map = devm_kcalloc(dev,
581 BITS_TO_LONGS(ep->num_ob_windows),
582 sizeof(long),
583 GFP_KERNEL);
584 if (!ep->ob_window_map)
585 return -ENOMEM;
586
587 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
588 GFP_KERNEL);
589 if (!addr)
590 return -ENOMEM;
591 ep->outbound_addr = addr;
592
593 epc = devm_pci_epc_create(dev, &epc_ops);
594 if (IS_ERR(epc)) {
595 dev_err(dev, "Failed to create epc device\n");
596 return PTR_ERR(epc);
597 }
598
599 ep->epc = epc;
600 epc_set_drvdata(epc, ep);
601
602 if (ep->ops->ep_init)
603 ep->ops->ep_init(ep);
604
605 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
606 if (ret < 0)
607 epc->max_functions = 1;
608
609 ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
610 ep->page_size);
611 if (ret < 0) {
612 dev_err(dev, "Failed to initialize address space\n");
613 return ret;
614 }
615
616 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
617 epc->mem->window.page_size);
618 if (!ep->msi_mem) {
619 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
620 return -ENOMEM;
621 }
622
623 if (ep->ops->get_features) {
624 epc_features = ep->ops->get_features(ep);
625 if (epc_features->core_init_notifier)
626 return 0;
627 }
628
629 return dw_pcie_ep_init_complete(ep);
630}
631EXPORT_SYMBOL_GPL(dw_pcie_ep_init);