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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19
20#include "pcie-designware.h"
21
22#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
23
24/* External local bus interface registers */
25#define PLR_OFFSET 0x700
26#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
27#define FAST_LINK_MODE BIT(7)
28#define LINK_CAPABLE_MASK GENMASK(21, 16)
29#define LINK_CAPABLE_X1 BIT(16)
30
31#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
32#define NUM_OF_LANES_MASK GENMASK(12, 8)
33#define NUM_OF_LANES_X1 BIT(8)
34#define DIRECT_SPEED_CHANGE BIT(17)
35
36#define TYPE1_HDR_OFFSET 0x0
37#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
38#define PCI_IO_EN BIT(0)
39#define PCI_MEM_SPACE_EN BIT(1)
40#define PCI_BUS_MASTER_EN BIT(2)
41
42#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
43#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
44
45#define PCIE_CAP_OFFSET 0x70
46#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
47#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
48#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
49#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
50#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
51
52/* PCIe specific config registers */
53#define PCIE_CFG0 0x0
54#define APP_LTSSM_ENABLE BIT(7)
55
56#define PCIE_CFG_STATUS12 0x30
57#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
58#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
59#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
60
61#define PCIE_CFG_STATUS17 0x44
62#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
63
64#define WAIT_LINKUP_TIMEOUT 4000
65#define PORT_CLK_RATE 100000000UL
66#define MAX_PAYLOAD_SIZE 256
67#define MAX_READ_REQ_SIZE 256
68#define MESON_PCIE_PHY_POWERUP 0x1c
69#define PCIE_RESET_DELAY 500
70#define PCIE_SHARED_RESET 1
71#define PCIE_NORMAL_RESET 0
72
73enum pcie_data_rate {
74 PCIE_GEN1,
75 PCIE_GEN2,
76 PCIE_GEN3,
77 PCIE_GEN4
78};
79
80struct meson_pcie_mem_res {
81 void __iomem *elbi_base;
82 void __iomem *cfg_base;
83 void __iomem *phy_base;
84};
85
86struct meson_pcie_clk_res {
87 struct clk *clk;
88 struct clk *mipi_gate;
89 struct clk *port_clk;
90 struct clk *general_clk;
91};
92
93struct meson_pcie_rc_reset {
94 struct reset_control *phy;
95 struct reset_control *port;
96 struct reset_control *apb;
97};
98
99struct meson_pcie {
100 struct dw_pcie pci;
101 struct meson_pcie_mem_res mem_res;
102 struct meson_pcie_clk_res clk_res;
103 struct meson_pcie_rc_reset mrst;
104 struct gpio_desc *reset_gpio;
105};
106
107static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
108 const char *id,
109 u32 reset_type)
110{
111 struct device *dev = mp->pci.dev;
112 struct reset_control *reset;
113
114 if (reset_type == PCIE_SHARED_RESET)
115 reset = devm_reset_control_get_shared(dev, id);
116 else
117 reset = devm_reset_control_get(dev, id);
118
119 return reset;
120}
121
122static int meson_pcie_get_resets(struct meson_pcie *mp)
123{
124 struct meson_pcie_rc_reset *mrst = &mp->mrst;
125
126 mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
127 if (IS_ERR(mrst->phy))
128 return PTR_ERR(mrst->phy);
129 reset_control_deassert(mrst->phy);
130
131 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
132 if (IS_ERR(mrst->port))
133 return PTR_ERR(mrst->port);
134 reset_control_deassert(mrst->port);
135
136 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
137 if (IS_ERR(mrst->apb))
138 return PTR_ERR(mrst->apb);
139 reset_control_deassert(mrst->apb);
140
141 return 0;
142}
143
144static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
145 struct meson_pcie *mp,
146 const char *id)
147{
148 struct device *dev = mp->pci.dev;
149 struct resource *res;
150
151 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
152
153 return devm_ioremap_resource(dev, res);
154}
155
156static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
157 struct meson_pcie *mp,
158 const char *id)
159{
160 struct device *dev = mp->pci.dev;
161 struct resource *res;
162
163 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
164 if (!res) {
165 dev_err(dev, "No REG resource %s\n", id);
166 return ERR_PTR(-ENXIO);
167 }
168
169 return devm_ioremap(dev, res->start, resource_size(res));
170}
171
172static int meson_pcie_get_mems(struct platform_device *pdev,
173 struct meson_pcie *mp)
174{
175 mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
176 if (IS_ERR(mp->mem_res.elbi_base))
177 return PTR_ERR(mp->mem_res.elbi_base);
178
179 mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
180 if (IS_ERR(mp->mem_res.cfg_base))
181 return PTR_ERR(mp->mem_res.cfg_base);
182
183 /* Meson SoC has two PCI controllers use same phy register*/
184 mp->mem_res.phy_base = meson_pcie_get_mem_shared(pdev, mp, "phy");
185 if (IS_ERR(mp->mem_res.phy_base))
186 return PTR_ERR(mp->mem_res.phy_base);
187
188 return 0;
189}
190
191static void meson_pcie_power_on(struct meson_pcie *mp)
192{
193 writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
194}
195
196static void meson_pcie_reset(struct meson_pcie *mp)
197{
198 struct meson_pcie_rc_reset *mrst = &mp->mrst;
199
200 reset_control_assert(mrst->phy);
201 udelay(PCIE_RESET_DELAY);
202 reset_control_deassert(mrst->phy);
203 udelay(PCIE_RESET_DELAY);
204
205 reset_control_assert(mrst->port);
206 reset_control_assert(mrst->apb);
207 udelay(PCIE_RESET_DELAY);
208 reset_control_deassert(mrst->port);
209 reset_control_deassert(mrst->apb);
210 udelay(PCIE_RESET_DELAY);
211}
212
213static inline struct clk *meson_pcie_probe_clock(struct device *dev,
214 const char *id, u64 rate)
215{
216 struct clk *clk;
217 int ret;
218
219 clk = devm_clk_get(dev, id);
220 if (IS_ERR(clk))
221 return clk;
222
223 if (rate) {
224 ret = clk_set_rate(clk, rate);
225 if (ret) {
226 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
227 return ERR_PTR(ret);
228 }
229 }
230
231 ret = clk_prepare_enable(clk);
232 if (ret) {
233 dev_err(dev, "couldn't enable clk\n");
234 return ERR_PTR(ret);
235 }
236
237 devm_add_action_or_reset(dev,
238 (void (*) (void *))clk_disable_unprepare,
239 clk);
240
241 return clk;
242}
243
244static int meson_pcie_probe_clocks(struct meson_pcie *mp)
245{
246 struct device *dev = mp->pci.dev;
247 struct meson_pcie_clk_res *res = &mp->clk_res;
248
249 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
250 if (IS_ERR(res->port_clk))
251 return PTR_ERR(res->port_clk);
252
253 res->mipi_gate = meson_pcie_probe_clock(dev, "pcie_mipi_en", 0);
254 if (IS_ERR(res->mipi_gate))
255 return PTR_ERR(res->mipi_gate);
256
257 res->general_clk = meson_pcie_probe_clock(dev, "pcie_general", 0);
258 if (IS_ERR(res->general_clk))
259 return PTR_ERR(res->general_clk);
260
261 res->clk = meson_pcie_probe_clock(dev, "pcie", 0);
262 if (IS_ERR(res->clk))
263 return PTR_ERR(res->clk);
264
265 return 0;
266}
267
268static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
269{
270 writel(val, mp->mem_res.elbi_base + reg);
271}
272
273static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
274{
275 return readl(mp->mem_res.elbi_base + reg);
276}
277
278static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
279{
280 return readl(mp->mem_res.cfg_base + reg);
281}
282
283static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
284{
285 writel(val, mp->mem_res.cfg_base + reg);
286}
287
288static void meson_pcie_assert_reset(struct meson_pcie *mp)
289{
290 gpiod_set_value_cansleep(mp->reset_gpio, 0);
291 udelay(500);
292 gpiod_set_value_cansleep(mp->reset_gpio, 1);
293}
294
295static void meson_pcie_init_dw(struct meson_pcie *mp)
296{
297 u32 val;
298
299 val = meson_cfg_readl(mp, PCIE_CFG0);
300 val |= APP_LTSSM_ENABLE;
301 meson_cfg_writel(mp, val, PCIE_CFG0);
302
303 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
304 val &= ~LINK_CAPABLE_MASK;
305 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
306
307 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
308 val |= LINK_CAPABLE_X1 | FAST_LINK_MODE;
309 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
310
311 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
312 val &= ~NUM_OF_LANES_MASK;
313 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
314
315 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
316 val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
317 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
318
319 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
320 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
321}
322
323static int meson_size_to_payload(struct meson_pcie *mp, int size)
324{
325 struct device *dev = mp->pci.dev;
326
327 /*
328 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
329 * So if input size is not 2^order alignment or less than 2^7 or bigger
330 * than 2^12, just set to default size 2^(1+7).
331 */
332 if (!is_power_of_2(size) || size < 128 || size > 4096) {
333 dev_warn(dev, "payload size %d, set to default 256\n", size);
334 return 1;
335 }
336
337 return fls(size) - 8;
338}
339
340static void meson_set_max_payload(struct meson_pcie *mp, int size)
341{
342 u32 val;
343 int max_payload_size = meson_size_to_payload(mp, size);
344
345 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
346 val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
347 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
348
349 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
350 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
351 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
352}
353
354static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
355{
356 u32 val;
357 int max_rd_req_size = meson_size_to_payload(mp, size);
358
359 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
360 val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
361 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
362
363 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
364 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
365 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
366}
367
368static inline void meson_enable_memory_space(struct meson_pcie *mp)
369{
370 /* Set the RC Bus Master, Memory Space and I/O Space enables */
371 meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
372 PCIE_STATUS_COMMAND);
373}
374
375static int meson_pcie_establish_link(struct meson_pcie *mp)
376{
377 struct dw_pcie *pci = &mp->pci;
378 struct pcie_port *pp = &pci->pp;
379
380 meson_pcie_init_dw(mp);
381 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
382 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
383
384 dw_pcie_setup_rc(pp);
385 meson_enable_memory_space(mp);
386
387 meson_pcie_assert_reset(mp);
388
389 return dw_pcie_wait_for_link(pci);
390}
391
392static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
393{
394 if (IS_ENABLED(CONFIG_PCI_MSI))
395 dw_pcie_msi_init(&mp->pci.pp);
396}
397
398static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
399 u32 *val)
400{
401 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
402 int ret;
403
404 ret = dw_pcie_read(pci->dbi_base + where, size, val);
405 if (ret != PCIBIOS_SUCCESSFUL)
406 return ret;
407
408 /*
409 * There is a bug in the MESON AXG PCIe controller whereby software
410 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
411 * the return value in the config accessors.
412 */
413 if (where == PCI_CLASS_REVISION && size == 4)
414 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
415 else if (where == PCI_CLASS_DEVICE && size == 2)
416 *val = PCI_CLASS_BRIDGE_PCI;
417 else if (where == PCI_CLASS_DEVICE && size == 1)
418 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
419 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
420 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
421
422 return PCIBIOS_SUCCESSFUL;
423}
424
425static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
426 int size, u32 val)
427{
428 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
429
430 return dw_pcie_write(pci->dbi_base + where, size, val);
431}
432
433static int meson_pcie_link_up(struct dw_pcie *pci)
434{
435 struct meson_pcie *mp = to_meson_pcie(pci);
436 struct device *dev = pci->dev;
437 u32 speed_okay = 0;
438 u32 cnt = 0;
439 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
440
441 do {
442 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
443 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
444 smlh_up = IS_SMLH_LINK_UP(state12);
445 rdlh_up = IS_RDLH_LINK_UP(state12);
446 ltssm_up = IS_LTSSM_UP(state12);
447
448 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
449 speed_okay = 1;
450
451 if (smlh_up)
452 dev_dbg(dev, "smlh_link_up is on\n");
453 if (rdlh_up)
454 dev_dbg(dev, "rdlh_link_up is on\n");
455 if (ltssm_up)
456 dev_dbg(dev, "ltssm_up is on\n");
457 if (speed_okay)
458 dev_dbg(dev, "speed_okay\n");
459
460 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
461 return 1;
462
463 cnt++;
464
465 udelay(10);
466 } while (cnt < WAIT_LINKUP_TIMEOUT);
467
468 dev_err(dev, "error: wait linkup timeout\n");
469 return 0;
470}
471
472static int meson_pcie_host_init(struct pcie_port *pp)
473{
474 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
475 struct meson_pcie *mp = to_meson_pcie(pci);
476 int ret;
477
478 ret = meson_pcie_establish_link(mp);
479 if (ret)
480 return ret;
481
482 meson_pcie_enable_interrupts(mp);
483
484 return 0;
485}
486
487static const struct dw_pcie_host_ops meson_pcie_host_ops = {
488 .rd_own_conf = meson_pcie_rd_own_conf,
489 .wr_own_conf = meson_pcie_wr_own_conf,
490 .host_init = meson_pcie_host_init,
491};
492
493static int meson_add_pcie_port(struct meson_pcie *mp,
494 struct platform_device *pdev)
495{
496 struct dw_pcie *pci = &mp->pci;
497 struct pcie_port *pp = &pci->pp;
498 struct device *dev = &pdev->dev;
499 int ret;
500
501 if (IS_ENABLED(CONFIG_PCI_MSI)) {
502 pp->msi_irq = platform_get_irq(pdev, 0);
503 if (pp->msi_irq < 0) {
504 dev_err(dev, "failed to get MSI IRQ\n");
505 return pp->msi_irq;
506 }
507 }
508
509 pp->ops = &meson_pcie_host_ops;
510 pci->dbi_base = mp->mem_res.elbi_base;
511
512 ret = dw_pcie_host_init(pp);
513 if (ret) {
514 dev_err(dev, "failed to initialize host\n");
515 return ret;
516 }
517
518 return 0;
519}
520
521static const struct dw_pcie_ops dw_pcie_ops = {
522 .link_up = meson_pcie_link_up,
523};
524
525static int meson_pcie_probe(struct platform_device *pdev)
526{
527 struct device *dev = &pdev->dev;
528 struct dw_pcie *pci;
529 struct meson_pcie *mp;
530 int ret;
531
532 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
533 if (!mp)
534 return -ENOMEM;
535
536 pci = &mp->pci;
537 pci->dev = dev;
538 pci->ops = &dw_pcie_ops;
539
540 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
541 if (IS_ERR(mp->reset_gpio)) {
542 dev_err(dev, "get reset gpio failed\n");
543 return PTR_ERR(mp->reset_gpio);
544 }
545
546 ret = meson_pcie_get_resets(mp);
547 if (ret) {
548 dev_err(dev, "get reset resource failed, %d\n", ret);
549 return ret;
550 }
551
552 ret = meson_pcie_get_mems(pdev, mp);
553 if (ret) {
554 dev_err(dev, "get memory resource failed, %d\n", ret);
555 return ret;
556 }
557
558 meson_pcie_power_on(mp);
559 meson_pcie_reset(mp);
560
561 ret = meson_pcie_probe_clocks(mp);
562 if (ret) {
563 dev_err(dev, "init clock resources failed, %d\n", ret);
564 return ret;
565 }
566
567 platform_set_drvdata(pdev, mp);
568
569 ret = meson_add_pcie_port(mp, pdev);
570 if (ret < 0) {
571 dev_err(dev, "Add PCIe port failed, %d\n", ret);
572 return ret;
573 }
574
575 return 0;
576}
577
578static const struct of_device_id meson_pcie_of_match[] = {
579 {
580 .compatible = "amlogic,axg-pcie",
581 },
582 {},
583};
584
585static struct platform_driver meson_pcie_driver = {
586 .probe = meson_pcie_probe,
587 .driver = {
588 .name = "meson-pcie",
589 .of_match_table = meson_pcie_of_match,
590 },
591};
592
593builtin_platform_driver(meson_pcie_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19#include <linux/phy/phy.h>
20
21#include "pcie-designware.h"
22
23#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
24
25/* External local bus interface registers */
26#define PLR_OFFSET 0x700
27#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
28#define FAST_LINK_MODE BIT(7)
29#define LINK_CAPABLE_MASK GENMASK(21, 16)
30#define LINK_CAPABLE_X1 BIT(16)
31
32#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
33#define NUM_OF_LANES_MASK GENMASK(12, 8)
34#define NUM_OF_LANES_X1 BIT(8)
35#define DIRECT_SPEED_CHANGE BIT(17)
36
37#define TYPE1_HDR_OFFSET 0x0
38#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
39#define PCI_IO_EN BIT(0)
40#define PCI_MEM_SPACE_EN BIT(1)
41#define PCI_BUS_MASTER_EN BIT(2)
42
43#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
44#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
45
46#define PCIE_CAP_OFFSET 0x70
47#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
48#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
49#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
50#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
51#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
52
53/* PCIe specific config registers */
54#define PCIE_CFG0 0x0
55#define APP_LTSSM_ENABLE BIT(7)
56
57#define PCIE_CFG_STATUS12 0x30
58#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
59#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
60#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
61
62#define PCIE_CFG_STATUS17 0x44
63#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
64
65#define WAIT_LINKUP_TIMEOUT 4000
66#define PORT_CLK_RATE 100000000UL
67#define MAX_PAYLOAD_SIZE 256
68#define MAX_READ_REQ_SIZE 256
69#define PCIE_RESET_DELAY 500
70#define PCIE_SHARED_RESET 1
71#define PCIE_NORMAL_RESET 0
72
73enum pcie_data_rate {
74 PCIE_GEN1,
75 PCIE_GEN2,
76 PCIE_GEN3,
77 PCIE_GEN4
78};
79
80struct meson_pcie_mem_res {
81 void __iomem *elbi_base;
82 void __iomem *cfg_base;
83};
84
85struct meson_pcie_clk_res {
86 struct clk *clk;
87 struct clk *port_clk;
88 struct clk *general_clk;
89};
90
91struct meson_pcie_rc_reset {
92 struct reset_control *port;
93 struct reset_control *apb;
94};
95
96struct meson_pcie {
97 struct dw_pcie pci;
98 struct meson_pcie_mem_res mem_res;
99 struct meson_pcie_clk_res clk_res;
100 struct meson_pcie_rc_reset mrst;
101 struct gpio_desc *reset_gpio;
102 struct phy *phy;
103};
104
105static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
106 const char *id,
107 u32 reset_type)
108{
109 struct device *dev = mp->pci.dev;
110 struct reset_control *reset;
111
112 if (reset_type == PCIE_SHARED_RESET)
113 reset = devm_reset_control_get_shared(dev, id);
114 else
115 reset = devm_reset_control_get(dev, id);
116
117 return reset;
118}
119
120static int meson_pcie_get_resets(struct meson_pcie *mp)
121{
122 struct meson_pcie_rc_reset *mrst = &mp->mrst;
123
124 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
125 if (IS_ERR(mrst->port))
126 return PTR_ERR(mrst->port);
127 reset_control_deassert(mrst->port);
128
129 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
130 if (IS_ERR(mrst->apb))
131 return PTR_ERR(mrst->apb);
132 reset_control_deassert(mrst->apb);
133
134 return 0;
135}
136
137static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
138 struct meson_pcie *mp,
139 const char *id)
140{
141 struct device *dev = mp->pci.dev;
142 struct resource *res;
143
144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
145
146 return devm_ioremap_resource(dev, res);
147}
148
149static int meson_pcie_get_mems(struct platform_device *pdev,
150 struct meson_pcie *mp)
151{
152 mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
153 if (IS_ERR(mp->mem_res.elbi_base))
154 return PTR_ERR(mp->mem_res.elbi_base);
155
156 mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
157 if (IS_ERR(mp->mem_res.cfg_base))
158 return PTR_ERR(mp->mem_res.cfg_base);
159
160 return 0;
161}
162
163static int meson_pcie_power_on(struct meson_pcie *mp)
164{
165 int ret = 0;
166
167 ret = phy_init(mp->phy);
168 if (ret)
169 return ret;
170
171 ret = phy_power_on(mp->phy);
172 if (ret) {
173 phy_exit(mp->phy);
174 return ret;
175 }
176
177 return 0;
178}
179
180static void meson_pcie_power_off(struct meson_pcie *mp)
181{
182 phy_power_off(mp->phy);
183 phy_exit(mp->phy);
184}
185
186static int meson_pcie_reset(struct meson_pcie *mp)
187{
188 struct meson_pcie_rc_reset *mrst = &mp->mrst;
189 int ret = 0;
190
191 ret = phy_reset(mp->phy);
192 if (ret)
193 return ret;
194
195 reset_control_assert(mrst->port);
196 reset_control_assert(mrst->apb);
197 udelay(PCIE_RESET_DELAY);
198 reset_control_deassert(mrst->port);
199 reset_control_deassert(mrst->apb);
200 udelay(PCIE_RESET_DELAY);
201
202 return 0;
203}
204
205static inline struct clk *meson_pcie_probe_clock(struct device *dev,
206 const char *id, u64 rate)
207{
208 struct clk *clk;
209 int ret;
210
211 clk = devm_clk_get(dev, id);
212 if (IS_ERR(clk))
213 return clk;
214
215 if (rate) {
216 ret = clk_set_rate(clk, rate);
217 if (ret) {
218 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
219 return ERR_PTR(ret);
220 }
221 }
222
223 ret = clk_prepare_enable(clk);
224 if (ret) {
225 dev_err(dev, "couldn't enable clk\n");
226 return ERR_PTR(ret);
227 }
228
229 devm_add_action_or_reset(dev,
230 (void (*) (void *))clk_disable_unprepare,
231 clk);
232
233 return clk;
234}
235
236static int meson_pcie_probe_clocks(struct meson_pcie *mp)
237{
238 struct device *dev = mp->pci.dev;
239 struct meson_pcie_clk_res *res = &mp->clk_res;
240
241 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
242 if (IS_ERR(res->port_clk))
243 return PTR_ERR(res->port_clk);
244
245 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
246 if (IS_ERR(res->general_clk))
247 return PTR_ERR(res->general_clk);
248
249 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
250 if (IS_ERR(res->clk))
251 return PTR_ERR(res->clk);
252
253 return 0;
254}
255
256static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
257{
258 writel(val, mp->mem_res.elbi_base + reg);
259}
260
261static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
262{
263 return readl(mp->mem_res.elbi_base + reg);
264}
265
266static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
267{
268 return readl(mp->mem_res.cfg_base + reg);
269}
270
271static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
272{
273 writel(val, mp->mem_res.cfg_base + reg);
274}
275
276static void meson_pcie_assert_reset(struct meson_pcie *mp)
277{
278 gpiod_set_value_cansleep(mp->reset_gpio, 1);
279 udelay(500);
280 gpiod_set_value_cansleep(mp->reset_gpio, 0);
281}
282
283static void meson_pcie_init_dw(struct meson_pcie *mp)
284{
285 u32 val;
286
287 val = meson_cfg_readl(mp, PCIE_CFG0);
288 val |= APP_LTSSM_ENABLE;
289 meson_cfg_writel(mp, val, PCIE_CFG0);
290
291 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
292 val &= ~(LINK_CAPABLE_MASK | FAST_LINK_MODE);
293 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
294
295 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
296 val |= LINK_CAPABLE_X1;
297 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
298
299 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
300 val &= ~NUM_OF_LANES_MASK;
301 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
302
303 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
304 val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
305 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
306
307 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
308 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
309}
310
311static int meson_size_to_payload(struct meson_pcie *mp, int size)
312{
313 struct device *dev = mp->pci.dev;
314
315 /*
316 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
317 * So if input size is not 2^order alignment or less than 2^7 or bigger
318 * than 2^12, just set to default size 2^(1+7).
319 */
320 if (!is_power_of_2(size) || size < 128 || size > 4096) {
321 dev_warn(dev, "payload size %d, set to default 256\n", size);
322 return 1;
323 }
324
325 return fls(size) - 8;
326}
327
328static void meson_set_max_payload(struct meson_pcie *mp, int size)
329{
330 u32 val;
331 int max_payload_size = meson_size_to_payload(mp, size);
332
333 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
334 val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
335 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
336
337 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
338 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
339 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
340}
341
342static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
343{
344 u32 val;
345 int max_rd_req_size = meson_size_to_payload(mp, size);
346
347 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
348 val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
349 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
350
351 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
352 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
353 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
354}
355
356static inline void meson_enable_memory_space(struct meson_pcie *mp)
357{
358 /* Set the RC Bus Master, Memory Space and I/O Space enables */
359 meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
360 PCIE_STATUS_COMMAND);
361}
362
363static int meson_pcie_establish_link(struct meson_pcie *mp)
364{
365 struct dw_pcie *pci = &mp->pci;
366 struct pcie_port *pp = &pci->pp;
367
368 meson_pcie_init_dw(mp);
369 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
370 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
371
372 dw_pcie_setup_rc(pp);
373 meson_enable_memory_space(mp);
374
375 meson_pcie_assert_reset(mp);
376
377 return dw_pcie_wait_for_link(pci);
378}
379
380static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
381{
382 if (IS_ENABLED(CONFIG_PCI_MSI))
383 dw_pcie_msi_init(&mp->pci.pp);
384}
385
386static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
387 u32 *val)
388{
389 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
390 int ret;
391
392 ret = dw_pcie_read(pci->dbi_base + where, size, val);
393 if (ret != PCIBIOS_SUCCESSFUL)
394 return ret;
395
396 /*
397 * There is a bug in the MESON AXG PCIe controller whereby software
398 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
399 * the return value in the config accessors.
400 */
401 if (where == PCI_CLASS_REVISION && size == 4)
402 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
403 else if (where == PCI_CLASS_DEVICE && size == 2)
404 *val = PCI_CLASS_BRIDGE_PCI;
405 else if (where == PCI_CLASS_DEVICE && size == 1)
406 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
407 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
408 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
409
410 return PCIBIOS_SUCCESSFUL;
411}
412
413static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
414 int size, u32 val)
415{
416 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
417
418 return dw_pcie_write(pci->dbi_base + where, size, val);
419}
420
421static int meson_pcie_link_up(struct dw_pcie *pci)
422{
423 struct meson_pcie *mp = to_meson_pcie(pci);
424 struct device *dev = pci->dev;
425 u32 speed_okay = 0;
426 u32 cnt = 0;
427 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
428
429 do {
430 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
431 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
432 smlh_up = IS_SMLH_LINK_UP(state12);
433 rdlh_up = IS_RDLH_LINK_UP(state12);
434 ltssm_up = IS_LTSSM_UP(state12);
435
436 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
437 speed_okay = 1;
438
439 if (smlh_up)
440 dev_dbg(dev, "smlh_link_up is on\n");
441 if (rdlh_up)
442 dev_dbg(dev, "rdlh_link_up is on\n");
443 if (ltssm_up)
444 dev_dbg(dev, "ltssm_up is on\n");
445 if (speed_okay)
446 dev_dbg(dev, "speed_okay\n");
447
448 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
449 return 1;
450
451 cnt++;
452
453 udelay(10);
454 } while (cnt < WAIT_LINKUP_TIMEOUT);
455
456 dev_err(dev, "error: wait linkup timeout\n");
457 return 0;
458}
459
460static int meson_pcie_host_init(struct pcie_port *pp)
461{
462 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
463 struct meson_pcie *mp = to_meson_pcie(pci);
464 int ret;
465
466 ret = meson_pcie_establish_link(mp);
467 if (ret)
468 return ret;
469
470 meson_pcie_enable_interrupts(mp);
471
472 return 0;
473}
474
475static const struct dw_pcie_host_ops meson_pcie_host_ops = {
476 .rd_own_conf = meson_pcie_rd_own_conf,
477 .wr_own_conf = meson_pcie_wr_own_conf,
478 .host_init = meson_pcie_host_init,
479};
480
481static int meson_add_pcie_port(struct meson_pcie *mp,
482 struct platform_device *pdev)
483{
484 struct dw_pcie *pci = &mp->pci;
485 struct pcie_port *pp = &pci->pp;
486 struct device *dev = &pdev->dev;
487 int ret;
488
489 if (IS_ENABLED(CONFIG_PCI_MSI)) {
490 pp->msi_irq = platform_get_irq(pdev, 0);
491 if (pp->msi_irq < 0)
492 return pp->msi_irq;
493 }
494
495 pp->ops = &meson_pcie_host_ops;
496 pci->dbi_base = mp->mem_res.elbi_base;
497
498 ret = dw_pcie_host_init(pp);
499 if (ret) {
500 dev_err(dev, "failed to initialize host\n");
501 return ret;
502 }
503
504 return 0;
505}
506
507static const struct dw_pcie_ops dw_pcie_ops = {
508 .link_up = meson_pcie_link_up,
509};
510
511static int meson_pcie_probe(struct platform_device *pdev)
512{
513 struct device *dev = &pdev->dev;
514 struct dw_pcie *pci;
515 struct meson_pcie *mp;
516 int ret;
517
518 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
519 if (!mp)
520 return -ENOMEM;
521
522 pci = &mp->pci;
523 pci->dev = dev;
524 pci->ops = &dw_pcie_ops;
525
526 mp->phy = devm_phy_get(dev, "pcie");
527 if (IS_ERR(mp->phy)) {
528 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
529 return PTR_ERR(mp->phy);
530 }
531
532 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
533 if (IS_ERR(mp->reset_gpio)) {
534 dev_err(dev, "get reset gpio failed\n");
535 return PTR_ERR(mp->reset_gpio);
536 }
537
538 ret = meson_pcie_get_resets(mp);
539 if (ret) {
540 dev_err(dev, "get reset resource failed, %d\n", ret);
541 return ret;
542 }
543
544 ret = meson_pcie_get_mems(pdev, mp);
545 if (ret) {
546 dev_err(dev, "get memory resource failed, %d\n", ret);
547 return ret;
548 }
549
550 ret = meson_pcie_power_on(mp);
551 if (ret) {
552 dev_err(dev, "phy power on failed, %d\n", ret);
553 return ret;
554 }
555
556 ret = meson_pcie_reset(mp);
557 if (ret) {
558 dev_err(dev, "reset failed, %d\n", ret);
559 goto err_phy;
560 }
561
562 ret = meson_pcie_probe_clocks(mp);
563 if (ret) {
564 dev_err(dev, "init clock resources failed, %d\n", ret);
565 goto err_phy;
566 }
567
568 platform_set_drvdata(pdev, mp);
569
570 ret = meson_add_pcie_port(mp, pdev);
571 if (ret < 0) {
572 dev_err(dev, "Add PCIe port failed, %d\n", ret);
573 goto err_phy;
574 }
575
576 return 0;
577
578err_phy:
579 meson_pcie_power_off(mp);
580 return ret;
581}
582
583static const struct of_device_id meson_pcie_of_match[] = {
584 {
585 .compatible = "amlogic,axg-pcie",
586 },
587 {
588 .compatible = "amlogic,g12a-pcie",
589 },
590 {},
591};
592
593static struct platform_driver meson_pcie_driver = {
594 .probe = meson_pcie_probe,
595 .driver = {
596 .name = "meson-pcie",
597 .of_match_table = meson_pcie_of_match,
598 },
599};
600
601builtin_platform_driver(meson_pcie_driver);