1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
 4 */
 5
 6#ifndef MEMORY_TEGRA_MC_H
 7#define MEMORY_TEGRA_MC_H
 8
 9#include <linux/io.h>
10#include <linux/types.h>
11
12#include <soc/tegra/mc.h>
13
14#define MC_INT_DECERR_MTS (1 << 16)
15#define MC_INT_SECERR_SEC (1 << 13)
16#define MC_INT_DECERR_VPR (1 << 12)
17#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
18#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
19#define MC_INT_ARBITRATION_EMEM (1 << 9)
20#define MC_INT_SECURITY_VIOLATION (1 << 8)
21#define MC_INT_INVALID_GART_PAGE (1 << 7)
22#define MC_INT_DECERR_EMEM (1 << 6)
23
24static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
25{
26	return readl_relaxed(mc->regs + offset);
27}
28
29static inline void mc_writel(struct tegra_mc *mc, u32 value,
30			     unsigned long offset)
31{
32	writel_relaxed(value, mc->regs + offset);
33}
34
35extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
36
37#ifdef CONFIG_ARCH_TEGRA_2x_SOC
38extern const struct tegra_mc_soc tegra20_mc_soc;
39#endif
40
41#ifdef CONFIG_ARCH_TEGRA_3x_SOC
42extern const struct tegra_mc_soc tegra30_mc_soc;
43#endif
44
45#ifdef CONFIG_ARCH_TEGRA_114_SOC
46extern const struct tegra_mc_soc tegra114_mc_soc;
47#endif
48
49#ifdef CONFIG_ARCH_TEGRA_124_SOC
50extern const struct tegra_mc_soc tegra124_mc_soc;
51#endif
52
53#ifdef CONFIG_ARCH_TEGRA_132_SOC
54extern const struct tegra_mc_soc tegra132_mc_soc;
55#endif
56
57#ifdef CONFIG_ARCH_TEGRA_210_SOC
58extern const struct tegra_mc_soc tegra210_mc_soc;
59#endif
60
61#endif /* MEMORY_TEGRA_MC_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
 4 */
 5
 6#ifndef MEMORY_TEGRA_MC_H
 7#define MEMORY_TEGRA_MC_H
 8
 9#include <linux/io.h>
10#include <linux/types.h>
11
12#include <soc/tegra/mc.h>
13
14#define MC_INT_DECERR_MTS (1 << 16)
15#define MC_INT_SECERR_SEC (1 << 13)
16#define MC_INT_DECERR_VPR (1 << 12)
17#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
18#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
19#define MC_INT_ARBITRATION_EMEM (1 << 9)
20#define MC_INT_SECURITY_VIOLATION (1 << 8)
21#define MC_INT_INVALID_GART_PAGE (1 << 7)
22#define MC_INT_DECERR_EMEM (1 << 6)
23
24static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
25{
26	return readl_relaxed(mc->regs + offset);
27}
28
29static inline void mc_writel(struct tegra_mc *mc, u32 value,
30			     unsigned long offset)
31{
32	writel_relaxed(value, mc->regs + offset);
33}
34
35extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
36
37#ifdef CONFIG_ARCH_TEGRA_2x_SOC
38extern const struct tegra_mc_soc tegra20_mc_soc;
39#endif
40
41#ifdef CONFIG_ARCH_TEGRA_3x_SOC
42extern const struct tegra_mc_soc tegra30_mc_soc;
43#endif
44
45#ifdef CONFIG_ARCH_TEGRA_114_SOC
46extern const struct tegra_mc_soc tegra114_mc_soc;
47#endif
48
49#ifdef CONFIG_ARCH_TEGRA_124_SOC
50extern const struct tegra_mc_soc tegra124_mc_soc;
51#endif
52
53#ifdef CONFIG_ARCH_TEGRA_132_SOC
54extern const struct tegra_mc_soc tegra132_mc_soc;
55#endif
56
57#ifdef CONFIG_ARCH_TEGRA_210_SOC
58extern const struct tegra_mc_soc tegra210_mc_soc;
59#endif
60
61#endif /* MEMORY_TEGRA_MC_H */