1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4#ifndef _ICE_ADMINQ_CMD_H_
   5#define _ICE_ADMINQ_CMD_H_
   6
   7/* This header file defines the Admin Queue commands, error codes and
   8 * descriptor format. It is shared between Firmware and Software.
   9 */
  10
  11#define ICE_MAX_VSI			768
  12#define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9
  13#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728
  14
  15struct ice_aqc_generic {
  16	__le32 param0;
  17	__le32 param1;
  18	__le32 addr_high;
  19	__le32 addr_low;
  20};
  21
  22/* Get version (direct 0x0001) */
  23struct ice_aqc_get_ver {
  24	__le32 rom_ver;
  25	__le32 fw_build;
  26	u8 fw_branch;
  27	u8 fw_major;
  28	u8 fw_minor;
  29	u8 fw_patch;
  30	u8 api_branch;
  31	u8 api_major;
  32	u8 api_minor;
  33	u8 api_patch;
  34};
  35
  36/* Send driver version (indirect 0x0002) */
  37struct ice_aqc_driver_ver {
  38	u8 major_ver;
  39	u8 minor_ver;
  40	u8 build_ver;
  41	u8 subbuild_ver;
  42	u8 reserved[4];
  43	__le32 addr_high;
  44	__le32 addr_low;
  45};
  46
  47/* Queue Shutdown (direct 0x0003) */
  48struct ice_aqc_q_shutdown {
  49	u8 driver_unloading;
  50#define ICE_AQC_DRIVER_UNLOADING	BIT(0)
  51	u8 reserved[15];
  52};
  53
  54/* Request resource ownership (direct 0x0008)
  55 * Release resource ownership (direct 0x0009)
  56 */
  57struct ice_aqc_req_res {
  58	__le16 res_id;
  59#define ICE_AQC_RES_ID_NVM		1
  60#define ICE_AQC_RES_ID_SDP		2
  61#define ICE_AQC_RES_ID_CHNG_LOCK	3
  62#define ICE_AQC_RES_ID_GLBL_LOCK	4
  63	__le16 access_type;
  64#define ICE_AQC_RES_ACCESS_READ		1
  65#define ICE_AQC_RES_ACCESS_WRITE	2
  66
  67	/* Upon successful completion, FW writes this value and driver is
  68	 * expected to release resource before timeout. This value is provided
  69	 * in milliseconds.
  70	 */
  71	__le32 timeout;
  72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000
  73#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000
  74#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000
  75#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000
  76	/* For SDP: pin ID of the SDP */
  77	__le32 res_number;
  78	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
  79	__le16 status;
  80#define ICE_AQ_RES_GLBL_SUCCESS		0
  81#define ICE_AQ_RES_GLBL_IN_PROG		1
  82#define ICE_AQ_RES_GLBL_DONE		2
  83	u8 reserved[2];
  84};
  85
  86/* Get function capabilities (indirect 0x000A)
  87 * Get device capabilities (indirect 0x000B)
  88 */
  89struct ice_aqc_list_caps {
  90	u8 cmd_flags;
  91	u8 pf_index;
  92	u8 reserved[2];
  93	__le32 count;
  94	__le32 addr_high;
  95	__le32 addr_low;
  96};
  97
  98/* Device/Function buffer entry, repeated per reported capability */
  99struct ice_aqc_list_caps_elem {
 100	__le16 cap;
 101#define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
 102#define ICE_AQC_CAPS_SRIOV				0x0012
 103#define ICE_AQC_CAPS_VF					0x0013
 104#define ICE_AQC_CAPS_VSI				0x0017
 105#define ICE_AQC_CAPS_DCB				0x0018
 106#define ICE_AQC_CAPS_RSS				0x0040
 107#define ICE_AQC_CAPS_RXQS				0x0041
 108#define ICE_AQC_CAPS_TXQS				0x0042
 109#define ICE_AQC_CAPS_MSIX				0x0043
 
 
 110#define ICE_AQC_CAPS_MAX_MTU				0x0047
 
 
 
 
 
 
 
 
 111
 112	u8 major_ver;
 113	u8 minor_ver;
 114	/* Number of resources described by this capability */
 115	__le32 number;
 116	/* Only meaningful for some types of resources */
 117	__le32 logical_id;
 118	/* Only meaningful for some types of resources */
 119	__le32 phys_id;
 120	__le64 rsvd1;
 121	__le64 rsvd2;
 122};
 123
 124/* Manage MAC address, read command - indirect (0x0107)
 125 * This struct is also used for the response
 126 */
 127struct ice_aqc_manage_mac_read {
 128	__le16 flags; /* Zeroed by device driver */
 129#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID		BIT(4)
 130#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID		BIT(5)
 131#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID		BIT(6)
 132#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID		BIT(7)
 133#define ICE_AQC_MAN_MAC_READ_S			4
 134#define ICE_AQC_MAN_MAC_READ_M			(0xF << ICE_AQC_MAN_MAC_READ_S)
 135	u8 rsvd[2];
 136	u8 num_addr; /* Used in response */
 137	u8 rsvd1[3];
 138	__le32 addr_high;
 139	__le32 addr_low;
 140};
 141
 142/* Response buffer format for manage MAC read command */
 143struct ice_aqc_manage_mac_read_resp {
 144	u8 lport_num;
 145	u8 addr_type;
 146#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN		0
 147#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL		1
 148	u8 mac_addr[ETH_ALEN];
 149};
 150
 151/* Manage MAC address, write command - direct (0x0108) */
 152struct ice_aqc_manage_mac_write {
 153	u8 rsvd;
 154	u8 flags;
 155#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN		BIT(0)
 156#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP	BIT(1)
 157#define ICE_AQC_MAN_MAC_WR_S		6
 158#define ICE_AQC_MAN_MAC_WR_M		(3 << ICE_AQC_MAN_MAC_WR_S)
 159#define ICE_AQC_MAN_MAC_UPDATE_LAA	0
 160#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL	(BIT(0) << ICE_AQC_MAN_MAC_WR_S)
 161	/* High 16 bits of MAC address in big endian order */
 162	__be16 sah;
 163	/* Low 32 bits of MAC address in big endian order */
 164	__be32 sal;
 165	__le32 addr_high;
 166	__le32 addr_low;
 167};
 168
 169/* Clear PXE Command and response (direct 0x0110) */
 170struct ice_aqc_clear_pxe {
 171	u8 rx_cnt;
 172#define ICE_AQC_CLEAR_PXE_RX_CNT		0x2
 173	u8 reserved[15];
 174};
 175
 176/* Get switch configuration (0x0200) */
 177struct ice_aqc_get_sw_cfg {
 178	/* Reserved for command and copy of request flags for response */
 179	__le16 flags;
 180	/* First desc in case of command and next_elem in case of response
 181	 * In case of response, if it is not zero, means all the configuration
 182	 * was not returned and new command shall be sent with this value in
 183	 * the 'first desc' field
 184	 */
 185	__le16 element;
 186	/* Reserved for command, only used for response */
 187	__le16 num_elems;
 188	__le16 rsvd;
 189	__le32 addr_high;
 190	__le32 addr_low;
 191};
 192
 193/* Each entry in the response buffer is of the following type: */
 194struct ice_aqc_get_sw_cfg_resp_elem {
 195	/* VSI/Port Number */
 196	__le16 vsi_port_num;
 197#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S	0
 198#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M	\
 199			(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
 200#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S	14
 201#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M	(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
 202#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT	0
 203#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT	1
 204#define ICE_AQC_GET_SW_CONF_RESP_VSI		2
 205
 206	/* SWID VSI/Port belongs to */
 207	__le16 swid;
 208
 209	/* Bit 14..0 : PF/VF number VSI belongs to
 210	 * Bit 15 : VF indication bit
 211	 */
 212	__le16 pf_vf_num;
 213#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S	0
 214#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M	\
 215				(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
 216#define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)
 217};
 218
 219/* The response buffer is as follows. Note that the length of the
 220 * elements array varies with the length of the command response.
 221 */
 222struct ice_aqc_get_sw_cfg_resp {
 223	struct ice_aqc_get_sw_cfg_resp_elem elements[1];
 224};
 225
 226/* These resource type defines are used for all switch resource
 227 * commands where a resource type is required, such as:
 228 * Get Resource Allocation command (indirect 0x0204)
 229 * Allocate Resources command (indirect 0x0208)
 230 * Free Resources command (indirect 0x0209)
 231 * Get Allocated Resource Descriptors Command (indirect 0x020A)
 232 */
 233#define ICE_AQC_RES_TYPE_VSI_LIST_REP			0x03
 234#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE			0x04
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 235
 236/* Allocate Resources command (indirect 0x0208)
 237 * Free Resources command (indirect 0x0209)
 238 */
 239struct ice_aqc_alloc_free_res_cmd {
 240	__le16 num_entries; /* Number of Resource entries */
 241	u8 reserved[6];
 242	__le32 addr_high;
 243	__le32 addr_low;
 244};
 245
 246/* Resource descriptor */
 247struct ice_aqc_res_elem {
 248	union {
 249		__le16 sw_resp;
 250		__le16 flu_resp;
 251	} e;
 252};
 253
 254/* Buffer for Allocate/Free Resources commands */
 255struct ice_aqc_alloc_free_res_elem {
 256	__le16 res_type; /* Types defined above cmd 0x0204 */
 257#define ICE_AQC_RES_TYPE_SHARED_S	7
 258#define ICE_AQC_RES_TYPE_SHARED_M	(0x1 << ICE_AQC_RES_TYPE_SHARED_S)
 259#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S	8
 260#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M	\
 261				(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
 262	__le16 num_elems;
 263	struct ice_aqc_res_elem elem[1];
 264};
 265
 266/* Add VSI (indirect 0x0210)
 267 * Update VSI (indirect 0x0211)
 268 * Get VSI (indirect 0x0212)
 269 * Free VSI (indirect 0x0213)
 270 */
 271struct ice_aqc_add_get_update_free_vsi {
 272	__le16 vsi_num;
 273#define ICE_AQ_VSI_NUM_S	0
 274#define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)
 275#define ICE_AQ_VSI_IS_VALID	BIT(15)
 276	__le16 cmd_flags;
 277#define ICE_AQ_VSI_KEEP_ALLOC	0x1
 278	u8 vf_id;
 279	u8 reserved;
 280	__le16 vsi_flags;
 281#define ICE_AQ_VSI_TYPE_S	0
 282#define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)
 283#define ICE_AQ_VSI_TYPE_VF	0x0
 284#define ICE_AQ_VSI_TYPE_VMDQ2	0x1
 285#define ICE_AQ_VSI_TYPE_PF	0x2
 286#define ICE_AQ_VSI_TYPE_EMP_MNG	0x3
 287	__le32 addr_high;
 288	__le32 addr_low;
 289};
 290
 291/* Response descriptor for:
 292 * Add VSI (indirect 0x0210)
 293 * Update VSI (indirect 0x0211)
 294 * Free VSI (indirect 0x0213)
 295 */
 296struct ice_aqc_add_update_free_vsi_resp {
 297	__le16 vsi_num;
 298	__le16 ext_status;
 299	__le16 vsi_used;
 300	__le16 vsi_free;
 301	__le32 addr_high;
 302	__le32 addr_low;
 303};
 304
 305struct ice_aqc_vsi_props {
 306	__le16 valid_sections;
 307#define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)
 308#define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)
 309#define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)
 310#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)
 311#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)
 312#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)
 313#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)
 314#define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)
 315#define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)
 316#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)
 317#define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)
 318	/* switch section */
 319	u8 sw_id;
 320	u8 sw_flags;
 321#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)
 322#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)
 323#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)
 324	u8 sw_flags2;
 325#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
 326#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	\
 327				(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
 328#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
 329#define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
 330	u8 veb_stat_id;
 331#define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
 332#define ICE_AQ_VSI_SW_VEB_STAT_ID_M	(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
 333#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)
 334	/* security section */
 335	u8 sec_flags;
 336#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)
 337#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)
 338#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S	4
 339#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M	(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
 340#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)
 341	u8 sec_reserved;
 342	/* VLAN section */
 343	__le16 pvid; /* VLANS include priority bits */
 344	u8 pvlan_reserved[2];
 345	u8 vlan_flags;
 346#define ICE_AQ_VSI_VLAN_MODE_S	0
 347#define ICE_AQ_VSI_VLAN_MODE_M	(0x3 << ICE_AQ_VSI_VLAN_MODE_S)
 348#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED	0x1
 349#define ICE_AQ_VSI_VLAN_MODE_TAGGED	0x2
 350#define ICE_AQ_VSI_VLAN_MODE_ALL	0x3
 351#define ICE_AQ_VSI_PVLAN_INSERT_PVID	BIT(2)
 352#define ICE_AQ_VSI_VLAN_EMOD_S		3
 353#define ICE_AQ_VSI_VLAN_EMOD_M		(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
 354#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH	(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
 355#define ICE_AQ_VSI_VLAN_EMOD_STR_UP	(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
 356#define ICE_AQ_VSI_VLAN_EMOD_STR	(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
 357#define ICE_AQ_VSI_VLAN_EMOD_NOTHING	(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
 358	u8 pvlan_reserved2[3];
 359	/* ingress egress up sections */
 360	__le32 ingress_table; /* bitmap, 3 bits per up */
 361#define ICE_AQ_VSI_UP_TABLE_UP0_S	0
 362#define ICE_AQ_VSI_UP_TABLE_UP0_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
 363#define ICE_AQ_VSI_UP_TABLE_UP1_S	3
 364#define ICE_AQ_VSI_UP_TABLE_UP1_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
 365#define ICE_AQ_VSI_UP_TABLE_UP2_S	6
 366#define ICE_AQ_VSI_UP_TABLE_UP2_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
 367#define ICE_AQ_VSI_UP_TABLE_UP3_S	9
 368#define ICE_AQ_VSI_UP_TABLE_UP3_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
 369#define ICE_AQ_VSI_UP_TABLE_UP4_S	12
 370#define ICE_AQ_VSI_UP_TABLE_UP4_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
 371#define ICE_AQ_VSI_UP_TABLE_UP5_S	15
 372#define ICE_AQ_VSI_UP_TABLE_UP5_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
 373#define ICE_AQ_VSI_UP_TABLE_UP6_S	18
 374#define ICE_AQ_VSI_UP_TABLE_UP6_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
 375#define ICE_AQ_VSI_UP_TABLE_UP7_S	21
 376#define ICE_AQ_VSI_UP_TABLE_UP7_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
 377	__le32 egress_table;   /* same defines as for ingress table */
 378	/* outer tags section */
 379	__le16 outer_tag;
 380	u8 outer_tag_flags;
 381#define ICE_AQ_VSI_OUTER_TAG_MODE_S	0
 382#define ICE_AQ_VSI_OUTER_TAG_MODE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
 383#define ICE_AQ_VSI_OUTER_TAG_NOTHING	0x0
 384#define ICE_AQ_VSI_OUTER_TAG_REMOVE	0x1
 385#define ICE_AQ_VSI_OUTER_TAG_COPY	0x2
 386#define ICE_AQ_VSI_OUTER_TAG_TYPE_S	2
 387#define ICE_AQ_VSI_OUTER_TAG_TYPE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
 388#define ICE_AQ_VSI_OUTER_TAG_NONE	0x0
 389#define ICE_AQ_VSI_OUTER_TAG_STAG	0x1
 390#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100	0x2
 391#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100	0x3
 392#define ICE_AQ_VSI_OUTER_TAG_INSERT	BIT(4)
 393#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
 394	u8 outer_tag_reserved;
 395	/* queue mapping section */
 396	__le16 mapping_flags;
 397#define ICE_AQ_VSI_Q_MAP_CONTIG	0x0
 398#define ICE_AQ_VSI_Q_MAP_NONCONTIG	BIT(0)
 399	__le16 q_mapping[16];
 400#define ICE_AQ_VSI_Q_S		0
 401#define ICE_AQ_VSI_Q_M		(0x7FF << ICE_AQ_VSI_Q_S)
 402	__le16 tc_mapping[8];
 403#define ICE_AQ_VSI_TC_Q_OFFSET_S	0
 404#define ICE_AQ_VSI_TC_Q_OFFSET_M	(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
 405#define ICE_AQ_VSI_TC_Q_NUM_S		11
 406#define ICE_AQ_VSI_TC_Q_NUM_M		(0xF << ICE_AQ_VSI_TC_Q_NUM_S)
 407	/* queueing option section */
 408	u8 q_opt_rss;
 409#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S	0
 410#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
 411#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI	0x0
 412#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF	0x2
 413#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL	0x3
 414#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S	2
 415#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M	(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
 416#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S	6
 417#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
 418#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ	(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
 419#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ	(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
 420#define ICE_AQ_VSI_Q_OPT_RSS_XOR	(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
 421#define ICE_AQ_VSI_Q_OPT_RSS_JHASH	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
 422	u8 q_opt_tc;
 423#define ICE_AQ_VSI_Q_OPT_TC_OVR_S	0
 424#define ICE_AQ_VSI_Q_OPT_TC_OVR_M	(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
 425#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR	BIT(7)
 426	u8 q_opt_flags;
 427#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN	BIT(0)
 428	u8 q_opt_reserved[3];
 429	/* outer up section */
 430	__le32 outer_up_table; /* same structure and defines as ingress tbl */
 431	/* section 10 */
 432	__le16 sect_10_reserved;
 433	/* flow director section */
 434	__le16 fd_options;
 435#define ICE_AQ_VSI_FD_ENABLE		BIT(0)
 436#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE	BIT(1)
 437#define ICE_AQ_VSI_FD_PROG_ENABLE	BIT(3)
 438	__le16 max_fd_fltr_dedicated;
 439	__le16 max_fd_fltr_shared;
 440	__le16 fd_def_q;
 441#define ICE_AQ_VSI_FD_DEF_Q_S		0
 442#define ICE_AQ_VSI_FD_DEF_Q_M		(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
 443#define ICE_AQ_VSI_FD_DEF_GRP_S	12
 444#define ICE_AQ_VSI_FD_DEF_GRP_M	(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
 445	__le16 fd_report_opt;
 446#define ICE_AQ_VSI_FD_REPORT_Q_S	0
 447#define ICE_AQ_VSI_FD_REPORT_Q_M	(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
 448#define ICE_AQ_VSI_FD_DEF_PRIORITY_S	12
 449#define ICE_AQ_VSI_FD_DEF_PRIORITY_M	(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
 450#define ICE_AQ_VSI_FD_DEF_DROP		BIT(15)
 451	/* PASID section */
 452	__le32 pasid_id;
 453#define ICE_AQ_VSI_PASID_ID_S		0
 454#define ICE_AQ_VSI_PASID_ID_M		(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
 455#define ICE_AQ_VSI_PASID_ID_VALID	BIT(31)
 456	u8 reserved[24];
 457};
 458
 459#define ICE_MAX_NUM_RECIPES 64
 460
 461/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
 462 */
 463struct ice_aqc_sw_rules {
 464	/* ops: add switch rules, referring the number of rules.
 465	 * ops: update switch rules, referring the number of filters
 466	 * ops: remove switch rules, referring the entry index.
 467	 * ops: get switch rules, referring to the number of filters.
 468	 */
 469	__le16 num_rules_fltr_entry_index;
 470	u8 reserved[6];
 471	__le32 addr_high;
 472	__le32 addr_low;
 473};
 474
 475/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
 476 * This structures describes the lookup rules and associated actions. "index"
 477 * is returned as part of a response to a successful Add command, and can be
 478 * used to identify the rule for Update/Get/Remove commands.
 479 */
 480struct ice_sw_rule_lkup_rx_tx {
 481	__le16 recipe_id;
 482#define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
 483	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
 484	__le16 src;
 485	__le32 act;
 486
 487	/* Bit 0:1 - Action type */
 488#define ICE_SINGLE_ACT_TYPE_S	0x00
 489#define ICE_SINGLE_ACT_TYPE_M	(0x3 << ICE_SINGLE_ACT_TYPE_S)
 490
 491	/* Bit 2 - Loop back enable
 492	 * Bit 3 - LAN enable
 493	 */
 494#define ICE_SINGLE_ACT_LB_ENABLE	BIT(2)
 495#define ICE_SINGLE_ACT_LAN_ENABLE	BIT(3)
 496
 497	/* Action type = 0 - Forward to VSI or VSI list */
 498#define ICE_SINGLE_ACT_VSI_FORWARDING	0x0
 499
 500#define ICE_SINGLE_ACT_VSI_ID_S		4
 501#define ICE_SINGLE_ACT_VSI_ID_M		(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
 502#define ICE_SINGLE_ACT_VSI_LIST_ID_S	4
 503#define ICE_SINGLE_ACT_VSI_LIST_ID_M	(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
 504	/* This bit needs to be set if action is forward to VSI list */
 505#define ICE_SINGLE_ACT_VSI_LIST		BIT(14)
 506#define ICE_SINGLE_ACT_VALID_BIT	BIT(17)
 507#define ICE_SINGLE_ACT_DROP		BIT(18)
 508
 509	/* Action type = 1 - Forward to Queue of Queue group */
 510#define ICE_SINGLE_ACT_TO_Q		0x1
 511#define ICE_SINGLE_ACT_Q_INDEX_S	4
 512#define ICE_SINGLE_ACT_Q_INDEX_M	(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
 513#define ICE_SINGLE_ACT_Q_REGION_S	15
 514#define ICE_SINGLE_ACT_Q_REGION_M	(0x7 << ICE_SINGLE_ACT_Q_REGION_S)
 515#define ICE_SINGLE_ACT_Q_PRIORITY	BIT(18)
 516
 517	/* Action type = 2 - Prune */
 518#define ICE_SINGLE_ACT_PRUNE		0x2
 519#define ICE_SINGLE_ACT_EGRESS		BIT(15)
 520#define ICE_SINGLE_ACT_INGRESS		BIT(16)
 521#define ICE_SINGLE_ACT_PRUNET		BIT(17)
 522	/* Bit 18 should be set to 0 for this action */
 523
 524	/* Action type = 2 - Pointer */
 525#define ICE_SINGLE_ACT_PTR		0x2
 526#define ICE_SINGLE_ACT_PTR_VAL_S	4
 527#define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
 528	/* Bit 18 should be set to 1 */
 529#define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
 530
 531	/* Action type = 3 - Other actions. Last two bits
 532	 * are other action identifier
 533	 */
 534#define ICE_SINGLE_ACT_OTHER_ACTS		0x3
 535#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S	17
 536#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M	\
 537				(0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
 538
 539	/* Bit 17:18 - Defines other actions */
 540	/* Other action = 0 - Mirror VSI */
 541#define ICE_SINGLE_OTHER_ACT_MIRROR		0
 542#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S	4
 543#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M	\
 544				(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
 545
 546	/* Other action = 3 - Set Stat count */
 547#define ICE_SINGLE_OTHER_ACT_STAT_COUNT		3
 548#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S	4
 549#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M	\
 550				(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
 551
 552	__le16 index; /* The index of the rule in the lookup table */
 553	/* Length and values of the header to be matched per recipe or
 554	 * lookup-type
 555	 */
 556	__le16 hdr_len;
 557	u8 hdr[1];
 558} __packed;
 559
 560/* Add/Update/Remove large action command/response entry
 561 * "index" is returned as part of a response to a successful Add command, and
 562 * can be used to identify the action for Update/Get/Remove commands.
 563 */
 564struct ice_sw_rule_lg_act {
 565	__le16 index; /* Index in large action table */
 566	__le16 size;
 567	__le32 act[1]; /* array of size for actions */
 568	/* Max number of large actions */
 569#define ICE_MAX_LG_ACT	4
 570	/* Bit 0:1 - Action type */
 571#define ICE_LG_ACT_TYPE_S	0
 572#define ICE_LG_ACT_TYPE_M	(0x7 << ICE_LG_ACT_TYPE_S)
 573
 574	/* Action type = 0 - Forward to VSI or VSI list */
 575#define ICE_LG_ACT_VSI_FORWARDING	0
 576#define ICE_LG_ACT_VSI_ID_S		3
 577#define ICE_LG_ACT_VSI_ID_M		(0x3FF << ICE_LG_ACT_VSI_ID_S)
 578#define ICE_LG_ACT_VSI_LIST_ID_S	3
 579#define ICE_LG_ACT_VSI_LIST_ID_M	(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
 580	/* This bit needs to be set if action is forward to VSI list */
 581#define ICE_LG_ACT_VSI_LIST		BIT(13)
 582
 583#define ICE_LG_ACT_VALID_BIT		BIT(16)
 584
 585	/* Action type = 1 - Forward to Queue of Queue group */
 586#define ICE_LG_ACT_TO_Q			0x1
 587#define ICE_LG_ACT_Q_INDEX_S		3
 588#define ICE_LG_ACT_Q_INDEX_M		(0x7FF << ICE_LG_ACT_Q_INDEX_S)
 589#define ICE_LG_ACT_Q_REGION_S		14
 590#define ICE_LG_ACT_Q_REGION_M		(0x7 << ICE_LG_ACT_Q_REGION_S)
 591#define ICE_LG_ACT_Q_PRIORITY_SET	BIT(17)
 592
 593	/* Action type = 2 - Prune */
 594#define ICE_LG_ACT_PRUNE		0x2
 595#define ICE_LG_ACT_EGRESS		BIT(14)
 596#define ICE_LG_ACT_INGRESS		BIT(15)
 597#define ICE_LG_ACT_PRUNET		BIT(16)
 598
 599	/* Action type = 3 - Mirror VSI */
 600#define ICE_LG_OTHER_ACT_MIRROR		0x3
 601#define ICE_LG_ACT_MIRROR_VSI_ID_S	3
 602#define ICE_LG_ACT_MIRROR_VSI_ID_M	(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
 603
 604	/* Action type = 5 - Generic Value */
 605#define ICE_LG_ACT_GENERIC		0x5
 606#define ICE_LG_ACT_GENERIC_VALUE_S	3
 607#define ICE_LG_ACT_GENERIC_VALUE_M	(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
 608#define ICE_LG_ACT_GENERIC_OFFSET_S	19
 609#define ICE_LG_ACT_GENERIC_OFFSET_M	(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
 610#define ICE_LG_ACT_GENERIC_PRIORITY_S	22
 611#define ICE_LG_ACT_GENERIC_PRIORITY_M	(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
 612#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX	7
 613
 614	/* Action = 7 - Set Stat count */
 615#define ICE_LG_ACT_STAT_COUNT		0x7
 616#define ICE_LG_ACT_STAT_COUNT_S		3
 617#define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
 
 618};
 619
 620/* Add/Update/Remove VSI list command/response entry
 621 * "index" is returned as part of a response to a successful Add command, and
 622 * can be used to identify the VSI list for Update/Get/Remove commands.
 623 */
 624struct ice_sw_rule_vsi_list {
 625	__le16 index; /* Index of VSI/Prune list */
 626	__le16 number_vsi;
 627	__le16 vsi[1]; /* Array of number_vsi VSI numbers */
 628};
 629
 630/* Query VSI list command/response entry */
 631struct ice_sw_rule_vsi_list_query {
 632	__le16 index;
 633	DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
 634} __packed;
 635
 636/* Add switch rule response:
 637 * Content of return buffer is same as the input buffer. The status field and
 638 * LUT index are updated as part of the response
 639 */
 640struct ice_aqc_sw_rules_elem {
 641	__le16 type; /* Switch rule type, one of T_... */
 642#define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
 643#define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
 644#define ICE_AQC_SW_RULES_T_LG_ACT		0x2
 645#define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
 646#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
 647#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
 648#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
 649	__le16 status;
 650	union {
 651		struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
 652		struct ice_sw_rule_lg_act lg_act;
 653		struct ice_sw_rule_vsi_list vsi_list;
 654		struct ice_sw_rule_vsi_list_query vsi_list_query;
 655	} __packed pdata;
 656};
 657
 658/* Get Default Topology (indirect 0x0400) */
 659struct ice_aqc_get_topo {
 660	u8 port_num;
 661	u8 num_branches;
 662	__le16 reserved1;
 663	__le32 reserved2;
 664	__le32 addr_high;
 665	__le32 addr_low;
 666};
 667
 668/* Update TSE (indirect 0x0403)
 669 * Get TSE (indirect 0x0404)
 670 * Add TSE (indirect 0x0401)
 671 * Delete TSE (indirect 0x040F)
 672 * Move TSE (indirect 0x0408)
 673 * Suspend Nodes (indirect 0x0409)
 674 * Resume Nodes (indirect 0x040A)
 675 */
 676struct ice_aqc_sched_elem_cmd {
 677	__le16 num_elem_req;	/* Used by commands */
 678	__le16 num_elem_resp;	/* Used by responses */
 679	__le32 reserved;
 680	__le32 addr_high;
 681	__le32 addr_low;
 682};
 683
 684/* This is the buffer for:
 685 * Suspend Nodes (indirect 0x0409)
 686 * Resume Nodes (indirect 0x040A)
 687 */
 688struct ice_aqc_suspend_resume_elem {
 689	__le32 teid[1];
 
 
 
 
 690};
 691
 692struct ice_aqc_elem_info_bw {
 693	__le16 bw_profile_idx;
 694	__le16 bw_alloc;
 695};
 696
 697struct ice_aqc_txsched_elem {
 698	u8 elem_type; /* Special field, reserved for some aq calls */
 699#define ICE_AQC_ELEM_TYPE_UNDEFINED		0x0
 700#define ICE_AQC_ELEM_TYPE_ROOT_PORT		0x1
 701#define ICE_AQC_ELEM_TYPE_TC			0x2
 702#define ICE_AQC_ELEM_TYPE_SE_GENERIC		0x3
 703#define ICE_AQC_ELEM_TYPE_ENTRY_POINT		0x4
 704#define ICE_AQC_ELEM_TYPE_LEAF			0x5
 705#define ICE_AQC_ELEM_TYPE_SE_PADDED		0x6
 706	u8 valid_sections;
 707#define ICE_AQC_ELEM_VALID_GENERIC		BIT(0)
 708#define ICE_AQC_ELEM_VALID_CIR			BIT(1)
 709#define ICE_AQC_ELEM_VALID_EIR			BIT(2)
 710#define ICE_AQC_ELEM_VALID_SHARED		BIT(3)
 711	u8 generic;
 712#define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
 713#define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
 714#define ICE_AQC_ELEM_GENERIC_PRIO_M	(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
 715#define ICE_AQC_ELEM_GENERIC_SP_S		0x4
 716#define ICE_AQC_ELEM_GENERIC_SP_M	(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
 717#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
 718#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
 719	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
 720	u8 flags; /* Special field, reserved for some aq calls */
 721#define ICE_AQC_ELEM_FLAG_SUSPEND_M		0x1
 722	struct ice_aqc_elem_info_bw cir_bw;
 723	struct ice_aqc_elem_info_bw eir_bw;
 724	__le16 srl_id;
 725	__le16 reserved2;
 726};
 727
 728struct ice_aqc_txsched_elem_data {
 729	__le32 parent_teid;
 730	__le32 node_teid;
 731	struct ice_aqc_txsched_elem data;
 732};
 733
 734struct ice_aqc_txsched_topo_grp_info_hdr {
 735	__le32 parent_teid;
 736	__le16 num_elems;
 737	__le16 reserved2;
 738};
 739
 740struct ice_aqc_add_elem {
 741	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
 742	struct ice_aqc_txsched_elem_data generic[1];
 743};
 744
 745struct ice_aqc_get_elem {
 746	struct ice_aqc_txsched_elem_data generic[1];
 747};
 748
 749struct ice_aqc_get_topo_elem {
 750	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
 751	struct ice_aqc_txsched_elem_data
 752		generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
 753};
 754
 755struct ice_aqc_delete_elem {
 756	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
 757	__le32 teid[1];
 758};
 759
 760/* Query Port ETS (indirect 0x040E)
 761 *
 762 * This indirect command is used to query port TC node configuration.
 763 */
 764struct ice_aqc_query_port_ets {
 765	__le32 port_teid;
 766	__le32 reserved;
 767	__le32 addr_high;
 768	__le32 addr_low;
 769};
 770
 771struct ice_aqc_port_ets_elem {
 772	u8 tc_valid_bits;
 773	u8 reserved[3];
 774	/* 3 bits for UP per TC 0-7, 4th byte reserved */
 775	__le32 up2tc;
 776	u8 tc_bw_share[8];
 777	__le32 port_eir_prof_id;
 778	__le32 port_cir_prof_id;
 779	/* 3 bits per Node priority to TC 0-7, 4th byte reserved */
 780	__le32 tc_node_prio;
 781#define ICE_TC_NODE_PRIO_S	0x4
 782	u8 reserved1[4];
 783	__le32 tc_node_teid[8]; /* Used for response, reserved in command */
 784};
 785
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 786/* Query Scheduler Resource Allocation (indirect 0x0412)
 787 * This indirect command retrieves the scheduler resources allocated by
 788 * EMP Firmware to the given PF.
 789 */
 790struct ice_aqc_query_txsched_res {
 791	u8 reserved[8];
 792	__le32 addr_high;
 793	__le32 addr_low;
 794};
 795
 796struct ice_aqc_generic_sched_props {
 797	__le16 phys_levels;
 798	__le16 logical_levels;
 799	u8 flattening_bitmap;
 800	u8 max_device_cgds;
 801	u8 max_pf_cgds;
 802	u8 rsvd0;
 803	__le16 rdma_qsets;
 804	u8 rsvd1[22];
 805};
 806
 807struct ice_aqc_layer_props {
 808	u8 logical_layer;
 809	u8 chunk_size;
 810	__le16 max_device_nodes;
 811	__le16 max_pf_nodes;
 812	u8 rsvd0[4];
 813	__le16 max_sibl_grp_sz;
 814	__le16 max_cir_rl_profiles;
 815	__le16 max_eir_rl_profiles;
 816	__le16 max_srl_profiles;
 817	u8 rsvd1[14];
 818};
 819
 820struct ice_aqc_query_txsched_res_resp {
 821	struct ice_aqc_generic_sched_props sched_props;
 822	struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
 823};
 824
 825/* Get PHY capabilities (indirect 0x0600) */
 826struct ice_aqc_get_phy_caps {
 827	u8 lport_num;
 828	u8 reserved;
 829	__le16 param0;
 830	/* 18.0 - Report qualified modules */
 831#define ICE_AQC_GET_PHY_RQM		BIT(0)
 832	/* 18.1 - 18.2 : Report mode
 833	 * 00b - Report NVM capabilities
 834	 * 01b - Report topology capabilities
 835	 * 10b - Report SW configured
 
 836	 */
 837#define ICE_AQC_REPORT_MODE_S		1
 838#define ICE_AQC_REPORT_MODE_M		(3 << ICE_AQC_REPORT_MODE_S)
 839#define ICE_AQC_REPORT_NVM_CAP		0
 840#define ICE_AQC_REPORT_TOPO_CAP		BIT(1)
 841#define ICE_AQC_REPORT_SW_CFG		BIT(2)
 
 842	__le32 reserved1;
 843	__le32 addr_high;
 844	__le32 addr_low;
 845};
 846
 847/* This is #define of PHY type (Extended):
 848 * The first set of defines is for phy_type_low.
 849 */
 850#define ICE_PHY_TYPE_LOW_100BASE_TX		BIT_ULL(0)
 851#define ICE_PHY_TYPE_LOW_100M_SGMII		BIT_ULL(1)
 852#define ICE_PHY_TYPE_LOW_1000BASE_T		BIT_ULL(2)
 853#define ICE_PHY_TYPE_LOW_1000BASE_SX		BIT_ULL(3)
 854#define ICE_PHY_TYPE_LOW_1000BASE_LX		BIT_ULL(4)
 855#define ICE_PHY_TYPE_LOW_1000BASE_KX		BIT_ULL(5)
 856#define ICE_PHY_TYPE_LOW_1G_SGMII		BIT_ULL(6)
 857#define ICE_PHY_TYPE_LOW_2500BASE_T		BIT_ULL(7)
 858#define ICE_PHY_TYPE_LOW_2500BASE_X		BIT_ULL(8)
 859#define ICE_PHY_TYPE_LOW_2500BASE_KX		BIT_ULL(9)
 860#define ICE_PHY_TYPE_LOW_5GBASE_T		BIT_ULL(10)
 861#define ICE_PHY_TYPE_LOW_5GBASE_KR		BIT_ULL(11)
 862#define ICE_PHY_TYPE_LOW_10GBASE_T		BIT_ULL(12)
 863#define ICE_PHY_TYPE_LOW_10G_SFI_DA		BIT_ULL(13)
 864#define ICE_PHY_TYPE_LOW_10GBASE_SR		BIT_ULL(14)
 865#define ICE_PHY_TYPE_LOW_10GBASE_LR		BIT_ULL(15)
 866#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1		BIT_ULL(16)
 867#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC	BIT_ULL(17)
 868#define ICE_PHY_TYPE_LOW_10G_SFI_C2C		BIT_ULL(18)
 869#define ICE_PHY_TYPE_LOW_25GBASE_T		BIT_ULL(19)
 870#define ICE_PHY_TYPE_LOW_25GBASE_CR		BIT_ULL(20)
 871#define ICE_PHY_TYPE_LOW_25GBASE_CR_S		BIT_ULL(21)
 872#define ICE_PHY_TYPE_LOW_25GBASE_CR1		BIT_ULL(22)
 873#define ICE_PHY_TYPE_LOW_25GBASE_SR		BIT_ULL(23)
 874#define ICE_PHY_TYPE_LOW_25GBASE_LR		BIT_ULL(24)
 875#define ICE_PHY_TYPE_LOW_25GBASE_KR		BIT_ULL(25)
 876#define ICE_PHY_TYPE_LOW_25GBASE_KR_S		BIT_ULL(26)
 877#define ICE_PHY_TYPE_LOW_25GBASE_KR1		BIT_ULL(27)
 878#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC	BIT_ULL(28)
 879#define ICE_PHY_TYPE_LOW_25G_AUI_C2C		BIT_ULL(29)
 880#define ICE_PHY_TYPE_LOW_40GBASE_CR4		BIT_ULL(30)
 881#define ICE_PHY_TYPE_LOW_40GBASE_SR4		BIT_ULL(31)
 882#define ICE_PHY_TYPE_LOW_40GBASE_LR4		BIT_ULL(32)
 883#define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)
 884#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)
 885#define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)
 886#define ICE_PHY_TYPE_LOW_50GBASE_CR2		BIT_ULL(36)
 887#define ICE_PHY_TYPE_LOW_50GBASE_SR2		BIT_ULL(37)
 888#define ICE_PHY_TYPE_LOW_50GBASE_LR2		BIT_ULL(38)
 889#define ICE_PHY_TYPE_LOW_50GBASE_KR2		BIT_ULL(39)
 890#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC	BIT_ULL(40)
 891#define ICE_PHY_TYPE_LOW_50G_LAUI2		BIT_ULL(41)
 892#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC	BIT_ULL(42)
 893#define ICE_PHY_TYPE_LOW_50G_AUI2		BIT_ULL(43)
 894#define ICE_PHY_TYPE_LOW_50GBASE_CP		BIT_ULL(44)
 895#define ICE_PHY_TYPE_LOW_50GBASE_SR		BIT_ULL(45)
 896#define ICE_PHY_TYPE_LOW_50GBASE_FR		BIT_ULL(46)
 897#define ICE_PHY_TYPE_LOW_50GBASE_LR		BIT_ULL(47)
 898#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4	BIT_ULL(48)
 899#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC	BIT_ULL(49)
 900#define ICE_PHY_TYPE_LOW_50G_AUI1		BIT_ULL(50)
 901#define ICE_PHY_TYPE_LOW_100GBASE_CR4		BIT_ULL(51)
 902#define ICE_PHY_TYPE_LOW_100GBASE_SR4		BIT_ULL(52)
 903#define ICE_PHY_TYPE_LOW_100GBASE_LR4		BIT_ULL(53)
 904#define ICE_PHY_TYPE_LOW_100GBASE_KR4		BIT_ULL(54)
 905#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC	BIT_ULL(55)
 906#define ICE_PHY_TYPE_LOW_100G_CAUI4		BIT_ULL(56)
 907#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC	BIT_ULL(57)
 908#define ICE_PHY_TYPE_LOW_100G_AUI4		BIT_ULL(58)
 909#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4	BIT_ULL(59)
 910#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4	BIT_ULL(60)
 911#define ICE_PHY_TYPE_LOW_100GBASE_CP2		BIT_ULL(61)
 912#define ICE_PHY_TYPE_LOW_100GBASE_SR2		BIT_ULL(62)
 913#define ICE_PHY_TYPE_LOW_100GBASE_DR		BIT_ULL(63)
 914#define ICE_PHY_TYPE_LOW_MAX_INDEX		63
 915/* The second set of defines is for phy_type_high. */
 916#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4	BIT_ULL(0)
 917#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC	BIT_ULL(1)
 918#define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)
 919#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)
 920#define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)
 921#define ICE_PHY_TYPE_HIGH_MAX_INDEX		19
 922
 923struct ice_aqc_get_phy_caps_data {
 924	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
 925	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
 926	u8 caps;
 927#define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)
 928#define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
 929#define ICE_AQC_PHY_LOW_POWER_MODE			BIT(2)
 930#define ICE_AQC_PHY_EN_LINK				BIT(3)
 931#define ICE_AQC_PHY_AN_MODE				BIT(4)
 932#define ICE_AQC_GET_PHY_EN_MOD_QUAL			BIT(5)
 933#define ICE_AQC_PHY_EN_AUTO_FEC				BIT(7)
 934#define ICE_AQC_PHY_CAPS_MASK				ICE_M(0xff, 0)
 935	u8 low_power_ctrl;
 936#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)
 
 
 
 937	__le16 eee_cap;
 938#define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)
 939#define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
 940#define ICE_AQC_PHY_EEE_EN_10GBASE_T			BIT(2)
 941#define ICE_AQC_PHY_EEE_EN_1000BASE_KX			BIT(3)
 942#define ICE_AQC_PHY_EEE_EN_10GBASE_KR			BIT(4)
 943#define ICE_AQC_PHY_EEE_EN_25GBASE_KR			BIT(5)
 944#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4			BIT(6)
 945	__le16 eeer_value;
 946	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
 947	u8 phy_fw_ver[8];
 948	u8 link_fec_options;
 949#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN		BIT(0)
 950#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ		BIT(1)
 951#define ICE_AQC_PHY_FEC_25G_RS_528_REQ			BIT(2)
 952#define ICE_AQC_PHY_FEC_25G_KR_REQ			BIT(3)
 953#define ICE_AQC_PHY_FEC_25G_RS_544_REQ			BIT(4)
 954#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)
 955#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)
 956#define ICE_AQC_PHY_FEC_MASK				ICE_M(0xdf, 0)
 957	u8 rsvd1;	/* Byte 35 reserved */
 
 958	u8 extended_compliance_code;
 959#define ICE_MODULE_TYPE_TOTAL_BYTE			3
 960	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
 961#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0
 962#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80
 
 963#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)
 964#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)
 965#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
 966#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR		BIT(5)
 967#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM		BIT(6)
 968#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER		BIT(7)
 969#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS			0xA0
 970#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS		0x86
 971	u8 qualified_module_count;
 972	u8 rsvd2[7];	/* Bytes 47:41 reserved */
 973#define ICE_AQC_QUAL_MOD_COUNT_MAX			16
 974	struct {
 975		u8 v_oui[3];
 976		u8 rsvd3;
 977		u8 v_part[16];
 978		__le32 v_rev;
 979		__le64 rsvd4;
 980	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
 981};
 982
 983/* Set PHY capabilities (direct 0x0601)
 984 * NOTE: This command must be followed by setup link and restart auto-neg
 985 */
 986struct ice_aqc_set_phy_cfg {
 987	u8 lport_num;
 988	u8 reserved[7];
 989	__le32 addr_high;
 990	__le32 addr_low;
 991};
 992
 993/* Set PHY config command data structure */
 994struct ice_aqc_set_phy_cfg_data {
 995	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
 996	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
 997	u8 caps;
 998#define ICE_AQ_PHY_ENA_VALID_MASK	ICE_M(0xef, 0)
 999#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)
1000#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)
1001#define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)
1002#define ICE_AQ_PHY_ENA_LINK		BIT(3)
1003#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)
1004#define ICE_AQ_PHY_ENA_LESM		BIT(6)
1005#define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)
1006	u8 low_power_ctrl;
1007	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1008	__le16 eeer_value;
1009	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1010	u8 rsvd1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1011};
1012
1013/* Restart AN command data structure (direct 0x0605)
1014 * Also used for response, with only the lport_num field present.
1015 */
1016struct ice_aqc_restart_an {
1017	u8 lport_num;
1018	u8 reserved;
1019	u8 cmd_flags;
1020#define ICE_AQC_RESTART_AN_LINK_RESTART	BIT(1)
1021#define ICE_AQC_RESTART_AN_LINK_ENABLE	BIT(2)
1022	u8 reserved2[13];
1023};
1024
1025/* Get link status (indirect 0x0607), also used for Link Status Event */
1026struct ice_aqc_get_link_status {
1027	u8 lport_num;
1028	u8 reserved;
1029	__le16 cmd_flags;
1030#define ICE_AQ_LSE_M			0x3
1031#define ICE_AQ_LSE_NOP			0x0
1032#define ICE_AQ_LSE_DIS			0x2
1033#define ICE_AQ_LSE_ENA			0x3
1034	/* only response uses this flag */
1035#define ICE_AQ_LSE_IS_ENABLED		0x1
1036	__le32 reserved2;
1037	__le32 addr_high;
1038	__le32 addr_low;
1039};
1040
1041/* Get link status response data structure, also used for Link Status Event */
1042struct ice_aqc_get_link_status_data {
1043	u8 topo_media_conflict;
1044#define ICE_AQ_LINK_TOPO_CONFLICT	BIT(0)
1045#define ICE_AQ_LINK_MEDIA_CONFLICT	BIT(1)
1046#define ICE_AQ_LINK_TOPO_CORRUPT	BIT(2)
1047	u8 reserved1;
 
 
 
 
 
 
1048	u8 link_info;
1049#define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
1050#define ICE_AQ_LINK_FAULT		BIT(1)
1051#define ICE_AQ_LINK_FAULT_TX		BIT(2)
1052#define ICE_AQ_LINK_FAULT_RX		BIT(3)
1053#define ICE_AQ_LINK_FAULT_REMOTE	BIT(4)
1054#define ICE_AQ_LINK_UP_PORT		BIT(5)	/* External Port Link Status */
1055#define ICE_AQ_MEDIA_AVAILABLE		BIT(6)
1056#define ICE_AQ_SIGNAL_DETECT		BIT(7)
1057	u8 an_info;
1058#define ICE_AQ_AN_COMPLETED		BIT(0)
1059#define ICE_AQ_LP_AN_ABILITY		BIT(1)
1060#define ICE_AQ_PD_FAULT			BIT(2)	/* Parallel Detection Fault */
1061#define ICE_AQ_FEC_EN			BIT(3)
1062#define ICE_AQ_PHY_LOW_POWER		BIT(4)	/* Low Power State */
1063#define ICE_AQ_LINK_PAUSE_TX		BIT(5)
1064#define ICE_AQ_LINK_PAUSE_RX		BIT(6)
1065#define ICE_AQ_QUALIFIED_MODULE		BIT(7)
1066	u8 ext_info;
1067#define ICE_AQ_LINK_PHY_TEMP_ALARM	BIT(0)
1068#define ICE_AQ_LINK_EXCESSIVE_ERRORS	BIT(1)	/* Excessive Link Errors */
1069	/* Port Tx Suspended */
1070#define ICE_AQ_LINK_TX_S		2
1071#define ICE_AQ_LINK_TX_M		(0x03 << ICE_AQ_LINK_TX_S)
1072#define ICE_AQ_LINK_TX_ACTIVE		0
1073#define ICE_AQ_LINK_TX_DRAINED		1
1074#define ICE_AQ_LINK_TX_FLUSHED		3
1075	u8 reserved2;
1076	__le16 max_frame_size;
1077	u8 cfg;
1078#define ICE_AQ_LINK_25G_KR_FEC_EN	BIT(0)
1079#define ICE_AQ_LINK_25G_RS_528_FEC_EN	BIT(1)
1080#define ICE_AQ_LINK_25G_RS_544_FEC_EN	BIT(2)
1081#define ICE_AQ_FEC_MASK			ICE_M(0x7, 0)
1082	/* Pacing Config */
1083#define ICE_AQ_CFG_PACING_S		3
1084#define ICE_AQ_CFG_PACING_M		(0xF << ICE_AQ_CFG_PACING_S)
1085#define ICE_AQ_CFG_PACING_TYPE_M	BIT(7)
1086#define ICE_AQ_CFG_PACING_TYPE_AVG	0
1087#define ICE_AQ_CFG_PACING_TYPE_FIXED	ICE_AQ_CFG_PACING_TYPE_M
1088	/* External Device Power Ability */
1089	u8 power_desc;
1090#define ICE_AQ_PWR_CLASS_M		0x3
1091#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH	0
1092#define ICE_AQ_LINK_PWR_BASET_HIGH	1
1093#define ICE_AQ_LINK_PWR_QSFP_CLASS_1	0
1094#define ICE_AQ_LINK_PWR_QSFP_CLASS_2	1
1095#define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2
1096#define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3
1097	__le16 link_speed;
 
1098#define ICE_AQ_LINK_SPEED_10MB		BIT(0)
1099#define ICE_AQ_LINK_SPEED_100MB		BIT(1)
1100#define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
1101#define ICE_AQ_LINK_SPEED_2500MB	BIT(3)
1102#define ICE_AQ_LINK_SPEED_5GB		BIT(4)
1103#define ICE_AQ_LINK_SPEED_10GB		BIT(5)
1104#define ICE_AQ_LINK_SPEED_20GB		BIT(6)
1105#define ICE_AQ_LINK_SPEED_25GB		BIT(7)
1106#define ICE_AQ_LINK_SPEED_40GB		BIT(8)
1107#define ICE_AQ_LINK_SPEED_50GB		BIT(9)
1108#define ICE_AQ_LINK_SPEED_100GB		BIT(10)
1109#define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)
1110	__le32 reserved3; /* Aligns next field to 8-byte boundary */
1111	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1112	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1113};
1114
1115/* Set event mask command (direct 0x0613) */
1116struct ice_aqc_set_event_mask {
1117	u8	lport_num;
1118	u8	reserved[7];
1119	__le16	event_mask;
1120#define ICE_AQ_LINK_EVENT_UPDOWN		BIT(1)
1121#define ICE_AQ_LINK_EVENT_MEDIA_NA		BIT(2)
1122#define ICE_AQ_LINK_EVENT_LINK_FAULT		BIT(3)
1123#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM	BIT(4)
1124#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS	BIT(5)
1125#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT		BIT(6)
1126#define ICE_AQ_LINK_EVENT_AN_COMPLETED		BIT(7)
1127#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL	BIT(8)
1128#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
1129	u8	reserved1[6];
1130};
1131
1132/* Set MAC Loopback command (direct 0x0620) */
1133struct ice_aqc_set_mac_lb {
1134	u8 lb_mode;
1135#define ICE_AQ_MAC_LB_EN		BIT(0)
1136#define ICE_AQ_MAC_LB_OSC_CLK		BIT(1)
1137	u8 reserved[15];
1138};
1139
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1140/* Set Port Identification LED (direct, 0x06E9) */
1141struct ice_aqc_set_port_id_led {
1142	u8 lport_num;
1143	u8 lport_num_valid;
1144	u8 ident_mode;
1145#define ICE_AQC_PORT_IDENT_LED_BLINK	BIT(0)
1146#define ICE_AQC_PORT_IDENT_LED_ORIG	0
1147	u8 rsvd[13];
1148};
1149
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1150/* NVM Read command (indirect 0x0701)
1151 * NVM Erase commands (direct 0x0702)
1152 * NVM Update commands (indirect 0x0703)
1153 */
1154struct ice_aqc_nvm {
 
1155	__le16 offset_low;
1156	u8 offset_high;
1157	u8 cmd_flags;
1158#define ICE_AQC_NVM_LAST_CMD		BIT(0)
1159#define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Update reply */
1160#define ICE_AQC_NVM_PRESERVATION_S	1
1161#define ICE_AQC_NVM_PRESERVATION_M	(3 << ICE_AQC_NVM_PRESERVATION_S)
1162#define ICE_AQC_NVM_NO_PRESERVATION	(0 << ICE_AQC_NVM_PRESERVATION_S)
1163#define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)
 
1164#define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << ICE_AQC_NVM_PRESERVATION_S)
 
 
 
 
 
 
1165#define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
1166	__le16 module_typeid;
1167	__le16 length;
1168#define ICE_AQC_NVM_ERASE_LEN	0xFFFF
1169	__le32 addr_high;
1170	__le32 addr_low;
1171};
1172
 
 
1173/* NVM Checksum Command (direct, 0x0706) */
1174struct ice_aqc_nvm_checksum {
1175	u8 flags;
1176#define ICE_AQC_NVM_CHECKSUM_VERIFY	BIT(0)
1177#define ICE_AQC_NVM_CHECKSUM_RECALC	BIT(1)
1178	u8 rsvd;
1179	__le16 checksum; /* Used only by response */
1180#define ICE_AQC_NVM_CHECKSUM_CORRECT	0xBABA
1181	u8 rsvd2[12];
1182};
1183
1184/**
1185 * Send to PF command (indirect 0x0801) ID is only used by PF
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1186 *
1187 * Send to VF command (indirect 0x0802) ID is only used by PF
1188 *
1189 */
1190struct ice_aqc_pf_vf_msg {
1191	__le32 id;
1192	u32 reserved;
1193	__le32 addr_high;
1194	__le32 addr_low;
1195};
1196
1197/* Get LLDP MIB (indirect 0x0A00)
1198 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1199 * as the format is the same.
1200 */
1201struct ice_aqc_lldp_get_mib {
1202	u8 type;
1203#define ICE_AQ_LLDP_MIB_TYPE_S			0
1204#define ICE_AQ_LLDP_MIB_TYPE_M			(0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1205#define ICE_AQ_LLDP_MIB_LOCAL			0
1206#define ICE_AQ_LLDP_MIB_REMOTE			1
1207#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE	2
1208#define ICE_AQ_LLDP_BRID_TYPE_S			2
1209#define ICE_AQ_LLDP_BRID_TYPE_M			(0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1210#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID	0
1211#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR		1
1212/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1213#define ICE_AQ_LLDP_TX_S			0x4
1214#define ICE_AQ_LLDP_TX_M			(0x03 << ICE_AQ_LLDP_TX_S)
1215#define ICE_AQ_LLDP_TX_ACTIVE			0
1216#define ICE_AQ_LLDP_TX_SUSPENDED		1
1217#define ICE_AQ_LLDP_TX_FLUSHED			3
1218/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1219 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1220 * Get LLDP MIB (0x0A00) response only.
1221 */
1222	u8 reserved1;
1223	__le16 local_len;
1224	__le16 remote_len;
1225	u8 reserved2[2];
1226	__le32 addr_high;
1227	__le32 addr_low;
1228};
1229
1230/* Configure LLDP MIB Change Event (direct 0x0A01) */
1231/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1232struct ice_aqc_lldp_set_mib_change {
1233	u8 command;
1234#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE		0x0
1235#define ICE_AQ_LLDP_MIB_UPDATE_DIS		0x1
1236	u8 reserved[15];
1237};
1238
1239/* Stop LLDP (direct 0x0A05) */
1240struct ice_aqc_lldp_stop {
1241	u8 command;
1242#define ICE_AQ_LLDP_AGENT_STATE_MASK	BIT(0)
1243#define ICE_AQ_LLDP_AGENT_STOP		0x0
1244#define ICE_AQ_LLDP_AGENT_SHUTDOWN	ICE_AQ_LLDP_AGENT_STATE_MASK
1245#define ICE_AQ_LLDP_AGENT_PERSIST_DIS	BIT(1)
1246	u8 reserved[15];
1247};
1248
1249/* Start LLDP (direct 0x0A06) */
1250struct ice_aqc_lldp_start {
1251	u8 command;
1252#define ICE_AQ_LLDP_AGENT_START		BIT(0)
1253#define ICE_AQ_LLDP_AGENT_PERSIST_ENA	BIT(1)
1254	u8 reserved[15];
1255};
1256
1257/* Get CEE DCBX Oper Config (0x0A07)
1258 * The command uses the generic descriptor struct and
1259 * returns the struct below as an indirect response.
1260 */
1261struct ice_aqc_get_cee_dcb_cfg_resp {
1262	u8 oper_num_tc;
1263	u8 oper_prio_tc[4];
1264	u8 oper_tc_bw[8];
1265	u8 oper_pfc_en;
1266	__le16 oper_app_prio;
1267#define ICE_AQC_CEE_APP_FCOE_S		0
1268#define ICE_AQC_CEE_APP_FCOE_M		(0x7 << ICE_AQC_CEE_APP_FCOE_S)
1269#define ICE_AQC_CEE_APP_ISCSI_S		3
1270#define ICE_AQC_CEE_APP_ISCSI_M		(0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1271#define ICE_AQC_CEE_APP_FIP_S		8
1272#define ICE_AQC_CEE_APP_FIP_M		(0x7 << ICE_AQC_CEE_APP_FIP_S)
1273	__le32 tlv_status;
1274#define ICE_AQC_CEE_PG_STATUS_S		0
1275#define ICE_AQC_CEE_PG_STATUS_M		(0x7 << ICE_AQC_CEE_PG_STATUS_S)
1276#define ICE_AQC_CEE_PFC_STATUS_S	3
1277#define ICE_AQC_CEE_PFC_STATUS_M	(0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1278#define ICE_AQC_CEE_FCOE_STATUS_S	8
1279#define ICE_AQC_CEE_FCOE_STATUS_M	(0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1280#define ICE_AQC_CEE_ISCSI_STATUS_S	11
1281#define ICE_AQC_CEE_ISCSI_STATUS_M	(0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1282#define ICE_AQC_CEE_FIP_STATUS_S	16
1283#define ICE_AQC_CEE_FIP_STATUS_M	(0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1284	u8 reserved[12];
1285};
1286
1287/* Set Local LLDP MIB (indirect 0x0A08)
1288 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1289 */
1290struct ice_aqc_lldp_set_local_mib {
1291	u8 type;
1292#define SET_LOCAL_MIB_TYPE_DCBX_M		BIT(0)
1293#define SET_LOCAL_MIB_TYPE_LOCAL_MIB		0
1294#define SET_LOCAL_MIB_TYPE_CEE_M		BIT(1)
1295#define SET_LOCAL_MIB_TYPE_CEE_WILLING		0
1296#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING	SET_LOCAL_MIB_TYPE_CEE_M
1297	u8 reserved0;
1298	__le16 length;
1299	u8 reserved1[4];
1300	__le32 addr_high;
1301	__le32 addr_low;
1302};
1303
1304/* Stop/Start LLDP Agent (direct 0x0A09)
1305 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1306 * The same structure is used for the response, with the command field
1307 * being used as the status field.
1308 */
1309struct ice_aqc_lldp_stop_start_specific_agent {
1310	u8 command;
1311#define ICE_AQC_START_STOP_AGENT_M		BIT(0)
1312#define ICE_AQC_START_STOP_AGENT_STOP_DCBX	0
1313#define ICE_AQC_START_STOP_AGENT_START_DCBX	ICE_AQC_START_STOP_AGENT_M
1314	u8 reserved[15];
1315};
1316
 
 
 
 
 
 
 
 
 
 
1317/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1318struct ice_aqc_get_set_rss_key {
1319#define ICE_AQC_GSET_RSS_KEY_VSI_VALID	BIT(15)
1320#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S	0
1321#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M	(0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1322	__le16 vsi_id;
1323	u8 reserved[6];
1324	__le32 addr_high;
1325	__le32 addr_low;
1326};
1327
1328#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE	0x28
1329#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE	0xC
1330#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1331				(ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1332				 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1333
1334struct ice_aqc_get_set_rss_keys {
1335	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1336	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1337};
1338
1339/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1340struct ice_aqc_get_set_rss_lut {
1341#define ICE_AQC_GSET_RSS_LUT_VSI_VALID	BIT(15)
1342#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S	0
1343#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M	(0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1344	__le16 vsi_id;
1345#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S	0
1346#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M	\
1347				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1348
1349#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI	 0
1350#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF	 1
1351#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL	 2
1352
1353#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S	 2
1354#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M	 \
1355				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1356
1357#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128	 128
1358#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1359#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512	 512
1360#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1361#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K	 2048
1362#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG	 2
1363
1364#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S	 4
1365#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M	 \
1366				(0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1367
1368	__le16 flags;
1369	__le32 reserved;
1370	__le32 addr_high;
1371	__le32 addr_low;
1372};
1373
 
 
 
 
 
 
 
 
 
1374/* Add Tx LAN Queues (indirect 0x0C30) */
1375struct ice_aqc_add_txqs {
1376	u8 num_qgrps;
1377	u8 reserved[3];
1378	__le32 reserved1;
1379	__le32 addr_high;
1380	__le32 addr_low;
1381};
1382
1383/* This is the descriptor of each queue entry for the Add Tx LAN Queues
1384 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1385 */
1386struct ice_aqc_add_txqs_perq {
1387	__le16 txq_id;
1388	u8 rsvd[2];
1389	__le32 q_teid;
1390	u8 txq_ctx[22];
1391	u8 rsvd2[2];
1392	struct ice_aqc_txsched_elem info;
1393};
1394
1395/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1396 * is an array of the following structs. Please note that the length of
1397 * each struct ice_aqc_add_tx_qgrp is variable due
1398 * to the variable number of queues in each group!
1399 */
1400struct ice_aqc_add_tx_qgrp {
1401	__le32 parent_teid;
1402	u8 num_txqs;
1403	u8 rsvd[3];
1404	struct ice_aqc_add_txqs_perq txqs[1];
1405};
1406
1407/* Disable Tx LAN Queues (indirect 0x0C31) */
1408struct ice_aqc_dis_txqs {
1409	u8 cmd_type;
1410#define ICE_AQC_Q_DIS_CMD_S		0
1411#define ICE_AQC_Q_DIS_CMD_M		(0x3 << ICE_AQC_Q_DIS_CMD_S)
1412#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET	(0 << ICE_AQC_Q_DIS_CMD_S)
1413#define ICE_AQC_Q_DIS_CMD_VM_RESET	BIT(ICE_AQC_Q_DIS_CMD_S)
1414#define ICE_AQC_Q_DIS_CMD_VF_RESET	(2 << ICE_AQC_Q_DIS_CMD_S)
1415#define ICE_AQC_Q_DIS_CMD_PF_RESET	(3 << ICE_AQC_Q_DIS_CMD_S)
1416#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL	BIT(2)
1417#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE	BIT(3)
1418	u8 num_entries;
1419	__le16 vmvf_and_timeout;
1420#define ICE_AQC_Q_DIS_VMVF_NUM_S	0
1421#define ICE_AQC_Q_DIS_VMVF_NUM_M	(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1422#define ICE_AQC_Q_DIS_TIMEOUT_S		10
1423#define ICE_AQC_Q_DIS_TIMEOUT_M		(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1424	__le32 blocked_cgds;
1425	__le32 addr_high;
1426	__le32 addr_low;
1427};
1428
1429/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1430 * contains the following structures, arrayed one after the
1431 * other.
1432 * Note: Since the q_id is 16 bits wide, if the
1433 * number of queues is even, then 2 bytes of alignment MUST be
1434 * added before the start of the next group, to allow correct
1435 * alignment of the parent_teid field.
1436 */
1437struct ice_aqc_dis_txq_item {
1438	__le32 parent_teid;
1439	u8 num_qs;
1440	u8 rsvd;
1441	/* The length of the q_id array varies according to num_qs */
1442	__le16 q_id[1];
1443	/* This only applies from F8 onward */
1444#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S		15
1445#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q	\
1446			(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1447#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET	\
1448			(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
 
 
 
 
 
 
 
 
 
1449};
1450
1451struct ice_aqc_dis_txq {
1452	struct ice_aqc_dis_txq_item qgrps[1];
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1453};
1454
1455/* Configure Firmware Logging Command (indirect 0xFF09)
1456 * Logging Information Read Response (indirect 0xFF10)
1457 * Note: The 0xFF10 command has no input parameters.
1458 */
1459struct ice_aqc_fw_logging {
1460	u8 log_ctrl;
1461#define ICE_AQC_FW_LOG_AQ_EN		BIT(0)
1462#define ICE_AQC_FW_LOG_UART_EN		BIT(1)
1463	u8 rsvd0;
1464	u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1465#define ICE_AQC_FW_LOG_AQ_VALID		BIT(0)
1466#define ICE_AQC_FW_LOG_UART_VALID	BIT(1)
1467	u8 rsvd1[5];
1468	__le32 addr_high;
1469	__le32 addr_low;
1470};
1471
1472enum ice_aqc_fw_logging_mod {
1473	ICE_AQC_FW_LOG_ID_GENERAL = 0,
1474	ICE_AQC_FW_LOG_ID_CTRL,
1475	ICE_AQC_FW_LOG_ID_LINK,
1476	ICE_AQC_FW_LOG_ID_LINK_TOPO,
1477	ICE_AQC_FW_LOG_ID_DNL,
1478	ICE_AQC_FW_LOG_ID_I2C,
1479	ICE_AQC_FW_LOG_ID_SDP,
1480	ICE_AQC_FW_LOG_ID_MDIO,
1481	ICE_AQC_FW_LOG_ID_ADMINQ,
1482	ICE_AQC_FW_LOG_ID_HDMA,
1483	ICE_AQC_FW_LOG_ID_LLDP,
1484	ICE_AQC_FW_LOG_ID_DCBX,
1485	ICE_AQC_FW_LOG_ID_DCB,
1486	ICE_AQC_FW_LOG_ID_NETPROXY,
1487	ICE_AQC_FW_LOG_ID_NVM,
1488	ICE_AQC_FW_LOG_ID_AUTH,
1489	ICE_AQC_FW_LOG_ID_VPD,
1490	ICE_AQC_FW_LOG_ID_IOSF,
1491	ICE_AQC_FW_LOG_ID_PARSER,
1492	ICE_AQC_FW_LOG_ID_SW,
1493	ICE_AQC_FW_LOG_ID_SCHEDULER,
1494	ICE_AQC_FW_LOG_ID_TXQ,
1495	ICE_AQC_FW_LOG_ID_RSVD,
1496	ICE_AQC_FW_LOG_ID_POST,
1497	ICE_AQC_FW_LOG_ID_WATCHDOG,
1498	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1499	ICE_AQC_FW_LOG_ID_MNG,
1500	ICE_AQC_FW_LOG_ID_MAX,
1501};
1502
1503/* This is the buffer for both of the logging commands.
1504 * The entry array size depends on the datalen parameter in the descriptor.
1505 * There will be a total of datalen / 2 entries.
1506 */
1507struct ice_aqc_fw_logging_data {
1508	__le16 entry[1];
1509#define ICE_AQC_FW_LOG_ID_S		0
1510#define ICE_AQC_FW_LOG_ID_M		(0xFFF << ICE_AQC_FW_LOG_ID_S)
1511
1512#define ICE_AQC_FW_LOG_CONF_SUCCESS	0	/* Used by response */
1513#define ICE_AQC_FW_LOG_CONF_BAD_INDX	BIT(12)	/* Used by response */
1514
1515#define ICE_AQC_FW_LOG_EN_S		12
1516#define ICE_AQC_FW_LOG_EN_M		(0xF << ICE_AQC_FW_LOG_EN_S)
1517#define ICE_AQC_FW_LOG_INFO_EN		BIT(12)	/* Used by command */
1518#define ICE_AQC_FW_LOG_INIT_EN		BIT(13)	/* Used by command */
1519#define ICE_AQC_FW_LOG_FLOW_EN		BIT(14)	/* Used by command */
1520#define ICE_AQC_FW_LOG_ERR_EN		BIT(15)	/* Used by command */
1521};
1522
1523/* Get/Clear FW Log (indirect 0xFF11) */
1524struct ice_aqc_get_clear_fw_log {
1525	u8 flags;
1526#define ICE_AQC_FW_LOG_CLEAR		BIT(0)
1527#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL	BIT(1)
1528	u8 rsvd1[7];
1529	__le32 addr_high;
1530	__le32 addr_low;
1531};
1532
1533/* Download Package (indirect 0x0C40) */
1534/* Also used for Update Package (indirect 0x0C42) */
1535struct ice_aqc_download_pkg {
1536	u8 flags;
1537#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01
1538	u8 reserved[3];
1539	__le32 reserved1;
1540	__le32 addr_high;
1541	__le32 addr_low;
1542};
1543
1544struct ice_aqc_download_pkg_resp {
1545	__le32 error_offset;
1546	__le32 error_info;
1547	__le32 addr_high;
1548	__le32 addr_low;
1549};
1550
1551/* Get Package Info List (indirect 0x0C43) */
1552struct ice_aqc_get_pkg_info_list {
1553	__le32 reserved1;
1554	__le32 reserved2;
1555	__le32 addr_high;
1556	__le32 addr_low;
1557};
1558
1559/* Version format for packages */
1560struct ice_pkg_ver {
1561	u8 major;
1562	u8 minor;
1563	u8 update;
1564	u8 draft;
1565};
1566
1567#define ICE_PKG_NAME_SIZE	32
 
 
1568
1569struct ice_aqc_get_pkg_info {
1570	struct ice_pkg_ver ver;
1571	char name[ICE_PKG_NAME_SIZE];
 
1572	u8 is_in_nvm;
1573	u8 is_active;
1574	u8 is_active_at_boot;
1575	u8 is_modified;
1576};
1577
1578/* Get Package Info List response buffer format (0x0C43) */
1579struct ice_aqc_get_pkg_info_resp {
1580	__le32 count;
1581	struct ice_aqc_get_pkg_info pkg_info[1];
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1582};
 
1583/**
1584 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1585 * @flags: ICE_AQ_FLAG_* flags
1586 * @opcode: AQ command opcode
1587 * @datalen: length in bytes of indirect/external data buffer
1588 * @retval: return value from firmware
1589 * @cookie_h: opaque data high-half
1590 * @cookie_l: opaque data low-half
1591 * @params: command-specific parameters
1592 *
1593 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1594 * (ATQ). The firmware writes back onto the command descriptor and returns
1595 * the result of the command. Asynchronous events that are not an immediate
1596 * result of the command are written to the Admin Receive Queue (ARQ) using
1597 * the same descriptor format. Descriptors are in little-endian notation with
1598 * 32-bit words.
1599 */
1600struct ice_aq_desc {
1601	__le16 flags;
1602	__le16 opcode;
1603	__le16 datalen;
1604	__le16 retval;
1605	__le32 cookie_high;
1606	__le32 cookie_low;
1607	union {
1608		u8 raw[16];
1609		struct ice_aqc_generic generic;
1610		struct ice_aqc_get_ver get_ver;
1611		struct ice_aqc_driver_ver driver_ver;
1612		struct ice_aqc_q_shutdown q_shutdown;
1613		struct ice_aqc_req_res res_owner;
1614		struct ice_aqc_manage_mac_read mac_read;
1615		struct ice_aqc_manage_mac_write mac_write;
1616		struct ice_aqc_clear_pxe clear_pxe;
1617		struct ice_aqc_list_caps get_cap;
1618		struct ice_aqc_get_phy_caps get_phy;
1619		struct ice_aqc_set_phy_cfg set_phy;
1620		struct ice_aqc_restart_an restart_an;
 
1621		struct ice_aqc_set_port_id_led set_port_id_led;
1622		struct ice_aqc_get_sw_cfg get_sw_conf;
1623		struct ice_aqc_sw_rules sw_rules;
1624		struct ice_aqc_get_topo get_topo;
1625		struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1626		struct ice_aqc_query_txsched_res query_sched_res;
1627		struct ice_aqc_query_port_ets port_ets;
 
1628		struct ice_aqc_nvm nvm;
1629		struct ice_aqc_nvm_checksum nvm_checksum;
 
 
1630		struct ice_aqc_pf_vf_msg virt;
1631		struct ice_aqc_lldp_get_mib lldp_get_mib;
1632		struct ice_aqc_lldp_set_mib_change lldp_set_event;
1633		struct ice_aqc_lldp_stop lldp_stop;
1634		struct ice_aqc_lldp_start lldp_start;
1635		struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1636		struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
 
1637		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1638		struct ice_aqc_get_set_rss_key get_set_rss_key;
 
1639		struct ice_aqc_add_txqs add_txqs;
1640		struct ice_aqc_dis_txqs dis_txqs;
 
1641		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1642		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1643		struct ice_aqc_fw_logging fw_logging;
1644		struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1645		struct ice_aqc_download_pkg download_pkg;
 
1646		struct ice_aqc_set_mac_lb set_mac_lb;
1647		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
 
1648		struct ice_aqc_set_event_mask set_event_mask;
1649		struct ice_aqc_get_link_status get_link_status;
 
 
1650	} params;
1651};
1652
1653/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1654#define ICE_AQ_LG_BUF	512
1655
1656#define ICE_AQ_FLAG_ERR_S	2
1657#define ICE_AQ_FLAG_LB_S	9
1658#define ICE_AQ_FLAG_RD_S	10
1659#define ICE_AQ_FLAG_BUF_S	12
1660#define ICE_AQ_FLAG_SI_S	13
1661
1662#define ICE_AQ_FLAG_ERR		BIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */
1663#define ICE_AQ_FLAG_LB		BIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */
1664#define ICE_AQ_FLAG_RD		BIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */
1665#define ICE_AQ_FLAG_BUF		BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1666#define ICE_AQ_FLAG_SI		BIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */
1667
1668/* error codes */
1669enum ice_aq_err {
1670	ICE_AQ_RC_OK		= 0,  /* Success */
1671	ICE_AQ_RC_EPERM		= 1,  /* Operation not permitted */
1672	ICE_AQ_RC_ENOENT	= 2,  /* No such element */
1673	ICE_AQ_RC_ENOMEM	= 9,  /* Out of memory */
1674	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */
1675	ICE_AQ_RC_EEXIST	= 13, /* Object already exists */
 
1676	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */
1677	ICE_AQ_RC_ENOSYS	= 17, /* Function not implemented */
 
1678	ICE_AQ_RC_ENOSEC	= 24, /* Missing security manifest */
1679	ICE_AQ_RC_EBADSIG	= 25, /* Bad RSA signature */
1680	ICE_AQ_RC_ESVN		= 26, /* SVN number prohibits this package */
1681	ICE_AQ_RC_EBADMAN	= 27, /* Manifest hash mismatch */
1682	ICE_AQ_RC_EBADBUF	= 28, /* Buffer hash mismatches manifest */
1683};
1684
1685/* Admin Queue command opcodes */
1686enum ice_adminq_opc {
1687	/* AQ commands */
1688	ice_aqc_opc_get_ver				= 0x0001,
1689	ice_aqc_opc_driver_ver				= 0x0002,
1690	ice_aqc_opc_q_shutdown				= 0x0003,
1691
1692	/* resource ownership */
1693	ice_aqc_opc_req_res				= 0x0008,
1694	ice_aqc_opc_release_res				= 0x0009,
1695
1696	/* device/function capabilities */
1697	ice_aqc_opc_list_func_caps			= 0x000A,
1698	ice_aqc_opc_list_dev_caps			= 0x000B,
1699
1700	/* manage MAC address */
1701	ice_aqc_opc_manage_mac_read			= 0x0107,
1702	ice_aqc_opc_manage_mac_write			= 0x0108,
1703
1704	/* PXE */
1705	ice_aqc_opc_clear_pxe_mode			= 0x0110,
1706
1707	/* internal switch commands */
1708	ice_aqc_opc_get_sw_cfg				= 0x0200,
1709
1710	/* Alloc/Free/Get Resources */
1711	ice_aqc_opc_alloc_res				= 0x0208,
1712	ice_aqc_opc_free_res				= 0x0209,
1713
1714	/* VSI commands */
1715	ice_aqc_opc_add_vsi				= 0x0210,
1716	ice_aqc_opc_update_vsi				= 0x0211,
1717	ice_aqc_opc_free_vsi				= 0x0213,
1718
1719	/* switch rules population commands */
1720	ice_aqc_opc_add_sw_rules			= 0x02A0,
1721	ice_aqc_opc_update_sw_rules			= 0x02A1,
1722	ice_aqc_opc_remove_sw_rules			= 0x02A2,
1723
1724	ice_aqc_opc_clear_pf_cfg			= 0x02A4,
1725
1726	/* transmit scheduler commands */
1727	ice_aqc_opc_get_dflt_topo			= 0x0400,
1728	ice_aqc_opc_add_sched_elems			= 0x0401,
 
1729	ice_aqc_opc_get_sched_elems			= 0x0404,
 
1730	ice_aqc_opc_suspend_sched_elems			= 0x0409,
1731	ice_aqc_opc_resume_sched_elems			= 0x040A,
1732	ice_aqc_opc_query_port_ets			= 0x040E,
1733	ice_aqc_opc_delete_sched_elems			= 0x040F,
 
1734	ice_aqc_opc_query_sched_res			= 0x0412,
 
1735
1736	/* PHY commands */
1737	ice_aqc_opc_get_phy_caps			= 0x0600,
1738	ice_aqc_opc_set_phy_cfg				= 0x0601,
 
1739	ice_aqc_opc_restart_an				= 0x0605,
1740	ice_aqc_opc_get_link_status			= 0x0607,
1741	ice_aqc_opc_set_event_mask			= 0x0613,
1742	ice_aqc_opc_set_mac_lb				= 0x0620,
 
1743	ice_aqc_opc_set_port_id_led			= 0x06E9,
 
1744
1745	/* NVM commands */
1746	ice_aqc_opc_nvm_read				= 0x0701,
 
 
1747	ice_aqc_opc_nvm_checksum			= 0x0706,
 
 
 
 
1748
1749	/* PF/VF mailbox commands */
1750	ice_mbx_opc_send_msg_to_pf			= 0x0801,
1751	ice_mbx_opc_send_msg_to_vf			= 0x0802,
1752	/* LLDP commands */
1753	ice_aqc_opc_lldp_get_mib			= 0x0A00,
1754	ice_aqc_opc_lldp_set_mib_change			= 0x0A01,
1755	ice_aqc_opc_lldp_stop				= 0x0A05,
1756	ice_aqc_opc_lldp_start				= 0x0A06,
1757	ice_aqc_opc_get_cee_dcb_cfg			= 0x0A07,
1758	ice_aqc_opc_lldp_set_local_mib			= 0x0A08,
1759	ice_aqc_opc_lldp_stop_start_specific_agent	= 0x0A09,
 
1760
1761	/* RSS commands */
1762	ice_aqc_opc_set_rss_key				= 0x0B02,
1763	ice_aqc_opc_set_rss_lut				= 0x0B03,
1764	ice_aqc_opc_get_rss_key				= 0x0B04,
1765	ice_aqc_opc_get_rss_lut				= 0x0B05,
1766
 
 
 
1767	/* Tx queue handling commands/events */
1768	ice_aqc_opc_add_txqs				= 0x0C30,
1769	ice_aqc_opc_dis_txqs				= 0x0C31,
 
1770
1771	/* package commands */
1772	ice_aqc_opc_download_pkg			= 0x0C40,
 
1773	ice_aqc_opc_get_pkg_info_list			= 0x0C43,
 
 
 
 
 
1774
1775	/* debug commands */
1776	ice_aqc_opc_fw_logging				= 0xFF09,
1777	ice_aqc_opc_fw_logging_info			= 0xFF10,
1778};
1779
1780#endif /* _ICE_ADMINQ_CMD_H_ */