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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/export.h>
11#include <linux/gpio.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <net/dsa.h>
19#include <net/switchdev.h>
20
21#include "ksz_common.h"
22#include "ksz8795_reg.h"
23
24static const struct {
25 char string[ETH_GSTRING_LEN];
26} mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
27 { "rx_hi" },
28 { "rx_undersize" },
29 { "rx_fragments" },
30 { "rx_oversize" },
31 { "rx_jabbers" },
32 { "rx_symbol_err" },
33 { "rx_crc_err" },
34 { "rx_align_err" },
35 { "rx_mac_ctrl" },
36 { "rx_pause" },
37 { "rx_bcast" },
38 { "rx_mcast" },
39 { "rx_ucast" },
40 { "rx_64_or_less" },
41 { "rx_65_127" },
42 { "rx_128_255" },
43 { "rx_256_511" },
44 { "rx_512_1023" },
45 { "rx_1024_1522" },
46 { "rx_1523_2000" },
47 { "rx_2001" },
48 { "tx_hi" },
49 { "tx_late_col" },
50 { "tx_pause" },
51 { "tx_bcast" },
52 { "tx_mcast" },
53 { "tx_ucast" },
54 { "tx_deferred" },
55 { "tx_total_col" },
56 { "tx_exc_col" },
57 { "tx_single_col" },
58 { "tx_mult_col" },
59 { "rx_total" },
60 { "tx_total" },
61 { "rx_discards" },
62 { "tx_discards" },
63};
64
65static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
66{
67 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
68}
69
70static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
71 bool set)
72{
73 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
74 bits, set ? bits : 0);
75}
76
77static int ksz8795_reset_switch(struct ksz_device *dev)
78{
79 /* reset switch */
80 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
81 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
82 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
83
84 return 0;
85}
86
87static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
88{
89 u8 hi, lo;
90
91 /* Number of queues can only be 1, 2, or 4. */
92 switch (queue) {
93 case 4:
94 case 3:
95 queue = PORT_QUEUE_SPLIT_4;
96 break;
97 case 2:
98 queue = PORT_QUEUE_SPLIT_2;
99 break;
100 default:
101 queue = PORT_QUEUE_SPLIT_1;
102 }
103 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
104 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
105 lo &= ~PORT_QUEUE_SPLIT_L;
106 if (queue & PORT_QUEUE_SPLIT_2)
107 lo |= PORT_QUEUE_SPLIT_L;
108 hi &= ~PORT_QUEUE_SPLIT_H;
109 if (queue & PORT_QUEUE_SPLIT_4)
110 hi |= PORT_QUEUE_SPLIT_H;
111 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
112 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
113
114 /* Default is port based for egress rate limit. */
115 if (queue != PORT_QUEUE_SPLIT_1)
116 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
117 true);
118}
119
120static void ksz8795_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
121 u64 *cnt)
122{
123 u16 ctrl_addr;
124 u32 data;
125 u8 check;
126 int loop;
127
128 ctrl_addr = addr + SWITCH_COUNTER_NUM * port;
129 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
130
131 mutex_lock(&dev->alu_mutex);
132 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
133
134 /* It is almost guaranteed to always read the valid bit because of
135 * slow SPI speed.
136 */
137 for (loop = 2; loop > 0; loop--) {
138 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
139
140 if (check & MIB_COUNTER_VALID) {
141 ksz_read32(dev, REG_IND_DATA_LO, &data);
142 if (check & MIB_COUNTER_OVERFLOW)
143 *cnt += MIB_COUNTER_VALUE + 1;
144 *cnt += data & MIB_COUNTER_VALUE;
145 break;
146 }
147 }
148 mutex_unlock(&dev->alu_mutex);
149}
150
151static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
152 u64 *dropped, u64 *cnt)
153{
154 u16 ctrl_addr;
155 u32 data;
156 u8 check;
157 int loop;
158
159 addr -= SWITCH_COUNTER_NUM;
160 ctrl_addr = (KS_MIB_TOTAL_RX_1 - KS_MIB_TOTAL_RX_0) * port;
161 ctrl_addr += addr + KS_MIB_TOTAL_RX_0;
162 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
163
164 mutex_lock(&dev->alu_mutex);
165 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
166
167 /* It is almost guaranteed to always read the valid bit because of
168 * slow SPI speed.
169 */
170 for (loop = 2; loop > 0; loop--) {
171 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
172
173 if (check & MIB_COUNTER_VALID) {
174 ksz_read32(dev, REG_IND_DATA_LO, &data);
175 if (addr < 2) {
176 u64 total;
177
178 total = check & MIB_TOTAL_BYTES_H;
179 total <<= 32;
180 *cnt += total;
181 *cnt += data;
182 if (check & MIB_COUNTER_OVERFLOW) {
183 total = MIB_TOTAL_BYTES_H + 1;
184 total <<= 32;
185 *cnt += total;
186 }
187 } else {
188 if (check & MIB_COUNTER_OVERFLOW)
189 *cnt += MIB_PACKET_DROPPED + 1;
190 *cnt += data & MIB_PACKET_DROPPED;
191 }
192 break;
193 }
194 }
195 mutex_unlock(&dev->alu_mutex);
196}
197
198static void ksz8795_freeze_mib(struct ksz_device *dev, int port, bool freeze)
199{
200 /* enable the port for flush/freeze function */
201 if (freeze)
202 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
203 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
204
205 /* disable the port after freeze is done */
206 if (!freeze)
207 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
208}
209
210static void ksz8795_port_init_cnt(struct ksz_device *dev, int port)
211{
212 struct ksz_port_mib *mib = &dev->ports[port].mib;
213
214 /* flush all enabled port MIB counters */
215 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
216 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
217 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
218
219 mib->cnt_ptr = 0;
220
221 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
222 while (mib->cnt_ptr < dev->reg_mib_cnt) {
223 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
224 &mib->counters[mib->cnt_ptr]);
225 ++mib->cnt_ptr;
226 }
227
228 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
229 while (mib->cnt_ptr < dev->mib_cnt) {
230 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
231 NULL, &mib->counters[mib->cnt_ptr]);
232 ++mib->cnt_ptr;
233 }
234 mib->cnt_ptr = 0;
235 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
236}
237
238static void ksz8795_r_table(struct ksz_device *dev, int table, u16 addr,
239 u64 *data)
240{
241 u16 ctrl_addr;
242
243 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
244
245 mutex_lock(&dev->alu_mutex);
246 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
247 ksz_read64(dev, REG_IND_DATA_HI, data);
248 mutex_unlock(&dev->alu_mutex);
249}
250
251static void ksz8795_w_table(struct ksz_device *dev, int table, u16 addr,
252 u64 data)
253{
254 u16 ctrl_addr;
255
256 ctrl_addr = IND_ACC_TABLE(table) | addr;
257
258 mutex_lock(&dev->alu_mutex);
259 ksz_write64(dev, REG_IND_DATA_HI, data);
260 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
261 mutex_unlock(&dev->alu_mutex);
262}
263
264static int ksz8795_valid_dyn_entry(struct ksz_device *dev, u8 *data)
265{
266 int timeout = 100;
267
268 do {
269 ksz_read8(dev, REG_IND_DATA_CHECK, data);
270 timeout--;
271 } while ((*data & DYNAMIC_MAC_TABLE_NOT_READY) && timeout);
272
273 /* Entry is not ready for accessing. */
274 if (*data & DYNAMIC_MAC_TABLE_NOT_READY) {
275 return -EAGAIN;
276 /* Entry is ready for accessing. */
277 } else {
278 ksz_read8(dev, REG_IND_DATA_8, data);
279
280 /* There is no valid entry in the table. */
281 if (*data & DYNAMIC_MAC_TABLE_MAC_EMPTY)
282 return -ENXIO;
283 }
284 return 0;
285}
286
287static int ksz8795_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
288 u8 *mac_addr, u8 *fid, u8 *src_port,
289 u8 *timestamp, u16 *entries)
290{
291 u32 data_hi, data_lo;
292 u16 ctrl_addr;
293 u8 data;
294 int rc;
295
296 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
297
298 mutex_lock(&dev->alu_mutex);
299 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
300
301 rc = ksz8795_valid_dyn_entry(dev, &data);
302 if (rc == -EAGAIN) {
303 if (addr == 0)
304 *entries = 0;
305 } else if (rc == -ENXIO) {
306 *entries = 0;
307 /* At least one valid entry in the table. */
308 } else {
309 u64 buf = 0;
310 int cnt;
311
312 ksz_read64(dev, REG_IND_DATA_HI, &buf);
313 data_hi = (u32)(buf >> 32);
314 data_lo = (u32)buf;
315
316 /* Check out how many valid entry in the table. */
317 cnt = data & DYNAMIC_MAC_TABLE_ENTRIES_H;
318 cnt <<= DYNAMIC_MAC_ENTRIES_H_S;
319 cnt |= (data_hi & DYNAMIC_MAC_TABLE_ENTRIES) >>
320 DYNAMIC_MAC_ENTRIES_S;
321 *entries = cnt + 1;
322
323 *fid = (data_hi & DYNAMIC_MAC_TABLE_FID) >>
324 DYNAMIC_MAC_FID_S;
325 *src_port = (data_hi & DYNAMIC_MAC_TABLE_SRC_PORT) >>
326 DYNAMIC_MAC_SRC_PORT_S;
327 *timestamp = (data_hi & DYNAMIC_MAC_TABLE_TIMESTAMP) >>
328 DYNAMIC_MAC_TIMESTAMP_S;
329
330 mac_addr[5] = (u8)data_lo;
331 mac_addr[4] = (u8)(data_lo >> 8);
332 mac_addr[3] = (u8)(data_lo >> 16);
333 mac_addr[2] = (u8)(data_lo >> 24);
334
335 mac_addr[1] = (u8)data_hi;
336 mac_addr[0] = (u8)(data_hi >> 8);
337 rc = 0;
338 }
339 mutex_unlock(&dev->alu_mutex);
340
341 return rc;
342}
343
344static int ksz8795_r_sta_mac_table(struct ksz_device *dev, u16 addr,
345 struct alu_struct *alu)
346{
347 u32 data_hi, data_lo;
348 u64 data;
349
350 ksz8795_r_table(dev, TABLE_STATIC_MAC, addr, &data);
351 data_hi = data >> 32;
352 data_lo = (u32)data;
353 if (data_hi & (STATIC_MAC_TABLE_VALID | STATIC_MAC_TABLE_OVERRIDE)) {
354 alu->mac[5] = (u8)data_lo;
355 alu->mac[4] = (u8)(data_lo >> 8);
356 alu->mac[3] = (u8)(data_lo >> 16);
357 alu->mac[2] = (u8)(data_lo >> 24);
358 alu->mac[1] = (u8)data_hi;
359 alu->mac[0] = (u8)(data_hi >> 8);
360 alu->port_forward = (data_hi & STATIC_MAC_TABLE_FWD_PORTS) >>
361 STATIC_MAC_FWD_PORTS_S;
362 alu->is_override =
363 (data_hi & STATIC_MAC_TABLE_OVERRIDE) ? 1 : 0;
364 data_hi >>= 1;
365 alu->is_use_fid = (data_hi & STATIC_MAC_TABLE_USE_FID) ? 1 : 0;
366 alu->fid = (data_hi & STATIC_MAC_TABLE_FID) >>
367 STATIC_MAC_FID_S;
368 return 0;
369 }
370 return -ENXIO;
371}
372
373static void ksz8795_w_sta_mac_table(struct ksz_device *dev, u16 addr,
374 struct alu_struct *alu)
375{
376 u32 data_hi, data_lo;
377 u64 data;
378
379 data_lo = ((u32)alu->mac[2] << 24) |
380 ((u32)alu->mac[3] << 16) |
381 ((u32)alu->mac[4] << 8) | alu->mac[5];
382 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
383 data_hi |= (u32)alu->port_forward << STATIC_MAC_FWD_PORTS_S;
384
385 if (alu->is_override)
386 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
387 if (alu->is_use_fid) {
388 data_hi |= STATIC_MAC_TABLE_USE_FID;
389 data_hi |= (u32)alu->fid << STATIC_MAC_FID_S;
390 }
391 if (alu->is_static)
392 data_hi |= STATIC_MAC_TABLE_VALID;
393 else
394 data_hi &= ~STATIC_MAC_TABLE_OVERRIDE;
395
396 data = (u64)data_hi << 32 | data_lo;
397 ksz8795_w_table(dev, TABLE_STATIC_MAC, addr, data);
398}
399
400static void ksz8795_from_vlan(u16 vlan, u8 *fid, u8 *member, u8 *valid)
401{
402 *fid = vlan & VLAN_TABLE_FID;
403 *member = (vlan & VLAN_TABLE_MEMBERSHIP) >> VLAN_TABLE_MEMBERSHIP_S;
404 *valid = !!(vlan & VLAN_TABLE_VALID);
405}
406
407static void ksz8795_to_vlan(u8 fid, u8 member, u8 valid, u16 *vlan)
408{
409 *vlan = fid;
410 *vlan |= (u16)member << VLAN_TABLE_MEMBERSHIP_S;
411 if (valid)
412 *vlan |= VLAN_TABLE_VALID;
413}
414
415static void ksz8795_r_vlan_entries(struct ksz_device *dev, u16 addr)
416{
417 u64 data;
418 int i;
419
420 ksz8795_r_table(dev, TABLE_VLAN, addr, &data);
421 addr *= 4;
422 for (i = 0; i < 4; i++) {
423 dev->vlan_cache[addr + i].table[0] = (u16)data;
424 data >>= VLAN_TABLE_S;
425 }
426}
427
428static void ksz8795_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
429{
430 int index;
431 u16 *data;
432 u16 addr;
433 u64 buf;
434
435 data = (u16 *)&buf;
436 addr = vid / 4;
437 index = vid & 3;
438 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
439 *vlan = data[index];
440}
441
442static void ksz8795_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
443{
444 int index;
445 u16 *data;
446 u16 addr;
447 u64 buf;
448
449 data = (u16 *)&buf;
450 addr = vid / 4;
451 index = vid & 3;
452 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
453 data[index] = vlan;
454 dev->vlan_cache[vid].table[0] = vlan;
455 ksz8795_w_table(dev, TABLE_VLAN, addr, buf);
456}
457
458static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
459{
460 u8 restart, speed, ctrl, link;
461 int processed = true;
462 u16 data = 0;
463 u8 p = phy;
464
465 switch (reg) {
466 case PHY_REG_CTRL:
467 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
468 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
469 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
470 if (restart & PORT_PHY_LOOPBACK)
471 data |= PHY_LOOPBACK;
472 if (ctrl & PORT_FORCE_100_MBIT)
473 data |= PHY_SPEED_100MBIT;
474 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
475 data |= PHY_AUTO_NEG_ENABLE;
476 if (restart & PORT_POWER_DOWN)
477 data |= PHY_POWER_DOWN;
478 if (restart & PORT_AUTO_NEG_RESTART)
479 data |= PHY_AUTO_NEG_RESTART;
480 if (ctrl & PORT_FORCE_FULL_DUPLEX)
481 data |= PHY_FULL_DUPLEX;
482 if (speed & PORT_HP_MDIX)
483 data |= PHY_HP_MDIX;
484 if (restart & PORT_FORCE_MDIX)
485 data |= PHY_FORCE_MDIX;
486 if (restart & PORT_AUTO_MDIX_DISABLE)
487 data |= PHY_AUTO_MDIX_DISABLE;
488 if (restart & PORT_TX_DISABLE)
489 data |= PHY_TRANSMIT_DISABLE;
490 if (restart & PORT_LED_OFF)
491 data |= PHY_LED_DISABLE;
492 break;
493 case PHY_REG_STATUS:
494 ksz_pread8(dev, p, P_LINK_STATUS, &link);
495 data = PHY_100BTX_FD_CAPABLE |
496 PHY_100BTX_CAPABLE |
497 PHY_10BT_FD_CAPABLE |
498 PHY_10BT_CAPABLE |
499 PHY_AUTO_NEG_CAPABLE;
500 if (link & PORT_AUTO_NEG_COMPLETE)
501 data |= PHY_AUTO_NEG_ACKNOWLEDGE;
502 if (link & PORT_STAT_LINK_GOOD)
503 data |= PHY_LINK_STATUS;
504 break;
505 case PHY_REG_ID_1:
506 data = KSZ8795_ID_HI;
507 break;
508 case PHY_REG_ID_2:
509 data = KSZ8795_ID_LO;
510 break;
511 case PHY_REG_AUTO_NEGOTIATION:
512 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
513 data = PHY_AUTO_NEG_802_3;
514 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
515 data |= PHY_AUTO_NEG_SYM_PAUSE;
516 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
517 data |= PHY_AUTO_NEG_100BTX_FD;
518 if (ctrl & PORT_AUTO_NEG_100BTX)
519 data |= PHY_AUTO_NEG_100BTX;
520 if (ctrl & PORT_AUTO_NEG_10BT_FD)
521 data |= PHY_AUTO_NEG_10BT_FD;
522 if (ctrl & PORT_AUTO_NEG_10BT)
523 data |= PHY_AUTO_NEG_10BT;
524 break;
525 case PHY_REG_REMOTE_CAPABILITY:
526 ksz_pread8(dev, p, P_REMOTE_STATUS, &link);
527 data = PHY_AUTO_NEG_802_3;
528 if (link & PORT_REMOTE_SYM_PAUSE)
529 data |= PHY_AUTO_NEG_SYM_PAUSE;
530 if (link & PORT_REMOTE_100BTX_FD)
531 data |= PHY_AUTO_NEG_100BTX_FD;
532 if (link & PORT_REMOTE_100BTX)
533 data |= PHY_AUTO_NEG_100BTX;
534 if (link & PORT_REMOTE_10BT_FD)
535 data |= PHY_AUTO_NEG_10BT_FD;
536 if (link & PORT_REMOTE_10BT)
537 data |= PHY_AUTO_NEG_10BT;
538 if (data & ~PHY_AUTO_NEG_802_3)
539 data |= PHY_REMOTE_ACKNOWLEDGE_NOT;
540 break;
541 default:
542 processed = false;
543 break;
544 }
545 if (processed)
546 *val = data;
547}
548
549static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
550{
551 u8 p = phy;
552 u8 restart, speed, ctrl, data;
553
554 switch (reg) {
555 case PHY_REG_CTRL:
556
557 /* Do not support PHY reset function. */
558 if (val & PHY_RESET)
559 break;
560 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
561 data = speed;
562 if (val & PHY_HP_MDIX)
563 data |= PORT_HP_MDIX;
564 else
565 data &= ~PORT_HP_MDIX;
566 if (data != speed)
567 ksz_pwrite8(dev, p, P_SPEED_STATUS, data);
568 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
569 data = ctrl;
570 if (!(val & PHY_AUTO_NEG_ENABLE))
571 data |= PORT_AUTO_NEG_DISABLE;
572 else
573 data &= ~PORT_AUTO_NEG_DISABLE;
574
575 /* Fiber port does not support auto-negotiation. */
576 if (dev->ports[p].fiber)
577 data |= PORT_AUTO_NEG_DISABLE;
578 if (val & PHY_SPEED_100MBIT)
579 data |= PORT_FORCE_100_MBIT;
580 else
581 data &= ~PORT_FORCE_100_MBIT;
582 if (val & PHY_FULL_DUPLEX)
583 data |= PORT_FORCE_FULL_DUPLEX;
584 else
585 data &= ~PORT_FORCE_FULL_DUPLEX;
586 if (data != ctrl)
587 ksz_pwrite8(dev, p, P_FORCE_CTRL, data);
588 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
589 data = restart;
590 if (val & PHY_LED_DISABLE)
591 data |= PORT_LED_OFF;
592 else
593 data &= ~PORT_LED_OFF;
594 if (val & PHY_TRANSMIT_DISABLE)
595 data |= PORT_TX_DISABLE;
596 else
597 data &= ~PORT_TX_DISABLE;
598 if (val & PHY_AUTO_NEG_RESTART)
599 data |= PORT_AUTO_NEG_RESTART;
600 else
601 data &= ~(PORT_AUTO_NEG_RESTART);
602 if (val & PHY_POWER_DOWN)
603 data |= PORT_POWER_DOWN;
604 else
605 data &= ~PORT_POWER_DOWN;
606 if (val & PHY_AUTO_MDIX_DISABLE)
607 data |= PORT_AUTO_MDIX_DISABLE;
608 else
609 data &= ~PORT_AUTO_MDIX_DISABLE;
610 if (val & PHY_FORCE_MDIX)
611 data |= PORT_FORCE_MDIX;
612 else
613 data &= ~PORT_FORCE_MDIX;
614 if (val & PHY_LOOPBACK)
615 data |= PORT_PHY_LOOPBACK;
616 else
617 data &= ~PORT_PHY_LOOPBACK;
618 if (data != restart)
619 ksz_pwrite8(dev, p, P_NEG_RESTART_CTRL, data);
620 break;
621 case PHY_REG_AUTO_NEGOTIATION:
622 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
623 data = ctrl;
624 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
625 PORT_AUTO_NEG_100BTX_FD |
626 PORT_AUTO_NEG_100BTX |
627 PORT_AUTO_NEG_10BT_FD |
628 PORT_AUTO_NEG_10BT);
629 if (val & PHY_AUTO_NEG_SYM_PAUSE)
630 data |= PORT_AUTO_NEG_SYM_PAUSE;
631 if (val & PHY_AUTO_NEG_100BTX_FD)
632 data |= PORT_AUTO_NEG_100BTX_FD;
633 if (val & PHY_AUTO_NEG_100BTX)
634 data |= PORT_AUTO_NEG_100BTX;
635 if (val & PHY_AUTO_NEG_10BT_FD)
636 data |= PORT_AUTO_NEG_10BT_FD;
637 if (val & PHY_AUTO_NEG_10BT)
638 data |= PORT_AUTO_NEG_10BT;
639 if (data != ctrl)
640 ksz_pwrite8(dev, p, P_LOCAL_CTRL, data);
641 break;
642 default:
643 break;
644 }
645}
646
647static enum dsa_tag_protocol ksz8795_get_tag_protocol(struct dsa_switch *ds,
648 int port)
649{
650 return DSA_TAG_PROTO_KSZ8795;
651}
652
653static void ksz8795_get_strings(struct dsa_switch *ds, int port,
654 u32 stringset, uint8_t *buf)
655{
656 int i;
657
658 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
659 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
660 ETH_GSTRING_LEN);
661 }
662}
663
664static void ksz8795_cfg_port_member(struct ksz_device *dev, int port,
665 u8 member)
666{
667 u8 data;
668
669 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
670 data &= ~PORT_VLAN_MEMBERSHIP;
671 data |= (member & dev->port_mask);
672 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
673 dev->ports[port].member = member;
674}
675
676static void ksz8795_port_stp_state_set(struct dsa_switch *ds, int port,
677 u8 state)
678{
679 struct ksz_device *dev = ds->priv;
680 int forward = dev->member;
681 struct ksz_port *p;
682 int member = -1;
683 u8 data;
684
685 p = &dev->ports[port];
686
687 ksz_pread8(dev, port, P_STP_CTRL, &data);
688 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
689
690 switch (state) {
691 case BR_STATE_DISABLED:
692 data |= PORT_LEARN_DISABLE;
693 if (port < SWITCH_PORT_NUM)
694 member = 0;
695 break;
696 case BR_STATE_LISTENING:
697 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
698 if (port < SWITCH_PORT_NUM &&
699 p->stp_state == BR_STATE_DISABLED)
700 member = dev->host_mask | p->vid_member;
701 break;
702 case BR_STATE_LEARNING:
703 data |= PORT_RX_ENABLE;
704 break;
705 case BR_STATE_FORWARDING:
706 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
707
708 /* This function is also used internally. */
709 if (port == dev->cpu_port)
710 break;
711
712 /* Port is a member of a bridge. */
713 if (dev->br_member & BIT(port)) {
714 dev->member |= BIT(port);
715 member = dev->member;
716 } else {
717 member = dev->host_mask | p->vid_member;
718 }
719 break;
720 case BR_STATE_BLOCKING:
721 data |= PORT_LEARN_DISABLE;
722 if (port < SWITCH_PORT_NUM &&
723 p->stp_state == BR_STATE_DISABLED)
724 member = dev->host_mask | p->vid_member;
725 break;
726 default:
727 dev_err(ds->dev, "invalid STP state: %d\n", state);
728 return;
729 }
730
731 ksz_pwrite8(dev, port, P_STP_CTRL, data);
732 p->stp_state = state;
733 if (data & PORT_RX_ENABLE)
734 dev->rx_ports |= BIT(port);
735 else
736 dev->rx_ports &= ~BIT(port);
737 if (data & PORT_TX_ENABLE)
738 dev->tx_ports |= BIT(port);
739 else
740 dev->tx_ports &= ~BIT(port);
741
742 /* Port membership may share register with STP state. */
743 if (member >= 0 && member != p->member)
744 ksz8795_cfg_port_member(dev, port, (u8)member);
745
746 /* Check if forwarding needs to be updated. */
747 if (state != BR_STATE_FORWARDING) {
748 if (dev->br_member & BIT(port))
749 dev->member &= ~BIT(port);
750 }
751
752 /* When topology has changed the function ksz_update_port_member
753 * should be called to modify port forwarding behavior.
754 */
755 if (forward != dev->member)
756 ksz_update_port_member(dev, port);
757}
758
759static void ksz8795_flush_dyn_mac_table(struct ksz_device *dev, int port)
760{
761 u8 learn[TOTAL_PORT_NUM];
762 int first, index, cnt;
763 struct ksz_port *p;
764
765 if ((uint)port < TOTAL_PORT_NUM) {
766 first = port;
767 cnt = port + 1;
768 } else {
769 /* Flush all ports. */
770 first = 0;
771 cnt = dev->mib_port_cnt;
772 }
773 for (index = first; index < cnt; index++) {
774 p = &dev->ports[index];
775 if (!p->on)
776 continue;
777 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
778 if (!(learn[index] & PORT_LEARN_DISABLE))
779 ksz_pwrite8(dev, index, P_STP_CTRL,
780 learn[index] | PORT_LEARN_DISABLE);
781 }
782 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
783 for (index = first; index < cnt; index++) {
784 p = &dev->ports[index];
785 if (!p->on)
786 continue;
787 if (!(learn[index] & PORT_LEARN_DISABLE))
788 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
789 }
790}
791
792static int ksz8795_port_vlan_filtering(struct dsa_switch *ds, int port,
793 bool flag)
794{
795 struct ksz_device *dev = ds->priv;
796
797 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
798
799 return 0;
800}
801
802static void ksz8795_port_vlan_add(struct dsa_switch *ds, int port,
803 const struct switchdev_obj_port_vlan *vlan)
804{
805 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
806 struct ksz_device *dev = ds->priv;
807 u16 data, vid, new_pvid = 0;
808 u8 fid, member, valid;
809
810 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
811
812 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
813 ksz8795_r_vlan_table(dev, vid, &data);
814 ksz8795_from_vlan(data, &fid, &member, &valid);
815
816 /* First time to setup the VLAN entry. */
817 if (!valid) {
818 /* Need to find a way to map VID to FID. */
819 fid = 1;
820 valid = 1;
821 }
822 member |= BIT(port);
823
824 ksz8795_to_vlan(fid, member, valid, &data);
825 ksz8795_w_vlan_table(dev, vid, data);
826
827 /* change PVID */
828 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
829 new_pvid = vid;
830 }
831
832 if (new_pvid) {
833 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
834 vid &= 0xfff;
835 vid |= new_pvid;
836 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
837 }
838}
839
840static int ksz8795_port_vlan_del(struct dsa_switch *ds, int port,
841 const struct switchdev_obj_port_vlan *vlan)
842{
843 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
844 struct ksz_device *dev = ds->priv;
845 u16 data, vid, pvid, new_pvid = 0;
846 u8 fid, member, valid;
847
848 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
849 pvid = pvid & 0xFFF;
850
851 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
852
853 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
854 ksz8795_r_vlan_table(dev, vid, &data);
855 ksz8795_from_vlan(data, &fid, &member, &valid);
856
857 member &= ~BIT(port);
858
859 /* Invalidate the entry if no more member. */
860 if (!member) {
861 fid = 0;
862 valid = 0;
863 }
864
865 if (pvid == vid)
866 new_pvid = 1;
867
868 ksz8795_to_vlan(fid, member, valid, &data);
869 ksz8795_w_vlan_table(dev, vid, data);
870 }
871
872 if (new_pvid != pvid)
873 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, pvid);
874
875 return 0;
876}
877
878static int ksz8795_port_mirror_add(struct dsa_switch *ds, int port,
879 struct dsa_mall_mirror_tc_entry *mirror,
880 bool ingress)
881{
882 struct ksz_device *dev = ds->priv;
883
884 if (ingress) {
885 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
886 dev->mirror_rx |= BIT(port);
887 } else {
888 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
889 dev->mirror_tx |= BIT(port);
890 }
891
892 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
893
894 /* configure mirror port */
895 if (dev->mirror_rx || dev->mirror_tx)
896 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
897 PORT_MIRROR_SNIFFER, true);
898
899 return 0;
900}
901
902static void ksz8795_port_mirror_del(struct dsa_switch *ds, int port,
903 struct dsa_mall_mirror_tc_entry *mirror)
904{
905 struct ksz_device *dev = ds->priv;
906 u8 data;
907
908 if (mirror->ingress) {
909 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
910 dev->mirror_rx &= ~BIT(port);
911 } else {
912 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
913 dev->mirror_tx &= ~BIT(port);
914 }
915
916 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
917
918 if (!dev->mirror_rx && !dev->mirror_tx)
919 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
920 PORT_MIRROR_SNIFFER, false);
921}
922
923static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
924{
925 struct ksz_port *p = &dev->ports[port];
926 u8 data8, member;
927
928 /* enable broadcast storm limit */
929 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
930
931 ksz8795_set_prio_queue(dev, port, 4);
932
933 /* disable DiffServ priority */
934 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
935
936 /* replace priority */
937 ksz_port_cfg(dev, port, P_802_1P_CTRL, PORT_802_1P_REMAPPING, false);
938
939 /* enable 802.1p priority */
940 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
941
942 if (cpu_port) {
943 /* Configure MII interface for proper network communication. */
944 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
945 data8 &= ~PORT_INTERFACE_TYPE;
946 data8 &= ~PORT_GMII_1GPS_MODE;
947 switch (dev->interface) {
948 case PHY_INTERFACE_MODE_MII:
949 p->phydev.speed = SPEED_100;
950 break;
951 case PHY_INTERFACE_MODE_RMII:
952 data8 |= PORT_INTERFACE_RMII;
953 p->phydev.speed = SPEED_100;
954 break;
955 case PHY_INTERFACE_MODE_GMII:
956 data8 |= PORT_GMII_1GPS_MODE;
957 data8 |= PORT_INTERFACE_GMII;
958 p->phydev.speed = SPEED_1000;
959 break;
960 default:
961 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
962 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
963 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
964 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
965 data8 |= PORT_RGMII_ID_IN_ENABLE;
966 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
967 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
968 data8 |= PORT_RGMII_ID_OUT_ENABLE;
969 data8 |= PORT_GMII_1GPS_MODE;
970 data8 |= PORT_INTERFACE_RGMII;
971 p->phydev.speed = SPEED_1000;
972 break;
973 }
974 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
975 p->phydev.duplex = 1;
976
977 member = dev->port_mask;
978 dev->on_ports = dev->host_mask;
979 dev->live_ports = dev->host_mask;
980 } else {
981 member = dev->host_mask | p->vid_member;
982 dev->on_ports |= BIT(port);
983
984 /* Link was detected before port is enabled. */
985 if (p->phydev.link)
986 dev->live_ports |= BIT(port);
987 }
988 ksz8795_cfg_port_member(dev, port, member);
989}
990
991static void ksz8795_config_cpu_port(struct dsa_switch *ds)
992{
993 struct ksz_device *dev = ds->priv;
994 struct ksz_port *p;
995 u8 remote;
996 int i;
997
998 ds->num_ports = dev->port_cnt + 1;
999
1000 /* Switch marks the maximum frame with extra byte as oversize. */
1001 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1002 ksz_cfg(dev, S_TAIL_TAG_CTRL, SW_TAIL_TAG_ENABLE, true);
1003
1004 p = &dev->ports[dev->cpu_port];
1005 p->vid_member = dev->port_mask;
1006 p->on = 1;
1007
1008 ksz8795_port_setup(dev, dev->cpu_port, true);
1009 dev->member = dev->host_mask;
1010
1011 for (i = 0; i < SWITCH_PORT_NUM; i++) {
1012 p = &dev->ports[i];
1013
1014 /* Initialize to non-zero so that ksz_cfg_port_member() will
1015 * be called.
1016 */
1017 p->vid_member = BIT(i);
1018 p->member = dev->port_mask;
1019 ksz8795_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1020
1021 /* Last port may be disabled. */
1022 if (i == dev->port_cnt)
1023 break;
1024 p->on = 1;
1025 p->phy = 1;
1026 }
1027 for (i = 0; i < dev->phy_port_cnt; i++) {
1028 p = &dev->ports[i];
1029 if (!p->on)
1030 continue;
1031 ksz_pread8(dev, i, P_REMOTE_STATUS, &remote);
1032 if (remote & PORT_FIBER_MODE)
1033 p->fiber = 1;
1034 if (p->fiber)
1035 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1036 true);
1037 else
1038 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1039 false);
1040 }
1041}
1042
1043static int ksz8795_setup(struct dsa_switch *ds)
1044{
1045 struct ksz_device *dev = ds->priv;
1046 struct alu_struct alu;
1047 int i, ret = 0;
1048
1049 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1050 dev->num_vlans, GFP_KERNEL);
1051 if (!dev->vlan_cache)
1052 return -ENOMEM;
1053
1054 ret = ksz8795_reset_switch(dev);
1055 if (ret) {
1056 dev_err(ds->dev, "failed to reset switch\n");
1057 return ret;
1058 }
1059
1060 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1061
1062 /* Enable automatic fast aging when link changed detected. */
1063 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1064
1065 /* Enable aggressive back off algorithm in half duplex mode. */
1066 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1067 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1068
1069 /*
1070 * Make sure unicast VLAN boundary is set as default and
1071 * enable no excessive collision drop.
1072 */
1073 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1074 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1075 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1076
1077 ksz8795_config_cpu_port(ds);
1078
1079 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1080
1081 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1082
1083 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1084
1085 /* set broadcast storm protection 10% rate */
1086 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1087 BROADCAST_STORM_RATE,
1088 (BROADCAST_STORM_VALUE *
1089 BROADCAST_STORM_PROT_RATE) / 100);
1090
1091 for (i = 0; i < VLAN_TABLE_ENTRIES; i++)
1092 ksz8795_r_vlan_entries(dev, i);
1093
1094 /* Setup STP address for STP operation. */
1095 memset(&alu, 0, sizeof(alu));
1096 ether_addr_copy(alu.mac, eth_stp_addr);
1097 alu.is_static = true;
1098 alu.is_override = true;
1099 alu.port_forward = dev->host_mask;
1100
1101 ksz8795_w_sta_mac_table(dev, 0, &alu);
1102
1103 ksz_init_mib_timer(dev);
1104
1105 return 0;
1106}
1107
1108static const struct dsa_switch_ops ksz8795_switch_ops = {
1109 .get_tag_protocol = ksz8795_get_tag_protocol,
1110 .setup = ksz8795_setup,
1111 .phy_read = ksz_phy_read16,
1112 .phy_write = ksz_phy_write16,
1113 .adjust_link = ksz_adjust_link,
1114 .port_enable = ksz_enable_port,
1115 .port_disable = ksz_disable_port,
1116 .get_strings = ksz8795_get_strings,
1117 .get_ethtool_stats = ksz_get_ethtool_stats,
1118 .get_sset_count = ksz_sset_count,
1119 .port_bridge_join = ksz_port_bridge_join,
1120 .port_bridge_leave = ksz_port_bridge_leave,
1121 .port_stp_state_set = ksz8795_port_stp_state_set,
1122 .port_fast_age = ksz_port_fast_age,
1123 .port_vlan_filtering = ksz8795_port_vlan_filtering,
1124 .port_vlan_prepare = ksz_port_vlan_prepare,
1125 .port_vlan_add = ksz8795_port_vlan_add,
1126 .port_vlan_del = ksz8795_port_vlan_del,
1127 .port_fdb_dump = ksz_port_fdb_dump,
1128 .port_mdb_prepare = ksz_port_mdb_prepare,
1129 .port_mdb_add = ksz_port_mdb_add,
1130 .port_mdb_del = ksz_port_mdb_del,
1131 .port_mirror_add = ksz8795_port_mirror_add,
1132 .port_mirror_del = ksz8795_port_mirror_del,
1133};
1134
1135static u32 ksz8795_get_port_addr(int port, int offset)
1136{
1137 return PORT_CTRL_ADDR(port, offset);
1138}
1139
1140static int ksz8795_switch_detect(struct ksz_device *dev)
1141{
1142 u8 id1, id2;
1143 u16 id16;
1144 int ret;
1145
1146 /* read chip id */
1147 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1148 if (ret)
1149 return ret;
1150
1151 id1 = id16 >> 8;
1152 id2 = id16 & SW_CHIP_ID_M;
1153 if (id1 != FAMILY_ID ||
1154 (id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1155 return -ENODEV;
1156
1157 dev->mib_port_cnt = TOTAL_PORT_NUM;
1158 dev->phy_port_cnt = SWITCH_PORT_NUM;
1159 dev->port_cnt = SWITCH_PORT_NUM;
1160
1161 if (id2 == CHIP_ID_95) {
1162 u8 val;
1163
1164 id2 = 0x95;
1165 ksz_read8(dev, REG_PORT_1_STATUS_0, &val);
1166 if (val & PORT_FIBER_MODE)
1167 id2 = 0x65;
1168 } else if (id2 == CHIP_ID_94) {
1169 dev->port_cnt--;
1170 dev->last_port = dev->port_cnt;
1171 id2 = 0x94;
1172 }
1173 id16 &= ~0xff;
1174 id16 |= id2;
1175 dev->chip_id = id16;
1176
1177 dev->cpu_port = dev->mib_port_cnt - 1;
1178 dev->host_mask = BIT(dev->cpu_port);
1179
1180 return 0;
1181}
1182
1183struct ksz_chip_data {
1184 u16 chip_id;
1185 const char *dev_name;
1186 int num_vlans;
1187 int num_alus;
1188 int num_statics;
1189 int cpu_ports;
1190 int port_cnt;
1191};
1192
1193static const struct ksz_chip_data ksz8795_switch_chips[] = {
1194 {
1195 .chip_id = 0x8795,
1196 .dev_name = "KSZ8795",
1197 .num_vlans = 4096,
1198 .num_alus = 0,
1199 .num_statics = 8,
1200 .cpu_ports = 0x10, /* can be configured as cpu port */
1201 .port_cnt = 4, /* total physical port count */
1202 },
1203 {
1204 .chip_id = 0x8794,
1205 .dev_name = "KSZ8794",
1206 .num_vlans = 4096,
1207 .num_alus = 0,
1208 .num_statics = 8,
1209 .cpu_ports = 0x10, /* can be configured as cpu port */
1210 .port_cnt = 3, /* total physical port count */
1211 },
1212 {
1213 .chip_id = 0x8765,
1214 .dev_name = "KSZ8765",
1215 .num_vlans = 4096,
1216 .num_alus = 0,
1217 .num_statics = 8,
1218 .cpu_ports = 0x10, /* can be configured as cpu port */
1219 .port_cnt = 4, /* total physical port count */
1220 },
1221};
1222
1223static int ksz8795_switch_init(struct ksz_device *dev)
1224{
1225 int i;
1226
1227 dev->ds->ops = &ksz8795_switch_ops;
1228
1229 for (i = 0; i < ARRAY_SIZE(ksz8795_switch_chips); i++) {
1230 const struct ksz_chip_data *chip = &ksz8795_switch_chips[i];
1231
1232 if (dev->chip_id == chip->chip_id) {
1233 dev->name = chip->dev_name;
1234 dev->num_vlans = chip->num_vlans;
1235 dev->num_alus = chip->num_alus;
1236 dev->num_statics = chip->num_statics;
1237 dev->port_cnt = chip->port_cnt;
1238 dev->cpu_ports = chip->cpu_ports;
1239
1240 break;
1241 }
1242 }
1243
1244 /* no switch found */
1245 if (!dev->cpu_ports)
1246 return -ENODEV;
1247
1248 dev->port_mask = BIT(dev->port_cnt) - 1;
1249 dev->port_mask |= dev->host_mask;
1250
1251 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1252 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1253
1254 i = dev->mib_port_cnt;
1255 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1256 GFP_KERNEL);
1257 if (!dev->ports)
1258 return -ENOMEM;
1259 for (i = 0; i < dev->mib_port_cnt; i++) {
1260 mutex_init(&dev->ports[i].mib.cnt_mutex);
1261 dev->ports[i].mib.counters =
1262 devm_kzalloc(dev->dev,
1263 sizeof(u64) *
1264 (TOTAL_SWITCH_COUNTER_NUM + 1),
1265 GFP_KERNEL);
1266 if (!dev->ports[i].mib.counters)
1267 return -ENOMEM;
1268 }
1269
1270 return 0;
1271}
1272
1273static void ksz8795_switch_exit(struct ksz_device *dev)
1274{
1275 ksz8795_reset_switch(dev);
1276}
1277
1278static const struct ksz_dev_ops ksz8795_dev_ops = {
1279 .get_port_addr = ksz8795_get_port_addr,
1280 .cfg_port_member = ksz8795_cfg_port_member,
1281 .flush_dyn_mac_table = ksz8795_flush_dyn_mac_table,
1282 .port_setup = ksz8795_port_setup,
1283 .r_phy = ksz8795_r_phy,
1284 .w_phy = ksz8795_w_phy,
1285 .r_dyn_mac_table = ksz8795_r_dyn_mac_table,
1286 .r_sta_mac_table = ksz8795_r_sta_mac_table,
1287 .w_sta_mac_table = ksz8795_w_sta_mac_table,
1288 .r_mib_cnt = ksz8795_r_mib_cnt,
1289 .r_mib_pkt = ksz8795_r_mib_pkt,
1290 .freeze_mib = ksz8795_freeze_mib,
1291 .port_init_cnt = ksz8795_port_init_cnt,
1292 .shutdown = ksz8795_reset_switch,
1293 .detect = ksz8795_switch_detect,
1294 .init = ksz8795_switch_init,
1295 .exit = ksz8795_switch_exit,
1296};
1297
1298int ksz8795_switch_register(struct ksz_device *dev)
1299{
1300 return ksz_switch_register(dev, &ksz8795_dev_ops);
1301}
1302EXPORT_SYMBOL(ksz8795_switch_register);
1303
1304MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1305MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1306MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/export.h>
12#include <linux/gpio.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_data/microchip-ksz.h>
16#include <linux/phy.h>
17#include <linux/etherdevice.h>
18#include <linux/if_bridge.h>
19#include <linux/micrel_phy.h>
20#include <net/dsa.h>
21#include <net/switchdev.h>
22#include <linux/phylink.h>
23
24#include "ksz_common.h"
25#include "ksz8795_reg.h"
26#include "ksz8.h"
27
28static const u8 ksz8795_regs[] = {
29 [REG_IND_CTRL_0] = 0x6E,
30 [REG_IND_DATA_8] = 0x70,
31 [REG_IND_DATA_CHECK] = 0x72,
32 [REG_IND_DATA_HI] = 0x71,
33 [REG_IND_DATA_LO] = 0x75,
34 [REG_IND_MIB_CHECK] = 0x74,
35 [P_FORCE_CTRL] = 0x0C,
36 [P_LINK_STATUS] = 0x0E,
37 [P_LOCAL_CTRL] = 0x07,
38 [P_NEG_RESTART_CTRL] = 0x0D,
39 [P_REMOTE_STATUS] = 0x08,
40 [P_SPEED_STATUS] = 0x09,
41 [S_TAIL_TAG_CTRL] = 0x0C,
42};
43
44static const u32 ksz8795_masks[] = {
45 [PORT_802_1P_REMAPPING] = BIT(7),
46 [SW_TAIL_TAG_ENABLE] = BIT(1),
47 [MIB_COUNTER_OVERFLOW] = BIT(6),
48 [MIB_COUNTER_VALID] = BIT(5),
49 [VLAN_TABLE_FID] = GENMASK(6, 0),
50 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
51 [VLAN_TABLE_VALID] = BIT(12),
52 [STATIC_MAC_TABLE_VALID] = BIT(21),
53 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
54 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
55 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
56 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
57 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
58 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
59 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
60 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
61 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
62 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
63 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
64};
65
66static const u8 ksz8795_shifts[] = {
67 [VLAN_TABLE_MEMBERSHIP_S] = 7,
68 [VLAN_TABLE] = 16,
69 [STATIC_MAC_FWD_PORTS] = 16,
70 [STATIC_MAC_FID] = 24,
71 [DYNAMIC_MAC_ENTRIES_H] = 3,
72 [DYNAMIC_MAC_ENTRIES] = 29,
73 [DYNAMIC_MAC_FID] = 16,
74 [DYNAMIC_MAC_TIMESTAMP] = 27,
75 [DYNAMIC_MAC_SRC_PORT] = 24,
76};
77
78static const u8 ksz8863_regs[] = {
79 [REG_IND_CTRL_0] = 0x79,
80 [REG_IND_DATA_8] = 0x7B,
81 [REG_IND_DATA_CHECK] = 0x7B,
82 [REG_IND_DATA_HI] = 0x7C,
83 [REG_IND_DATA_LO] = 0x80,
84 [REG_IND_MIB_CHECK] = 0x80,
85 [P_FORCE_CTRL] = 0x0C,
86 [P_LINK_STATUS] = 0x0E,
87 [P_LOCAL_CTRL] = 0x0C,
88 [P_NEG_RESTART_CTRL] = 0x0D,
89 [P_REMOTE_STATUS] = 0x0E,
90 [P_SPEED_STATUS] = 0x0F,
91 [S_TAIL_TAG_CTRL] = 0x03,
92};
93
94static const u32 ksz8863_masks[] = {
95 [PORT_802_1P_REMAPPING] = BIT(3),
96 [SW_TAIL_TAG_ENABLE] = BIT(6),
97 [MIB_COUNTER_OVERFLOW] = BIT(7),
98 [MIB_COUNTER_VALID] = BIT(6),
99 [VLAN_TABLE_FID] = GENMASK(15, 12),
100 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
101 [VLAN_TABLE_VALID] = BIT(19),
102 [STATIC_MAC_TABLE_VALID] = BIT(19),
103 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
104 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
105 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
106 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
107 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
108 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
109 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
110 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
111 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
112 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
113 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
114};
115
116static u8 ksz8863_shifts[] = {
117 [VLAN_TABLE_MEMBERSHIP_S] = 16,
118 [STATIC_MAC_FWD_PORTS] = 16,
119 [STATIC_MAC_FID] = 22,
120 [DYNAMIC_MAC_ENTRIES_H] = 3,
121 [DYNAMIC_MAC_ENTRIES] = 24,
122 [DYNAMIC_MAC_FID] = 16,
123 [DYNAMIC_MAC_TIMESTAMP] = 24,
124 [DYNAMIC_MAC_SRC_PORT] = 20,
125};
126
127struct mib_names {
128 char string[ETH_GSTRING_LEN];
129};
130
131static const struct mib_names ksz87xx_mib_names[] = {
132 { "rx_hi" },
133 { "rx_undersize" },
134 { "rx_fragments" },
135 { "rx_oversize" },
136 { "rx_jabbers" },
137 { "rx_symbol_err" },
138 { "rx_crc_err" },
139 { "rx_align_err" },
140 { "rx_mac_ctrl" },
141 { "rx_pause" },
142 { "rx_bcast" },
143 { "rx_mcast" },
144 { "rx_ucast" },
145 { "rx_64_or_less" },
146 { "rx_65_127" },
147 { "rx_128_255" },
148 { "rx_256_511" },
149 { "rx_512_1023" },
150 { "rx_1024_1522" },
151 { "rx_1523_2000" },
152 { "rx_2001" },
153 { "tx_hi" },
154 { "tx_late_col" },
155 { "tx_pause" },
156 { "tx_bcast" },
157 { "tx_mcast" },
158 { "tx_ucast" },
159 { "tx_deferred" },
160 { "tx_total_col" },
161 { "tx_exc_col" },
162 { "tx_single_col" },
163 { "tx_mult_col" },
164 { "rx_total" },
165 { "tx_total" },
166 { "rx_discards" },
167 { "tx_discards" },
168};
169
170static const struct mib_names ksz88xx_mib_names[] = {
171 { "rx" },
172 { "rx_hi" },
173 { "rx_undersize" },
174 { "rx_fragments" },
175 { "rx_oversize" },
176 { "rx_jabbers" },
177 { "rx_symbol_err" },
178 { "rx_crc_err" },
179 { "rx_align_err" },
180 { "rx_mac_ctrl" },
181 { "rx_pause" },
182 { "rx_bcast" },
183 { "rx_mcast" },
184 { "rx_ucast" },
185 { "rx_64_or_less" },
186 { "rx_65_127" },
187 { "rx_128_255" },
188 { "rx_256_511" },
189 { "rx_512_1023" },
190 { "rx_1024_1522" },
191 { "tx" },
192 { "tx_hi" },
193 { "tx_late_col" },
194 { "tx_pause" },
195 { "tx_bcast" },
196 { "tx_mcast" },
197 { "tx_ucast" },
198 { "tx_deferred" },
199 { "tx_total_col" },
200 { "tx_exc_col" },
201 { "tx_single_col" },
202 { "tx_mult_col" },
203 { "rx_discards" },
204 { "tx_discards" },
205};
206
207static bool ksz_is_ksz88x3(struct ksz_device *dev)
208{
209 return dev->chip_id == 0x8830;
210}
211
212static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
213{
214 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
215}
216
217static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
218 bool set)
219{
220 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
221 bits, set ? bits : 0);
222}
223
224static int ksz8_reset_switch(struct ksz_device *dev)
225{
226 if (ksz_is_ksz88x3(dev)) {
227 /* reset switch */
228 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
229 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
230 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
231 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
232 } else {
233 /* reset switch */
234 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
235 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
236 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
237 }
238
239 return 0;
240}
241
242static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
243{
244 u8 hi, lo;
245
246 /* Number of queues can only be 1, 2, or 4. */
247 switch (queue) {
248 case 4:
249 case 3:
250 queue = PORT_QUEUE_SPLIT_4;
251 break;
252 case 2:
253 queue = PORT_QUEUE_SPLIT_2;
254 break;
255 default:
256 queue = PORT_QUEUE_SPLIT_1;
257 }
258 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
259 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
260 lo &= ~PORT_QUEUE_SPLIT_L;
261 if (queue & PORT_QUEUE_SPLIT_2)
262 lo |= PORT_QUEUE_SPLIT_L;
263 hi &= ~PORT_QUEUE_SPLIT_H;
264 if (queue & PORT_QUEUE_SPLIT_4)
265 hi |= PORT_QUEUE_SPLIT_H;
266 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
267 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
268
269 /* Default is port based for egress rate limit. */
270 if (queue != PORT_QUEUE_SPLIT_1)
271 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
272 true);
273}
274
275static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
276{
277 struct ksz8 *ksz8 = dev->priv;
278 const u32 *masks;
279 const u8 *regs;
280 u16 ctrl_addr;
281 u32 data;
282 u8 check;
283 int loop;
284
285 masks = ksz8->masks;
286 regs = ksz8->regs;
287
288 ctrl_addr = addr + dev->reg_mib_cnt * port;
289 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
290
291 mutex_lock(&dev->alu_mutex);
292 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
293
294 /* It is almost guaranteed to always read the valid bit because of
295 * slow SPI speed.
296 */
297 for (loop = 2; loop > 0; loop--) {
298 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
299
300 if (check & masks[MIB_COUNTER_VALID]) {
301 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
302 if (check & masks[MIB_COUNTER_OVERFLOW])
303 *cnt += MIB_COUNTER_VALUE + 1;
304 *cnt += data & MIB_COUNTER_VALUE;
305 break;
306 }
307 }
308 mutex_unlock(&dev->alu_mutex);
309}
310
311static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
312 u64 *dropped, u64 *cnt)
313{
314 struct ksz8 *ksz8 = dev->priv;
315 const u32 *masks;
316 const u8 *regs;
317 u16 ctrl_addr;
318 u32 data;
319 u8 check;
320 int loop;
321
322 masks = ksz8->masks;
323 regs = ksz8->regs;
324
325 addr -= dev->reg_mib_cnt;
326 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
327 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
328 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
329
330 mutex_lock(&dev->alu_mutex);
331 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
332
333 /* It is almost guaranteed to always read the valid bit because of
334 * slow SPI speed.
335 */
336 for (loop = 2; loop > 0; loop--) {
337 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
338
339 if (check & masks[MIB_COUNTER_VALID]) {
340 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
341 if (addr < 2) {
342 u64 total;
343
344 total = check & MIB_TOTAL_BYTES_H;
345 total <<= 32;
346 *cnt += total;
347 *cnt += data;
348 if (check & masks[MIB_COUNTER_OVERFLOW]) {
349 total = MIB_TOTAL_BYTES_H + 1;
350 total <<= 32;
351 *cnt += total;
352 }
353 } else {
354 if (check & masks[MIB_COUNTER_OVERFLOW])
355 *cnt += MIB_PACKET_DROPPED + 1;
356 *cnt += data & MIB_PACKET_DROPPED;
357 }
358 break;
359 }
360 }
361 mutex_unlock(&dev->alu_mutex);
362}
363
364static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
365 u64 *dropped, u64 *cnt)
366{
367 struct ksz8 *ksz8 = dev->priv;
368 const u8 *regs = ksz8->regs;
369 u32 *last = (u32 *)dropped;
370 u16 ctrl_addr;
371 u32 data;
372 u32 cur;
373
374 addr -= dev->reg_mib_cnt;
375 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
376 KSZ8863_MIB_PACKET_DROPPED_RX_0;
377 ctrl_addr += port;
378 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
379
380 mutex_lock(&dev->alu_mutex);
381 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
382 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
383 mutex_unlock(&dev->alu_mutex);
384
385 data &= MIB_PACKET_DROPPED;
386 cur = last[addr];
387 if (data != cur) {
388 last[addr] = data;
389 if (data < cur)
390 data += MIB_PACKET_DROPPED + 1;
391 data -= cur;
392 *cnt += data;
393 }
394}
395
396static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
397 u64 *dropped, u64 *cnt)
398{
399 if (ksz_is_ksz88x3(dev))
400 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
401 else
402 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
403}
404
405static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
406{
407 if (ksz_is_ksz88x3(dev))
408 return;
409
410 /* enable the port for flush/freeze function */
411 if (freeze)
412 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
413 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
414
415 /* disable the port after freeze is done */
416 if (!freeze)
417 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
418}
419
420static void ksz8_port_init_cnt(struct ksz_device *dev, int port)
421{
422 struct ksz_port_mib *mib = &dev->ports[port].mib;
423 u64 *dropped;
424
425 if (!ksz_is_ksz88x3(dev)) {
426 /* flush all enabled port MIB counters */
427 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
428 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
429 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
430 }
431
432 mib->cnt_ptr = 0;
433
434 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
435 while (mib->cnt_ptr < dev->reg_mib_cnt) {
436 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
437 &mib->counters[mib->cnt_ptr]);
438 ++mib->cnt_ptr;
439 }
440
441 /* last one in storage */
442 dropped = &mib->counters[dev->mib_cnt];
443
444 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
445 while (mib->cnt_ptr < dev->mib_cnt) {
446 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
447 dropped, &mib->counters[mib->cnt_ptr]);
448 ++mib->cnt_ptr;
449 }
450 mib->cnt_ptr = 0;
451 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
452}
453
454static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
455{
456 struct ksz8 *ksz8 = dev->priv;
457 const u8 *regs = ksz8->regs;
458 u16 ctrl_addr;
459
460 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
461
462 mutex_lock(&dev->alu_mutex);
463 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
464 ksz_read64(dev, regs[REG_IND_DATA_HI], data);
465 mutex_unlock(&dev->alu_mutex);
466}
467
468static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
469{
470 struct ksz8 *ksz8 = dev->priv;
471 const u8 *regs = ksz8->regs;
472 u16 ctrl_addr;
473
474 ctrl_addr = IND_ACC_TABLE(table) | addr;
475
476 mutex_lock(&dev->alu_mutex);
477 ksz_write64(dev, regs[REG_IND_DATA_HI], data);
478 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
479 mutex_unlock(&dev->alu_mutex);
480}
481
482static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
483{
484 struct ksz8 *ksz8 = dev->priv;
485 int timeout = 100;
486 const u32 *masks;
487 const u8 *regs;
488
489 masks = ksz8->masks;
490 regs = ksz8->regs;
491
492 do {
493 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
494 timeout--;
495 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
496
497 /* Entry is not ready for accessing. */
498 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
499 return -EAGAIN;
500 /* Entry is ready for accessing. */
501 } else {
502 ksz_read8(dev, regs[REG_IND_DATA_8], data);
503
504 /* There is no valid entry in the table. */
505 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
506 return -ENXIO;
507 }
508 return 0;
509}
510
511static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
512 u8 *mac_addr, u8 *fid, u8 *src_port,
513 u8 *timestamp, u16 *entries)
514{
515 struct ksz8 *ksz8 = dev->priv;
516 u32 data_hi, data_lo;
517 const u8 *shifts;
518 const u32 *masks;
519 const u8 *regs;
520 u16 ctrl_addr;
521 u8 data;
522 int rc;
523
524 shifts = ksz8->shifts;
525 masks = ksz8->masks;
526 regs = ksz8->regs;
527
528 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
529
530 mutex_lock(&dev->alu_mutex);
531 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
532
533 rc = ksz8_valid_dyn_entry(dev, &data);
534 if (rc == -EAGAIN) {
535 if (addr == 0)
536 *entries = 0;
537 } else if (rc == -ENXIO) {
538 *entries = 0;
539 /* At least one valid entry in the table. */
540 } else {
541 u64 buf = 0;
542 int cnt;
543
544 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
545 data_hi = (u32)(buf >> 32);
546 data_lo = (u32)buf;
547
548 /* Check out how many valid entry in the table. */
549 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
550 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
551 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
552 shifts[DYNAMIC_MAC_ENTRIES];
553 *entries = cnt + 1;
554
555 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
556 shifts[DYNAMIC_MAC_FID];
557 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
558 shifts[DYNAMIC_MAC_SRC_PORT];
559 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
560 shifts[DYNAMIC_MAC_TIMESTAMP];
561
562 mac_addr[5] = (u8)data_lo;
563 mac_addr[4] = (u8)(data_lo >> 8);
564 mac_addr[3] = (u8)(data_lo >> 16);
565 mac_addr[2] = (u8)(data_lo >> 24);
566
567 mac_addr[1] = (u8)data_hi;
568 mac_addr[0] = (u8)(data_hi >> 8);
569 rc = 0;
570 }
571 mutex_unlock(&dev->alu_mutex);
572
573 return rc;
574}
575
576static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
577 struct alu_struct *alu)
578{
579 struct ksz8 *ksz8 = dev->priv;
580 u32 data_hi, data_lo;
581 const u8 *shifts;
582 const u32 *masks;
583 u64 data;
584
585 shifts = ksz8->shifts;
586 masks = ksz8->masks;
587
588 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
589 data_hi = data >> 32;
590 data_lo = (u32)data;
591 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] |
592 masks[STATIC_MAC_TABLE_OVERRIDE])) {
593 alu->mac[5] = (u8)data_lo;
594 alu->mac[4] = (u8)(data_lo >> 8);
595 alu->mac[3] = (u8)(data_lo >> 16);
596 alu->mac[2] = (u8)(data_lo >> 24);
597 alu->mac[1] = (u8)data_hi;
598 alu->mac[0] = (u8)(data_hi >> 8);
599 alu->port_forward =
600 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
601 shifts[STATIC_MAC_FWD_PORTS];
602 alu->is_override =
603 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
604 data_hi >>= 1;
605 alu->is_static = true;
606 alu->is_use_fid =
607 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
608 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
609 shifts[STATIC_MAC_FID];
610 return 0;
611 }
612 return -ENXIO;
613}
614
615static void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
616 struct alu_struct *alu)
617{
618 struct ksz8 *ksz8 = dev->priv;
619 u32 data_hi, data_lo;
620 const u8 *shifts;
621 const u32 *masks;
622 u64 data;
623
624 shifts = ksz8->shifts;
625 masks = ksz8->masks;
626
627 data_lo = ((u32)alu->mac[2] << 24) |
628 ((u32)alu->mac[3] << 16) |
629 ((u32)alu->mac[4] << 8) | alu->mac[5];
630 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
631 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
632
633 if (alu->is_override)
634 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
635 if (alu->is_use_fid) {
636 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
637 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
638 }
639 if (alu->is_static)
640 data_hi |= masks[STATIC_MAC_TABLE_VALID];
641 else
642 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
643
644 data = (u64)data_hi << 32 | data_lo;
645 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
646}
647
648static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
649 u8 *member, u8 *valid)
650{
651 struct ksz8 *ksz8 = dev->priv;
652 const u8 *shifts;
653 const u32 *masks;
654
655 shifts = ksz8->shifts;
656 masks = ksz8->masks;
657
658 *fid = vlan & masks[VLAN_TABLE_FID];
659 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
660 shifts[VLAN_TABLE_MEMBERSHIP_S];
661 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
662}
663
664static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
665 u16 *vlan)
666{
667 struct ksz8 *ksz8 = dev->priv;
668 const u8 *shifts;
669 const u32 *masks;
670
671 shifts = ksz8->shifts;
672 masks = ksz8->masks;
673
674 *vlan = fid;
675 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
676 if (valid)
677 *vlan |= masks[VLAN_TABLE_VALID];
678}
679
680static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
681{
682 struct ksz8 *ksz8 = dev->priv;
683 const u8 *shifts;
684 u64 data;
685 int i;
686
687 shifts = ksz8->shifts;
688
689 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
690 addr *= 4;
691 for (i = 0; i < 4; i++) {
692 dev->vlan_cache[addr + i].table[0] = (u16)data;
693 data >>= shifts[VLAN_TABLE];
694 }
695}
696
697static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
698{
699 int index;
700 u16 *data;
701 u16 addr;
702 u64 buf;
703
704 data = (u16 *)&buf;
705 addr = vid / 4;
706 index = vid & 3;
707 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
708 *vlan = data[index];
709}
710
711static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
712{
713 int index;
714 u16 *data;
715 u16 addr;
716 u64 buf;
717
718 data = (u16 *)&buf;
719 addr = vid / 4;
720 index = vid & 3;
721 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
722 data[index] = vlan;
723 dev->vlan_cache[vid].table[0] = vlan;
724 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
725}
726
727static void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
728{
729 struct ksz8 *ksz8 = dev->priv;
730 u8 restart, speed, ctrl, link;
731 const u8 *regs = ksz8->regs;
732 int processed = true;
733 u8 val1, val2;
734 u16 data = 0;
735 u8 p = phy;
736
737 switch (reg) {
738 case MII_BMCR:
739 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
740 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
741 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
742 if (restart & PORT_PHY_LOOPBACK)
743 data |= BMCR_LOOPBACK;
744 if (ctrl & PORT_FORCE_100_MBIT)
745 data |= BMCR_SPEED100;
746 if (ksz_is_ksz88x3(dev)) {
747 if ((ctrl & PORT_AUTO_NEG_ENABLE))
748 data |= BMCR_ANENABLE;
749 } else {
750 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
751 data |= BMCR_ANENABLE;
752 }
753 if (restart & PORT_POWER_DOWN)
754 data |= BMCR_PDOWN;
755 if (restart & PORT_AUTO_NEG_RESTART)
756 data |= BMCR_ANRESTART;
757 if (ctrl & PORT_FORCE_FULL_DUPLEX)
758 data |= BMCR_FULLDPLX;
759 if (speed & PORT_HP_MDIX)
760 data |= KSZ886X_BMCR_HP_MDIX;
761 if (restart & PORT_FORCE_MDIX)
762 data |= KSZ886X_BMCR_FORCE_MDI;
763 if (restart & PORT_AUTO_MDIX_DISABLE)
764 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
765 if (restart & PORT_TX_DISABLE)
766 data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
767 if (restart & PORT_LED_OFF)
768 data |= KSZ886X_BMCR_DISABLE_LED;
769 break;
770 case MII_BMSR:
771 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
772 data = BMSR_100FULL |
773 BMSR_100HALF |
774 BMSR_10FULL |
775 BMSR_10HALF |
776 BMSR_ANEGCAPABLE;
777 if (link & PORT_AUTO_NEG_COMPLETE)
778 data |= BMSR_ANEGCOMPLETE;
779 if (link & PORT_STAT_LINK_GOOD)
780 data |= BMSR_LSTATUS;
781 break;
782 case MII_PHYSID1:
783 data = KSZ8795_ID_HI;
784 break;
785 case MII_PHYSID2:
786 if (ksz_is_ksz88x3(dev))
787 data = KSZ8863_ID_LO;
788 else
789 data = KSZ8795_ID_LO;
790 break;
791 case MII_ADVERTISE:
792 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
793 data = ADVERTISE_CSMA;
794 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
795 data |= ADVERTISE_PAUSE_CAP;
796 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
797 data |= ADVERTISE_100FULL;
798 if (ctrl & PORT_AUTO_NEG_100BTX)
799 data |= ADVERTISE_100HALF;
800 if (ctrl & PORT_AUTO_NEG_10BT_FD)
801 data |= ADVERTISE_10FULL;
802 if (ctrl & PORT_AUTO_NEG_10BT)
803 data |= ADVERTISE_10HALF;
804 break;
805 case MII_LPA:
806 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
807 data = LPA_SLCT;
808 if (link & PORT_REMOTE_SYM_PAUSE)
809 data |= LPA_PAUSE_CAP;
810 if (link & PORT_REMOTE_100BTX_FD)
811 data |= LPA_100FULL;
812 if (link & PORT_REMOTE_100BTX)
813 data |= LPA_100HALF;
814 if (link & PORT_REMOTE_10BT_FD)
815 data |= LPA_10FULL;
816 if (link & PORT_REMOTE_10BT)
817 data |= LPA_10HALF;
818 if (data & ~LPA_SLCT)
819 data |= LPA_LPACK;
820 break;
821 case PHY_REG_LINK_MD:
822 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
823 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
824 if (val1 & PORT_START_CABLE_DIAG)
825 data |= PHY_START_CABLE_DIAG;
826
827 if (val1 & PORT_CABLE_10M_SHORT)
828 data |= PHY_CABLE_10M_SHORT;
829
830 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
831 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
832
833 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
834 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
835 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
836 break;
837 case PHY_REG_PHY_CTRL:
838 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
839 if (link & PORT_MDIX_STATUS)
840 data |= KSZ886X_CTRL_MDIX_STAT;
841 break;
842 default:
843 processed = false;
844 break;
845 }
846 if (processed)
847 *val = data;
848}
849
850static void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
851{
852 struct ksz8 *ksz8 = dev->priv;
853 u8 restart, speed, ctrl, data;
854 const u8 *regs = ksz8->regs;
855 u8 p = phy;
856
857 switch (reg) {
858 case MII_BMCR:
859
860 /* Do not support PHY reset function. */
861 if (val & BMCR_RESET)
862 break;
863 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
864 data = speed;
865 if (val & KSZ886X_BMCR_HP_MDIX)
866 data |= PORT_HP_MDIX;
867 else
868 data &= ~PORT_HP_MDIX;
869 if (data != speed)
870 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
871 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
872 data = ctrl;
873 if (ksz_is_ksz88x3(dev)) {
874 if ((val & BMCR_ANENABLE))
875 data |= PORT_AUTO_NEG_ENABLE;
876 else
877 data &= ~PORT_AUTO_NEG_ENABLE;
878 } else {
879 if (!(val & BMCR_ANENABLE))
880 data |= PORT_AUTO_NEG_DISABLE;
881 else
882 data &= ~PORT_AUTO_NEG_DISABLE;
883
884 /* Fiber port does not support auto-negotiation. */
885 if (dev->ports[p].fiber)
886 data |= PORT_AUTO_NEG_DISABLE;
887 }
888
889 if (val & BMCR_SPEED100)
890 data |= PORT_FORCE_100_MBIT;
891 else
892 data &= ~PORT_FORCE_100_MBIT;
893 if (val & BMCR_FULLDPLX)
894 data |= PORT_FORCE_FULL_DUPLEX;
895 else
896 data &= ~PORT_FORCE_FULL_DUPLEX;
897 if (data != ctrl)
898 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
899 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
900 data = restart;
901 if (val & KSZ886X_BMCR_DISABLE_LED)
902 data |= PORT_LED_OFF;
903 else
904 data &= ~PORT_LED_OFF;
905 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
906 data |= PORT_TX_DISABLE;
907 else
908 data &= ~PORT_TX_DISABLE;
909 if (val & BMCR_ANRESTART)
910 data |= PORT_AUTO_NEG_RESTART;
911 else
912 data &= ~(PORT_AUTO_NEG_RESTART);
913 if (val & BMCR_PDOWN)
914 data |= PORT_POWER_DOWN;
915 else
916 data &= ~PORT_POWER_DOWN;
917 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
918 data |= PORT_AUTO_MDIX_DISABLE;
919 else
920 data &= ~PORT_AUTO_MDIX_DISABLE;
921 if (val & KSZ886X_BMCR_FORCE_MDI)
922 data |= PORT_FORCE_MDIX;
923 else
924 data &= ~PORT_FORCE_MDIX;
925 if (val & BMCR_LOOPBACK)
926 data |= PORT_PHY_LOOPBACK;
927 else
928 data &= ~PORT_PHY_LOOPBACK;
929 if (data != restart)
930 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data);
931 break;
932 case MII_ADVERTISE:
933 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
934 data = ctrl;
935 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
936 PORT_AUTO_NEG_100BTX_FD |
937 PORT_AUTO_NEG_100BTX |
938 PORT_AUTO_NEG_10BT_FD |
939 PORT_AUTO_NEG_10BT);
940 if (val & ADVERTISE_PAUSE_CAP)
941 data |= PORT_AUTO_NEG_SYM_PAUSE;
942 if (val & ADVERTISE_100FULL)
943 data |= PORT_AUTO_NEG_100BTX_FD;
944 if (val & ADVERTISE_100HALF)
945 data |= PORT_AUTO_NEG_100BTX;
946 if (val & ADVERTISE_10FULL)
947 data |= PORT_AUTO_NEG_10BT_FD;
948 if (val & ADVERTISE_10HALF)
949 data |= PORT_AUTO_NEG_10BT;
950 if (data != ctrl)
951 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
952 break;
953 case PHY_REG_LINK_MD:
954 if (val & PHY_START_CABLE_DIAG)
955 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
956 break;
957 default:
958 break;
959 }
960}
961
962static enum dsa_tag_protocol ksz8_get_tag_protocol(struct dsa_switch *ds,
963 int port,
964 enum dsa_tag_protocol mp)
965{
966 struct ksz_device *dev = ds->priv;
967
968 /* ksz88x3 uses the same tag schema as KSZ9893 */
969 return ksz_is_ksz88x3(dev) ?
970 DSA_TAG_PROTO_KSZ9893 : DSA_TAG_PROTO_KSZ8795;
971}
972
973static u32 ksz8_sw_get_phy_flags(struct dsa_switch *ds, int port)
974{
975 /* Silicon Errata Sheet (DS80000830A):
976 * Port 1 does not work with LinkMD Cable-Testing.
977 * Port 1 does not respond to received PAUSE control frames.
978 */
979 if (!port)
980 return MICREL_KSZ8_P1_ERRATA;
981
982 return 0;
983}
984
985static void ksz8_get_strings(struct dsa_switch *ds, int port,
986 u32 stringset, uint8_t *buf)
987{
988 struct ksz_device *dev = ds->priv;
989 int i;
990
991 for (i = 0; i < dev->mib_cnt; i++) {
992 memcpy(buf + i * ETH_GSTRING_LEN,
993 dev->mib_names[i].string, ETH_GSTRING_LEN);
994 }
995}
996
997static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
998{
999 u8 data;
1000
1001 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1002 data &= ~PORT_VLAN_MEMBERSHIP;
1003 data |= (member & dev->port_mask);
1004 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1005 dev->ports[port].member = member;
1006}
1007
1008static void ksz8_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1009{
1010 struct ksz_device *dev = ds->priv;
1011 int forward = dev->member;
1012 struct ksz_port *p;
1013 int member = -1;
1014 u8 data;
1015
1016 p = &dev->ports[port];
1017
1018 ksz_pread8(dev, port, P_STP_CTRL, &data);
1019 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1020
1021 switch (state) {
1022 case BR_STATE_DISABLED:
1023 data |= PORT_LEARN_DISABLE;
1024 if (port < dev->phy_port_cnt)
1025 member = 0;
1026 break;
1027 case BR_STATE_LISTENING:
1028 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1029 if (port < dev->phy_port_cnt &&
1030 p->stp_state == BR_STATE_DISABLED)
1031 member = dev->host_mask | p->vid_member;
1032 break;
1033 case BR_STATE_LEARNING:
1034 data |= PORT_RX_ENABLE;
1035 break;
1036 case BR_STATE_FORWARDING:
1037 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
1038
1039 /* This function is also used internally. */
1040 if (port == dev->cpu_port)
1041 break;
1042
1043 /* Port is a member of a bridge. */
1044 if (dev->br_member & BIT(port)) {
1045 dev->member |= BIT(port);
1046 member = dev->member;
1047 } else {
1048 member = dev->host_mask | p->vid_member;
1049 }
1050 break;
1051 case BR_STATE_BLOCKING:
1052 data |= PORT_LEARN_DISABLE;
1053 if (port < dev->phy_port_cnt &&
1054 p->stp_state == BR_STATE_DISABLED)
1055 member = dev->host_mask | p->vid_member;
1056 break;
1057 default:
1058 dev_err(ds->dev, "invalid STP state: %d\n", state);
1059 return;
1060 }
1061
1062 ksz_pwrite8(dev, port, P_STP_CTRL, data);
1063 p->stp_state = state;
1064 /* Port membership may share register with STP state. */
1065 if (member >= 0 && member != p->member)
1066 ksz8_cfg_port_member(dev, port, (u8)member);
1067
1068 /* Check if forwarding needs to be updated. */
1069 if (state != BR_STATE_FORWARDING) {
1070 if (dev->br_member & BIT(port))
1071 dev->member &= ~BIT(port);
1072 }
1073
1074 /* When topology has changed the function ksz_update_port_member
1075 * should be called to modify port forwarding behavior.
1076 */
1077 if (forward != dev->member)
1078 ksz_update_port_member(dev, port);
1079}
1080
1081static void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1082{
1083 u8 learn[DSA_MAX_PORTS];
1084 int first, index, cnt;
1085 struct ksz_port *p;
1086
1087 if ((uint)port < dev->port_cnt) {
1088 first = port;
1089 cnt = port + 1;
1090 } else {
1091 /* Flush all ports. */
1092 first = 0;
1093 cnt = dev->port_cnt;
1094 }
1095 for (index = first; index < cnt; index++) {
1096 p = &dev->ports[index];
1097 if (!p->on)
1098 continue;
1099 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
1100 if (!(learn[index] & PORT_LEARN_DISABLE))
1101 ksz_pwrite8(dev, index, P_STP_CTRL,
1102 learn[index] | PORT_LEARN_DISABLE);
1103 }
1104 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1105 for (index = first; index < cnt; index++) {
1106 p = &dev->ports[index];
1107 if (!p->on)
1108 continue;
1109 if (!(learn[index] & PORT_LEARN_DISABLE))
1110 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
1111 }
1112}
1113
1114static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag,
1115 struct netlink_ext_ack *extack)
1116{
1117 struct ksz_device *dev = ds->priv;
1118
1119 if (ksz_is_ksz88x3(dev))
1120 return -ENOTSUPP;
1121
1122 /* Discard packets with VID not enabled on the switch */
1123 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1124
1125 /* Discard packets with VID not enabled on the ingress port */
1126 for (port = 0; port < dev->phy_port_cnt; ++port)
1127 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1128 flag);
1129
1130 return 0;
1131}
1132
1133static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1134{
1135 if (ksz_is_ksz88x3(dev)) {
1136 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1137 0x03 << (4 - 2 * port), state);
1138 } else {
1139 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1140 }
1141}
1142
1143static int ksz8_port_vlan_add(struct dsa_switch *ds, int port,
1144 const struct switchdev_obj_port_vlan *vlan,
1145 struct netlink_ext_ack *extack)
1146{
1147 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1148 struct ksz_device *dev = ds->priv;
1149 struct ksz_port *p = &dev->ports[port];
1150 u16 data, new_pvid = 0;
1151 u8 fid, member, valid;
1152
1153 if (ksz_is_ksz88x3(dev))
1154 return -ENOTSUPP;
1155
1156 /* If a VLAN is added with untagged flag different from the
1157 * port's Remove Tag flag, we need to change the latter.
1158 * Ignore VID 0, which is always untagged.
1159 * Ignore CPU port, which will always be tagged.
1160 */
1161 if (untagged != p->remove_tag && vlan->vid != 0 &&
1162 port != dev->cpu_port) {
1163 unsigned int vid;
1164
1165 /* Reject attempts to add a VLAN that requires the
1166 * Remove Tag flag to be changed, unless there are no
1167 * other VLANs currently configured.
1168 */
1169 for (vid = 1; vid < dev->num_vlans; ++vid) {
1170 /* Skip the VID we are going to add or reconfigure */
1171 if (vid == vlan->vid)
1172 continue;
1173
1174 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1175 &fid, &member, &valid);
1176 if (valid && (member & BIT(port)))
1177 return -EINVAL;
1178 }
1179
1180 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1181 p->remove_tag = untagged;
1182 }
1183
1184 ksz8_r_vlan_table(dev, vlan->vid, &data);
1185 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1186
1187 /* First time to setup the VLAN entry. */
1188 if (!valid) {
1189 /* Need to find a way to map VID to FID. */
1190 fid = 1;
1191 valid = 1;
1192 }
1193 member |= BIT(port);
1194
1195 ksz8_to_vlan(dev, fid, member, valid, &data);
1196 ksz8_w_vlan_table(dev, vlan->vid, data);
1197
1198 /* change PVID */
1199 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1200 new_pvid = vlan->vid;
1201
1202 if (new_pvid) {
1203 u16 vid;
1204
1205 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1206 vid &= ~VLAN_VID_MASK;
1207 vid |= new_pvid;
1208 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1209
1210 ksz8_port_enable_pvid(dev, port, true);
1211 }
1212
1213 return 0;
1214}
1215
1216static int ksz8_port_vlan_del(struct dsa_switch *ds, int port,
1217 const struct switchdev_obj_port_vlan *vlan)
1218{
1219 struct ksz_device *dev = ds->priv;
1220 u16 data, pvid;
1221 u8 fid, member, valid;
1222
1223 if (ksz_is_ksz88x3(dev))
1224 return -ENOTSUPP;
1225
1226 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1227 pvid = pvid & 0xFFF;
1228
1229 ksz8_r_vlan_table(dev, vlan->vid, &data);
1230 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1231
1232 member &= ~BIT(port);
1233
1234 /* Invalidate the entry if no more member. */
1235 if (!member) {
1236 fid = 0;
1237 valid = 0;
1238 }
1239
1240 ksz8_to_vlan(dev, fid, member, valid, &data);
1241 ksz8_w_vlan_table(dev, vlan->vid, data);
1242
1243 if (pvid == vlan->vid)
1244 ksz8_port_enable_pvid(dev, port, false);
1245
1246 return 0;
1247}
1248
1249static int ksz8_port_mirror_add(struct dsa_switch *ds, int port,
1250 struct dsa_mall_mirror_tc_entry *mirror,
1251 bool ingress)
1252{
1253 struct ksz_device *dev = ds->priv;
1254
1255 if (ingress) {
1256 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1257 dev->mirror_rx |= BIT(port);
1258 } else {
1259 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1260 dev->mirror_tx |= BIT(port);
1261 }
1262
1263 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1264
1265 /* configure mirror port */
1266 if (dev->mirror_rx || dev->mirror_tx)
1267 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1268 PORT_MIRROR_SNIFFER, true);
1269
1270 return 0;
1271}
1272
1273static void ksz8_port_mirror_del(struct dsa_switch *ds, int port,
1274 struct dsa_mall_mirror_tc_entry *mirror)
1275{
1276 struct ksz_device *dev = ds->priv;
1277 u8 data;
1278
1279 if (mirror->ingress) {
1280 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1281 dev->mirror_rx &= ~BIT(port);
1282 } else {
1283 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1284 dev->mirror_tx &= ~BIT(port);
1285 }
1286
1287 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1288
1289 if (!dev->mirror_rx && !dev->mirror_tx)
1290 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1291 PORT_MIRROR_SNIFFER, false);
1292}
1293
1294static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1295{
1296 struct ksz_port *p = &dev->ports[port];
1297 u8 data8;
1298
1299 if (!p->interface && dev->compat_interface) {
1300 dev_warn(dev->dev,
1301 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1302 "Please update your device tree.\n",
1303 port);
1304 p->interface = dev->compat_interface;
1305 }
1306
1307 /* Configure MII interface for proper network communication. */
1308 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
1309 data8 &= ~PORT_INTERFACE_TYPE;
1310 data8 &= ~PORT_GMII_1GPS_MODE;
1311 switch (p->interface) {
1312 case PHY_INTERFACE_MODE_MII:
1313 p->phydev.speed = SPEED_100;
1314 break;
1315 case PHY_INTERFACE_MODE_RMII:
1316 data8 |= PORT_INTERFACE_RMII;
1317 p->phydev.speed = SPEED_100;
1318 break;
1319 case PHY_INTERFACE_MODE_GMII:
1320 data8 |= PORT_GMII_1GPS_MODE;
1321 data8 |= PORT_INTERFACE_GMII;
1322 p->phydev.speed = SPEED_1000;
1323 break;
1324 default:
1325 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
1326 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
1327 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1328 p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1329 data8 |= PORT_RGMII_ID_IN_ENABLE;
1330 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1331 p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1332 data8 |= PORT_RGMII_ID_OUT_ENABLE;
1333 data8 |= PORT_GMII_1GPS_MODE;
1334 data8 |= PORT_INTERFACE_RGMII;
1335 p->phydev.speed = SPEED_1000;
1336 break;
1337 }
1338 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
1339 p->phydev.duplex = 1;
1340}
1341
1342static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1343{
1344 struct ksz_port *p = &dev->ports[port];
1345 struct ksz8 *ksz8 = dev->priv;
1346 const u32 *masks;
1347 u8 member;
1348
1349 masks = ksz8->masks;
1350
1351 /* enable broadcast storm limit */
1352 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1353
1354 if (!ksz_is_ksz88x3(dev))
1355 ksz8795_set_prio_queue(dev, port, 4);
1356
1357 /* disable DiffServ priority */
1358 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1359
1360 /* replace priority */
1361 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1362 masks[PORT_802_1P_REMAPPING], false);
1363
1364 /* enable 802.1p priority */
1365 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1366
1367 if (cpu_port) {
1368 if (!ksz_is_ksz88x3(dev))
1369 ksz8795_cpu_interface_select(dev, port);
1370
1371 member = dev->port_mask;
1372 } else {
1373 member = dev->host_mask | p->vid_member;
1374 }
1375 ksz8_cfg_port_member(dev, port, member);
1376}
1377
1378static void ksz8_config_cpu_port(struct dsa_switch *ds)
1379{
1380 struct ksz_device *dev = ds->priv;
1381 struct ksz8 *ksz8 = dev->priv;
1382 const u8 *regs = ksz8->regs;
1383 struct ksz_port *p;
1384 const u32 *masks;
1385 u8 remote;
1386 int i;
1387
1388 masks = ksz8->masks;
1389
1390 /* Switch marks the maximum frame with extra byte as oversize. */
1391 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1392 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1393
1394 p = &dev->ports[dev->cpu_port];
1395 p->vid_member = dev->port_mask;
1396 p->on = 1;
1397
1398 ksz8_port_setup(dev, dev->cpu_port, true);
1399 dev->member = dev->host_mask;
1400
1401 for (i = 0; i < dev->phy_port_cnt; i++) {
1402 p = &dev->ports[i];
1403
1404 /* Initialize to non-zero so that ksz_cfg_port_member() will
1405 * be called.
1406 */
1407 p->vid_member = BIT(i);
1408 p->member = dev->port_mask;
1409 ksz8_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1410
1411 /* Last port may be disabled. */
1412 if (i == dev->phy_port_cnt)
1413 break;
1414 p->on = 1;
1415 p->phy = 1;
1416 }
1417 for (i = 0; i < dev->phy_port_cnt; i++) {
1418 p = &dev->ports[i];
1419 if (!p->on)
1420 continue;
1421 if (!ksz_is_ksz88x3(dev)) {
1422 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1423 if (remote & PORT_FIBER_MODE)
1424 p->fiber = 1;
1425 }
1426 if (p->fiber)
1427 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1428 true);
1429 else
1430 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1431 false);
1432 }
1433}
1434
1435static int ksz8_setup(struct dsa_switch *ds)
1436{
1437 struct ksz_device *dev = ds->priv;
1438 struct alu_struct alu;
1439 int i, ret = 0;
1440
1441 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1442 dev->num_vlans, GFP_KERNEL);
1443 if (!dev->vlan_cache)
1444 return -ENOMEM;
1445
1446 ret = ksz8_reset_switch(dev);
1447 if (ret) {
1448 dev_err(ds->dev, "failed to reset switch\n");
1449 return ret;
1450 }
1451
1452 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1453
1454 /* Enable automatic fast aging when link changed detected. */
1455 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1456
1457 /* Enable aggressive back off algorithm in half duplex mode. */
1458 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1459 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1460
1461 /*
1462 * Make sure unicast VLAN boundary is set as default and
1463 * enable no excessive collision drop.
1464 */
1465 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1466 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1467 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1468
1469 ksz8_config_cpu_port(ds);
1470
1471 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1472
1473 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1474
1475 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1476
1477 if (!ksz_is_ksz88x3(dev))
1478 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1479
1480 /* set broadcast storm protection 10% rate */
1481 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1482 BROADCAST_STORM_RATE,
1483 (BROADCAST_STORM_VALUE *
1484 BROADCAST_STORM_PROT_RATE) / 100);
1485
1486 for (i = 0; i < (dev->num_vlans / 4); i++)
1487 ksz8_r_vlan_entries(dev, i);
1488
1489 /* Setup STP address for STP operation. */
1490 memset(&alu, 0, sizeof(alu));
1491 ether_addr_copy(alu.mac, eth_stp_addr);
1492 alu.is_static = true;
1493 alu.is_override = true;
1494 alu.port_forward = dev->host_mask;
1495
1496 ksz8_w_sta_mac_table(dev, 0, &alu);
1497
1498 ksz_init_mib_timer(dev);
1499
1500 ds->configure_vlan_while_not_filtering = false;
1501
1502 return 0;
1503}
1504
1505static void ksz8_validate(struct dsa_switch *ds, int port,
1506 unsigned long *supported,
1507 struct phylink_link_state *state)
1508{
1509 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1510 struct ksz_device *dev = ds->priv;
1511
1512 if (port == dev->cpu_port) {
1513 if (state->interface != PHY_INTERFACE_MODE_RMII &&
1514 state->interface != PHY_INTERFACE_MODE_MII &&
1515 state->interface != PHY_INTERFACE_MODE_NA)
1516 goto unsupported;
1517 } else {
1518 if (state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1519 state->interface != PHY_INTERFACE_MODE_NA)
1520 goto unsupported;
1521 }
1522
1523 /* Allow all the expected bits */
1524 phylink_set_port_modes(mask);
1525 phylink_set(mask, Autoneg);
1526
1527 /* Silicon Errata Sheet (DS80000830A):
1528 * "Port 1 does not respond to received flow control PAUSE frames"
1529 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1530 * switches.
1531 */
1532 if (!ksz_is_ksz88x3(dev) || port)
1533 phylink_set(mask, Pause);
1534
1535 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1536 if (!ksz_is_ksz88x3(dev))
1537 phylink_set(mask, Asym_Pause);
1538
1539 /* 10M and 100M are only supported */
1540 phylink_set(mask, 10baseT_Half);
1541 phylink_set(mask, 10baseT_Full);
1542 phylink_set(mask, 100baseT_Half);
1543 phylink_set(mask, 100baseT_Full);
1544
1545 bitmap_and(supported, supported, mask,
1546 __ETHTOOL_LINK_MODE_MASK_NBITS);
1547 bitmap_and(state->advertising, state->advertising, mask,
1548 __ETHTOOL_LINK_MODE_MASK_NBITS);
1549
1550 return;
1551
1552unsupported:
1553 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1554 dev_err(ds->dev, "Unsupported interface: %s, port: %d\n",
1555 phy_modes(state->interface), port);
1556}
1557
1558static const struct dsa_switch_ops ksz8_switch_ops = {
1559 .get_tag_protocol = ksz8_get_tag_protocol,
1560 .get_phy_flags = ksz8_sw_get_phy_flags,
1561 .setup = ksz8_setup,
1562 .phy_read = ksz_phy_read16,
1563 .phy_write = ksz_phy_write16,
1564 .phylink_validate = ksz8_validate,
1565 .phylink_mac_link_down = ksz_mac_link_down,
1566 .port_enable = ksz_enable_port,
1567 .get_strings = ksz8_get_strings,
1568 .get_ethtool_stats = ksz_get_ethtool_stats,
1569 .get_sset_count = ksz_sset_count,
1570 .port_bridge_join = ksz_port_bridge_join,
1571 .port_bridge_leave = ksz_port_bridge_leave,
1572 .port_stp_state_set = ksz8_port_stp_state_set,
1573 .port_fast_age = ksz_port_fast_age,
1574 .port_vlan_filtering = ksz8_port_vlan_filtering,
1575 .port_vlan_add = ksz8_port_vlan_add,
1576 .port_vlan_del = ksz8_port_vlan_del,
1577 .port_fdb_dump = ksz_port_fdb_dump,
1578 .port_mdb_add = ksz_port_mdb_add,
1579 .port_mdb_del = ksz_port_mdb_del,
1580 .port_mirror_add = ksz8_port_mirror_add,
1581 .port_mirror_del = ksz8_port_mirror_del,
1582};
1583
1584static u32 ksz8_get_port_addr(int port, int offset)
1585{
1586 return PORT_CTRL_ADDR(port, offset);
1587}
1588
1589static int ksz8_switch_detect(struct ksz_device *dev)
1590{
1591 u8 id1, id2;
1592 u16 id16;
1593 int ret;
1594
1595 /* read chip id */
1596 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1597 if (ret)
1598 return ret;
1599
1600 id1 = id16 >> 8;
1601 id2 = id16 & SW_CHIP_ID_M;
1602
1603 switch (id1) {
1604 case KSZ87_FAMILY_ID:
1605 if ((id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1606 return -ENODEV;
1607
1608 if (id2 == CHIP_ID_95) {
1609 u8 val;
1610
1611 id2 = 0x95;
1612 ksz_read8(dev, REG_PORT_STATUS_0, &val);
1613 if (val & PORT_FIBER_MODE)
1614 id2 = 0x65;
1615 } else if (id2 == CHIP_ID_94) {
1616 id2 = 0x94;
1617 }
1618 break;
1619 case KSZ88_FAMILY_ID:
1620 if (id2 != CHIP_ID_63)
1621 return -ENODEV;
1622 break;
1623 default:
1624 dev_err(dev->dev, "invalid family id: %d\n", id1);
1625 return -ENODEV;
1626 }
1627 id16 &= ~0xff;
1628 id16 |= id2;
1629 dev->chip_id = id16;
1630
1631 return 0;
1632}
1633
1634struct ksz_chip_data {
1635 u16 chip_id;
1636 const char *dev_name;
1637 int num_vlans;
1638 int num_alus;
1639 int num_statics;
1640 int cpu_ports;
1641 int port_cnt;
1642};
1643
1644static const struct ksz_chip_data ksz8_switch_chips[] = {
1645 {
1646 .chip_id = 0x8795,
1647 .dev_name = "KSZ8795",
1648 .num_vlans = 4096,
1649 .num_alus = 0,
1650 .num_statics = 8,
1651 .cpu_ports = 0x10, /* can be configured as cpu port */
1652 .port_cnt = 5, /* total cpu and user ports */
1653 },
1654 {
1655 /*
1656 * WARNING
1657 * =======
1658 * KSZ8794 is similar to KSZ8795, except the port map
1659 * contains a gap between external and CPU ports, the
1660 * port map is NOT continuous. The per-port register
1661 * map is shifted accordingly too, i.e. registers at
1662 * offset 0x40 are NOT used on KSZ8794 and they ARE
1663 * used on KSZ8795 for external port 3.
1664 * external cpu
1665 * KSZ8794 0,1,2 4
1666 * KSZ8795 0,1,2,3 4
1667 * KSZ8765 0,1,2,3 4
1668 */
1669 .chip_id = 0x8794,
1670 .dev_name = "KSZ8794",
1671 .num_vlans = 4096,
1672 .num_alus = 0,
1673 .num_statics = 8,
1674 .cpu_ports = 0x10, /* can be configured as cpu port */
1675 .port_cnt = 4, /* total cpu and user ports */
1676 },
1677 {
1678 .chip_id = 0x8765,
1679 .dev_name = "KSZ8765",
1680 .num_vlans = 4096,
1681 .num_alus = 0,
1682 .num_statics = 8,
1683 .cpu_ports = 0x10, /* can be configured as cpu port */
1684 .port_cnt = 5, /* total cpu and user ports */
1685 },
1686 {
1687 .chip_id = 0x8830,
1688 .dev_name = "KSZ8863/KSZ8873",
1689 .num_vlans = 16,
1690 .num_alus = 0,
1691 .num_statics = 8,
1692 .cpu_ports = 0x4, /* can be configured as cpu port */
1693 .port_cnt = 3,
1694 },
1695};
1696
1697static int ksz8_switch_init(struct ksz_device *dev)
1698{
1699 struct ksz8 *ksz8 = dev->priv;
1700 int i;
1701
1702 dev->ds->ops = &ksz8_switch_ops;
1703
1704 for (i = 0; i < ARRAY_SIZE(ksz8_switch_chips); i++) {
1705 const struct ksz_chip_data *chip = &ksz8_switch_chips[i];
1706
1707 if (dev->chip_id == chip->chip_id) {
1708 dev->name = chip->dev_name;
1709 dev->num_vlans = chip->num_vlans;
1710 dev->num_alus = chip->num_alus;
1711 dev->num_statics = chip->num_statics;
1712 dev->port_cnt = fls(chip->cpu_ports);
1713 dev->cpu_port = fls(chip->cpu_ports) - 1;
1714 dev->phy_port_cnt = dev->port_cnt - 1;
1715 dev->cpu_ports = chip->cpu_ports;
1716 dev->host_mask = chip->cpu_ports;
1717 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) |
1718 chip->cpu_ports;
1719 break;
1720 }
1721 }
1722
1723 /* no switch found */
1724 if (!dev->cpu_ports)
1725 return -ENODEV;
1726
1727 if (ksz_is_ksz88x3(dev)) {
1728 ksz8->regs = ksz8863_regs;
1729 ksz8->masks = ksz8863_masks;
1730 ksz8->shifts = ksz8863_shifts;
1731 dev->mib_cnt = ARRAY_SIZE(ksz88xx_mib_names);
1732 dev->mib_names = ksz88xx_mib_names;
1733 } else {
1734 ksz8->regs = ksz8795_regs;
1735 ksz8->masks = ksz8795_masks;
1736 ksz8->shifts = ksz8795_shifts;
1737 dev->mib_cnt = ARRAY_SIZE(ksz87xx_mib_names);
1738 dev->mib_names = ksz87xx_mib_names;
1739 }
1740
1741 dev->reg_mib_cnt = MIB_COUNTER_NUM;
1742
1743 dev->ports = devm_kzalloc(dev->dev,
1744 dev->port_cnt * sizeof(struct ksz_port),
1745 GFP_KERNEL);
1746 if (!dev->ports)
1747 return -ENOMEM;
1748 for (i = 0; i < dev->port_cnt; i++) {
1749 mutex_init(&dev->ports[i].mib.cnt_mutex);
1750 dev->ports[i].mib.counters =
1751 devm_kzalloc(dev->dev,
1752 sizeof(u64) *
1753 (dev->mib_cnt + 1),
1754 GFP_KERNEL);
1755 if (!dev->ports[i].mib.counters)
1756 return -ENOMEM;
1757 }
1758
1759 /* set the real number of ports */
1760 dev->ds->num_ports = dev->port_cnt;
1761
1762 /* We rely on software untagging on the CPU port, so that we
1763 * can support both tagged and untagged VLANs
1764 */
1765 dev->ds->untag_bridge_pvid = true;
1766
1767 /* VLAN filtering is partly controlled by the global VLAN
1768 * Enable flag
1769 */
1770 dev->ds->vlan_filtering_is_global = true;
1771
1772 return 0;
1773}
1774
1775static void ksz8_switch_exit(struct ksz_device *dev)
1776{
1777 ksz8_reset_switch(dev);
1778}
1779
1780static const struct ksz_dev_ops ksz8_dev_ops = {
1781 .get_port_addr = ksz8_get_port_addr,
1782 .cfg_port_member = ksz8_cfg_port_member,
1783 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
1784 .port_setup = ksz8_port_setup,
1785 .r_phy = ksz8_r_phy,
1786 .w_phy = ksz8_w_phy,
1787 .r_dyn_mac_table = ksz8_r_dyn_mac_table,
1788 .r_sta_mac_table = ksz8_r_sta_mac_table,
1789 .w_sta_mac_table = ksz8_w_sta_mac_table,
1790 .r_mib_cnt = ksz8_r_mib_cnt,
1791 .r_mib_pkt = ksz8_r_mib_pkt,
1792 .freeze_mib = ksz8_freeze_mib,
1793 .port_init_cnt = ksz8_port_init_cnt,
1794 .shutdown = ksz8_reset_switch,
1795 .detect = ksz8_switch_detect,
1796 .init = ksz8_switch_init,
1797 .exit = ksz8_switch_exit,
1798};
1799
1800int ksz8_switch_register(struct ksz_device *dev)
1801{
1802 return ksz_switch_register(dev, &ksz8_dev_ops);
1803}
1804EXPORT_SYMBOL(ksz8_switch_register);
1805
1806MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1807MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1808MODULE_LICENSE("GPL");