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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Message Handling Unit Version 2 (MHUv2) driver.
4 *
5 * Copyright (C) 2020 ARM Ltd.
6 * Copyright (C) 2020 Linaro Ltd.
7 *
8 * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
9 * bit long) and the driver allows any combination of both the transport
10 * protocol modes: data-transfer and doorbell, to be used on those channel
11 * windows.
12 *
13 * The transport protocols should be specified in the device tree entry for the
14 * device. The transport protocols determine how the underlying hardware
15 * resources of the device are utilized when transmitting data. Refer to the
16 * device tree bindings of the ARM MHUv2 controller for more details.
17 *
18 * The number of registered mailbox channels is dependent on both the underlying
19 * hardware - mainly the number of channel windows implemented by the platform,
20 * as well as the selected transport protocols.
21 *
22 * The MHUv2 controller can work both as a sender and receiver, but the driver
23 * and the DT bindings support unidirectional transfers for better allocation of
24 * the channels. That is, this driver will be probed for two separate devices
25 * for each mailbox controller, a sender device and a receiver device.
26 */
27
28#include <linux/amba/bus.h>
29#include <linux/interrupt.h>
30#include <linux/mailbox_controller.h>
31#include <linux/mailbox/arm_mhuv2_message.h>
32#include <linux/module.h>
33#include <linux/of_address.h>
34#include <linux/spinlock.h>
35
36/* ====== MHUv2 Registers ====== */
37
38/* Maximum number of channel windows */
39#define MHUV2_CH_WN_MAX 124
40/* Number of combined interrupt status registers */
41#define MHUV2_CMB_INT_ST_REG_CNT 4
42#define MHUV2_STAT_BYTES (sizeof(u32))
43#define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__)
44
45#define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46#define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
47
48/* Register Message Handling Unit Configuration fields */
49struct mhu_cfg_t {
50 u32 num_ch : 7;
51 u32 pad : 25;
52} __packed;
53
54/* register Interrupt Status fields */
55struct int_st_t {
56 u32 nr2r : 1;
57 u32 r2nr : 1;
58 u32 pad : 30;
59} __packed;
60
61/* Register Interrupt Clear fields */
62struct int_clr_t {
63 u32 nr2r : 1;
64 u32 r2nr : 1;
65 u32 pad : 30;
66} __packed;
67
68/* Register Interrupt Enable fields */
69struct int_en_t {
70 u32 r2nr : 1;
71 u32 nr2r : 1;
72 u32 chcomb : 1;
73 u32 pad : 29;
74} __packed;
75
76/* Register Implementer Identification fields */
77struct iidr_t {
78 u32 implementer : 12;
79 u32 revision : 4;
80 u32 variant : 4;
81 u32 product_id : 12;
82} __packed;
83
84/* Register Architecture Identification Register fields */
85struct aidr_t {
86 u32 arch_minor_rev : 4;
87 u32 arch_major_rev : 4;
88 u32 pad : 24;
89} __packed;
90
91/* Sender Channel Window fields */
92struct mhu2_send_ch_wn_reg {
93 u32 stat;
94 u8 pad1[0x0C - 0x04];
95 u32 stat_set;
96 u32 int_st;
97 u32 int_clr;
98 u32 int_en;
99 u8 pad2[0x20 - 0x1C];
100} __packed;
101
102/* Sender frame register fields */
103struct mhu2_send_frame_reg {
104 struct mhu2_send_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
105 struct mhu_cfg_t mhu_cfg;
106 u32 resp_cfg;
107 u32 access_request;
108 u32 access_ready;
109 struct int_st_t int_st;
110 struct int_clr_t int_clr;
111 struct int_en_t int_en;
112 u32 reserved0;
113 u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
114 u8 pad[0xFC8 - 0xFB0];
115 struct iidr_t iidr;
116 struct aidr_t aidr;
117} __packed;
118
119/* Receiver Channel Window fields */
120struct mhu2_recv_ch_wn_reg {
121 u32 stat;
122 u32 stat_masked;
123 u32 stat_clear;
124 u8 reserved0[0x10 - 0x0C];
125 u32 mask;
126 u32 mask_set;
127 u32 mask_clear;
128 u8 pad[0x20 - 0x1C];
129} __packed;
130
131/* Receiver frame register fields */
132struct mhu2_recv_frame_reg {
133 struct mhu2_recv_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
134 struct mhu_cfg_t mhu_cfg;
135 u8 reserved0[0xF90 - 0xF84];
136 struct int_st_t int_st;
137 struct int_clr_t int_clr;
138 struct int_en_t int_en;
139 u32 pad;
140 u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
141 u8 reserved2[0xFC8 - 0xFB0];
142 struct iidr_t iidr;
143 struct aidr_t aidr;
144} __packed;
145
146
147/* ====== MHUv2 data structures ====== */
148
149enum mhuv2_transport_protocol {
150 DOORBELL = 0,
151 DATA_TRANSFER = 1
152};
153
154enum mhuv2_frame {
155 RECEIVER_FRAME,
156 SENDER_FRAME
157};
158
159/**
160 * struct mhuv2 - MHUv2 mailbox controller data
161 *
162 * @mbox: Mailbox controller belonging to the MHU frame.
163 * @send/recv: Base address of the register mapping region.
164 * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
165 * @irq: Interrupt.
166 * @windows: Channel windows implemented by the platform.
167 * @minor: Minor version of the controller.
168 * @length: Length of the protocols array in bytes.
169 * @protocols: Raw protocol information, derived from device tree.
170 * @doorbell_pending_lock: spinlock required for correct operation of Tx
171 * interrupt for doorbells.
172 */
173struct mhuv2 {
174 struct mbox_controller mbox;
175 union {
176 struct mhu2_send_frame_reg __iomem *send;
177 struct mhu2_recv_frame_reg __iomem *recv;
178 };
179 enum mhuv2_frame frame;
180 unsigned int irq;
181 unsigned int windows;
182 unsigned int minor;
183 unsigned int length;
184 u32 *protocols;
185
186 spinlock_t doorbell_pending_lock;
187};
188
189#define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
190
191/**
192 * struct mhuv2_protocol_ops - MHUv2 operations
193 *
194 * Each transport protocol must provide an implementation of the operations
195 * provided here.
196 *
197 * @rx_startup: Startup callback for receiver.
198 * @rx_shutdown: Shutdown callback for receiver.
199 * @read_data: Reads and clears newly available data.
200 * @tx_startup: Startup callback for receiver.
201 * @tx_shutdown: Shutdown callback for receiver.
202 * @last_tx_done: Report back if the last tx is completed or not.
203 * @send_data: Send data to the receiver.
204 */
205struct mhuv2_protocol_ops {
206 int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
207 void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
208 void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan);
209
210 void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
211 void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
212 int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan);
213 int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg);
214};
215
216/*
217 * MHUv2 mailbox channel's private information
218 *
219 * @ops: protocol specific ops for the channel.
220 * @ch_wn_idx: Channel window index allocated to the channel.
221 * @windows: Total number of windows consumed by the channel, only relevant
222 * in DATA_TRANSFER protocol.
223 * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant
224 * in DOORBELL protocol.
225 * @pending: Flag indicating pending doorbell interrupt, only relevant in
226 * DOORBELL protocol.
227 */
228struct mhuv2_mbox_chan_priv {
229 const struct mhuv2_protocol_ops *ops;
230 u32 ch_wn_idx;
231 union {
232 u32 windows;
233 struct {
234 u32 doorbell;
235 u32 pending;
236 };
237 };
238};
239
240/* Macro for reading a bitfield within a physically mapped packed struct */
241#define readl_relaxed_bitfield(_regptr, _type, _field) \
242 ({ \
243 u32 _regval; \
244 _regval = readl_relaxed((_regptr)); \
245 (*(_type *)(&_regval))._field; \
246 })
247
248/* Macro for writing a bitfield within a physically mapped packed struct */
249#define writel_relaxed_bitfield(_value, _regptr, _type, _field) \
250 ({ \
251 u32 _regval; \
252 _regval = readl_relaxed(_regptr); \
253 (*(_type *)(&_regval))._field = _value; \
254 writel_relaxed(_regval, _regptr); \
255 })
256
257
258/* =================== Doorbell transport protocol operations =============== */
259
260static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan)
261{
262 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
263
264 writel_relaxed(BIT(priv->doorbell),
265 &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear);
266 return 0;
267}
268
269static void mhuv2_doorbell_rx_shutdown(struct mhuv2 *mhu,
270 struct mbox_chan *chan)
271{
272 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
273
274 writel_relaxed(BIT(priv->doorbell),
275 &mhu->recv->ch_wn[priv->ch_wn_idx].mask_set);
276}
277
278static void *mhuv2_doorbell_read_data(struct mhuv2 *mhu, struct mbox_chan *chan)
279{
280 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
281
282 writel_relaxed(BIT(priv->doorbell),
283 &mhu->recv->ch_wn[priv->ch_wn_idx].stat_clear);
284 return NULL;
285}
286
287static int mhuv2_doorbell_last_tx_done(struct mhuv2 *mhu,
288 struct mbox_chan *chan)
289{
290 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
291
292 return !(readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat) &
293 BIT(priv->doorbell));
294}
295
296static int mhuv2_doorbell_send_data(struct mhuv2 *mhu, struct mbox_chan *chan,
297 void *arg)
298{
299 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
300 unsigned long flags;
301
302 spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
303
304 priv->pending = 1;
305 writel_relaxed(BIT(priv->doorbell),
306 &mhu->send->ch_wn[priv->ch_wn_idx].stat_set);
307
308 spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
309
310 return 0;
311}
312
313static const struct mhuv2_protocol_ops mhuv2_doorbell_ops = {
314 .rx_startup = mhuv2_doorbell_rx_startup,
315 .rx_shutdown = mhuv2_doorbell_rx_shutdown,
316 .read_data = mhuv2_doorbell_read_data,
317 .last_tx_done = mhuv2_doorbell_last_tx_done,
318 .send_data = mhuv2_doorbell_send_data,
319};
320#define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops)
321
322/* ============= Data transfer transport protocol operations ================ */
323
324static int mhuv2_data_transfer_rx_startup(struct mhuv2 *mhu,
325 struct mbox_chan *chan)
326{
327 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
328 int i = priv->ch_wn_idx + priv->windows - 1;
329
330 /*
331 * The protocol mandates that all but the last status register must be
332 * masked.
333 */
334 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear);
335 return 0;
336}
337
338static void mhuv2_data_transfer_rx_shutdown(struct mhuv2 *mhu,
339 struct mbox_chan *chan)
340{
341 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
342 int i = priv->ch_wn_idx + priv->windows - 1;
343
344 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
345}
346
347static void *mhuv2_data_transfer_read_data(struct mhuv2 *mhu,
348 struct mbox_chan *chan)
349{
350 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
351 const int windows = priv->windows;
352 struct arm_mhuv2_mbox_msg *msg;
353 u32 *data;
354 int i, idx;
355
356 msg = kzalloc(sizeof(*msg) + windows * MHUV2_STAT_BYTES, GFP_KERNEL);
357 if (!msg)
358 return ERR_PTR(-ENOMEM);
359
360 data = msg->data = msg + 1;
361 msg->len = windows * MHUV2_STAT_BYTES;
362
363 /*
364 * Messages are expected in order of most significant word to least
365 * significant word. Refer mhuv2_data_transfer_send_data() for more
366 * details.
367 *
368 * We also need to read the stat register instead of stat_masked, as we
369 * masked all but the last window.
370 *
371 * Last channel window must be cleared as the final operation. Upon
372 * clearing the last channel window register, which is unmasked in
373 * data-transfer protocol, the interrupt is de-asserted.
374 */
375 for (i = 0; i < windows; i++) {
376 idx = priv->ch_wn_idx + i;
377 data[windows - 1 - i] = readl_relaxed(&mhu->recv->ch_wn[idx].stat);
378 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
379 }
380
381 return msg;
382}
383
384static void mhuv2_data_transfer_tx_startup(struct mhuv2 *mhu,
385 struct mbox_chan *chan)
386{
387 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
388 int i = priv->ch_wn_idx + priv->windows - 1;
389
390 /* Enable interrupts only for the last window */
391 if (mhu->minor) {
392 writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr);
393 writel_relaxed(0x1, &mhu->send->ch_wn[i].int_en);
394 }
395}
396
397static void mhuv2_data_transfer_tx_shutdown(struct mhuv2 *mhu,
398 struct mbox_chan *chan)
399{
400 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
401 int i = priv->ch_wn_idx + priv->windows - 1;
402
403 if (mhu->minor)
404 writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
405}
406
407static int mhuv2_data_transfer_last_tx_done(struct mhuv2 *mhu,
408 struct mbox_chan *chan)
409{
410 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
411 int i = priv->ch_wn_idx + priv->windows - 1;
412
413 /* Just checking the last channel window should be enough */
414 return !readl_relaxed(&mhu->send->ch_wn[i].stat);
415}
416
417/*
418 * Message will be transmitted from most significant to least significant word.
419 * This is to allow for messages shorter than channel windows to still trigger
420 * the receiver interrupt which gets activated when the last stat register is
421 * written. As an example, a 6-word message is to be written on a 4-channel MHU
422 * connection: Registers marked with '*' are masked, and will not generate an
423 * interrupt on the receiver side once written.
424 *
425 * u32 *data = [0x00000001], [0x00000002], [0x00000003], [0x00000004],
426 * [0x00000005], [0x00000006]
427 *
428 * ROUND 1:
429 * stat reg To write Write sequence
430 * [ stat 3 ] <- [0x00000001] 4 <- triggers interrupt on receiver
431 * [ stat 2 ] <- [0x00000002] 3
432 * [ stat 1 ] <- [0x00000003] 2
433 * [ stat 0 ] <- [0x00000004] 1
434 *
435 * data += 4 // Increment data pointer by number of stat regs
436 *
437 * ROUND 2:
438 * stat reg To write Write sequence
439 * [ stat 3 ] <- [0x00000005] 2 <- triggers interrupt on receiver
440 * [ stat 2 ] <- [0x00000006] 1
441 * [ stat 1 ] <- [0x00000000]
442 * [ stat 0 ] <- [0x00000000]
443 */
444static int mhuv2_data_transfer_send_data(struct mhuv2 *mhu,
445 struct mbox_chan *chan, void *arg)
446{
447 const struct arm_mhuv2_mbox_msg *msg = arg;
448 int bytes_left = msg->len, bytes_to_send, bytes_in_round, i;
449 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
450 int windows = priv->windows;
451 u32 *data = msg->data, word;
452
453 while (bytes_left) {
454 if (!data[0]) {
455 dev_err(mhu->mbox.dev, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver");
456 return -EINVAL;
457 }
458
459 while(!mhuv2_data_transfer_last_tx_done(mhu, chan))
460 continue;
461
462 bytes_in_round = min(bytes_left, (int)(windows * MHUV2_STAT_BYTES));
463
464 for (i = windows - 1; i >= 0; i--) {
465 /* Data less than windows can transfer ? */
466 if (unlikely(bytes_in_round <= i * MHUV2_STAT_BYTES))
467 continue;
468
469 word = data[i];
470 bytes_to_send = bytes_in_round & (MHUV2_STAT_BYTES - 1);
471 if (unlikely(bytes_to_send))
472 word &= LSB_MASK(bytes_to_send);
473 else
474 bytes_to_send = MHUV2_STAT_BYTES;
475
476 writel_relaxed(word, &mhu->send->ch_wn[priv->ch_wn_idx + windows - 1 - i].stat_set);
477 bytes_left -= bytes_to_send;
478 bytes_in_round -= bytes_to_send;
479 }
480
481 data += windows;
482 }
483
484 return 0;
485}
486
487static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops = {
488 .rx_startup = mhuv2_data_transfer_rx_startup,
489 .rx_shutdown = mhuv2_data_transfer_rx_shutdown,
490 .read_data = mhuv2_data_transfer_read_data,
491 .tx_startup = mhuv2_data_transfer_tx_startup,
492 .tx_shutdown = mhuv2_data_transfer_tx_shutdown,
493 .last_tx_done = mhuv2_data_transfer_last_tx_done,
494 .send_data = mhuv2_data_transfer_send_data,
495};
496
497/* Interrupt handlers */
498
499static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 __iomem *reg)
500{
501 struct mbox_chan *chans = mhu->mbox.chans;
502 int channel = 0, i, offset = 0, windows, protocol, ch_wn;
503 u32 stat;
504
505 for (i = 0; i < MHUV2_CMB_INT_ST_REG_CNT; i++) {
506 stat = readl_relaxed(reg + i);
507 if (!stat)
508 continue;
509
510 ch_wn = i * MHUV2_STAT_BITS + __builtin_ctz(stat);
511
512 for (i = 0; i < mhu->length; i += 2) {
513 protocol = mhu->protocols[i];
514 windows = mhu->protocols[i + 1];
515
516 if (ch_wn >= offset + windows) {
517 if (protocol == DOORBELL)
518 channel += MHUV2_STAT_BITS * windows;
519 else
520 channel++;
521
522 offset += windows;
523 continue;
524 }
525
526 /* Return first chan of the window in doorbell mode */
527 if (protocol == DOORBELL)
528 channel += MHUV2_STAT_BITS * (ch_wn - offset);
529
530 return &chans[channel];
531 }
532 }
533
534 return ERR_PTR(-EIO);
535}
536
537static irqreturn_t mhuv2_sender_interrupt(int irq, void *data)
538{
539 struct mhuv2 *mhu = data;
540 struct device *dev = mhu->mbox.dev;
541 struct mhuv2_mbox_chan_priv *priv;
542 struct mbox_chan *chan;
543 unsigned long flags;
544 int i, found = 0;
545 u32 stat;
546
547 chan = get_irq_chan_comb(mhu, mhu->send->chcomb_int_st);
548 if (IS_ERR(chan)) {
549 dev_warn(dev, "Failed to find channel for the Tx interrupt\n");
550 return IRQ_NONE;
551 }
552 priv = chan->con_priv;
553
554 if (!IS_PROTOCOL_DOORBELL(priv)) {
555 writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + priv->windows - 1].int_clr);
556
557 if (chan->cl) {
558 mbox_chan_txdone(chan, 0);
559 return IRQ_HANDLED;
560 }
561
562 dev_warn(dev, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n",
563 priv->ch_wn_idx);
564 return IRQ_NONE;
565 }
566
567 /* Clear the interrupt first, so we don't miss any doorbell later */
568 writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx].int_clr);
569
570 /*
571 * In Doorbell mode, make sure no new transitions happen while the
572 * interrupt handler is trying to find the finished doorbell tx
573 * operations, else we may think few of the transfers were complete
574 * before they actually were.
575 */
576 spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
577
578 /*
579 * In case of doorbell mode, the first channel of the window is returned
580 * by get_irq_chan_comb(). Find all the pending channels here.
581 */
582 stat = readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat);
583
584 for (i = 0; i < MHUV2_STAT_BITS; i++) {
585 priv = chan[i].con_priv;
586
587 /* Find cases where pending was 1, but stat's bit is cleared */
588 if (priv->pending ^ ((stat >> i) & 0x1)) {
589 BUG_ON(!priv->pending);
590
591 if (!chan->cl) {
592 dev_warn(dev, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n",
593 priv->ch_wn_idx, i);
594 continue;
595 }
596
597 mbox_chan_txdone(&chan[i], 0);
598 priv->pending = 0;
599 found++;
600 }
601 }
602
603 spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
604
605 if (!found) {
606 /*
607 * We may have already processed the doorbell in the previous
608 * iteration if the interrupt came right after we cleared it but
609 * before we read the stat register.
610 */
611 dev_dbg(dev, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n",
612 priv->ch_wn_idx);
613 return IRQ_NONE;
614 }
615
616 return IRQ_HANDLED;
617}
618
619static struct mbox_chan *get_irq_chan_comb_rx(struct mhuv2 *mhu)
620{
621 struct mhuv2_mbox_chan_priv *priv;
622 struct mbox_chan *chan;
623 u32 stat;
624
625 chan = get_irq_chan_comb(mhu, mhu->recv->chcomb_int_st);
626 if (IS_ERR(chan))
627 return chan;
628
629 priv = chan->con_priv;
630 if (!IS_PROTOCOL_DOORBELL(priv))
631 return chan;
632
633 /*
634 * In case of doorbell mode, the first channel of the window is returned
635 * by the routine. Find the exact channel here.
636 */
637 stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
638 BUG_ON(!stat);
639
640 return chan + __builtin_ctz(stat);
641}
642
643static struct mbox_chan *get_irq_chan_stat_rx(struct mhuv2 *mhu)
644{
645 struct mbox_chan *chans = mhu->mbox.chans;
646 struct mhuv2_mbox_chan_priv *priv;
647 u32 stat;
648 int i = 0;
649
650 while (i < mhu->mbox.num_chans) {
651 priv = chans[i].con_priv;
652 stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
653
654 if (stat) {
655 if (IS_PROTOCOL_DOORBELL(priv))
656 i += __builtin_ctz(stat);
657 return &chans[i];
658 }
659
660 i += IS_PROTOCOL_DOORBELL(priv) ? MHUV2_STAT_BITS : 1;
661 }
662
663 return ERR_PTR(-EIO);
664}
665
666static struct mbox_chan *get_irq_chan_rx(struct mhuv2 *mhu)
667{
668 if (!mhu->minor)
669 return get_irq_chan_stat_rx(mhu);
670
671 return get_irq_chan_comb_rx(mhu);
672}
673
674static irqreturn_t mhuv2_receiver_interrupt(int irq, void *arg)
675{
676 struct mhuv2 *mhu = arg;
677 struct mbox_chan *chan = get_irq_chan_rx(mhu);
678 struct device *dev = mhu->mbox.dev;
679 struct mhuv2_mbox_chan_priv *priv;
680 int ret = IRQ_NONE;
681 void *data;
682
683 if (IS_ERR(chan)) {
684 dev_warn(dev, "Failed to find channel for the rx interrupt\n");
685 return IRQ_NONE;
686 }
687 priv = chan->con_priv;
688
689 /* Read and clear the data first */
690 data = priv->ops->read_data(mhu, chan);
691
692 if (!chan->cl) {
693 dev_warn(dev, "Received data on channel (%u) not currently attached to a mailbox client\n",
694 priv->ch_wn_idx);
695 } else if (IS_ERR(data)) {
696 dev_err(dev, "Failed to read data: %lu\n", PTR_ERR(data));
697 } else {
698 mbox_chan_received_data(chan, data);
699 ret = IRQ_HANDLED;
700 }
701
702 if (!IS_ERR(data))
703 kfree(data);
704
705 return ret;
706}
707
708/* Sender and receiver ops */
709static bool mhuv2_sender_last_tx_done(struct mbox_chan *chan)
710{
711 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
712 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
713
714 return priv->ops->last_tx_done(mhu, chan);
715}
716
717static int mhuv2_sender_send_data(struct mbox_chan *chan, void *data)
718{
719 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
720 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
721
722 if (!priv->ops->last_tx_done(mhu, chan))
723 return -EBUSY;
724
725 return priv->ops->send_data(mhu, chan, data);
726}
727
728static int mhuv2_sender_startup(struct mbox_chan *chan)
729{
730 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
731 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
732
733 if (priv->ops->tx_startup)
734 priv->ops->tx_startup(mhu, chan);
735 return 0;
736}
737
738static void mhuv2_sender_shutdown(struct mbox_chan *chan)
739{
740 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
741 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
742
743 if (priv->ops->tx_shutdown)
744 priv->ops->tx_shutdown(mhu, chan);
745}
746
747static const struct mbox_chan_ops mhuv2_sender_ops = {
748 .send_data = mhuv2_sender_send_data,
749 .startup = mhuv2_sender_startup,
750 .shutdown = mhuv2_sender_shutdown,
751 .last_tx_done = mhuv2_sender_last_tx_done,
752};
753
754static int mhuv2_receiver_startup(struct mbox_chan *chan)
755{
756 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
757 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
758
759 return priv->ops->rx_startup(mhu, chan);
760}
761
762static void mhuv2_receiver_shutdown(struct mbox_chan *chan)
763{
764 struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
765 struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
766
767 priv->ops->rx_shutdown(mhu, chan);
768}
769
770static int mhuv2_receiver_send_data(struct mbox_chan *chan, void *data)
771{
772 dev_err(chan->mbox->dev,
773 "Trying to transmit on a receiver MHU frame\n");
774 return -EIO;
775}
776
777static bool mhuv2_receiver_last_tx_done(struct mbox_chan *chan)
778{
779 dev_err(chan->mbox->dev, "Trying to Tx poll on a receiver MHU frame\n");
780 return true;
781}
782
783static const struct mbox_chan_ops mhuv2_receiver_ops = {
784 .send_data = mhuv2_receiver_send_data,
785 .startup = mhuv2_receiver_startup,
786 .shutdown = mhuv2_receiver_shutdown,
787 .last_tx_done = mhuv2_receiver_last_tx_done,
788};
789
790static struct mbox_chan *mhuv2_mbox_of_xlate(struct mbox_controller *mbox,
791 const struct of_phandle_args *pa)
792{
793 struct mhuv2 *mhu = mhu_from_mbox(mbox);
794 struct mbox_chan *chans = mbox->chans;
795 int channel = 0, i, offset, doorbell, protocol, windows;
796
797 if (pa->args_count != 2)
798 return ERR_PTR(-EINVAL);
799
800 offset = pa->args[0];
801 doorbell = pa->args[1];
802 if (doorbell >= MHUV2_STAT_BITS)
803 goto out;
804
805 for (i = 0; i < mhu->length; i += 2) {
806 protocol = mhu->protocols[i];
807 windows = mhu->protocols[i + 1];
808
809 if (protocol == DOORBELL) {
810 if (offset < windows)
811 return &chans[channel + MHUV2_STAT_BITS * offset + doorbell];
812
813 channel += MHUV2_STAT_BITS * windows;
814 offset -= windows;
815 } else {
816 if (offset == 0) {
817 if (doorbell)
818 goto out;
819
820 return &chans[channel];
821 }
822
823 channel++;
824 offset--;
825 }
826 }
827
828out:
829 dev_err(mbox->dev, "Couldn't xlate to a valid channel (%d: %d)\n",
830 pa->args[0], doorbell);
831 return ERR_PTR(-ENODEV);
832}
833
834static int mhuv2_verify_protocol(struct mhuv2 *mhu)
835{
836 struct device *dev = mhu->mbox.dev;
837 int protocol, windows, channels = 0, total_windows = 0, i;
838
839 for (i = 0; i < mhu->length; i += 2) {
840 protocol = mhu->protocols[i];
841 windows = mhu->protocols[i + 1];
842
843 if (!windows) {
844 dev_err(dev, "Window size can't be zero (%d)\n", i);
845 return -EINVAL;
846 }
847 total_windows += windows;
848
849 if (protocol == DOORBELL) {
850 channels += MHUV2_STAT_BITS * windows;
851 } else if (protocol == DATA_TRANSFER) {
852 channels++;
853 } else {
854 dev_err(dev, "Invalid protocol (%d) present in %s property at index %d\n",
855 protocol, MHUV2_PROTOCOL_PROP, i);
856 return -EINVAL;
857 }
858 }
859
860 if (total_windows > mhu->windows) {
861 dev_err(dev, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n",
862 total_windows, mhu->windows);
863 return -EINVAL;
864 }
865
866 mhu->mbox.num_chans = channels;
867 return 0;
868}
869
870static int mhuv2_allocate_channels(struct mhuv2 *mhu)
871{
872 struct mbox_controller *mbox = &mhu->mbox;
873 struct mhuv2_mbox_chan_priv *priv;
874 struct device *dev = mbox->dev;
875 struct mbox_chan *chans;
876 int protocol, windows = 0, next_window = 0, i, j, k;
877
878 chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL);
879 if (!chans)
880 return -ENOMEM;
881
882 mbox->chans = chans;
883
884 for (i = 0; i < mhu->length; i += 2) {
885 next_window += windows;
886
887 protocol = mhu->protocols[i];
888 windows = mhu->protocols[i + 1];
889
890 if (protocol == DATA_TRANSFER) {
891 priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
892 if (!priv)
893 return -ENOMEM;
894
895 priv->ch_wn_idx = next_window;
896 priv->ops = &mhuv2_data_transfer_ops;
897 priv->windows = windows;
898 chans++->con_priv = priv;
899 continue;
900 }
901
902 for (j = 0; j < windows; j++) {
903 for (k = 0; k < MHUV2_STAT_BITS; k++) {
904 priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
905 if (!priv)
906 return -ENOMEM;
907
908 priv->ch_wn_idx = next_window + j;
909 priv->ops = &mhuv2_doorbell_ops;
910 priv->doorbell = k;
911 chans++->con_priv = priv;
912 }
913
914 /*
915 * Permanently enable interrupt as we can't
916 * control it per doorbell.
917 */
918 if (mhu->frame == SENDER_FRAME && mhu->minor)
919 writel_relaxed(0x1, &mhu->send->ch_wn[priv->ch_wn_idx].int_en);
920 }
921 }
922
923 /* Make sure we have initialized all channels */
924 BUG_ON(chans - mbox->chans != mbox->num_chans);
925
926 return 0;
927}
928
929static int mhuv2_parse_channels(struct mhuv2 *mhu)
930{
931 struct device *dev = mhu->mbox.dev;
932 const struct device_node *np = dev->of_node;
933 int ret, count;
934 u32 *protocols;
935
936 count = of_property_count_u32_elems(np, MHUV2_PROTOCOL_PROP);
937 if (count <= 0 || count % 2) {
938 dev_err(dev, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP,
939 count);
940 return -EINVAL;
941 }
942
943 protocols = devm_kmalloc_array(dev, count, sizeof(*protocols), GFP_KERNEL);
944 if (!protocols)
945 return -ENOMEM;
946
947 ret = of_property_read_u32_array(np, MHUV2_PROTOCOL_PROP, protocols, count);
948 if (ret) {
949 dev_err(dev, "Failed to read %s property: %d\n",
950 MHUV2_PROTOCOL_PROP, ret);
951 return ret;
952 }
953
954 mhu->protocols = protocols;
955 mhu->length = count;
956
957 ret = mhuv2_verify_protocol(mhu);
958 if (ret)
959 return ret;
960
961 return mhuv2_allocate_channels(mhu);
962}
963
964static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu,
965 void __iomem *reg)
966{
967 struct device *dev = mhu->mbox.dev;
968 int ret, i;
969
970 mhu->frame = SENDER_FRAME;
971 mhu->mbox.ops = &mhuv2_sender_ops;
972 mhu->send = reg;
973
974 mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, struct mhu_cfg_t, num_ch);
975 mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, struct aidr_t, arch_minor_rev);
976
977 spin_lock_init(&mhu->doorbell_pending_lock);
978
979 /*
980 * For minor version 1 and forward, tx interrupt is provided by
981 * the controller.
982 */
983 if (mhu->minor && adev->irq[0]) {
984 ret = devm_request_threaded_irq(dev, adev->irq[0], NULL,
985 mhuv2_sender_interrupt,
986 IRQF_ONESHOT, "mhuv2-tx", mhu);
987 if (ret) {
988 dev_err(dev, "Failed to request tx IRQ, fallback to polling mode: %d\n",
989 ret);
990 } else {
991 mhu->mbox.txdone_irq = true;
992 mhu->mbox.txdone_poll = false;
993 mhu->irq = adev->irq[0];
994
995 writel_relaxed_bitfield(1, &mhu->send->int_en, struct int_en_t, chcomb);
996
997 /* Disable all channel interrupts */
998 for (i = 0; i < mhu->windows; i++)
999 writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
1000
1001 goto out;
1002 }
1003 }
1004
1005 mhu->mbox.txdone_irq = false;
1006 mhu->mbox.txdone_poll = true;
1007 mhu->mbox.txpoll_period = 1;
1008
1009out:
1010 /* Wait for receiver to be ready */
1011 writel_relaxed(0x1, &mhu->send->access_request);
1012 while (!readl_relaxed(&mhu->send->access_ready))
1013 continue;
1014
1015 return 0;
1016}
1017
1018static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu,
1019 void __iomem *reg)
1020{
1021 struct device *dev = mhu->mbox.dev;
1022 int ret, i;
1023
1024 mhu->frame = RECEIVER_FRAME;
1025 mhu->mbox.ops = &mhuv2_receiver_ops;
1026 mhu->recv = reg;
1027
1028 mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, struct mhu_cfg_t, num_ch);
1029 mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, struct aidr_t, arch_minor_rev);
1030
1031 mhu->irq = adev->irq[0];
1032 if (!mhu->irq) {
1033 dev_err(dev, "Missing receiver IRQ\n");
1034 return -EINVAL;
1035 }
1036
1037 ret = devm_request_threaded_irq(dev, mhu->irq, NULL,
1038 mhuv2_receiver_interrupt, IRQF_ONESHOT,
1039 "mhuv2-rx", mhu);
1040 if (ret) {
1041 dev_err(dev, "Failed to request rx IRQ\n");
1042 return ret;
1043 }
1044
1045 /* Mask all the channel windows */
1046 for (i = 0; i < mhu->windows; i++)
1047 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
1048
1049 if (mhu->minor)
1050 writel_relaxed_bitfield(1, &mhu->recv->int_en, struct int_en_t, chcomb);
1051
1052 return 0;
1053}
1054
1055static int mhuv2_probe(struct amba_device *adev, const struct amba_id *id)
1056{
1057 struct device *dev = &adev->dev;
1058 const struct device_node *np = dev->of_node;
1059 struct mhuv2 *mhu;
1060 void __iomem *reg;
1061 int ret = -EINVAL;
1062
1063 reg = devm_of_iomap(dev, dev->of_node, 0, NULL);
1064 if (!reg)
1065 return -ENOMEM;
1066
1067 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
1068 if (!mhu)
1069 return -ENOMEM;
1070
1071 mhu->mbox.dev = dev;
1072 mhu->mbox.of_xlate = mhuv2_mbox_of_xlate;
1073
1074 if (of_device_is_compatible(np, "arm,mhuv2-tx"))
1075 ret = mhuv2_tx_init(adev, mhu, reg);
1076 else if (of_device_is_compatible(np, "arm,mhuv2-rx"))
1077 ret = mhuv2_rx_init(adev, mhu, reg);
1078 else
1079 dev_err(dev, "Invalid compatible property\n");
1080
1081 if (ret)
1082 return ret;
1083
1084 /* Channel windows can't be 0 */
1085 BUG_ON(!mhu->windows);
1086
1087 ret = mhuv2_parse_channels(mhu);
1088 if (ret)
1089 return ret;
1090
1091 amba_set_drvdata(adev, mhu);
1092
1093 ret = devm_mbox_controller_register(dev, &mhu->mbox);
1094 if (ret)
1095 dev_err(dev, "failed to register ARM MHUv2 driver %d\n", ret);
1096
1097 return ret;
1098}
1099
1100static void mhuv2_remove(struct amba_device *adev)
1101{
1102 struct mhuv2 *mhu = amba_get_drvdata(adev);
1103
1104 if (mhu->frame == SENDER_FRAME)
1105 writel_relaxed(0x0, &mhu->send->access_request);
1106}
1107
1108static struct amba_id mhuv2_ids[] = {
1109 {
1110 /* 2.0 */
1111 .id = 0xbb0d1,
1112 .mask = 0xfffff,
1113 },
1114 {
1115 /* 2.1 */
1116 .id = 0xbb076,
1117 .mask = 0xfffff,
1118 },
1119 { 0, 0 },
1120};
1121MODULE_DEVICE_TABLE(amba, mhuv2_ids);
1122
1123static struct amba_driver mhuv2_driver = {
1124 .drv = {
1125 .name = "arm-mhuv2",
1126 },
1127 .id_table = mhuv2_ids,
1128 .probe = mhuv2_probe,
1129 .remove = mhuv2_remove,
1130};
1131module_amba_driver(mhuv2_driver);
1132
1133MODULE_LICENSE("GPL v2");
1134MODULE_DESCRIPTION("ARM MHUv2 Driver");
1135MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
1136MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");