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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SMU_V13_0_H__
24#define __SMU_V13_0_H__
25
26#include "amdgpu_smu.h"
27
28#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
30#define SMU13_DRIVER_IF_VERSION_ALDE 0x07
31
32/* MP Apertures */
33#define MP0_Public 0x03800000
34#define MP0_SRAM 0x03900000
35#define MP1_Public 0x03b00000
36#define MP1_SRAM 0x03c00004
37
38/* address block */
39#define smnMP1_FIRMWARE_FLAGS 0x3010024
40#define smnMP0_FW_INTF 0x30101c0
41#define smnMP1_PUB_CTRL 0x3010b14
42
43#define TEMP_RANGE_MIN (0)
44#define TEMP_RANGE_MAX (80 * 1000)
45
46#define SMU13_TOOL_SIZE 0x19000
47
48#define MAX_DPM_LEVELS 16
49#define MAX_PCIE_CONF 2
50
51#define CTF_OFFSET_EDGE 5
52#define CTF_OFFSET_HOTSPOT 5
53#define CTF_OFFSET_MEM 5
54
55struct smu_13_0_max_sustainable_clocks {
56 uint32_t display_clock;
57 uint32_t phy_clock;
58 uint32_t pixel_clock;
59 uint32_t uclock;
60 uint32_t dcef_clock;
61 uint32_t soc_clock;
62};
63
64struct smu_13_0_dpm_clk_level {
65 bool enabled;
66 uint32_t value;
67};
68
69struct smu_13_0_dpm_table {
70 uint32_t min; /* MHz */
71 uint32_t max; /* MHz */
72 uint32_t count;
73 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
74};
75
76struct smu_13_0_pcie_table {
77 uint8_t pcie_gen[MAX_PCIE_CONF];
78 uint8_t pcie_lane[MAX_PCIE_CONF];
79};
80
81struct smu_13_0_dpm_tables {
82 struct smu_13_0_dpm_table soc_table;
83 struct smu_13_0_dpm_table gfx_table;
84 struct smu_13_0_dpm_table uclk_table;
85 struct smu_13_0_dpm_table eclk_table;
86 struct smu_13_0_dpm_table vclk_table;
87 struct smu_13_0_dpm_table dclk_table;
88 struct smu_13_0_dpm_table dcef_table;
89 struct smu_13_0_dpm_table pixel_table;
90 struct smu_13_0_dpm_table display_table;
91 struct smu_13_0_dpm_table phy_table;
92 struct smu_13_0_dpm_table fclk_table;
93 struct smu_13_0_pcie_table pcie_table;
94};
95
96struct smu_13_0_dpm_context {
97 struct smu_13_0_dpm_tables dpm_tables;
98 uint32_t workload_policy_mask;
99 uint32_t dcef_min_ds_clk;
100};
101
102enum smu_13_0_power_state {
103 SMU_13_0_POWER_STATE__D0 = 0,
104 SMU_13_0_POWER_STATE__D1,
105 SMU_13_0_POWER_STATE__D3, /* Sleep*/
106 SMU_13_0_POWER_STATE__D4, /* Hibernate*/
107 SMU_13_0_POWER_STATE__D5, /* Power off*/
108};
109
110struct smu_13_0_power_context {
111 uint32_t power_source;
112 uint8_t in_power_limit_boost_mode;
113 enum smu_13_0_power_state power_state;
114};
115
116enum smu_v13_0_baco_seq {
117 BACO_SEQ_BACO = 0,
118 BACO_SEQ_MSR,
119 BACO_SEQ_BAMACO,
120 BACO_SEQ_ULPS,
121 BACO_SEQ_COUNT,
122};
123
124#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
125
126int smu_v13_0_init_microcode(struct smu_context *smu);
127
128void smu_v13_0_fini_microcode(struct smu_context *smu);
129
130int smu_v13_0_load_microcode(struct smu_context *smu);
131
132int smu_v13_0_init_smc_tables(struct smu_context *smu);
133
134int smu_v13_0_fini_smc_tables(struct smu_context *smu);
135
136int smu_v13_0_init_power(struct smu_context *smu);
137
138int smu_v13_0_fini_power(struct smu_context *smu);
139
140int smu_v13_0_check_fw_status(struct smu_context *smu);
141
142int smu_v13_0_setup_pptable(struct smu_context *smu);
143
144int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
145
146int smu_v13_0_check_fw_version(struct smu_context *smu);
147
148int smu_v13_0_set_driver_table_location(struct smu_context *smu);
149
150int smu_v13_0_set_tool_table_location(struct smu_context *smu);
151
152int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
153
154int smu_v13_0_system_features_control(struct smu_context *smu,
155 bool en);
156
157int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
158
159int smu_v13_0_set_allowed_mask(struct smu_context *smu);
160
161int smu_v13_0_notify_display_change(struct smu_context *smu);
162
163int smu_v13_0_get_current_power_limit(struct smu_context *smu,
164 uint32_t *power_limit);
165
166int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n);
167
168int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
169
170int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
171
172int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
173
174int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
175
176int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
177
178int
179smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
180 struct pp_display_clock_request
181 *clock_req);
182
183uint32_t
184smu_v13_0_get_fan_control_mode(struct smu_context *smu);
185
186int
187smu_v13_0_set_fan_control_mode(struct smu_context *smu,
188 uint32_t mode);
189
190int
191smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
192
193int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
194 uint32_t speed);
195
196int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
197 uint32_t pstate);
198
199int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
200
201int smu_v13_0_register_irq_handler(struct smu_context *smu);
202
203int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
204
205int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
206 struct pp_smu_nv_clock_table *max_clocks);
207
208bool smu_v13_0_baco_is_support(struct smu_context *smu);
209
210enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
211
212int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
213
214int smu_v13_0_baco_enter(struct smu_context *smu);
215int smu_v13_0_baco_exit(struct smu_context *smu);
216
217int smu_v13_0_mode1_reset(struct smu_context *smu);
218int smu_v13_0_mode2_reset(struct smu_context *smu);
219
220int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
221 uint32_t *min, uint32_t *max);
222
223int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
224 uint32_t min, uint32_t max);
225
226int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
227 enum smu_clk_type clk_type,
228 uint32_t min,
229 uint32_t max);
230
231int smu_v13_0_set_performance_level(struct smu_context *smu,
232 enum amd_dpm_forced_level level);
233
234int smu_v13_0_set_power_source(struct smu_context *smu,
235 enum smu_power_src_type power_src);
236
237int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
238 enum smu_clk_type clk_type,
239 uint16_t level,
240 uint32_t *value);
241
242int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
243 enum smu_clk_type clk_type,
244 uint32_t *value);
245
246int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
247 enum smu_clk_type clk_type,
248 struct smu_13_0_dpm_table *single_dpm_table);
249
250int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
251 enum smu_clk_type clk_type,
252 uint32_t *min_value,
253 uint32_t *max_value);
254
255int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
256
257int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
258
259int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
260
261int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
262
263int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
264 bool enablement);
265
266int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
267 uint64_t event_arg);
268
269#endif
270#endif