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1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_CLK_MGR_H__
27#define __DAL_CLK_MGR_H__
28
29#include "dc.h"
30
31#define DCN_MINIMUM_DISPCLK_Khz 100000
32#define DCN_MINIMUM_DPPCLK_Khz 100000
33
34#ifdef CONFIG_DRM_AMD_DC_DCN2_1
35/* Constants */
36#define DDR4_DRAM_WIDTH 64
37#define WM_A 0
38#define WM_B 1
39#define WM_C 2
40#define WM_D 3
41#define WM_SET_COUNT 4
42#endif
43
44#define DCN_MINIMUM_DISPCLK_Khz 100000
45#define DCN_MINIMUM_DPPCLK_Khz 100000
46
47#ifdef CONFIG_DRM_AMD_DC_DCN2_1
48/* Will these bw structures be ASIC specific? */
49
50#define MAX_NUM_DPM_LVL 4
51#define WM_SET_COUNT 4
52
53
54struct clk_limit_table_entry {
55 unsigned int voltage; /* milivolts withh 2 fractional bits */
56 unsigned int dcfclk_mhz;
57 unsigned int fclk_mhz;
58 unsigned int memclk_mhz;
59 unsigned int socclk_mhz;
60};
61
62/* This table is contiguous */
63struct clk_limit_table {
64 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
65 unsigned int num_entries;
66};
67
68struct wm_range_table_entry {
69 unsigned int wm_inst;
70 unsigned int wm_type;
71 double pstate_latency_us;
72 bool valid;
73};
74
75
76struct clk_log_info {
77 bool enabled;
78 char *pBuf;
79 unsigned int bufSize;
80 unsigned int *sum_chars_printed;
81};
82
83struct clk_state_registers_and_bypass {
84 uint32_t dcfclk;
85 uint32_t dcf_deep_sleep_divider;
86 uint32_t dcf_deep_sleep_allow;
87 uint32_t dprefclk;
88 uint32_t dispclk;
89 uint32_t dppclk;
90
91 uint32_t dppclk_bypass;
92 uint32_t dcfclk_bypass;
93 uint32_t dprefclk_bypass;
94 uint32_t dispclk_bypass;
95};
96
97struct rv1_clk_internal {
98 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
99 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
100 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
101 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
102 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
103
104 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
105 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
106 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
107};
108
109struct rn_clk_internal {
110 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
111 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
112 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
113 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
114 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
115 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
116
117 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
118 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
119 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
120 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
121
122};
123
124/* For dtn logging and debugging */
125struct clk_state_registers {
126 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
127 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
128 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
129 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
130 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
131};
132
133/* TODO: combine this with the above */
134struct clk_bypass {
135 uint32_t dcfclk_bypass;
136 uint32_t dispclk_pypass;
137 uint32_t dprefclk_bypass;
138};
139/*
140 * This table is not contiguous, can have holes, each
141 * entry correspond to one set of WM. For example if
142 * we have 2 DPM and LPDDR, we will WM set A, B and
143 * D occupied, C will be emptry.
144 */
145struct wm_table {
146 struct wm_range_table_entry entries[WM_SET_COUNT];
147};
148
149struct clk_bw_params {
150 unsigned int vram_type;
151 unsigned int num_channels;
152 struct clk_limit_table clk_table;
153 struct wm_table wm_table;
154};
155#endif
156/* Public interfaces */
157
158struct clk_states {
159 uint32_t dprefclk_khz;
160};
161
162struct clk_mgr_funcs {
163 /*
164 * This function should set new clocks based on the input "safe_to_lower".
165 * If safe_to_lower == false, then only clocks which are to be increased
166 * should changed.
167 * If safe_to_lower == true, then only clocks which are to be decreased
168 * should be changed.
169 */
170 void (*update_clocks)(struct clk_mgr *clk_mgr,
171 struct dc_state *context,
172 bool safe_to_lower);
173
174 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
175
176 void (*init_clocks)(struct clk_mgr *clk_mgr);
177
178 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
179 void (*get_clock)(struct clk_mgr *clk_mgr,
180 struct dc_state *context,
181 enum dc_clock_type clock_type,
182 struct dc_clock_config *clock_cfg);
183};
184
185struct clk_mgr {
186 struct dc_context *ctx;
187 struct clk_mgr_funcs *funcs;
188 struct dc_clocks clks;
189 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
190#ifdef CONFIG_DRM_AMD_DC_DCN2_1
191 struct clk_bw_params *bw_params;
192#endif
193};
194
195/* forward declarations */
196struct dccg;
197
198struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
199
200void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
201
202#endif /* __DAL_CLK_MGR_H__ */
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_CLK_MGR_H__
27#define __DAL_CLK_MGR_H__
28
29#include "dc.h"
30#include "dm_pp_smu.h"
31
32#define DCN_MINIMUM_DISPCLK_Khz 100000
33#define DCN_MINIMUM_DPPCLK_Khz 100000
34
35/* Constants */
36#define DDR4_DRAM_WIDTH 64
37#define WM_A 0
38#define WM_B 1
39#define WM_C 2
40#define WM_D 3
41#define WM_SET_COUNT 4
42
43#define DCN_MINIMUM_DISPCLK_Khz 100000
44#define DCN_MINIMUM_DPPCLK_Khz 100000
45
46struct dcn3_clk_internal {
47 int dummy;
48 /*TODO:
49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
55
56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
60 */
61};
62
63struct dcn301_clk_internal {
64 int dummy;
65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
71
72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
76};
77
78/* Will these bw structures be ASIC specific? */
79
80#define MAX_NUM_DPM_LVL 8
81#define WM_SET_COUNT 4
82
83
84struct clk_limit_table_entry {
85 unsigned int voltage; /* milivolts withh 2 fractional bits */
86 unsigned int dcfclk_mhz;
87 unsigned int fclk_mhz;
88 unsigned int memclk_mhz;
89 unsigned int socclk_mhz;
90 unsigned int dtbclk_mhz;
91 unsigned int dispclk_mhz;
92 unsigned int dppclk_mhz;
93 unsigned int phyclk_mhz;
94 unsigned int wck_ratio;
95};
96
97/* This table is contiguous */
98struct clk_limit_table {
99 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
100 unsigned int num_entries;
101};
102
103struct wm_range_table_entry {
104 unsigned int wm_inst;
105 unsigned int wm_type;
106 double pstate_latency_us;
107 double sr_exit_time_us;
108 double sr_enter_plus_exit_time_us;
109 bool valid;
110};
111
112struct nv_wm_range_entry {
113 bool valid;
114
115 struct {
116 uint8_t wm_type;
117 uint16_t min_dcfclk;
118 uint16_t max_dcfclk;
119 uint16_t min_uclk;
120 uint16_t max_uclk;
121 } pmfw_breakdown;
122
123 struct {
124 double pstate_latency_us;
125 double sr_exit_time_us;
126 double sr_enter_plus_exit_time_us;
127 } dml_input;
128};
129
130struct clk_log_info {
131 bool enabled;
132 char *pBuf;
133 unsigned int bufSize;
134 unsigned int *sum_chars_printed;
135};
136
137struct clk_state_registers_and_bypass {
138 uint32_t dcfclk;
139 uint32_t dcf_deep_sleep_divider;
140 uint32_t dcf_deep_sleep_allow;
141 uint32_t dprefclk;
142 uint32_t dispclk;
143 uint32_t dppclk;
144
145 uint32_t dppclk_bypass;
146 uint32_t dcfclk_bypass;
147 uint32_t dprefclk_bypass;
148 uint32_t dispclk_bypass;
149};
150
151struct rv1_clk_internal {
152 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
153 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
154 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
155 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
156 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
157
158 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
159 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
160 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
161};
162
163struct rn_clk_internal {
164 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
165 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
166 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
167 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
168 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
169 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
170
171 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
172 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
173 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
174 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
175
176};
177
178/* For dtn logging and debugging */
179struct clk_state_registers {
180 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
181 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
182 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
183 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
184 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
185};
186
187/* TODO: combine this with the above */
188struct clk_bypass {
189 uint32_t dcfclk_bypass;
190 uint32_t dispclk_pypass;
191 uint32_t dprefclk_bypass;
192};
193/*
194 * This table is not contiguous, can have holes, each
195 * entry correspond to one set of WM. For example if
196 * we have 2 DPM and LPDDR, we will WM set A, B and
197 * D occupied, C will be emptry.
198 */
199struct wm_table {
200 union {
201 struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
202 struct wm_range_table_entry entries[WM_SET_COUNT];
203 };
204};
205
206struct dummy_pstate_entry {
207 unsigned int dram_speed_mts;
208 unsigned int dummy_pstate_latency_us;
209};
210
211struct clk_bw_params {
212 unsigned int vram_type;
213 unsigned int num_channels;
214 struct clk_limit_table clk_table;
215 struct wm_table wm_table;
216 struct dummy_pstate_entry dummy_pstate_table[4];
217};
218/* Public interfaces */
219
220struct clk_states {
221 uint32_t dprefclk_khz;
222};
223
224struct clk_mgr_funcs {
225 /*
226 * This function should set new clocks based on the input "safe_to_lower".
227 * If safe_to_lower == false, then only clocks which are to be increased
228 * should changed.
229 * If safe_to_lower == true, then only clocks which are to be decreased
230 * should be changed.
231 */
232 void (*update_clocks)(struct clk_mgr *clk_mgr,
233 struct dc_state *context,
234 bool safe_to_lower);
235
236 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
237
238 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
239
240 void (*init_clocks)(struct clk_mgr *clk_mgr);
241
242 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
243 void (*get_clock)(struct clk_mgr *clk_mgr,
244 struct dc_state *context,
245 enum dc_clock_type clock_type,
246 struct dc_clock_config *clock_cfg);
247
248 bool (*are_clock_states_equal) (struct dc_clocks *a,
249 struct dc_clocks *b);
250 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
251
252 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
253 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
254 /*
255 * Send message to PMFW to set hard min memclk frequency
256 * When current_mode = false, set DPM0
257 * When current_mode = true, set required clock for current mode
258 */
259 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
260
261 /* Send message to PMFW to set hard max memclk frequency to highest DPM */
262 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
263
264 /* Get current memclk states from PMFW, update relevant structures */
265 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
266
267 /* Get SMU present */
268 bool (*is_smu_present)(struct clk_mgr *clk_mgr);
269};
270
271struct clk_mgr {
272 struct dc_context *ctx;
273 struct clk_mgr_funcs *funcs;
274 struct dc_clocks clks;
275 bool psr_allow_active_cache;
276 bool force_smu_not_present;
277 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
278 int dentist_vco_freq_khz;
279 struct clk_state_registers_and_bypass boot_snapshot;
280 struct clk_bw_params *bw_params;
281 struct pp_smu_wm_range_sets ranges;
282};
283
284/* forward declarations */
285struct dccg;
286
287struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
288
289void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
290
291void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
292
293void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
294
295#endif /* __DAL_CLK_MGR_H__ */