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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2017 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#include <uapi/asm/bitfield.h>
32
33#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
34static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
35{
36 switch (cvmx_get_octeon_family()) {
37 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
43 return 0x0000000000003CB0ull;
44 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
45 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
46 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
47 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
48 return 0x0000000000003CB0ull;
49 /* Else, fall through */
50 default:
51 return 0x0000000000023CB0ull;
52 }
53}
54
55
56union cvmx_sli_ctl_portx {
57 uint64_t u64;
58 struct cvmx_sli_ctl_portx_s {
59 __BITFIELD_FIELD(uint64_t reserved_22_63:42,
60 __BITFIELD_FIELD(uint64_t intd:1,
61 __BITFIELD_FIELD(uint64_t intc:1,
62 __BITFIELD_FIELD(uint64_t intb:1,
63 __BITFIELD_FIELD(uint64_t inta:1,
64 __BITFIELD_FIELD(uint64_t dis_port:1,
65 __BITFIELD_FIELD(uint64_t waitl_com:1,
66 __BITFIELD_FIELD(uint64_t intd_map:2,
67 __BITFIELD_FIELD(uint64_t intc_map:2,
68 __BITFIELD_FIELD(uint64_t intb_map:2,
69 __BITFIELD_FIELD(uint64_t inta_map:2,
70 __BITFIELD_FIELD(uint64_t ctlp_ro:1,
71 __BITFIELD_FIELD(uint64_t reserved_6_6:1,
72 __BITFIELD_FIELD(uint64_t ptlp_ro:1,
73 __BITFIELD_FIELD(uint64_t reserved_1_4:4,
74 __BITFIELD_FIELD(uint64_t wait_com:1,
75 ;))))))))))))))))
76 } s;
77};
78
79union cvmx_sli_mem_access_ctl {
80 uint64_t u64;
81 struct cvmx_sli_mem_access_ctl_s {
82 __BITFIELD_FIELD(uint64_t reserved_14_63:50,
83 __BITFIELD_FIELD(uint64_t max_word:4,
84 __BITFIELD_FIELD(uint64_t timer:10,
85 ;)))
86 } s;
87};
88
89union cvmx_sli_s2m_portx_ctl {
90 uint64_t u64;
91 struct cvmx_sli_s2m_portx_ctl_s {
92 __BITFIELD_FIELD(uint64_t reserved_5_63:59,
93 __BITFIELD_FIELD(uint64_t wind_d:1,
94 __BITFIELD_FIELD(uint64_t bar0_d:1,
95 __BITFIELD_FIELD(uint64_t mrrs:3,
96 ;))))
97 } s;
98};
99
100union cvmx_sli_mem_access_subidx {
101 uint64_t u64;
102 struct cvmx_sli_mem_access_subidx_s {
103 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
104 __BITFIELD_FIELD(uint64_t zero:1,
105 __BITFIELD_FIELD(uint64_t port:3,
106 __BITFIELD_FIELD(uint64_t nmerge:1,
107 __BITFIELD_FIELD(uint64_t esr:2,
108 __BITFIELD_FIELD(uint64_t esw:2,
109 __BITFIELD_FIELD(uint64_t wtype:2,
110 __BITFIELD_FIELD(uint64_t rtype:2,
111 __BITFIELD_FIELD(uint64_t ba:30,
112 ;)))))))))
113 } s;
114 struct cvmx_sli_mem_access_subidx_cn68xx {
115 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
116 __BITFIELD_FIELD(uint64_t zero:1,
117 __BITFIELD_FIELD(uint64_t port:3,
118 __BITFIELD_FIELD(uint64_t nmerge:1,
119 __BITFIELD_FIELD(uint64_t esr:2,
120 __BITFIELD_FIELD(uint64_t esw:2,
121 __BITFIELD_FIELD(uint64_t wtype:2,
122 __BITFIELD_FIELD(uint64_t rtype:2,
123 __BITFIELD_FIELD(uint64_t ba:28,
124 __BITFIELD_FIELD(uint64_t reserved_0_1:2,
125 ;))))))))))
126 } cn68xx;
127};
128
129#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2017 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#include <uapi/asm/bitfield.h>
32
33#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
34static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
35{
36 switch (cvmx_get_octeon_family()) {
37 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
43 return 0x0000000000003CB0ull;
44 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
45 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
46 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
47 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
48 return 0x0000000000003CB0ull;
49 fallthrough;
50 default:
51 return 0x0000000000023CB0ull;
52 }
53}
54
55
56union cvmx_sli_ctl_portx {
57 uint64_t u64;
58 struct cvmx_sli_ctl_portx_s {
59 __BITFIELD_FIELD(uint64_t reserved_22_63:42,
60 __BITFIELD_FIELD(uint64_t intd:1,
61 __BITFIELD_FIELD(uint64_t intc:1,
62 __BITFIELD_FIELD(uint64_t intb:1,
63 __BITFIELD_FIELD(uint64_t inta:1,
64 __BITFIELD_FIELD(uint64_t dis_port:1,
65 __BITFIELD_FIELD(uint64_t waitl_com:1,
66 __BITFIELD_FIELD(uint64_t intd_map:2,
67 __BITFIELD_FIELD(uint64_t intc_map:2,
68 __BITFIELD_FIELD(uint64_t intb_map:2,
69 __BITFIELD_FIELD(uint64_t inta_map:2,
70 __BITFIELD_FIELD(uint64_t ctlp_ro:1,
71 __BITFIELD_FIELD(uint64_t reserved_6_6:1,
72 __BITFIELD_FIELD(uint64_t ptlp_ro:1,
73 __BITFIELD_FIELD(uint64_t reserved_1_4:4,
74 __BITFIELD_FIELD(uint64_t wait_com:1,
75 ;))))))))))))))))
76 } s;
77};
78
79union cvmx_sli_mem_access_ctl {
80 uint64_t u64;
81 struct cvmx_sli_mem_access_ctl_s {
82 __BITFIELD_FIELD(uint64_t reserved_14_63:50,
83 __BITFIELD_FIELD(uint64_t max_word:4,
84 __BITFIELD_FIELD(uint64_t timer:10,
85 ;)))
86 } s;
87};
88
89union cvmx_sli_s2m_portx_ctl {
90 uint64_t u64;
91 struct cvmx_sli_s2m_portx_ctl_s {
92 __BITFIELD_FIELD(uint64_t reserved_5_63:59,
93 __BITFIELD_FIELD(uint64_t wind_d:1,
94 __BITFIELD_FIELD(uint64_t bar0_d:1,
95 __BITFIELD_FIELD(uint64_t mrrs:3,
96 ;))))
97 } s;
98};
99
100union cvmx_sli_mem_access_subidx {
101 uint64_t u64;
102 struct cvmx_sli_mem_access_subidx_s {
103 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
104 __BITFIELD_FIELD(uint64_t zero:1,
105 __BITFIELD_FIELD(uint64_t port:3,
106 __BITFIELD_FIELD(uint64_t nmerge:1,
107 __BITFIELD_FIELD(uint64_t esr:2,
108 __BITFIELD_FIELD(uint64_t esw:2,
109 __BITFIELD_FIELD(uint64_t wtype:2,
110 __BITFIELD_FIELD(uint64_t rtype:2,
111 __BITFIELD_FIELD(uint64_t ba:30,
112 ;)))))))))
113 } s;
114 struct cvmx_sli_mem_access_subidx_cn68xx {
115 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
116 __BITFIELD_FIELD(uint64_t zero:1,
117 __BITFIELD_FIELD(uint64_t port:3,
118 __BITFIELD_FIELD(uint64_t nmerge:1,
119 __BITFIELD_FIELD(uint64_t esr:2,
120 __BITFIELD_FIELD(uint64_t esw:2,
121 __BITFIELD_FIELD(uint64_t wtype:2,
122 __BITFIELD_FIELD(uint64_t rtype:2,
123 __BITFIELD_FIELD(uint64_t ba:28,
124 __BITFIELD_FIELD(uint64_t reserved_0_1:2,
125 ;))))))))))
126 } cn68xx;
127};
128
129#endif