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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_LAN_TX_RX_H_
5#define _ICE_LAN_TX_RX_H_
6
7union ice_32byte_rx_desc {
8 struct {
9 __le64 pkt_addr; /* Packet buffer address */
10 __le64 hdr_addr; /* Header buffer address */
11 /* bit 0 of hdr_addr is DD bit */
12 __le64 rsvd1;
13 __le64 rsvd2;
14 } read;
15 struct {
16 struct {
17 struct {
18 __le16 mirroring_status;
19 __le16 l2tag1;
20 } lo_dword;
21 union {
22 __le32 rss; /* RSS Hash */
23 __le32 fd_id; /* Flow Director filter ID */
24 } hi_dword;
25 } qword0;
26 struct {
27 /* status/error/PTYPE/length */
28 __le64 status_error_len;
29 } qword1;
30 struct {
31 __le16 ext_status; /* extended status */
32 __le16 rsvd;
33 __le16 l2tag2_1;
34 __le16 l2tag2_2;
35 } qword2;
36 struct {
37 __le32 reserved;
38 __le32 fd_id;
39 } qword3;
40 } wb; /* writeback */
41};
42
43struct ice_rx_ptype_decoded {
44 u32 ptype:10;
45 u32 known:1;
46 u32 outer_ip:1;
47 u32 outer_ip_ver:2;
48 u32 outer_frag:1;
49 u32 tunnel_type:3;
50 u32 tunnel_end_prot:2;
51 u32 tunnel_end_frag:1;
52 u32 inner_prot:4;
53 u32 payload_layer:3;
54};
55
56enum ice_rx_ptype_outer_ip {
57 ICE_RX_PTYPE_OUTER_L2 = 0,
58 ICE_RX_PTYPE_OUTER_IP = 1,
59};
60
61enum ice_rx_ptype_outer_ip_ver {
62 ICE_RX_PTYPE_OUTER_NONE = 0,
63 ICE_RX_PTYPE_OUTER_IPV4 = 1,
64 ICE_RX_PTYPE_OUTER_IPV6 = 2,
65};
66
67enum ice_rx_ptype_outer_fragmented {
68 ICE_RX_PTYPE_NOT_FRAG = 0,
69 ICE_RX_PTYPE_FRAG = 1,
70};
71
72enum ice_rx_ptype_tunnel_type {
73 ICE_RX_PTYPE_TUNNEL_NONE = 0,
74 ICE_RX_PTYPE_TUNNEL_IP_IP = 1,
75 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
76 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
77 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
78};
79
80enum ice_rx_ptype_tunnel_end_prot {
81 ICE_RX_PTYPE_TUNNEL_END_NONE = 0,
82 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1,
83 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2,
84};
85
86enum ice_rx_ptype_inner_prot {
87 ICE_RX_PTYPE_INNER_PROT_NONE = 0,
88 ICE_RX_PTYPE_INNER_PROT_UDP = 1,
89 ICE_RX_PTYPE_INNER_PROT_TCP = 2,
90 ICE_RX_PTYPE_INNER_PROT_SCTP = 3,
91 ICE_RX_PTYPE_INNER_PROT_ICMP = 4,
92 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5,
93};
94
95enum ice_rx_ptype_payload_layer {
96 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
97 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
98 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
99 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
100};
101
102/* Rx Flex Descriptor
103 * This descriptor is used instead of the legacy version descriptor when
104 * ice_rlan_ctx.adv_desc is set
105 */
106union ice_32b_rx_flex_desc {
107 struct {
108 __le64 pkt_addr; /* Packet buffer address */
109 __le64 hdr_addr; /* Header buffer address */
110 /* bit 0 of hdr_addr is DD bit */
111 __le64 rsvd1;
112 __le64 rsvd2;
113 } read;
114 struct {
115 /* Qword 0 */
116 u8 rxdid; /* descriptor builder profile ID */
117 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
118 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
119 __le16 pkt_len; /* [15:14] are reserved */
120 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
121 /* sph=[11:11] */
122 /* ff1/ext=[15:12] */
123
124 /* Qword 1 */
125 __le16 status_error0;
126 __le16 l2tag1;
127 __le16 flex_meta0;
128 __le16 flex_meta1;
129
130 /* Qword 2 */
131 __le16 status_error1;
132 u8 flex_flags2;
133 u8 time_stamp_low;
134 __le16 l2tag2_1st;
135 __le16 l2tag2_2nd;
136
137 /* Qword 3 */
138 __le16 flex_meta2;
139 __le16 flex_meta3;
140 union {
141 struct {
142 __le16 flex_meta4;
143 __le16 flex_meta5;
144 } flex;
145 __le32 ts_high;
146 } flex_ts;
147 } wb; /* writeback */
148};
149
150/* Rx Flex Descriptor NIC Profile
151 * This descriptor corresponds to RxDID 2 which contains
152 * metadata fields for RSS, flow ID and timestamp info
153 */
154struct ice_32b_rx_flex_desc_nic {
155 /* Qword 0 */
156 u8 rxdid;
157 u8 mir_id_umb_cast;
158 __le16 ptype_flexi_flags0;
159 __le16 pkt_len;
160 __le16 hdr_len_sph_flex_flags1;
161
162 /* Qword 1 */
163 __le16 status_error0;
164 __le16 l2tag1;
165 __le32 rss_hash;
166
167 /* Qword 2 */
168 __le16 status_error1;
169 u8 flexi_flags2;
170 u8 ts_low;
171 __le16 l2tag2_1st;
172 __le16 l2tag2_2nd;
173
174 /* Qword 3 */
175 __le32 flow_id;
176 union {
177 struct {
178 __le16 vlan_id;
179 __le16 flow_id_ipv6;
180 } flex;
181 __le32 ts_high;
182 } flex_ts;
183};
184
185/* Receive Flex Descriptor profile IDs: There are a total
186 * of 64 profiles where profile IDs 0/1 are for legacy; and
187 * profiles 2-63 are flex profiles that can be programmed
188 * with a specific metadata (profile 7 reserved for HW)
189 */
190enum ice_rxdid {
191 ICE_RXDID_LEGACY_0 = 0,
192 ICE_RXDID_LEGACY_1 = 1,
193 ICE_RXDID_FLEX_NIC = 2,
194 ICE_RXDID_FLEX_NIC_2 = 6,
195 ICE_RXDID_HW = 7,
196 ICE_RXDID_LAST = 63,
197};
198
199/* Receive Flex Descriptor Rx opcode values */
200#define ICE_RX_OPC_MDID 0x01
201
202/* Receive Descriptor MDID values */
203enum ice_flex_rx_mdid {
204 ICE_RX_MDID_FLOW_ID_LOWER = 5,
205 ICE_RX_MDID_FLOW_ID_HIGH,
206 ICE_RX_MDID_SRC_VSI = 19,
207 ICE_RX_MDID_HASH_LOW = 56,
208 ICE_RX_MDID_HASH_HIGH,
209};
210
211/* Rx/Tx Flag64 packet flag bits */
212enum ice_flg64_bits {
213 ICE_FLG_PKT_DSI = 0,
214 ICE_FLG_EVLAN_x8100 = 15,
215 ICE_FLG_EVLAN_x9100,
216 ICE_FLG_VLAN_x8100,
217 ICE_FLG_TNL_MAC = 22,
218 ICE_FLG_TNL_VLAN,
219 ICE_FLG_PKT_FRG,
220 ICE_FLG_FIN = 32,
221 ICE_FLG_SYN,
222 ICE_FLG_RST,
223 ICE_FLG_TNL0 = 38,
224 ICE_FLG_TNL1,
225 ICE_FLG_TNL2,
226 ICE_FLG_UDP_GRE,
227 ICE_FLG_RSVD = 63
228};
229
230/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
231#define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
232
233/* for ice_32byte_rx_flex_desc.pkt_length member */
234#define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
235
236enum ice_rx_flex_desc_status_error_0_bits {
237 /* Note: These are predefined bit offsets */
238 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
239 ICE_RX_FLEX_DESC_STATUS0_EOF_S,
240 ICE_RX_FLEX_DESC_STATUS0_HBO_S,
241 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
242 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
243 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
244 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
245 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
246 ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
247 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
248 ICE_RX_FLEX_DESC_STATUS0_RXE_S,
249 ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
250 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
251 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
252 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
253 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
254 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
255};
256
257#define ICE_RXQ_CTX_SIZE_DWORDS 8
258#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
259#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
260#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
261#define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
262
263/* RLAN Rx queue context data
264 *
265 * The sizes of the variables may be larger than needed due to crossing byte
266 * boundaries. If we do not have the width of the variable set to the correct
267 * size then we could end up shifting bits off the top of the variable when the
268 * variable is at the top of a byte and crosses over into the next byte.
269 */
270struct ice_rlan_ctx {
271 u16 head;
272 u16 cpuid; /* bigger than needed, see above for reason */
273#define ICE_RLAN_BASE_S 7
274 u64 base;
275 u16 qlen;
276#define ICE_RLAN_CTX_DBUF_S 7
277 u16 dbuf; /* bigger than needed, see above for reason */
278#define ICE_RLAN_CTX_HBUF_S 6
279 u16 hbuf; /* bigger than needed, see above for reason */
280 u8 dtype;
281 u8 dsize;
282 u8 crcstrip;
283 u8 l2tsel;
284 u8 hsplit_0;
285 u8 hsplit_1;
286 u8 showiv;
287 u32 rxmax; /* bigger than needed, see above for reason */
288 u8 tphrdesc_ena;
289 u8 tphwdesc_ena;
290 u8 tphdata_ena;
291 u8 tphhead_ena;
292 u16 lrxqthresh; /* bigger than needed, see above for reason */
293 u8 prefena; /* NOTE: normally must be set to 1 at init */
294};
295
296struct ice_ctx_ele {
297 u16 offset;
298 u16 size_of;
299 u16 width;
300 u16 lsb;
301};
302
303#define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \
304 .offset = offsetof(struct _struct, _ele), \
305 .size_of = FIELD_SIZEOF(struct _struct, _ele), \
306 .width = _width, \
307 .lsb = _lsb, \
308}
309
310/* for hsplit_0 field of Rx RLAN context */
311enum ice_rlan_ctx_rx_hsplit_0 {
312 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0,
313 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1,
314 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2,
315 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
316 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8,
317};
318
319/* for hsplit_1 field of Rx RLAN context */
320enum ice_rlan_ctx_rx_hsplit_1 {
321 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0,
322 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1,
323 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2,
324};
325
326/* Tx Descriptor */
327struct ice_tx_desc {
328 __le64 buf_addr; /* Address of descriptor's data buf */
329 __le64 cmd_type_offset_bsz;
330};
331
332enum ice_tx_desc_dtype_value {
333 ICE_TX_DESC_DTYPE_DATA = 0x0,
334 ICE_TX_DESC_DTYPE_CTX = 0x1,
335 /* DESC_DONE - HW has completed write-back of descriptor */
336 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
337};
338
339#define ICE_TXD_QW1_CMD_S 4
340#define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S)
341
342enum ice_tx_desc_cmd_bits {
343 ICE_TX_DESC_CMD_EOP = 0x0001,
344 ICE_TX_DESC_CMD_RS = 0x0002,
345 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008,
346 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
347 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
348 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
349 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
350 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
351 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
352};
353
354#define ICE_TXD_QW1_OFFSET_S 16
355#define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
356
357enum ice_tx_desc_len_fields {
358 /* Note: These are predefined bit offsets */
359 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
360 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
361 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
362};
363
364#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
365#define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
366#define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
367
368/* Tx descriptor field limits in bytes */
369#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
370 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
371#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
372 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
373#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
374 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
375
376#define ICE_TXD_QW1_TX_BUF_SZ_S 34
377#define ICE_TXD_QW1_L2TAG1_S 48
378
379/* Context descriptors */
380struct ice_tx_ctx_desc {
381 __le32 tunneling_params;
382 __le16 l2tag2;
383 __le16 rsvd;
384 __le64 qw1;
385};
386
387#define ICE_TXD_CTX_QW1_CMD_S 4
388#define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
389
390#define ICE_TXD_CTX_QW1_TSO_LEN_S 30
391#define ICE_TXD_CTX_QW1_TSO_LEN_M \
392 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
393
394#define ICE_TXD_CTX_QW1_MSS_S 50
395
396enum ice_tx_ctx_desc_cmd_bits {
397 ICE_TX_CTX_DESC_TSO = 0x01,
398 ICE_TX_CTX_DESC_TSYN = 0x02,
399 ICE_TX_CTX_DESC_IL2TAG2 = 0x04,
400 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
401 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
402 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
403 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
404 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30,
405 ICE_TX_CTX_DESC_RESERVED = 0x40
406};
407
408#define ICE_LAN_TXQ_MAX_QGRPS 127
409#define ICE_LAN_TXQ_MAX_QDIS 1023
410
411/* Tx queue context data
412 *
413 * The sizes of the variables may be larger than needed due to crossing byte
414 * boundaries. If we do not have the width of the variable set to the correct
415 * size then we could end up shifting bits off the top of the variable when the
416 * variable is at the top of a byte and crosses over into the next byte.
417 */
418struct ice_tlan_ctx {
419#define ICE_TLAN_CTX_BASE_S 7
420 u64 base; /* base is defined in 128-byte units */
421 u8 port_num;
422 u16 cgd_num; /* bigger than needed, see above for reason */
423 u8 pf_num;
424 u16 vmvf_num;
425 u8 vmvf_type;
426#define ICE_TLAN_CTX_VMVF_TYPE_VF 0
427#define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1
428#define ICE_TLAN_CTX_VMVF_TYPE_PF 2
429 u16 src_vsi;
430 u8 tsyn_ena;
431 u8 internal_usage_flag;
432 u8 alt_vlan;
433 u16 cpuid; /* bigger than needed, see above for reason */
434 u8 wb_mode;
435 u8 tphrd_desc;
436 u8 tphrd;
437 u8 tphwr_desc;
438 u16 cmpq_id;
439 u16 qnum_in_func;
440 u8 itr_notification_mode;
441 u8 adjust_prof_id;
442 u32 qlen; /* bigger than needed, see above for reason */
443 u8 quanta_prof_idx;
444 u8 tso_ena;
445 u16 tso_qnum;
446 u8 legacy_int;
447 u8 drop_ena;
448 u8 cache_prof_idx;
449 u8 pkt_shaper_prof_idx;
450 u8 int_q_state; /* width not needed - internal do not write */
451};
452
453/* macro to make the table lines short */
454#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
455 { PTYPE, \
456 1, \
457 ICE_RX_PTYPE_OUTER_##OUTER_IP, \
458 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
459 ICE_RX_PTYPE_##OUTER_FRAG, \
460 ICE_RX_PTYPE_TUNNEL_##T, \
461 ICE_RX_PTYPE_TUNNEL_END_##TE, \
462 ICE_RX_PTYPE_##TEF, \
463 ICE_RX_PTYPE_INNER_PROT_##I, \
464 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
465
466#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
467
468/* shorter macros makes the table fit but are terse */
469#define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
470
471/* Lookup table mapping the HW PTYPE to the bit field for decoding */
472static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
473 /* L2 Packet types */
474 ICE_PTT_UNUSED_ENTRY(0),
475 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
476 ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
477};
478
479static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)
480{
481 return ice_ptype_lkup[ptype];
482}
483
484#define ICE_LINK_SPEED_UNKNOWN 0
485#define ICE_LINK_SPEED_10MBPS 10
486#define ICE_LINK_SPEED_100MBPS 100
487#define ICE_LINK_SPEED_1000MBPS 1000
488#define ICE_LINK_SPEED_2500MBPS 2500
489#define ICE_LINK_SPEED_5000MBPS 5000
490#define ICE_LINK_SPEED_10000MBPS 10000
491#define ICE_LINK_SPEED_20000MBPS 20000
492#define ICE_LINK_SPEED_25000MBPS 25000
493#define ICE_LINK_SPEED_40000MBPS 40000
494#define ICE_LINK_SPEED_50000MBPS 50000
495#define ICE_LINK_SPEED_100000MBPS 100000
496
497#endif /* _ICE_LAN_TX_RX_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_LAN_TX_RX_H_
5#define _ICE_LAN_TX_RX_H_
6
7union ice_32byte_rx_desc {
8 struct {
9 __le64 pkt_addr; /* Packet buffer address */
10 __le64 hdr_addr; /* Header buffer address */
11 /* bit 0 of hdr_addr is DD bit */
12 __le64 rsvd1;
13 __le64 rsvd2;
14 } read;
15 struct {
16 struct {
17 struct {
18 __le16 mirroring_status;
19 __le16 l2tag1;
20 } lo_dword;
21 union {
22 __le32 rss; /* RSS Hash */
23 __le32 fd_id; /* Flow Director filter ID */
24 } hi_dword;
25 } qword0;
26 struct {
27 /* status/error/PTYPE/length */
28 __le64 status_error_len;
29 } qword1;
30 struct {
31 __le16 ext_status; /* extended status */
32 __le16 rsvd;
33 __le16 l2tag2_1;
34 __le16 l2tag2_2;
35 } qword2;
36 struct {
37 __le32 reserved;
38 __le32 fd_id;
39 } qword3;
40 } wb; /* writeback */
41};
42
43struct ice_fltr_desc {
44 __le64 qidx_compq_space_stat;
45 __le64 dtype_cmd_vsi_fdid;
46};
47
48#define ICE_FXD_FLTR_QW0_QINDEX_S 0
49#define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)
50#define ICE_FXD_FLTR_QW0_COMP_Q_S 11
51#define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
52#define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL
53
54#define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12
55#define ICE_FXD_FLTR_QW0_COMP_REPORT_M \
56 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)
57#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL
58#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW 0x2ULL
59
60#define ICE_FXD_FLTR_QW0_FD_SPACE_S 14
61#define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)
62#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL
63
64#define ICE_FXD_FLTR_QW0_STAT_CNT_S 16
65#define ICE_FXD_FLTR_QW0_STAT_CNT_M \
66 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)
67#define ICE_FXD_FLTR_QW0_STAT_ENA_S 29
68#define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)
69#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL
70
71#define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31
72#define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
73#define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL
74#define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL
75
76#define ICE_FXD_FLTR_QW0_TO_Q_S 32
77#define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)
78#define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL
79
80#define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35
81#define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)
82#define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL
83
84#define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38
85#define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \
86 (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)
87#define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL
88
89#define ICE_FXD_FLTR_QW0_DROP_S 40
90#define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
91#define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL
92#define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL
93
94#define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41
95#define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)
96#define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL
97
98#define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44
99#define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)
100#define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL
101
102#define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48
103#define ICE_FXD_FLTR_QW0_FLEX_VAL_M \
104 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)
105#define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL
106
107#define ICE_FXD_FLTR_QW1_DTYPE_S 0
108#define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)
109#define ICE_FXD_FLTR_QW1_PCMD_S 4
110#define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
111#define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL
112#define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL
113
114#define ICE_FXD_FLTR_QW1_PROF_PRI_S 5
115#define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)
116#define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL
117
118#define ICE_FXD_FLTR_QW1_PROF_S 8
119#define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)
120#define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL
121
122#define ICE_FXD_FLTR_QW1_FD_VSI_S 14
123#define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)
124#define ICE_FXD_FLTR_QW1_SWAP_S 24
125#define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
126#define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL
127#define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL
128
129#define ICE_FXD_FLTR_QW1_FDID_PRI_S 25
130#define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
131#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL
132#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL
133
134#define ICE_FXD_FLTR_QW1_FDID_MDID_S 28
135#define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
136#define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL
137
138#define ICE_FXD_FLTR_QW1_FDID_S 32
139#define ICE_FXD_FLTR_QW1_FDID_M \
140 (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
141#define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL
142
143/* definition for FD filter programming status descriptor WB format */
144#define ICE_FXD_FLTR_WB_QW1_DD_S 0
145#define ICE_FXD_FLTR_WB_QW1_DD_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
146#define ICE_FXD_FLTR_WB_QW1_DD_YES 0x1ULL
147
148#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S 1
149#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M \
150 (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
151#define ICE_FXD_FLTR_WB_QW1_PROG_ADD 0x0ULL
152#define ICE_FXD_FLTR_WB_QW1_PROG_DEL 0x1ULL
153
154#define ICE_FXD_FLTR_WB_QW1_FAIL_S 4
155#define ICE_FXD_FLTR_WB_QW1_FAIL_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
156#define ICE_FXD_FLTR_WB_QW1_FAIL_YES 0x1ULL
157
158#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5
159#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \
160 (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
161#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL
162
163struct ice_rx_ptype_decoded {
164 u32 known:1;
165 u32 outer_ip:1;
166 u32 outer_ip_ver:2;
167 u32 outer_frag:1;
168 u32 tunnel_type:3;
169 u32 tunnel_end_prot:2;
170 u32 tunnel_end_frag:1;
171 u32 inner_prot:4;
172 u32 payload_layer:3;
173};
174
175enum ice_rx_ptype_outer_ip {
176 ICE_RX_PTYPE_OUTER_L2 = 0,
177 ICE_RX_PTYPE_OUTER_IP = 1,
178};
179
180enum ice_rx_ptype_outer_ip_ver {
181 ICE_RX_PTYPE_OUTER_NONE = 0,
182 ICE_RX_PTYPE_OUTER_IPV4 = 1,
183 ICE_RX_PTYPE_OUTER_IPV6 = 2,
184};
185
186enum ice_rx_ptype_outer_fragmented {
187 ICE_RX_PTYPE_NOT_FRAG = 0,
188 ICE_RX_PTYPE_FRAG = 1,
189};
190
191enum ice_rx_ptype_tunnel_type {
192 ICE_RX_PTYPE_TUNNEL_NONE = 0,
193 ICE_RX_PTYPE_TUNNEL_IP_IP = 1,
194 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
195 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
196 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
197};
198
199enum ice_rx_ptype_tunnel_end_prot {
200 ICE_RX_PTYPE_TUNNEL_END_NONE = 0,
201 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1,
202 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2,
203};
204
205enum ice_rx_ptype_inner_prot {
206 ICE_RX_PTYPE_INNER_PROT_NONE = 0,
207 ICE_RX_PTYPE_INNER_PROT_UDP = 1,
208 ICE_RX_PTYPE_INNER_PROT_TCP = 2,
209 ICE_RX_PTYPE_INNER_PROT_SCTP = 3,
210 ICE_RX_PTYPE_INNER_PROT_ICMP = 4,
211 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5,
212};
213
214enum ice_rx_ptype_payload_layer {
215 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
216 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
217 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
218 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
219};
220
221/* Rx Flex Descriptor
222 * This descriptor is used instead of the legacy version descriptor when
223 * ice_rlan_ctx.adv_desc is set
224 */
225union ice_32b_rx_flex_desc {
226 struct {
227 __le64 pkt_addr; /* Packet buffer address */
228 __le64 hdr_addr; /* Header buffer address */
229 /* bit 0 of hdr_addr is DD bit */
230 __le64 rsvd1;
231 __le64 rsvd2;
232 } read;
233 struct {
234 /* Qword 0 */
235 u8 rxdid; /* descriptor builder profile ID */
236 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
237 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
238 __le16 pkt_len; /* [15:14] are reserved */
239 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
240 /* sph=[11:11] */
241 /* ff1/ext=[15:12] */
242
243 /* Qword 1 */
244 __le16 status_error0;
245 __le16 l2tag1;
246 __le16 flex_meta0;
247 __le16 flex_meta1;
248
249 /* Qword 2 */
250 __le16 status_error1;
251 u8 flex_flags2;
252 u8 time_stamp_low;
253 __le16 l2tag2_1st;
254 __le16 l2tag2_2nd;
255
256 /* Qword 3 */
257 __le16 flex_meta2;
258 __le16 flex_meta3;
259 union {
260 struct {
261 __le16 flex_meta4;
262 __le16 flex_meta5;
263 } flex;
264 __le32 ts_high;
265 } flex_ts;
266 } wb; /* writeback */
267};
268
269/* Rx Flex Descriptor NIC Profile
270 * This descriptor corresponds to RxDID 2 which contains
271 * metadata fields for RSS, flow ID and timestamp info
272 */
273struct ice_32b_rx_flex_desc_nic {
274 /* Qword 0 */
275 u8 rxdid;
276 u8 mir_id_umb_cast;
277 __le16 ptype_flexi_flags0;
278 __le16 pkt_len;
279 __le16 hdr_len_sph_flex_flags1;
280
281 /* Qword 1 */
282 __le16 status_error0;
283 __le16 l2tag1;
284 __le32 rss_hash;
285
286 /* Qword 2 */
287 __le16 status_error1;
288 u8 flexi_flags2;
289 u8 ts_low;
290 __le16 l2tag2_1st;
291 __le16 l2tag2_2nd;
292
293 /* Qword 3 */
294 __le32 flow_id;
295 union {
296 struct {
297 __le16 vlan_id;
298 __le16 flow_id_ipv6;
299 } flex;
300 __le32 ts_high;
301 } flex_ts;
302};
303
304/* Receive Flex Descriptor profile IDs: There are a total
305 * of 64 profiles where profile IDs 0/1 are for legacy; and
306 * profiles 2-63 are flex profiles that can be programmed
307 * with a specific metadata (profile 7 reserved for HW)
308 */
309enum ice_rxdid {
310 ICE_RXDID_LEGACY_0 = 0,
311 ICE_RXDID_LEGACY_1 = 1,
312 ICE_RXDID_FLEX_NIC = 2,
313 ICE_RXDID_FLEX_NIC_2 = 6,
314 ICE_RXDID_HW = 7,
315 ICE_RXDID_LAST = 63,
316};
317
318/* Receive Flex Descriptor Rx opcode values */
319#define ICE_RX_OPC_MDID 0x01
320
321/* Receive Descriptor MDID values that access packet flags */
322enum ice_flex_mdid_pkt_flags {
323 ICE_RX_MDID_PKT_FLAGS_15_0 = 20,
324 ICE_RX_MDID_PKT_FLAGS_31_16,
325 ICE_RX_MDID_PKT_FLAGS_47_32,
326 ICE_RX_MDID_PKT_FLAGS_63_48,
327};
328
329/* Receive Descriptor MDID values */
330enum ice_flex_rx_mdid {
331 ICE_RX_MDID_FLOW_ID_LOWER = 5,
332 ICE_RX_MDID_FLOW_ID_HIGH,
333 ICE_RX_MDID_SRC_VSI = 19,
334 ICE_RX_MDID_HASH_LOW = 56,
335 ICE_RX_MDID_HASH_HIGH,
336};
337
338/* Rx/Tx Flag64 packet flag bits */
339enum ice_flg64_bits {
340 ICE_FLG_PKT_DSI = 0,
341 ICE_FLG_EVLAN_x8100 = 14,
342 ICE_FLG_EVLAN_x9100,
343 ICE_FLG_VLAN_x8100,
344 ICE_FLG_TNL_MAC = 22,
345 ICE_FLG_TNL_VLAN,
346 ICE_FLG_PKT_FRG,
347 ICE_FLG_FIN = 32,
348 ICE_FLG_SYN,
349 ICE_FLG_RST,
350 ICE_FLG_TNL0 = 38,
351 ICE_FLG_TNL1,
352 ICE_FLG_TNL2,
353 ICE_FLG_UDP_GRE,
354 ICE_FLG_RSVD = 63
355};
356
357/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
358#define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
359
360/* for ice_32byte_rx_flex_desc.pkt_length member */
361#define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
362
363enum ice_rx_flex_desc_status_error_0_bits {
364 /* Note: These are predefined bit offsets */
365 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
366 ICE_RX_FLEX_DESC_STATUS0_EOF_S,
367 ICE_RX_FLEX_DESC_STATUS0_HBO_S,
368 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
369 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
370 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
371 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
372 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
373 ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
374 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
375 ICE_RX_FLEX_DESC_STATUS0_RXE_S,
376 ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
377 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
378 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
379 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
380 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
381 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
382};
383
384enum ice_rx_flex_desc_status_error_1_bits {
385 /* Note: These are predefined bit offsets */
386 ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,
387 ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
388};
389
390#define ICE_RXQ_CTX_SIZE_DWORDS 8
391#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
392#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
393#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
394#define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
395
396/* RLAN Rx queue context data
397 *
398 * The sizes of the variables may be larger than needed due to crossing byte
399 * boundaries. If we do not have the width of the variable set to the correct
400 * size then we could end up shifting bits off the top of the variable when the
401 * variable is at the top of a byte and crosses over into the next byte.
402 */
403struct ice_rlan_ctx {
404 u16 head;
405 u16 cpuid; /* bigger than needed, see above for reason */
406#define ICE_RLAN_BASE_S 7
407 u64 base;
408 u16 qlen;
409#define ICE_RLAN_CTX_DBUF_S 7
410 u16 dbuf; /* bigger than needed, see above for reason */
411#define ICE_RLAN_CTX_HBUF_S 6
412 u16 hbuf; /* bigger than needed, see above for reason */
413 u8 dtype;
414 u8 dsize;
415 u8 crcstrip;
416 u8 l2tsel;
417 u8 hsplit_0;
418 u8 hsplit_1;
419 u8 showiv;
420 u32 rxmax; /* bigger than needed, see above for reason */
421 u8 tphrdesc_ena;
422 u8 tphwdesc_ena;
423 u8 tphdata_ena;
424 u8 tphhead_ena;
425 u16 lrxqthresh; /* bigger than needed, see above for reason */
426 u8 prefena; /* NOTE: normally must be set to 1 at init */
427};
428
429struct ice_ctx_ele {
430 u16 offset;
431 u16 size_of;
432 u16 width;
433 u16 lsb;
434};
435
436#define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \
437 .offset = offsetof(struct _struct, _ele), \
438 .size_of = sizeof_field(struct _struct, _ele), \
439 .width = _width, \
440 .lsb = _lsb, \
441}
442
443/* for hsplit_0 field of Rx RLAN context */
444enum ice_rlan_ctx_rx_hsplit_0 {
445 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0,
446 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1,
447 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2,
448 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
449 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8,
450};
451
452/* for hsplit_1 field of Rx RLAN context */
453enum ice_rlan_ctx_rx_hsplit_1 {
454 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0,
455 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1,
456 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2,
457};
458
459/* Tx Descriptor */
460struct ice_tx_desc {
461 __le64 buf_addr; /* Address of descriptor's data buf */
462 __le64 cmd_type_offset_bsz;
463};
464
465enum ice_tx_desc_dtype_value {
466 ICE_TX_DESC_DTYPE_DATA = 0x0,
467 ICE_TX_DESC_DTYPE_CTX = 0x1,
468 ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8,
469 /* DESC_DONE - HW has completed write-back of descriptor */
470 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
471};
472
473#define ICE_TXD_QW1_CMD_S 4
474#define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S)
475
476enum ice_tx_desc_cmd_bits {
477 ICE_TX_DESC_CMD_EOP = 0x0001,
478 ICE_TX_DESC_CMD_RS = 0x0002,
479 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008,
480 ICE_TX_DESC_CMD_DUMMY = 0x0010,
481 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
482 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
483 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
484 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
485 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
486 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
487 ICE_TX_DESC_CMD_RE = 0x0400,
488};
489
490#define ICE_TXD_QW1_OFFSET_S 16
491#define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
492
493enum ice_tx_desc_len_fields {
494 /* Note: These are predefined bit offsets */
495 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
496 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
497 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
498};
499
500#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
501#define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
502#define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
503
504/* Tx descriptor field limits in bytes */
505#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
506 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
507#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
508 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
509#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
510 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
511
512#define ICE_TXD_QW1_TX_BUF_SZ_S 34
513#define ICE_TXD_QW1_L2TAG1_S 48
514
515/* Context descriptors */
516struct ice_tx_ctx_desc {
517 __le32 tunneling_params;
518 __le16 l2tag2;
519 __le16 rsvd;
520 __le64 qw1;
521};
522
523#define ICE_TXD_CTX_QW1_CMD_S 4
524#define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
525
526#define ICE_TXD_CTX_QW1_TSO_LEN_S 30
527#define ICE_TXD_CTX_QW1_TSO_LEN_M \
528 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
529
530#define ICE_TXD_CTX_QW1_MSS_S 50
531
532enum ice_tx_ctx_desc_cmd_bits {
533 ICE_TX_CTX_DESC_TSO = 0x01,
534 ICE_TX_CTX_DESC_TSYN = 0x02,
535 ICE_TX_CTX_DESC_IL2TAG2 = 0x04,
536 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
537 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
538 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
539 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
540 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30,
541 ICE_TX_CTX_DESC_RESERVED = 0x40
542};
543
544enum ice_tx_ctx_desc_eipt_offload {
545 ICE_TX_CTX_EIPT_NONE = 0x0,
546 ICE_TX_CTX_EIPT_IPV6 = 0x1,
547 ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2,
548 ICE_TX_CTX_EIPT_IPV4 = 0x3
549};
550
551#define ICE_TXD_CTX_QW0_EIPLEN_S 2
552
553#define ICE_TXD_CTX_QW0_L4TUNT_S 9
554
555#define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
556#define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)
557
558#define ICE_TXD_CTX_QW0_NATLEN_S 12
559
560#define ICE_TXD_CTX_QW0_L4T_CS_S 23
561#define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
562
563#define ICE_LAN_TXQ_MAX_QGRPS 127
564#define ICE_LAN_TXQ_MAX_QDIS 1023
565
566/* Tx queue context data
567 *
568 * The sizes of the variables may be larger than needed due to crossing byte
569 * boundaries. If we do not have the width of the variable set to the correct
570 * size then we could end up shifting bits off the top of the variable when the
571 * variable is at the top of a byte and crosses over into the next byte.
572 */
573struct ice_tlan_ctx {
574#define ICE_TLAN_CTX_BASE_S 7
575 u64 base; /* base is defined in 128-byte units */
576 u8 port_num;
577 u16 cgd_num; /* bigger than needed, see above for reason */
578 u8 pf_num;
579 u16 vmvf_num;
580 u8 vmvf_type;
581#define ICE_TLAN_CTX_VMVF_TYPE_VF 0
582#define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1
583#define ICE_TLAN_CTX_VMVF_TYPE_PF 2
584 u16 src_vsi;
585 u8 tsyn_ena;
586 u8 internal_usage_flag;
587 u8 alt_vlan;
588 u16 cpuid; /* bigger than needed, see above for reason */
589 u8 wb_mode;
590 u8 tphrd_desc;
591 u8 tphrd;
592 u8 tphwr_desc;
593 u16 cmpq_id;
594 u16 qnum_in_func;
595 u8 itr_notification_mode;
596 u8 adjust_prof_id;
597 u32 qlen; /* bigger than needed, see above for reason */
598 u8 quanta_prof_idx;
599 u8 tso_ena;
600 u16 tso_qnum;
601 u8 legacy_int;
602 u8 drop_ena;
603 u8 cache_prof_idx;
604 u8 pkt_shaper_prof_idx;
605 u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
606};
607
608/* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the
609 * hardware to a bit-field that can be used by SW to more easily determine the
610 * packet type.
611 *
612 * Macros are used to shorten the table lines and make this table human
613 * readable.
614 *
615 * We store the PTYPE in the top byte of the bit field - this is just so that
616 * we can check that the table doesn't have a row missing, as the index into
617 * the table should be the PTYPE.
618 *
619 * Typical work flow:
620 *
621 * IF NOT ice_ptype_lkup[ptype].known
622 * THEN
623 * Packet is unknown
624 * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP
625 * Use the rest of the fields to look at the tunnels, inner protocols, etc
626 * ELSE
627 * Use the enum ice_rx_l2_ptype to decode the packet type
628 * ENDIF
629 */
630
631/* macro to make the table lines short, use explicit indexing with [PTYPE] */
632#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
633 [PTYPE] = { \
634 1, \
635 ICE_RX_PTYPE_OUTER_##OUTER_IP, \
636 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
637 ICE_RX_PTYPE_##OUTER_FRAG, \
638 ICE_RX_PTYPE_TUNNEL_##T, \
639 ICE_RX_PTYPE_TUNNEL_END_##TE, \
640 ICE_RX_PTYPE_##TEF, \
641 ICE_RX_PTYPE_INNER_PROT_##I, \
642 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
643
644#define ICE_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
645
646/* shorter macros makes the table fit but are terse */
647#define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
648#define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG
649
650/* Lookup table mapping in the 10-bit HW PTYPE to the bit field for decoding */
651static const struct ice_rx_ptype_decoded ice_ptype_lkup[BIT(10)] = {
652 /* L2 Packet types */
653 ICE_PTT_UNUSED_ENTRY(0),
654 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
655 ICE_PTT_UNUSED_ENTRY(2),
656 ICE_PTT_UNUSED_ENTRY(3),
657 ICE_PTT_UNUSED_ENTRY(4),
658 ICE_PTT_UNUSED_ENTRY(5),
659 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
660 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
661 ICE_PTT_UNUSED_ENTRY(8),
662 ICE_PTT_UNUSED_ENTRY(9),
663 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
664 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
665 ICE_PTT_UNUSED_ENTRY(12),
666 ICE_PTT_UNUSED_ENTRY(13),
667 ICE_PTT_UNUSED_ENTRY(14),
668 ICE_PTT_UNUSED_ENTRY(15),
669 ICE_PTT_UNUSED_ENTRY(16),
670 ICE_PTT_UNUSED_ENTRY(17),
671 ICE_PTT_UNUSED_ENTRY(18),
672 ICE_PTT_UNUSED_ENTRY(19),
673 ICE_PTT_UNUSED_ENTRY(20),
674 ICE_PTT_UNUSED_ENTRY(21),
675
676 /* Non Tunneled IPv4 */
677 ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
678 ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
679 ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
680 ICE_PTT_UNUSED_ENTRY(25),
681 ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
682 ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
683 ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
684
685 /* IPv4 --> IPv4 */
686 ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
687 ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
688 ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
689 ICE_PTT_UNUSED_ENTRY(32),
690 ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
691 ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
692 ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
693
694 /* IPv4 --> IPv6 */
695 ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
696 ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
697 ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
698 ICE_PTT_UNUSED_ENTRY(39),
699 ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
700 ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
701 ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
702
703 /* IPv4 --> GRE/NAT */
704 ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
705
706 /* IPv4 --> GRE/NAT --> IPv4 */
707 ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
708 ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
709 ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
710 ICE_PTT_UNUSED_ENTRY(47),
711 ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
712 ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
713 ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
714
715 /* IPv4 --> GRE/NAT --> IPv6 */
716 ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
717 ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
718 ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
719 ICE_PTT_UNUSED_ENTRY(54),
720 ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
721 ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
722 ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
723
724 /* IPv4 --> GRE/NAT --> MAC */
725 ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
726
727 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
728 ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
729 ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
730 ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
731 ICE_PTT_UNUSED_ENTRY(62),
732 ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
733 ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
734 ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
735
736 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
737 ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
738 ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
739 ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
740 ICE_PTT_UNUSED_ENTRY(69),
741 ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
742 ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
743 ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
744
745 /* IPv4 --> GRE/NAT --> MAC/VLAN */
746 ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
747
748 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
749 ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
750 ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
751 ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
752 ICE_PTT_UNUSED_ENTRY(77),
753 ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
754 ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
755 ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
756
757 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
758 ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
759 ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
760 ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
761 ICE_PTT_UNUSED_ENTRY(84),
762 ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
763 ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
764 ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
765
766 /* Non Tunneled IPv6 */
767 ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
768 ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
769 ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
770 ICE_PTT_UNUSED_ENTRY(91),
771 ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
772 ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
773 ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
774
775 /* IPv6 --> IPv4 */
776 ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
777 ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
778 ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
779 ICE_PTT_UNUSED_ENTRY(98),
780 ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
781 ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
782 ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
783
784 /* IPv6 --> IPv6 */
785 ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
786 ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
787 ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
788 ICE_PTT_UNUSED_ENTRY(105),
789 ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
790 ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
791 ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
792
793 /* IPv6 --> GRE/NAT */
794 ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
795
796 /* IPv6 --> GRE/NAT -> IPv4 */
797 ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
798 ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
799 ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
800 ICE_PTT_UNUSED_ENTRY(113),
801 ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
802 ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
803 ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
804
805 /* IPv6 --> GRE/NAT -> IPv6 */
806 ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
807 ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
808 ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
809 ICE_PTT_UNUSED_ENTRY(120),
810 ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
811 ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
812 ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
813
814 /* IPv6 --> GRE/NAT -> MAC */
815 ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
816
817 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
818 ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
819 ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
820 ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
821 ICE_PTT_UNUSED_ENTRY(128),
822 ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
823 ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
824 ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
825
826 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
827 ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
828 ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
829 ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
830 ICE_PTT_UNUSED_ENTRY(135),
831 ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
832 ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
833 ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
834
835 /* IPv6 --> GRE/NAT -> MAC/VLAN */
836 ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
837
838 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
839 ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
840 ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
841 ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
842 ICE_PTT_UNUSED_ENTRY(143),
843 ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
844 ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
845 ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
846
847 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
848 ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
849 ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
850 ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
851 ICE_PTT_UNUSED_ENTRY(150),
852 ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
853 ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
854 ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
855
856 /* unused entries */
857 [154 ... 1023] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
858};
859
860static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)
861{
862 return ice_ptype_lkup[ptype];
863}
864
865#define ICE_LINK_SPEED_UNKNOWN 0
866#define ICE_LINK_SPEED_10MBPS 10
867#define ICE_LINK_SPEED_100MBPS 100
868#define ICE_LINK_SPEED_1000MBPS 1000
869#define ICE_LINK_SPEED_2500MBPS 2500
870#define ICE_LINK_SPEED_5000MBPS 5000
871#define ICE_LINK_SPEED_10000MBPS 10000
872#define ICE_LINK_SPEED_20000MBPS 20000
873#define ICE_LINK_SPEED_25000MBPS 25000
874#define ICE_LINK_SPEED_40000MBPS 40000
875#define ICE_LINK_SPEED_50000MBPS 50000
876#define ICE_LINK_SPEED_100000MBPS 100000
877
878#endif /* _ICE_LAN_TX_RX_H_ */